OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32/trunk
    from Rev 230 to Rev 231
    ↔ Reverse comparison
  •

Rev 230 → Rev 231

/fpga/src/fms/fms.v
1,7 → 1,8
//
// fms.v -- FM synthesizer
//
// NOTE: this is a fake module for now
// NOTE: This is a fake module for now.
// It allows writing directly to the DAC.
//
 
 
25,18 → 26,25
output [15:0] sample_r;
 
reg [31:0] value;
reg value_needed;
 
always @(posedge clk) begin
if (reset) begin
value[31:0] <= 32'h0;
value_needed <= 0;
end else begin
if (en & wr & ~|addr[11:2]) begin
value[31:0] <= data_in[31:0];
value_needed <= 0;
end else begin
if (next) begin
value_needed <= 1;
end
end
end
end
 
assign data_out[31:0] = value[31:0];
assign data_out[31:0] = { 31'h0, value_needed };
assign wt = 0;
 
assign sample_l[15:0] = value[31:16];
/fpga/boards/xsa-xst-3/build/eco32.xise
15,24 → 15,24
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../toplevel/eco32.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../src/toplevel/eco32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../toplevel/eco32.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../src/toplevel/eco32.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../clk_rst/clk_rst.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../src/clk_rst/clk_rst.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../busctrl/busctrl.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../src/busctrl/busctrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../src/ram/sdr/ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
52,7 → 52,7
</file>
<file xil_pn:name="../../../src/dsp/bpp9/dsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../src/dsp/bpp9/display.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
104,7 → 104,7
</file>
<file xil_pn:name="../../../src/dsk/dsk.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../src/dsk/atactrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
118,9 → 118,17
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../bio/bio.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/fms/fms.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../src/dac/dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../src/bio/bio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
</files>
 
228,7 → 236,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|eco32" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../toplevel/eco32.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/toplevel/eco32.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/eco32" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
/fpga/boards/xsa-xst-3/build/eco32.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/fpga/boards/xsa-xst-3/doc/dac/dac_test.cfg
0,0 → 1,18
[timestart] 20170
[size] 1023 693
[pos] -1 -1
*-9.000000 20583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
dac_test.clk
dac_test.reset_in
dac_test.reset
@22
dac_test.sample_l[15:0]
dac_test.sample_r[15:0]
dac_test.dac_1.sr[63:0]
@28
dac_test.next
dac_test.mclk
dac_test.sclk
dac_test.lrck
dac_test.sdti
/fpga/boards/xsa-xst-3/doc/dac/dac_test.v
0,0 → 1,51
//
// dac_test.v -- test bench for DAC control circuit
//
 
`include "dac.v"
 
`timescale 1ns/1ns
 
module dac_test;
 
reg clk; // system clock (50 MHz)
reg reset_in; // reset, input
reg reset_s1; // reset, first synchronizer
reg reset; // reset, second synchronizer
reg [15:0] sample_l;
reg [15:0] sample_r;
wire next;
wire mclk;
wire sclk;
wire lrck;
wire sdti;
 
// instantiate the controller
dac dac_1(clk, reset,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
 
// simulation control
initial begin
#0 $dumpfile("dump.vcd");
$dumpvars(0, dac_test);
sample_l = 16'h0FF0;
sample_r = 16'hAA55;
clk = 1;
reset_in = 1;
#145 reset_in = 0;
#90000 $finish;
end
 
// clock generator
always begin
#10 clk = ~clk; // 20 nsec cycle time
end
 
// reset synchronizer
always @(posedge clk) begin
reset_s1 <= reset_in;
reset <= reset_s1;
end
 
endmodule
/fpga/boards/xsa-xst-3/doc/dac/dac.v
0,0 → 1,59
//
// dac.v -- DAC control circuit
//
 
`timescale 1ns/1ns
 
module dac(clk, reset,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
input clk;
input reset;
input [15:0] sample_l;
input [15:0] sample_r;
output next;
output mclk;
output sclk;
output lrck;
output sdti;
 
reg [9:0] timing;
reg [63:0] sr;
wire shift;
 
always @(posedge clk) begin
if (reset) begin
timing <= 10'h0;
end else begin
timing <= timing + 1;
end
end
 
assign mclk = timing[1];
assign sclk = timing[3];
assign lrck = timing[9];
 
assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;
assign shift = (timing[3:0] == 4'hF) ? 1 : 0;
 
always @(posedge clk) begin
if (reset) begin
sr <= 64'h0;
end else begin
if (next) begin
sr[63:52] <= 12'h000;
sr[51:32] <= { sample_l[15:0], 4'h0 };
sr[31:20] <= 12'h000;
sr[19: 0] <= { sample_r[15:0], 4'h0 };
end else begin
if (shift) begin
sr[63:1] <= sr[62:0];
sr[0] <= 1'b0;
end
end
end
end
 
assign sdti = sr[63];
 
endmodule
/fpga/boards/xsa-xst-3/doc/dac/Makefile
0,0 → 1,20
#
# Makefile for DAC control circuit test
#
 
all: dac_test
 
dac_test: dac.v dac_test.v
iverilog -Wall -o dac_test dac_test.v
 
run: dac_test
./dac_test
 
dump.vcd: dac_test
./dac_test
 
show: dump.vcd
gtkwave dump.vcd dac_test.cfg
 
clean:
rm -f *~ dac_test dump.vcd
/fpga/boards/xsa-xst-3/doc/dac/README
0,0 → 1,15
 
Timing Parameters
-----------------
 
clk = 50 MHz (20 nsec)
mclk = clk / 4 = 12.5 MHz (80 nsec)
sclk = mclk / 4 = 3.125 MHz (320 nsec)
lrck = sclk / 64 = 48.828 kHz (20.48 usec)
 
==>
 
fs = 48.828 kHz
mclk = 256 * fs = 12.5 MHz
sclk = 64 * fs = 3.125 MHz
 
/fpga/boards/xsa-xst-3/src/dac/dac.v
0,0 → 1,58
//
// dac.v -- DAC control circuit
//
 
 
module dac(clk, reset,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
input clk;
input reset;
input [15:0] sample_l;
input [15:0] sample_r;
output next;
output mclk;
output sclk;
output lrck;
output sdti;
 
reg [9:0] timing;
reg [63:0] sr;
wire shift;
 
always @(posedge clk) begin
if (reset) begin
timing <= 10'h0;
end else begin
timing <= timing + 1;
end
end
 
assign mclk = timing[1];
assign sclk = timing[3];
assign lrck = timing[9];
 
assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;
assign shift = (timing[3:0] == 4'hF) ? 1 : 0;
 
always @(posedge clk) begin
if (reset) begin
sr <= 64'h0;
end else begin
if (next) begin
sr[63:52] <= 12'h000;
sr[51:32] <= { sample_l[15:0], 4'h0 };
sr[31:20] <= 12'h000;
sr[19: 0] <= { sample_r[15:0], 4'h0 };
end else begin
if (shift) begin
sr[63:1] <= sr[62:0];
sr[0] <= 1'b0;
end
end
end
end
 
assign sdti = sr[63];
 
endmodule
/fpga/boards/xsa-xst-3/src/toplevel/eco32.v
45,6 → 45,10
ata_dmarq,
ata_dmack_n,
ata_iordy,
dac_mclk,
dac_sclk,
dac_lrck,
dac_sdti,
slot1_cs_n,
slot2_cs_n,
ether_cs_n,
104,6 → 108,11
input ata_dmarq;
output ata_dmack_n;
input ata_iordy;
// audio DAC
output dac_mclk;
output dac_sclk;
output dac_lrck;
output dac_sdti;
// expansion slot 1
output slot1_cs_n;
// expansion slot 2
201,6 → 210,17
wire [31:0] dsk_data_out;
wire dsk_wt;
wire dsk_irq;
// fms
wire fms_en;
wire fms_wr;
wire [11:2] fms_addr;
wire [31:0] fms_data_in;
wire [31:0] fms_data_out;
wire fms_wt;
// dac
wire [15:0] dac_sample_l;
wire [15:0] dac_sample_r;
wire dac_next;
// bio
wire bio_en;
wire bio_wr;
292,6 → 312,13
.dsk_data_in(dsk_data_in[31:0]),
.dsk_data_out(dsk_data_out[31:0]),
.dsk_wt(dsk_wt),
// fms
.fms_en(fms_en),
.fms_wr(fms_wr),
.fms_addr(fms_addr[11:2]),
.fms_data_in(fms_data_in[31:0]),
.fms_data_out(fms_data_out[31:0]),
.fms_wt(fms_wt),
// bio
.bio_en(bio_en),
.bio_wr(bio_wr),
478,6 → 505,32
.ata_iordy(ata_iordy)
);
 
fms fms1(
.clk(clk),
.reset(reset),
.en(fms_en),
.wr(fms_wr),
.addr(fms_addr[11:2]),
.data_in(fms_data_in[31:0]),
.data_out(fms_data_out[31:0]),
.wt(fms_wt),
.next(dac_next),
.sample_l(dac_sample_l[15:0]),
.sample_r(dac_sample_r[15:0])
);
 
dac dac1(
.clk(clk),
.reset(reset),
.sample_l(dac_sample_l[15:0]),
.sample_r(dac_sample_r[15:0]),
.next(dac_next),
.mclk(dac_mclk),
.sclk(dac_sclk),
.lrck(dac_lrck),
.sdti(dac_sdti)
);
 
assign pbus_a[4:3] = 2'b00;
assign slot1_cs_n = 1;
assign slot2_cs_n = 1;
/fpga/boards/xsa-xst-3/src/toplevel/eco32.ucf
168,6 → 168,14
NET "slot2_cs_n" LOC = "d16";
 
#
# audio DAC
#
NET "dac_mclk" LOC = "p11";
NET "dac_sclk" LOC = "t12";
NET "dac_lrck" LOC = "r12";
NET "dac_sdti" LOC = "m10";
 
#
# board I/O
#
NET "sw1_3" LOC = "k2";
/fpga/boards/xsa-xst-3/src/busctrl/busctrl.v
23,6 → 23,8
ser1_data_in, ser1_data_out, ser1_wt,
dsk_en, dsk_wr, dsk_addr,
dsk_data_in, dsk_data_out, dsk_wt,
fms_en, fms_wr, fms_addr,
fms_data_in, fms_data_out, fms_wt,
bio_en, bio_wr, bio_addr,
bio_data_in, bio_data_out, bio_wt);
// cpu
97,6 → 99,13
output [31:0] dsk_data_in;
input [31:0] dsk_data_out;
input dsk_wt;
// fms
output fms_en;
output fms_wr;
output [11:2] fms_addr;
output [31:0] fms_data_in;
input [31:0] fms_data_out;
input fms_wt;
// bio
output bio_en;
output bio_wr;
141,6 → 150,9
&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
assign dsk_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0;
assign fms_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h05
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
assign bio_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h10
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
156,6 → 168,7
(ser0_en == 1) ? ser0_wt :
(ser1_en == 1) ? ser1_wt :
(dsk_en == 1) ? dsk_wt :
(fms_en == 1) ? fms_wt :
(bio_en == 1) ? bio_wt :
1;
assign cpu_data_in[31:0] =
168,6 → 181,7
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } :
(ser1_en == 1) ? { 24'h000000, ser1_data_out[7:0] } :
(dsk_en == 1) ? dsk_data_out[31:0] :
(fms_en == 1) ? fms_data_out[31:0] :
(bio_en == 1) ? bio_data_out[31:0] :
32'h00000000;
 
217,6 → 231,11
assign dsk_addr[19:2] = cpu_addr[19:2];
assign dsk_data_in[31:0] = cpu_data_out[31:0];
 
// to fms
assign fms_wr = cpu_wr;
assign fms_addr[11:2] = cpu_addr[11:2];
assign fms_data_in[31:0] = cpu_data_out[31:0];
 
// to bio
assign bio_wr = cpu_wr;
assign bio_addr = cpu_addr[2];
/fpga/boards/s3e-500/build/eco32.xise
15,28 → 15,17
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../toplevel/eco32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../toplevel/eco32.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../clk_rst/clk_rst.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../busctrl/busctrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../toplevel/eco32.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../toplevel/eco32.ucf" xil_pn:type="FILE_UCF"/>
<file xil_pn:name="../clk_rst/clk_rst.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../busctrl/busctrl.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../src/ram/ddr/ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/ram/ddr/ddr_sdram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
44,7 → 33,7
</file>
<file xil_pn:name="../../../src/rom/28F128J3/rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../src/tmr/tmr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
52,7 → 41,7
</file>
<file xil_pn:name="../../../src/dsp/bpp3/dsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../src/dsp/bpp3/display.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
76,7 → 65,7
</file>
<file xil_pn:name="../../../src/kbd/kbd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/kbd/keyboard.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
84,7 → 73,7
</file>
<file xil_pn:name="../../../src/ser/ser.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../src/ser/rcvbuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
104,16 → 93,10
</file>
<file xil_pn:name="../../../src/fms/fms.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../spi/spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../bio/bio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../src/spi/spi.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../bio/bio.v" xil_pn:type="FILE_VERILOG"/>
</files>
 
<properties>
218,9 → 201,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|eco32" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../toplevel/eco32.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/eco32" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|cpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/cpu/cpu.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
278,7 → 261,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="eco32" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="cpu" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
290,10 → 273,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="eco32_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="eco32_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="eco32_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="eco32_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cpu_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="cpu_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cpu_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cpu_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
300,6 → 283,7
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
/fpga/boards/s3e-500/build/eco32.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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