URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
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/eco32/trunk
- from Rev 232 to Rev 233
- ↔ Reverse comparison
Rev 232 → Rev 233
/fpga/boards/xsa-xst-3/doc/dac/dac_test.cfg
4,13 → 4,14
*-9.000000 20583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
@28 |
dac_test.clk |
dac_test.reset_in |
dac_test.reset |
@22 |
dac_test.sample_l[15:0] |
dac_test.sample_r[15:0] |
dac_test.dac_1.timing[9:0] |
dac_test.dac_1.sr[63:0] |
@28 |
dac_test.dac_1.shift |
dac_test.next |
dac_test.mclk |
dac_test.sclk |
/fpga/boards/s3e-500/doc/dac/dac_test.cfg
0,0 → 1,18
[timestart] 41073 |
[size] 1023 693 |
[pos] -1 -1 |
*-6.000000 41100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
@28 |
dac_test.clk |
dac_test.reset |
@22 |
dac_test.sample_l[15:0] |
dac_test.sample_r[15:0] |
dac_test.dac_1.timing[9:0] |
dac_test.dac_1.sr[47:0] |
@28 |
dac_test.dac_1.shift |
dac_test.next |
dac_test.sck |
dac_test.sdi |
dac_test.ld |
/fpga/boards/s3e-500/doc/dac/dac_test.v
0,0 → 1,50
// |
// dac_test.v -- test bench for DAC control circuit |
// |
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`include "dac.v" |
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`timescale 1ns/1ns |
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module dac_test; |
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reg clk; // system clock (50 MHz) |
reg reset_in; // reset, input |
reg reset_s1; // reset, first synchronizer |
reg reset; // reset, second synchronizer |
reg [15:0] sample_l; |
reg [15:0] sample_r; |
wire next; |
wire sck; |
wire sdi; |
wire ld; |
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// instantiate the controller |
dac dac_1(clk, reset, |
sample_l, sample_r, next, |
sck, sdi, ld); |
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// simulation control |
initial begin |
#0 $dumpfile("dump.vcd"); |
$dumpvars(0, dac_test); |
sample_l = 16'h0FF0; |
sample_r = 16'hAA55; |
clk = 1; |
reset_in = 1; |
#145 reset_in = 0; |
#90000 $finish; |
end |
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// clock generator |
always begin |
#10 clk = ~clk; // 20 nsec cycle time |
end |
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// reset synchronizer |
always @(posedge clk) begin |
reset_s1 <= reset_in; |
reset <= reset_s1; |
end |
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endmodule |
/fpga/boards/s3e-500/doc/dac/dac.v
0,0 → 1,79
// |
// dac.v -- DAC control circuit |
// |
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`timescale 1ns/1ns |
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module dac(clk, reset, |
sample_l, sample_r, next, |
sck, sdi, ld); |
input clk; |
input reset; |
input [15:0] sample_l; |
input [15:0] sample_r; |
output next; |
output sck; |
output sdi; |
output reg ld; |
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reg [9:0] timing; |
reg [47:0] sr; |
wire shift; |
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always @(posedge clk) begin |
if (reset) begin |
timing <= 10'h0; |
end else begin |
timing <= timing + 1; |
end |
end |
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assign sck = timing[0]; |
assign next = (timing[9:0] == 10'h001) ? 1 : 0; |
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always @(posedge clk) begin |
if (reset) begin |
ld <= 1'b1; |
end else begin |
if (timing[9:0] == 10'h001) begin |
ld <= 1'b0; |
end |
if (timing[9:0] == 10'h031) begin |
ld <= 1'b1; |
end |
if (timing[9:0] == 10'h033) begin |
ld <= 1'b0; |
end |
if (timing[9:0] == 10'h063) begin |
ld <= 1'b1; |
end |
end |
end |
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assign shift = sck & ~ld; |
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always @(posedge clk) begin |
if (reset) begin |
sr <= 48'h0; |
end else begin |
if (next) begin |
sr[47:44] <= 4'b0011; |
sr[43:40] <= 4'b0000; |
sr[39:24] <= { ~sample_l[15], |
sample_l[14:0] }; |
sr[23:20] <= 4'b0011; |
sr[19:16] <= 4'b0001; |
sr[15: 0] <= { ~sample_r[15], |
sample_r[14:0] }; |
end else begin |
if (shift) begin |
sr[47:1] <= sr[46:0]; |
sr[0] <= 1'b0; |
end |
end |
end |
end |
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assign sdi = sr[47]; |
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endmodule |
/fpga/boards/s3e-500/doc/dac/Makefile
0,0 → 1,20
# |
# Makefile for DAC control circuit test |
# |
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all: dac_test |
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dac_test: dac.v dac_test.v |
iverilog -Wall -o dac_test dac_test.v |
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run: dac_test |
./dac_test |
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dump.vcd: dac_test |
./dac_test |
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show: dump.vcd |
gtkwave dump.vcd dac_test.cfg |
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clean: |
rm -f *~ dac_test dump.vcd |
/fpga/boards/s3e-500/doc/dac/README
0,0 → 1,14
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Timing Parameters |
----------------- |
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clk = 50 MHz (20 nsec) |
sck = clk / 2 = 25 MHz (40 nsec) |
50 bits per sample (a pair of 16 bit values) |
repeated after 512 sck cycles |
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==> |
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fs = 48.828 kHz |
less than 10% of SPI capacity used |
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