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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

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  • This comparison shows the changes necessary to convert path 
    /eco32/trunk
    from Rev 68 to Rev 69
    ↔ Reverse comparison
  •

Rev 68 → Rev 69

/fpga/src/eco32.v
138,7 → 138,7
// tmr
wire tmr_en;
wire tmr_wr;
wire tmr_addr;
wire [3:2] tmr_addr;
wire [31:0] tmr_data_in;
wire [31:0] tmr_data_out;
wire tmr_wt;
222,7 → 222,7
// tmr
.tmr_en(tmr_en),
.tmr_wr(tmr_wr),
.tmr_addr(tmr_addr),
.tmr_addr(tmr_addr[3:2]),
.tmr_data_in(tmr_data_in[31:0]),
.tmr_data_out(tmr_data_out[31:0]),
.tmr_wt(tmr_wt),
339,7 → 339,7
.reset(reset),
.en(tmr_en),
.wr(tmr_wr),
.addr(tmr_addr),
.addr(tmr_addr[3:2]),
.data_in(tmr_data_in[31:0]),
.data_out(tmr_data_out[31:0]),
.wt(tmr_wt),
/fpga/src/tmr/tmr.v
11,14 → 11,12
input reset;
input en;
input wr;
input addr;
input [3:2] addr;
input [31:0] data_in;
output [31:0] data_out;
output reg [31:0] data_out;
output wt;
output irq;
 
reg [5:0] prescaler;
reg tick;
reg [31:0] counter;
reg [31:0] divisor;
reg divisor_loaded;
27,34 → 25,15
reg ien;
 
always @(posedge clk) begin
if (reset == 1) begin
prescaler <= 6'd50;
tick <= 0;
end else begin
if (prescaler == 6'd1) begin
prescaler <= 6'd50;
tick <= 1;
end else begin
prescaler <= prescaler - 1;
tick <= 0;
end
end
end
 
always @(posedge clk) begin
if (divisor_loaded == 1) begin
counter <= divisor;
expired <= 0;
end else begin
if (tick == 1) begin
if (counter == 32'h00000001) begin
counter <= divisor;
expired <= 1;
end else begin
counter <= counter - 1;
expired <= 0;
end
if (counter == 32'h00000001) begin
counter <= divisor;
expired <= 1;
end else begin
counter <= counter - 1;
expired <= 0;
end
end
70,11 → 49,11
if (expired == 1) begin
alarm <= 1;
end else begin
if (en == 1 && wr == 1 && addr == 0) begin
if (en == 1 && wr == 1 && addr[3:2] == 2'b00) begin
alarm <= data_in[0];
ien <= data_in[1];
end
if (en == 1 && wr == 1 && addr == 1) begin
if (en == 1 && wr == 1 && addr[3:2] == 2'b01) begin
divisor <= data_in;
divisor_loaded <= 1;
end else begin
84,9 → 63,25
end
end
 
assign data_out =
(addr == 0) ? { 28'h0000000, 2'b00, ien, alarm } :
divisor;
always @(*) begin
case (addr[3:2])
2'b00:
// ctrl
data_out = { 28'h0000000, 2'b00, ien, alarm };
2'b01:
// divisor
data_out = divisor;
2'b10:
// counter
data_out = counter;
2'b11:
// not used
data_out = 32'hxxxxxxxx;
default:
data_out = 32'hxxxxxxxx;
endcase
end
 
assign wt = 0;
assign irq = ien & alarm;
 
/fpga/src/busctrl/busctrl.v
46,7 → 46,7
// tmr
output tmr_en;
output tmr_wr;
output tmr_addr;
output [3:2] tmr_addr;
output [31:0] tmr_data_in;
input [31:0] tmr_data_out;
input tmr_wt;
154,7 → 154,7
 
// to tmr
assign tmr_wr = cpu_wr;
assign tmr_addr = cpu_addr[2];
assign tmr_addr[3:2] = cpu_addr[3:2];
assign tmr_data_in[31:0] = cpu_data_out[31:0];
 
// to dsp

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