URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
Compare Revisions
- This comparison shows the changes necessary to convert path
/eco32/trunk
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/fpga/src/eco32.v
135,14 → 135,22
wire [20:0] rom_addr; |
wire [31:0] rom_data_out; |
wire rom_wt; |
// tmr |
wire tmr_en; |
wire tmr_wr; |
wire [3:2] tmr_addr; |
wire [31:0] tmr_data_in; |
wire [31:0] tmr_data_out; |
wire tmr_wt; |
wire tmr_irq; |
// tmr0 |
wire tmr0_en; |
wire tmr0_wr; |
wire [3:2] tmr0_addr; |
wire [31:0] tmr0_data_in; |
wire [31:0] tmr0_data_out; |
wire tmr0_wt; |
wire tmr0_irq; |
// tmr1 |
wire tmr1_en; |
wire tmr1_wr; |
wire [3:2] tmr1_addr; |
wire [31:0] tmr1_data_in; |
wire [31:0] tmr1_data_out; |
wire tmr1_wt; |
wire tmr1_irq; |
// dsp |
wire dsp_en; |
wire dsp_wr; |
219,13 → 227,20
.rom_addr(rom_addr[20:0]), |
.rom_data_out(rom_data_out[31:0]), |
.rom_wt(rom_wt), |
// tmr |
.tmr_en(tmr_en), |
.tmr_wr(tmr_wr), |
.tmr_addr(tmr_addr[3:2]), |
.tmr_data_in(tmr_data_in[31:0]), |
.tmr_data_out(tmr_data_out[31:0]), |
.tmr_wt(tmr_wt), |
// tmr0 |
.tmr0_en(tmr0_en), |
.tmr0_wr(tmr0_wr), |
.tmr0_addr(tmr0_addr[3:2]), |
.tmr0_data_in(tmr0_data_in[31:0]), |
.tmr0_data_out(tmr0_data_out[31:0]), |
.tmr0_wt(tmr0_wt), |
// tmr1 |
.tmr1_en(tmr1_en), |
.tmr1_wr(tmr1_wr), |
.tmr1_addr(tmr1_addr[3:2]), |
.tmr1_data_in(tmr1_data_in[31:0]), |
.tmr1_data_out(tmr1_data_out[31:0]), |
.tmr1_wt(tmr1_wt), |
// dsp |
.dsp_en(dsp_en), |
.dsp_wr(dsp_wr), |
276,8 → 291,8
.irq(cpu_irq[15:0]) |
); |
|
assign cpu_irq[15] = 1'b0; |
assign cpu_irq[14] = tmr_irq; |
assign cpu_irq[15] = tmr1_irq; |
assign cpu_irq[14] = tmr0_irq; |
assign cpu_irq[13] = 1'b0; |
assign cpu_irq[12] = 1'b0; |
assign cpu_irq[11] = 1'b0; |
334,18 → 349,30
.d(flash_d[15:0]) |
); |
|
tmr tmr1( |
tmr tmr1_0( |
.clk(clk), |
.reset(reset), |
.en(tmr_en), |
.wr(tmr_wr), |
.addr(tmr_addr[3:2]), |
.data_in(tmr_data_in[31:0]), |
.data_out(tmr_data_out[31:0]), |
.wt(tmr_wt), |
.irq(tmr_irq) |
.en(tmr0_en), |
.wr(tmr0_wr), |
.addr(tmr0_addr[3:2]), |
.data_in(tmr0_data_in[31:0]), |
.data_out(tmr0_data_out[31:0]), |
.wt(tmr0_wt), |
.irq(tmr0_irq) |
); |
|
tmr tmr1_1( |
.clk(clk), |
.reset(reset), |
.en(tmr1_en), |
.wr(tmr1_wr), |
.addr(tmr1_addr[3:2]), |
.data_in(tmr1_data_in[31:0]), |
.data_out(tmr1_data_out[31:0]), |
.wt(tmr1_wt), |
.irq(tmr1_irq) |
); |
|
dsp dsp1( |
.clk(clk), |
.reset(reset), |
/fpga/src/busctrl/busctrl.v
8,8 → 8,10
ram_data_in, ram_data_out, ram_wt, |
rom_en, rom_wr, rom_size, rom_addr, |
rom_data_out, rom_wt, |
tmr_en, tmr_wr, tmr_addr, |
tmr_data_in, tmr_data_out, tmr_wt, |
tmr0_en, tmr0_wr, tmr0_addr, |
tmr0_data_in, tmr0_data_out, tmr0_wt, |
tmr1_en, tmr1_wr, tmr1_addr, |
tmr1_data_in, tmr1_data_out, tmr1_wt, |
dsp_en, dsp_wr, dsp_addr, |
dsp_data_in, dsp_data_out, dsp_wt, |
kbd_en, kbd_wr, kbd_addr, |
43,13 → 45,20
output [20:0] rom_addr; |
input [31:0] rom_data_out; |
input rom_wt; |
// tmr |
output tmr_en; |
output tmr_wr; |
output [3:2] tmr_addr; |
output [31:0] tmr_data_in; |
input [31:0] tmr_data_out; |
input tmr_wt; |
// tmr0 |
output tmr0_en; |
output tmr0_wr; |
output [3:2] tmr0_addr; |
output [31:0] tmr0_data_in; |
input [31:0] tmr0_data_out; |
input tmr0_wt; |
// tmr1 |
output tmr1_en; |
output tmr1_wr; |
output [3:2] tmr1_addr; |
output [31:0] tmr1_data_in; |
input [31:0] tmr1_data_out; |
input tmr1_wt; |
// dsp |
output dsp_en; |
output dsp_wr; |
104,8 → 113,12
// I/O: architectural limit = 256 MB |
assign i_o_en = |
(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0; |
assign tmr_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00) ? 1 : 0; |
assign tmr0_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
assign tmr1_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00 |
&& cpu_addr[19:12] == 8'h01) ? 1 : 0; |
assign dsp_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0; |
assign kbd_en = |
123,7 → 136,8
assign cpu_wt = |
(ram_en == 1) ? ram_wt : |
(rom_en == 1) ? rom_wt : |
(tmr_en == 1) ? tmr_wt : |
(tmr0_en == 1) ? tmr0_wt : |
(tmr1_en == 1) ? tmr1_wt : |
(dsp_en == 1) ? dsp_wt : |
(kbd_en == 1) ? kbd_wt : |
(ser0_en == 1) ? ser0_wt : |
133,7 → 147,8
assign cpu_data_in[31:0] = |
(ram_en == 1) ? ram_data_out[31:0] : |
(rom_en == 1) ? rom_data_out[31:0] : |
(tmr_en == 1) ? tmr_data_out[31:0] : |
(tmr0_en == 1) ? tmr0_data_out[31:0] : |
(tmr1_en == 1) ? tmr1_data_out[31:0] : |
(dsp_en == 1) ? { 16'h0000, dsp_data_out[15:0] } : |
(kbd_en == 1) ? { 24'h000000, kbd_data_out[7:0] } : |
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } : |
152,11 → 167,16
assign rom_size[1:0] = cpu_size[1:0]; |
assign rom_addr[20:0] = cpu_addr[20:0]; |
|
// to tmr |
assign tmr_wr = cpu_wr; |
assign tmr_addr[3:2] = cpu_addr[3:2]; |
assign tmr_data_in[31:0] = cpu_data_out[31:0]; |
// to tmr0 |
assign tmr0_wr = cpu_wr; |
assign tmr0_addr[3:2] = cpu_addr[3:2]; |
assign tmr0_data_in[31:0] = cpu_data_out[31:0]; |
|
// to tmr1 |
assign tmr1_wr = cpu_wr; |
assign tmr1_addr[3:2] = cpu_addr[3:2]; |
assign tmr1_data_in[31:0] = cpu_data_out[31:0]; |
|
// to dsp |
assign dsp_wr = cpu_wr; |
assign dsp_addr[13:2] = cpu_addr[13:2]; |