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trunk/fpga/xsa-xst-3/eco32.bit
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Index: trunk/fpga/src/dsp/chrgenlo.init
===================================================================
--- trunk/fpga/src/dsp/chrgenlo.init (revision 214)
+++ trunk/fpga/src/dsp/chrgenlo.init (nonexistent)
@@ -1,64 +0,0 @@
- defparam character_rom_lo.INIT_00 = 256'h000000007E818199BD8181A5817E000000000000000000000000000000000000;
- defparam character_rom_lo.INIT_01 = 256'h00000000081C3E7F7F7F7F3600000000000000007EFFFFE7C3FFFFDBFF7E0000;
- defparam character_rom_lo.INIT_02 = 256'h000000003C1899E7E7E73C3C180000000000000000081C3E7F3E1C0800000000;
- defparam character_rom_lo.INIT_03 = 256'h000000000000183C3C18000000000000000000003C18187EFFFF7E3C18000000;
- defparam character_rom_lo.INIT_04 = 256'h00000000003C664242663C0000000000FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF;
- defparam character_rom_lo.INIT_05 = 256'h000000001E333333331E4C5870780000FFFFFFFFFFC399BDBD99C3FFFFFFFFFF;
- defparam character_rom_lo.INIT_06 = 256'h00000000070F0E0C0C0C0CFCCCFC00000000000018187E183C666666663C0000;
- defparam character_rom_lo.INIT_07 = 256'h000000001818DB3CE73CDB18180000000000000367E7E6C6C6C6C6FEC6FE0000;
- defparam character_rom_lo.INIT_08 = 256'h00000000406070787C7F7C7870604000000000000103070F1F7F1F0F07030100;
- defparam character_rom_lo.INIT_09 = 256'h0000000066660066666666666666000000000000183C7E181818187E3C180000;
- defparam character_rom_lo.INIT_0A = 256'h0000003E63301C366363361C06633E0000000000D8D8D8D8D8DEDBDBDBFE0000;
- defparam character_rom_lo.INIT_0B = 256'h0000007E183C7E181818187E3C180000000000007F7F7F7F0000000000000000;
- defparam character_rom_lo.INIT_0C = 256'h00000000183C7E18181818181818000000000000181818181818187E3C180000;
- defparam character_rom_lo.INIT_0D = 256'h0000000000000C067F060C000000000000000000000018307F30180000000000;
- defparam character_rom_lo.INIT_0E = 256'h00000000000014367F361400000000000000000000007F030303030000000000;
- defparam character_rom_lo.INIT_0F = 256'h0000000000081C1C3E3E7F7F0000000000000000007F7F3E3E1C1C0800000000;
- defparam character_rom_lo.INIT_10 = 256'h000000001818001818183C3C3C18000000000000000000000000000000000000;
- defparam character_rom_lo.INIT_11 = 256'h0000000036367F3636367F363600000000000000000000000000002466666600;
- defparam character_rom_lo.INIT_12 = 256'h000000006163060C183063430000000000000018183E6361603E0343633E1818;
- defparam character_rom_lo.INIT_13 = 256'h0000000000000000000000060C0C0C00000000006E3333333B6E1C36361C0000;
- defparam character_rom_lo.INIT_14 = 256'h000000000C18303030303030180C00000000000030180C0C0C0C0C0C18300000;
- defparam character_rom_lo.INIT_15 = 256'h00000000000018187E18180000000000000000000000663CFF3C660000000000;
- defparam character_rom_lo.INIT_16 = 256'h00000000000000007F000000000000000000000C181818000000000000000000;
- defparam character_rom_lo.INIT_17 = 256'h000000000103060C183060400000000000000000181800000000000000000000;
- defparam character_rom_lo.INIT_18 = 256'h000000007E1818181818181E1C180000000000003E6363676B6B7363633E0000;
- defparam character_rom_lo.INIT_19 = 256'h000000003E636060603C6060633E0000000000007F6303060C183060633E0000;
- defparam character_rom_lo.INIT_1A = 256'h000000003E636060703F0303037F000000000000783030307F33363C38300000;
- defparam character_rom_lo.INIT_1B = 256'h000000000C0C0C0C18306060637F0000000000003E636363633F0303061C0000;
- defparam character_rom_lo.INIT_1C = 256'h000000001E306060607E6363633E0000000000003E636363633E6363633E0000;
- defparam character_rom_lo.INIT_1D = 256'h000000000C181800000018180000000000000000001818000000181800000000;
- defparam character_rom_lo.INIT_1E = 256'h0000000000007F00007F000000000000000000006030180C060C183060000000;
- defparam character_rom_lo.INIT_1F = 256'h000000001818001818183063633E000000000000060C18306030180C06000000;
- defparam character_rom_lo.INIT_20 = 256'h00000000636363637F6363361C080000000000003E033B7B7B7B63633E000000;
- defparam character_rom_lo.INIT_21 = 256'h000000003C66430303030343663C0000000000003F666666663E6666663F0000;
- defparam character_rom_lo.INIT_22 = 256'h000000007F664606161E1646667F0000000000001F36666666666666361F0000;
- defparam character_rom_lo.INIT_23 = 256'h000000005C6663637B030343663C0000000000000F060606161E1646667F0000;
- defparam character_rom_lo.INIT_24 = 256'h000000003C18181818181818183C00000000000063636363637F636363630000;
- defparam character_rom_lo.INIT_25 = 256'h00000000676666361E1E363666670000000000001E3333333030303030780000;
- defparam character_rom_lo.INIT_26 = 256'h0000000063636363636B7F7F77630000000000007F66460606060606060F0000;
- defparam character_rom_lo.INIT_27 = 256'h000000001C36636363636363361C00000000000063636363737B7F6F67630000;
- defparam character_rom_lo.INIT_28 = 256'h000070303E7B6B6363636363633E0000000000000F060606063E6666663F0000;
- defparam character_rom_lo.INIT_29 = 256'h000000003E636360301C0663633E00000000000067666666363E6666663F0000;
- defparam character_rom_lo.INIT_2A = 256'h000000003E6363636363636363630000000000003C1818181818185A7E7E0000;
- defparam character_rom_lo.INIT_2B = 256'h0000000036367F6B6B6363636363000000000000081C36636363636363630000;
- defparam character_rom_lo.INIT_2C = 256'h000000003C181818183C66666666000000000000636336361C1C363663630000;
- defparam character_rom_lo.INIT_2D = 256'h000000003C0C0C0C0C0C0C0C0C3C0000000000007F6343060C183061637F0000;
- defparam character_rom_lo.INIT_2E = 256'h000000003C30303030303030303C000000000000406070381C0E070301000000;
- defparam character_rom_lo.INIT_2F = 256'h0000FF0000000000000000000000000000000000000000000000000063361C08;
- defparam character_rom_lo.INIT_30 = 256'h000000006E3333333E301E000000000000000000000000000000000000180C0C;
- defparam character_rom_lo.INIT_31 = 256'h000000003E63030303633E0000000000000000003B66666666361E0606070000;
- defparam character_rom_lo.INIT_32 = 256'h000000003E6303037F633E0000000000000000006E33333333363C3030380000;
- defparam character_rom_lo.INIT_33 = 256'h001E33303E33333333336E0000000000000000000F060606060F0626361C0000;
- defparam character_rom_lo.INIT_34 = 256'h000000003C18181818181C00181800000000000067666666666E360606070000;
- defparam character_rom_lo.INIT_35 = 256'h000000006766361E1E36660606070000003C6666606060606060700060600000;
- defparam character_rom_lo.INIT_36 = 256'h000000006B6B6B6B6B7F370000000000000000003C18181818181818181C0000;
- defparam character_rom_lo.INIT_37 = 256'h000000003E63636363633E0000000000000000006666666666663B0000000000;
- defparam character_rom_lo.INIT_38 = 256'h007830303E33333333336E0000000000000F06063E66666666663B0000000000;
- defparam character_rom_lo.INIT_39 = 256'h000000003E63301C06633E0000000000000000000F060606466E3B0000000000;
- defparam character_rom_lo.INIT_3A = 256'h000000006E333333333333000000000000000000386C0C0C0C0C3F0C0C080000;
- defparam character_rom_lo.INIT_3B = 256'h00000000367F6B6B636363000000000000000000183C66666666660000000000;
- defparam character_rom_lo.INIT_3C = 256'h001F30607E63636363636300000000000000000063361C1C1C36630000000000;
- defparam character_rom_lo.INIT_3D = 256'h0000000070181818180E181818700000000000007F63060C18337F0000000000;
- defparam character_rom_lo.INIT_3E = 256'h000000000E18181818701818180E000000000000181818181800181818180000;
- defparam character_rom_lo.INIT_3F = 256'h00000000007F636363361C08000000000000000000000000000000003B6E0000;
Index: trunk/fpga/src/dsp/dspchrhi.init
===================================================================
--- trunk/fpga/src/dsp/dspchrhi.init (revision 214)
+++ trunk/fpga/src/dsp/dspchrhi.init (nonexistent)
@@ -1,64 +0,0 @@
- defparam display_chr_hi.INIT_00 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_01 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_02 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_03 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_04 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_05 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_06 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_07 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_08 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_09 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_0A = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_0B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_0C = 256'h2726262727262422272627262627262624222626272626252222222222222222;
- defparam display_chr_hi.INIT_0D = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_0E = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_0F = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_10 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_11 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_12 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_13 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_14 = 256'h2727262726262726262422232322272227262626242223232222222222222222;
- defparam display_chr_hi.INIT_15 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_16 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_17 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_18 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_19 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_1A = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_1B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_1C = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_1D = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_1E = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_1F = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_20 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_21 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_22 = 256'h2222222222222227272627272627262625222222222222222222222222222222;
- defparam display_chr_hi.INIT_23 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_24 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_25 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_26 = 256'h2222222222222222222222262622222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_27 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_28 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_29 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_2A = 256'h2222222227262626262626252226262626272724222222222222222222222222;
- defparam display_chr_hi.INIT_2B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_2C = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_2D = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_2E = 256'h2222222222222222226262727262624222222222222222222222222222222222;
- defparam display_chr_hi.INIT_2F = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_30 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_31 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_32 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_33 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_34 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_35 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_36 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_37 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_38 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_39 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_3A = 256'h2222222222222222222222222222222222222222222222222222222222222222;
- defparam display_chr_hi.INIT_3B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
- defparam display_chr_hi.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_hi.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_hi.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_hi.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/dsp.v
===================================================================
--- trunk/fpga/src/dsp/dsp.v (revision 214)
+++ trunk/fpga/src/dsp/dsp.v (nonexistent)
@@ -1,65 +0,0 @@
-//
-// dsp.v -- character display interface
-//
-
-
-module dsp(clk, reset,
- addr, en, wr, wt,
- data_in, data_out,
- hsync, vsync,
- r, g, b);
- // internal interface
- input clk;
- input reset;
- input [13:2] addr;
- input en;
- input wr;
- output wt;
- input [15:0] data_in;
- output [15:0] data_out;
- // external interface
- output hsync;
- output vsync;
- output [2:0] r;
- output [2:0] g;
- output [2:0] b;
-
- reg state;
-
- display display1(
- .clk(clk),
- .dsp_row(addr[13:9]),
- .dsp_col(addr[8:2]),
- .dsp_en(en),
- .dsp_wr(wr),
- .dsp_wr_data(data_in[15:0]),
- .dsp_rd_data(data_out[15:0]),
- .hsync(hsync),
- .vsync(vsync),
- .r(r[2:0]),
- .g(g[2:0]),
- .b(b[2:0])
- );
-
- always @(posedge clk) begin
- if (reset == 1) begin
- state <= 1'b0;
- end else begin
- case (state)
- 1'b0:
- begin
- if (en == 1 && wr == 0) begin
- state <= 1'b1;
- end
- end
- 1'b1:
- begin
- state <= 1'b0;
- end
- endcase
- end
- end
-
- assign wt = (en == 1 && wr == 0 && state == 1'b0) ? 1 : 0;
-
-endmodule
Index: trunk/fpga/src/dsp/dspchrlo.init
===================================================================
--- trunk/fpga/src/dsp/dspchrlo.init (revision 214)
+++ trunk/fpga/src/dsp/dspchrlo.init (nonexistent)
@@ -1,64 +0,0 @@
- defparam display_chr_lo.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_0C = 256'h09010C000309040002050403010201080300050C000D09030000000000000000;
- defparam display_chr_lo.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_14 = 256'h0302050403010201080300000800080003050E090C0000030000000000000000;
- defparam display_chr_lo.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_22 = 256'h0000000000000009040903020506090E05000000000000000000000000000000;
- defparam display_chr_lo.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_26 = 256'h0000000000000000000000060F00000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_2A = 256'h000000000305030E05090303000405090C000001000000000000000000000000;
- defparam display_chr_lo.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_2E = 256'h000000000000000000E050303050907000000000000000000000000000000000;
- defparam display_chr_lo.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_chr_lo.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/chrgen.v
===================================================================
--- trunk/fpga/src/dsp/chrgen.v (revision 214)
+++ trunk/fpga/src/dsp/chrgen.v (nonexistent)
@@ -1,79 +0,0 @@
-//
-// chrgen.v -- character generator
-//
-
-
-module chrgen(clk, pixclk,
- chrcode, chrrow, chrcol,
- pixel,
- attcode_in, blank_in, hsync_in, vsync_in, blink_in,
- attcode_out, blank_out, hsync_out, vsync_out, blink_out);
- input clk;
- input pixclk;
- input [7:0] chrcode;
- input [3:0] chrrow;
- input [2:0] chrcol;
- output pixel;
- input [7:0] attcode_in;
- input blank_in;
- input hsync_in;
- input vsync_in;
- input blink_in;
- output reg [7:0] attcode_out;
- output reg blank_out;
- output reg hsync_out;
- output reg vsync_out;
- output reg blink_out;
-
- wire [13:0] addr;
- wire [0:0] pixel_lo;
- wire [0:0] pixel_hi;
-
- reg mux_ctrl;
-
- assign addr[13:7] = chrcode[6:0];
- assign addr[6:3] = chrrow[3:0];
- assign addr[2:0] = chrcol[2:0];
-
- assign pixel = (mux_ctrl == 0) ? pixel_lo[0] : pixel_hi[0];
-
- // RAMB16_S1: Spartan-3 16kx1 Single-Port RAM
-
- RAMB16_S1 character_rom_lo (
- .DO(pixel_lo), // 1-bit Data Output
- .ADDR(addr), // 14-bit Address Input
- .CLK(clk), // Clock
- .DI(1'b0), // 1-bit Data Input
- .EN(pixclk), // RAM Enable Input
- .SSR(1'b0), // Synchronous Set/Reset Input
- .WE(1'b0) // Write Enable Input
- );
-
- `include "chrgenlo.init"
-
- // RAMB16_S1: Spartan-3 16kx1 Single-Port RAM
-
- RAMB16_S1 character_rom_hi (
- .DO(pixel_hi), // 1-bit Data Output
- .ADDR(addr), // 14-bit Address Input
- .CLK(clk), // Clock
- .DI(1'b0), // 1-bit Data Input
- .EN(pixclk), // RAM Enable Input
- .SSR(1'b0), // Synchronous Set/Reset Input
- .WE(1'b0) // Write Enable Input
- );
-
- `include "chrgenhi.init"
-
- always @(posedge clk) begin
- if (pixclk == 1) begin
- attcode_out[7:0] <= attcode_in[7:0];
- blank_out <= blank_in;
- hsync_out <= hsync_in;
- vsync_out <= vsync_in;
- blink_out <= blink_in;
- mux_ctrl <= chrcode[7];
- end
- end
-
-endmodule
Index: trunk/fpga/src/dsp/dspmem.v
===================================================================
--- trunk/fpga/src/dsp/dspmem.v (revision 214)
+++ trunk/fpga/src/dsp/dspmem.v (nonexistent)
@@ -1,175 +0,0 @@
-//
-// dspmem.v -- display memory
-//
-
-
-module dspmem(rdwr_row, rdwr_col, wr_data, rd_data, en, wr,
- clk, pixclk,
- txtrow, txtcol, attcode, chrcode,
- chrrow_in, chrcol_in, blank_in,
- hsync_in, vsync_in, blink_in,
- chrrow_out, chrcol_out, blank_out,
- hsync_out, vsync_out, blink_out);
- input [4:0] rdwr_row;
- input [6:0] rdwr_col;
- input [15:0] wr_data;
- output [15:0] rd_data;
- input en;
- input wr;
- input clk;
- input pixclk;
- input [4:0] txtrow;
- input [6:0] txtcol;
- output [7:0] attcode;
- output [7:0] chrcode;
- input [3:0] chrrow_in;
- input [2:0] chrcol_in;
- input blank_in;
- input hsync_in;
- input vsync_in;
- input blink_in;
- output reg [3:0] chrrow_out;
- output reg [2:0] chrcol_out;
- output reg blank_out;
- output reg hsync_out;
- output reg vsync_out;
- output reg blink_out;
-
- wire [11:0] rdwr_addr;
- wire [3:0] rdwr_din_n3;
- wire [3:0] rdwr_din_n2;
- wire [3:0] rdwr_din_n1;
- wire [3:0] rdwr_din_n0;
- wire [3:0] rdwr_dout_n3;
- wire [3:0] rdwr_dout_n2;
- wire [3:0] rdwr_dout_n1;
- wire [3:0] rdwr_dout_n0;
-
- wire [11:0] rfsh_addr;
- wire [3:0] rfsh_din_n3;
- wire [3:0] rfsh_din_n2;
- wire [3:0] rfsh_din_n1;
- wire [3:0] rfsh_din_n0;
- wire [3:0] rfsh_dout_n3;
- wire [3:0] rfsh_dout_n2;
- wire [3:0] rfsh_dout_n1;
- wire [3:0] rfsh_dout_n0;
-
- assign rdwr_addr[11:7] = rdwr_row[4:0];
- assign rdwr_addr[6:0] = rdwr_col[6:0];
- assign rdwr_din_n3 = wr_data[15:12];
- assign rdwr_din_n2 = wr_data[11: 8];
- assign rdwr_din_n1 = wr_data[ 7: 4];
- assign rdwr_din_n0 = wr_data[ 3: 0];
- assign rd_data[15:12] = rdwr_dout_n3;
- assign rd_data[11: 8] = rdwr_dout_n2;
- assign rd_data[ 7: 4] = rdwr_dout_n1;
- assign rd_data[ 3: 0] = rdwr_dout_n0;
-
- assign rfsh_addr[11:7] = txtrow[4:0];
- assign rfsh_addr[6:0] = txtcol[6:0];
- assign rfsh_din_n3 = 4'b0000;
- assign rfsh_din_n2 = 4'b0000;
- assign rfsh_din_n1 = 4'b0000;
- assign rfsh_din_n0 = 4'b0000;
- assign attcode[7:4] = rfsh_dout_n3;
- assign attcode[3:0] = rfsh_dout_n2;
- assign chrcode[7:4] = rfsh_dout_n1;
- assign chrcode[3:0] = rfsh_dout_n0;
-
- // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
-
- RAMB16_S4_S4 display_att_hi (
- .DOA(rdwr_dout_n3), // Port A 4-bit Data Output
- .DOB(rfsh_dout_n3), // Port B 4-bit Data Output
- .ADDRA(rdwr_addr), // Port A 12-bit Address Input
- .ADDRB(rfsh_addr), // Port B 12-bit Address Input
- .CLKA(clk), // Port A Clock
- .CLKB(clk), // Port B Clock
- .DIA(rdwr_din_n3), // Port A 4-bit Data Input
- .DIB(rfsh_din_n3), // Port B 4-bit Data Input
- .ENA(en), // Port A RAM Enable Input
- .ENB(pixclk), // Port B RAM Enable Input
- .SSRA(1'b0), // Port A Synchronous Set/Reset Input
- .SSRB(1'b0), // Port B Synchronous Set/Reset Input
- .WEA(wr), // Port A Write Enable Input
- .WEB(1'b0) // Port B Write Enable Input
- );
-
- `include "dspatthi.init"
-
- // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
-
- RAMB16_S4_S4 display_att_lo (
- .DOA(rdwr_dout_n2), // Port A 4-bit Data Output
- .DOB(rfsh_dout_n2), // Port B 4-bit Data Output
- .ADDRA(rdwr_addr), // Port A 12-bit Address Input
- .ADDRB(rfsh_addr), // Port B 12-bit Address Input
- .CLKA(clk), // Port A Clock
- .CLKB(clk), // Port B Clock
- .DIA(rdwr_din_n2), // Port A 4-bit Data Input
- .DIB(rfsh_din_n2), // Port B 4-bit Data Input
- .ENA(en), // Port A RAM Enable Input
- .ENB(pixclk), // Port B RAM Enable Input
- .SSRA(1'b0), // Port A Synchronous Set/Reset Input
- .SSRB(1'b0), // Port B Synchronous Set/Reset Input
- .WEA(wr), // Port A Write Enable Input
- .WEB(1'b0) // Port B Write Enable Input
- );
-
- `include "dspattlo.init"
-
- // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
-
- RAMB16_S4_S4 display_chr_hi (
- .DOA(rdwr_dout_n1), // Port A 4-bit Data Output
- .DOB(rfsh_dout_n1), // Port B 4-bit Data Output
- .ADDRA(rdwr_addr), // Port A 12-bit Address Input
- .ADDRB(rfsh_addr), // Port B 12-bit Address Input
- .CLKA(clk), // Port A Clock
- .CLKB(clk), // Port B Clock
- .DIA(rdwr_din_n1), // Port A 4-bit Data Input
- .DIB(rfsh_din_n1), // Port B 4-bit Data Input
- .ENA(en), // Port A RAM Enable Input
- .ENB(pixclk), // Port B RAM Enable Input
- .SSRA(1'b0), // Port A Synchronous Set/Reset Input
- .SSRB(1'b0), // Port B Synchronous Set/Reset Input
- .WEA(wr), // Port A Write Enable Input
- .WEB(1'b0) // Port B Write Enable Input
- );
-
- `include "dspchrhi.init"
-
- // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
-
- RAMB16_S4_S4 display_chr_lo (
- .DOA(rdwr_dout_n0), // Port A 4-bit Data Output
- .DOB(rfsh_dout_n0), // Port B 4-bit Data Output
- .ADDRA(rdwr_addr), // Port A 12-bit Address Input
- .ADDRB(rfsh_addr), // Port B 12-bit Address Input
- .CLKA(clk), // Port A Clock
- .CLKB(clk), // Port B Clock
- .DIA(rdwr_din_n0), // Port A 4-bit Data Input
- .DIB(rfsh_din_n0), // Port B 4-bit Data Input
- .ENA(en), // Port A RAM Enable Input
- .ENB(pixclk), // Port B RAM Enable Input
- .SSRA(1'b0), // Port A Synchronous Set/Reset Input
- .SSRB(1'b0), // Port B Synchronous Set/Reset Input
- .WEA(wr), // Port A Write Enable Input
- .WEB(1'b0) // Port B Write Enable Input
- );
-
- `include "dspchrlo.init"
-
- always @(posedge clk) begin
- if (pixclk == 1) begin
- chrrow_out <= chrrow_in;
- chrcol_out <= chrcol_in;
- blank_out <= blank_in;
- hsync_out <= hsync_in;
- vsync_out <= vsync_in;
- blink_out <= blink_in;
- end
- end
-
-endmodule
Index: trunk/fpga/src/dsp/display.v
===================================================================
--- trunk/fpga/src/dsp/display.v (revision 214)
+++ trunk/fpga/src/dsp/display.v (nonexistent)
@@ -1,122 +0,0 @@
-//
-// display.v -- 30x80 character display, with attributes
-//
-
-
-module display(clk,
- dsp_row, dsp_col, dsp_en, dsp_wr,
- dsp_wr_data, dsp_rd_data,
- hsync, vsync, r, g, b);
- input clk;
- input [4:0] dsp_row;
- input [6:0] dsp_col;
- input dsp_en;
- input dsp_wr;
- input [15:0] dsp_wr_data;
- output [15:0] dsp_rd_data;
- output hsync;
- output vsync;
- output [2:0] r;
- output [2:0] g;
- output [2:0] b;
-
- wire pixclk;
- wire [4:0] timing_txtrow;
- wire [6:0] timing_txtcol;
- wire [3:0] timing_chrrow;
- wire [2:0] timing_chrcol;
- wire timing_blank;
- wire timing_hsync;
- wire timing_vsync;
- wire timing_blink;
- wire [7:0] dspmem_attcode;
- wire [7:0] dspmem_chrcode;
- wire [3:0] dspmem_chrrow;
- wire [2:0] dspmem_chrcol;
- wire dspmem_blank;
- wire dspmem_hsync;
- wire dspmem_vsync;
- wire dspmem_blink;
- wire [7:0] chrgen_attcode;
- wire chrgen_pixel;
- wire chrgen_blank;
- wire chrgen_hsync;
- wire chrgen_vsync;
- wire chrgen_blink;
-
- timing timing1(
- .clk(clk),
- .pixclk(pixclk),
- .txtrow(timing_txtrow[4:0]),
- .txtcol(timing_txtcol[6:0]),
- .chrrow(timing_chrrow[3:0]),
- .chrcol(timing_chrcol[2:0]),
- .blank(timing_blank),
- .hsync(timing_hsync),
- .vsync(timing_vsync),
- .blink(timing_blink)
- );
-
- dspmem dspmem1(
- .rdwr_row(dsp_row[4:0]),
- .rdwr_col(dsp_col[6:0]),
- .wr_data(dsp_wr_data[15:0]),
- .rd_data(dsp_rd_data[15:0]),
- .en(dsp_en),
- .wr(dsp_wr),
- .clk(clk),
- .pixclk(pixclk),
- .txtrow(timing_txtrow[4:0]),
- .txtcol(timing_txtcol[6:0]),
- .attcode(dspmem_attcode[7:0]),
- .chrcode(dspmem_chrcode[7:0]),
- .chrrow_in(timing_chrrow[3:0]),
- .chrcol_in(timing_chrcol[2:0]),
- .blank_in(timing_blank),
- .hsync_in(timing_hsync),
- .vsync_in(timing_vsync),
- .blink_in(timing_blink),
- .chrrow_out(dspmem_chrrow[3:0]),
- .chrcol_out(dspmem_chrcol[2:0]),
- .blank_out(dspmem_blank),
- .hsync_out(dspmem_hsync),
- .vsync_out(dspmem_vsync),
- .blink_out(dspmem_blink)
- );
-
- chrgen chrgen1(
- .clk(clk),
- .pixclk(pixclk),
- .chrcode(dspmem_chrcode[7:0]),
- .chrrow(dspmem_chrrow[3:0]),
- .chrcol(dspmem_chrcol[2:0]),
- .pixel(chrgen_pixel),
- .attcode_in(dspmem_attcode[7:0]),
- .blank_in(dspmem_blank),
- .hsync_in(dspmem_hsync),
- .vsync_in(dspmem_vsync),
- .blink_in(dspmem_blink),
- .attcode_out(chrgen_attcode[7:0]),
- .blank_out(chrgen_blank),
- .hsync_out(chrgen_hsync),
- .vsync_out(chrgen_vsync),
- .blink_out(chrgen_blink)
- );
-
- pixel pixel1(
- .clk(clk),
- .pixclk(pixclk),
- .attcode(chrgen_attcode[7:0]),
- .pixel(chrgen_pixel),
- .blank(chrgen_blank),
- .hsync_in(chrgen_hsync),
- .vsync_in(chrgen_vsync),
- .blink(chrgen_blink),
- .hsync(hsync),
- .vsync(vsync),
- .r(r[2:0]),
- .g(g[2:0]),
- .b(b[2:0])
- );
-
-endmodule
Index: trunk/fpga/src/dsp/pixel.v
===================================================================
--- trunk/fpga/src/dsp/pixel.v (revision 214)
+++ trunk/fpga/src/dsp/pixel.v (nonexistent)
@@ -1,69 +0,0 @@
-//
-// pixel.v -- last stage in display pipeline
-//
-
-
-module pixel(clk, pixclk, attcode,
- pixel, blank, hsync_in, vsync_in, blink,
- hsync, vsync, r, g, b);
- input clk;
- input pixclk;
- input [7:0] attcode;
- input pixel;
- input blank;
- input hsync_in;
- input vsync_in;
- input blink;
- output reg hsync;
- output reg vsync;
- output reg [2:0] r;
- output reg [2:0] g;
- output reg [2:0] b;
-
- wire blink_bit;
- wire bg_red;
- wire bg_green;
- wire bg_blue;
- wire inten_bit;
- wire fg_red;
- wire fg_green;
- wire fg_blue;
- wire foreground;
- wire intensify;
- wire red;
- wire green;
- wire blue;
-
- assign blink_bit = attcode[7];
- assign bg_red = attcode[6];
- assign bg_green = attcode[5];
- assign bg_blue = attcode[4];
- assign inten_bit = attcode[3];
- assign fg_red = attcode[2];
- assign fg_green = attcode[1];
- assign fg_blue = attcode[0];
-
- assign foreground = pixel & ~(blink_bit & blink);
- assign intensify = foreground & inten_bit;
-
- assign red = (foreground ? fg_red : bg_red);
- assign green = (foreground ? fg_green : bg_green);
- assign blue = (foreground ? fg_blue : bg_blue);
-
- always @(posedge clk) begin
- if (pixclk == 1) begin
- hsync <= hsync_in;
- vsync <= vsync_in;
- r[2] <= blank & red;
- r[1] <= blank & intensify;
- r[0] <= blank & red & intensify;
- g[2] <= blank & green;
- g[1] <= blank & intensify;
- g[0] <= blank & green & intensify;
- b[2] <= blank & blue;
- b[1] <= blank & intensify;
- b[0] <= blank & blue & intensify;
- end
- end
-
-endmodule
Index: trunk/fpga/src/dsp/dspatthi.init
===================================================================
--- trunk/fpga/src/dsp/dspatthi.init (revision 214)
+++ trunk/fpga/src/dsp/dspatthi.init (nonexistent)
@@ -1,64 +0,0 @@
- defparam display_att_hi.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_hi.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/chrgenhi.init
===================================================================
--- trunk/fpga/src/dsp/chrgenhi.init (revision 214)
+++ trunk/fpga/src/dsp/chrgenhi.init (nonexistent)
@@ -1,64 +0,0 @@
- defparam character_rom_hi.INIT_00 = 256'h000000006E333333333333003333000000003E60303C664303030343663C0000;
- defparam character_rom_hi.INIT_01 = 256'h000000006E3333333E301E00361C0800000000003E6303037F633E000C183000;
- defparam character_rom_hi.INIT_02 = 256'h000000006E3333333E301E00180C0600000000006E3333333E301E0033330000;
- defparam character_rom_hi.INIT_03 = 256'h0000003C60303C660606663C00000000000000006E3333333E301E001C361C00;
- defparam character_rom_hi.INIT_04 = 256'h000000003E6303037F633E0063630000000000003E6303037F633E00361C0800;
- defparam character_rom_hi.INIT_05 = 256'h000000003C18181818181C0066660000000000003E6303037F633E00180C0600;
- defparam character_rom_hi.INIT_06 = 256'h000000003C18181818181C00180C0600000000003C18181818181C00663C1800;
- defparam character_rom_hi.INIT_07 = 256'h000000006363637F6363361C001C361C000000006363637F6363361C08636300;
- defparam character_rom_hi.INIT_08 = 256'h00000000761B1B7E6C6E330000000000000000007F6606063E06667F00060C18;
- defparam character_rom_hi.INIT_09 = 256'h000000003E63636363633E00361C08000000000073333333337F3333367C0000;
- defparam character_rom_hi.INIT_0A = 256'h000000003E63636363633E00180C0600000000003E63636363633E0063630000;
- defparam character_rom_hi.INIT_0B = 256'h000000006E33333333333300180C0600000000006E33333333333300331E0C00;
- defparam character_rom_hi.INIT_0C = 256'h000000001C3663636363361C00636300001E30607E6363636363630063630000;
- defparam character_rom_hi.INIT_0D = 256'h0000000018183C66060606663C181800000000003E6363636363636300636300;
- defparam character_rom_hi.INIT_0E = 256'h000000001818187E187E183C66660000000000003F67060606060F0626361C00;
- defparam character_rom_hi.INIT_0F = 256'h00000E1B18181818187E181818D8700000000000633333337B33231F33331F00;
- defparam character_rom_hi.INIT_10 = 256'h000000003C18181818181C000C183000000000006E3333333E301E00060C1800;
- defparam character_rom_hi.INIT_11 = 256'h000000006E33333333333300060C1800000000003E63636363633E00060C1800;
- defparam character_rom_hi.INIT_12 = 256'h00000000636363737B7F6F6763003B6E000000006666666666663B003B6E0000;
- defparam character_rom_hi.INIT_13 = 256'h0000000000000000003E001C36361C000000000000000000007E007C36363C00;
- defparam character_rom_hi.INIT_14 = 256'h0000000000030303037F000000000000000000003E636303060C0C000C0C0000;
- defparam character_rom_hi.INIT_15 = 256'h0000F83060C973060C183363430303000000000000606060607F000000000000;
- defparam character_rom_hi.INIT_16 = 256'h00000000183C3C3C18181800181800000000F060FC5973660C18336343030300;
- defparam character_rom_hi.INIT_17 = 256'h0000000000003366CC66330000000000000000000000CC663366CC0000000000;
- defparam character_rom_hi.INIT_18 = 256'h55AA55AA55AA55AA55AA55AA55AA55AA22882288228822882288228822882288;
- defparam character_rom_hi.INIT_19 = 256'h18181818181818181818181818181818EEBBEEBBEEBBEEBBEEBBEEBBEEBBEEBB;
- defparam character_rom_hi.INIT_1A = 256'h18181818181818181F181F181818181818181818181818181F18181818181818;
- defparam character_rom_hi.INIT_1B = 256'h6C6C6C6C6C6C6C6C7F000000000000006C6C6C6C6C6C6C6C6F6C6C6C6C6C6C6C;
- defparam character_rom_hi.INIT_1C = 256'h6C6C6C6C6C6C6C6C6F606F6C6C6C6C6C18181818181818181F181F0000000000;
- defparam character_rom_hi.INIT_1D = 256'h6C6C6C6C6C6C6C6C6F607F00000000006C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C;
- defparam character_rom_hi.INIT_1E = 256'h00000000000000007F6C6C6C6C6C6C6C00000000000000007F606F6C6C6C6C6C;
- defparam character_rom_hi.INIT_1F = 256'h18181818181818181F0000000000000000000000000000001F181F1818181818;
- defparam character_rom_hi.INIT_20 = 256'h0000000000000000FF181818181818180000000000000000F818181818181818;
- defparam character_rom_hi.INIT_21 = 256'h1818181818181818F8181818181818181818181818181818FF00000000000000;
- defparam character_rom_hi.INIT_22 = 256'h1818181818181818FF181818181818180000000000000000FF00000000000000;
- defparam character_rom_hi.INIT_23 = 256'h6C6C6C6C6C6C6C6CEC6C6C6C6C6C6C6C1818181818181818F818F81818181818;
- defparam character_rom_hi.INIT_24 = 256'h6C6C6C6C6C6C6C6CEC0CFC00000000000000000000000000FC0CEC6C6C6C6C6C;
- defparam character_rom_hi.INIT_25 = 256'h6C6C6C6C6C6C6C6CEF00FF00000000000000000000000000FF00EF6C6C6C6C6C;
- defparam character_rom_hi.INIT_26 = 256'h0000000000000000FF00FF00000000006C6C6C6C6C6C6C6CEC0CEC6C6C6C6C6C;
- defparam character_rom_hi.INIT_27 = 256'h0000000000000000FF00FF18181818186C6C6C6C6C6C6C6CEF00EF6C6C6C6C6C;
- defparam character_rom_hi.INIT_28 = 256'h1818181818181818FF00FF00000000000000000000000000FF6C6C6C6C6C6C6C;
- defparam character_rom_hi.INIT_29 = 256'h0000000000000000FC6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CFF00000000000000;
- defparam character_rom_hi.INIT_2A = 256'h1818181818181818F818F800000000000000000000000000F818F81818181818;
- defparam character_rom_hi.INIT_2B = 256'h6C6C6C6C6C6C6C6CFF6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CFC00000000000000;
- defparam character_rom_hi.INIT_2C = 256'h00000000000000001F181818181818181818181818181818FF18FF1818181818;
- defparam character_rom_hi.INIT_2D = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1818181818181818F800000000000000;
- defparam character_rom_hi.INIT_2E = 256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFFFFF00000000000000;
- defparam character_rom_hi.INIT_2F = 256'h000000000000000000FFFFFFFFFFFFFFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0;
- defparam character_rom_hi.INIT_30 = 256'h00000303033F63633F633F0000000000000000006E3B1B1B1B3B6E0000000000;
- defparam character_rom_hi.INIT_31 = 256'h000000003636363636367F0100000000000000000303030303030363637F0000;
- defparam character_rom_hi.INIT_32 = 256'h000000000E1B1B1B1B1B7E0000000000000000007F63060C180C06637F000000;
- defparam character_rom_hi.INIT_33 = 256'h000000001818181818183B6E000000000000000306063E666666666600000000;
- defparam character_rom_hi.INIT_34 = 256'h000000001C3663637F6363361C000000000000007E183C6666663C187E000000;
- defparam character_rom_hi.INIT_35 = 256'h000000003C666666667C30180C780000000000007736363636636363361C0000;
- defparam character_rom_hi.INIT_36 = 256'h0000000003067ECFDBF37E60C00000000000000000007EDBDBDB7E0000000000;
- defparam character_rom_hi.INIT_37 = 256'h0000000063636363636363633E00000000000000380C0606063E06060C380000;
- defparam character_rom_hi.INIT_38 = 256'h00000000FF000018187E18180000000000000000007F00007F00007F00000000;
- defparam character_rom_hi.INIT_39 = 256'h000000007E0030180C060C1830000000000000007E000C18306030180C000000;
- defparam character_rom_hi.INIT_3A = 256'h000000000E1B1B1B18181818181818181818181818181818181818D8D8700000;
- defparam character_rom_hi.INIT_3B = 256'h0000000000003B6E003B6E000000000000000000001818007E00181800000000;
- defparam character_rom_hi.INIT_3C = 256'h0000000000000018180000000000000000000000000000000000001C36361C00;
- defparam character_rom_hi.INIT_3D = 256'h00000000383C3636373030303030F00000000000000000180000000000000000;
- defparam character_rom_hi.INIT_3E = 256'h0000000000000000001F13060C190E0000000000000000000036363636361B00;
- defparam character_rom_hi.INIT_3F = 256'h0000000000000000000000000000000000000000003E3E3E3E3E3E3E00000000;
Index: trunk/fpga/src/dsp/dspattlo.init
===================================================================
--- trunk/fpga/src/dsp/dspattlo.init (revision 214)
+++ trunk/fpga/src/dsp/dspattlo.init (nonexistent)
@@ -1,64 +0,0 @@
- defparam display_att_lo.INIT_00 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_01 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_02 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_03 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_04 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_05 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_06 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_07 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_08 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_09 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_0A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_0B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_0C = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_0D = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_0E = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_0F = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_10 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_11 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_12 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_13 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_14 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_15 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_16 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_17 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_18 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_19 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_1A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_1B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_1C = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_1D = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_1E = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_1F = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_20 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_21 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_22 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_23 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_24 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_25 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_26 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_27 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_28 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_29 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_2A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_2B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_2C = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_2D = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_2E = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_2F = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_30 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_31 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_32 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_33 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_34 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_35 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_36 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_37 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_38 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_39 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_3A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
- defparam display_att_lo.INIT_3B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
- defparam display_att_lo.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_lo.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_lo.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- defparam display_att_lo.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/timing.v
===================================================================
--- trunk/fpga/src/dsp/timing.v (revision 214)
+++ trunk/fpga/src/dsp/timing.v (nonexistent)
@@ -1,98 +0,0 @@
-//
-// timing.v -- timing generator
-//
-
-
-module timing(clk, pixclk,
- txtrow, txtcol,
- chrrow, chrcol,
- blank, hsync, vsync, blink);
- input clk;
- output pixclk;
- output [4:0] txtrow;
- output [6:0] txtcol;
- output [3:0] chrrow;
- output [2:0] chrcol;
- output blank;
- output hsync;
- output vsync;
- output reg blink;
-
- reg pclk;
- reg [9:0] hcnt;
- reg hblank, hsynch;
- reg [9:0] vcnt;
- reg vblank, vsynch;
- reg [5:0] bcnt;
-
- always @(posedge clk) begin
- pclk <= ~pclk;
- end
-
- assign pixclk = pclk;
-
- always @(posedge clk) begin
- if (pclk == 1) begin
- if (hcnt == 10'd799) begin
- hcnt <= 10'd0;
- hblank <= 1;
- end else begin
- hcnt <= hcnt + 1;
- end
- if (hcnt == 10'd639) begin
- hblank <= 0;
- end
- if (hcnt == 10'd655) begin
- hsynch <= 0;
- end
- if (hcnt == 10'd751) begin
- hsynch <= 1;
- end
- end
- end
-
- always @(posedge clk) begin
- if (pclk == 1 && hcnt == 10'd799) begin
- if (vcnt == 10'd524) begin
- vcnt <= 10'd0;
- vblank <= 1;
- end else begin
- vcnt <= vcnt + 1;
- end
- if (vcnt == 10'd479) begin
- vblank <= 0;
- end
- if (vcnt == 10'd489) begin
- vsynch <= 0;
- end
- if (vcnt == 10'd491) begin
- vsynch <= 1;
- end
- end
- end
-
- always @(posedge clk) begin
- if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin
- if (bcnt == 6'd59) begin
- bcnt <= 6'd0;
- blink <= 1;
- end else begin
- bcnt <= bcnt + 1;
- end
- if (bcnt == 6'd29) begin
- blink <= 0;
- end
- end
- end
-
- assign blank = hblank & vblank;
-
- assign hsync = hsynch;
- assign vsync = vsynch;
-
- assign txtrow[4:0] = vcnt[8:4];
- assign txtcol[6:0] = hcnt[9:3];
- assign chrrow[3:0] = vcnt[3:0];
- assign chrcol[2:0] = hcnt[2:0];
-
-endmodule
Index: trunk/fpga/src/dsp/bpp3/pixel.v
===================================================================
--- trunk/fpga/src/dsp/bpp3/pixel.v (nonexistent)
+++ trunk/fpga/src/dsp/bpp3/pixel.v (revision 215)
@@ -0,0 +1,62 @@
+//
+// pixel.v -- last stage in display pipeline
+//
+
+
+module pixel(clk, pixclk, attcode,
+ pixel, blank, hsync_in, vsync_in, blink,
+ hsync, vsync, r, g, b);
+ input clk;
+ input pixclk;
+ input [7:0] attcode;
+ input pixel;
+ input blank;
+ input hsync_in;
+ input vsync_in;
+ input blink;
+ output reg hsync;
+ output reg vsync;
+ output reg r;
+ output reg g;
+ output reg b;
+
+ wire blink_bit;
+ wire bg_red;
+ wire bg_green;
+ wire bg_blue;
+ wire invrs_bit;
+ wire fg_red;
+ wire fg_green;
+ wire fg_blue;
+ wire foreground;
+ wire red;
+ wire green;
+ wire blue;
+
+ assign blink_bit = attcode[7];
+ assign bg_red = attcode[6];
+ assign bg_green = attcode[5];
+ assign bg_blue = attcode[4];
+ assign invrs_bit = attcode[3];
+ assign fg_red = attcode[2];
+ assign fg_green = attcode[1];
+ assign fg_blue = attcode[0];
+
+ assign foreground =
+ (pixel & ~(blink_bit & blink)) ^ invrs_bit;
+
+ assign red = (foreground ? fg_red : bg_red);
+ assign green = (foreground ? fg_green : bg_green);
+ assign blue = (foreground ? fg_blue : bg_blue);
+
+ always @(posedge clk) begin
+ if (pixclk == 1) begin
+ hsync <= hsync_in;
+ vsync <= vsync_in;
+ r <= blank & red;
+ g <= blank & green;
+ b <= blank & blue;
+ end
+ end
+
+endmodule
Index: trunk/fpga/src/dsp/bpp3/display.v
===================================================================
--- trunk/fpga/src/dsp/bpp3/display.v (nonexistent)
+++ trunk/fpga/src/dsp/bpp3/display.v (revision 215)
@@ -0,0 +1,122 @@
+//
+// display.v -- 30x80 character display, with attributes
+//
+
+
+module display(clk,
+ dsp_row, dsp_col, dsp_en, dsp_wr,
+ dsp_wr_data, dsp_rd_data,
+ hsync, vsync, r, g, b);
+ input clk;
+ input [4:0] dsp_row;
+ input [6:0] dsp_col;
+ input dsp_en;
+ input dsp_wr;
+ input [15:0] dsp_wr_data;
+ output [15:0] dsp_rd_data;
+ output hsync;
+ output vsync;
+ output r;
+ output g;
+ output b;
+
+ wire pixclk;
+ wire [4:0] timing_txtrow;
+ wire [6:0] timing_txtcol;
+ wire [3:0] timing_chrrow;
+ wire [2:0] timing_chrcol;
+ wire timing_blank;
+ wire timing_hsync;
+ wire timing_vsync;
+ wire timing_blink;
+ wire [7:0] dspmem_attcode;
+ wire [7:0] dspmem_chrcode;
+ wire [3:0] dspmem_chrrow;
+ wire [2:0] dspmem_chrcol;
+ wire dspmem_blank;
+ wire dspmem_hsync;
+ wire dspmem_vsync;
+ wire dspmem_blink;
+ wire [7:0] chrgen_attcode;
+ wire chrgen_pixel;
+ wire chrgen_blank;
+ wire chrgen_hsync;
+ wire chrgen_vsync;
+ wire chrgen_blink;
+
+ timing timing1(
+ .clk(clk),
+ .pixclk(pixclk),
+ .txtrow(timing_txtrow[4:0]),
+ .txtcol(timing_txtcol[6:0]),
+ .chrrow(timing_chrrow[3:0]),
+ .chrcol(timing_chrcol[2:0]),
+ .blank(timing_blank),
+ .hsync(timing_hsync),
+ .vsync(timing_vsync),
+ .blink(timing_blink)
+ );
+
+ dspmem dspmem1(
+ .rdwr_row(dsp_row[4:0]),
+ .rdwr_col(dsp_col[6:0]),
+ .wr_data(dsp_wr_data[15:0]),
+ .rd_data(dsp_rd_data[15:0]),
+ .en(dsp_en),
+ .wr(dsp_wr),
+ .clk(clk),
+ .pixclk(pixclk),
+ .txtrow(timing_txtrow[4:0]),
+ .txtcol(timing_txtcol[6:0]),
+ .attcode(dspmem_attcode[7:0]),
+ .chrcode(dspmem_chrcode[7:0]),
+ .chrrow_in(timing_chrrow[3:0]),
+ .chrcol_in(timing_chrcol[2:0]),
+ .blank_in(timing_blank),
+ .hsync_in(timing_hsync),
+ .vsync_in(timing_vsync),
+ .blink_in(timing_blink),
+ .chrrow_out(dspmem_chrrow[3:0]),
+ .chrcol_out(dspmem_chrcol[2:0]),
+ .blank_out(dspmem_blank),
+ .hsync_out(dspmem_hsync),
+ .vsync_out(dspmem_vsync),
+ .blink_out(dspmem_blink)
+ );
+
+ chrgen chrgen1(
+ .clk(clk),
+ .pixclk(pixclk),
+ .chrcode(dspmem_chrcode[7:0]),
+ .chrrow(dspmem_chrrow[3:0]),
+ .chrcol(dspmem_chrcol[2:0]),
+ .pixel(chrgen_pixel),
+ .attcode_in(dspmem_attcode[7:0]),
+ .blank_in(dspmem_blank),
+ .hsync_in(dspmem_hsync),
+ .vsync_in(dspmem_vsync),
+ .blink_in(dspmem_blink),
+ .attcode_out(chrgen_attcode[7:0]),
+ .blank_out(chrgen_blank),
+ .hsync_out(chrgen_hsync),
+ .vsync_out(chrgen_vsync),
+ .blink_out(chrgen_blink)
+ );
+
+ pixel pixel1(
+ .clk(clk),
+ .pixclk(pixclk),
+ .attcode(chrgen_attcode[7:0]),
+ .pixel(chrgen_pixel),
+ .blank(chrgen_blank),
+ .hsync_in(chrgen_hsync),
+ .vsync_in(chrgen_vsync),
+ .blink(chrgen_blink),
+ .hsync(hsync),
+ .vsync(vsync),
+ .r(r),
+ .g(g),
+ .b(b)
+ );
+
+endmodule
Index: trunk/fpga/src/dsp/bpp3/dsp.v
===================================================================
--- trunk/fpga/src/dsp/bpp3/dsp.v (nonexistent)
+++ trunk/fpga/src/dsp/bpp3/dsp.v (revision 215)
@@ -0,0 +1,65 @@
+//
+// dsp.v -- character display interface
+//
+
+
+module dsp(clk, reset,
+ addr, en, wr, wt,
+ data_in, data_out,
+ hsync, vsync,
+ r, g, b);
+ // internal interface
+ input clk;
+ input reset;
+ input [13:2] addr;
+ input en;
+ input wr;
+ output wt;
+ input [15:0] data_in;
+ output [15:0] data_out;
+ // external interface
+ output hsync;
+ output vsync;
+ output r;
+ output g;
+ output b;
+
+ reg state;
+
+ display display1(
+ .clk(clk),
+ .dsp_row(addr[13:9]),
+ .dsp_col(addr[8:2]),
+ .dsp_en(en),
+ .dsp_wr(wr),
+ .dsp_wr_data(data_in[15:0]),
+ .dsp_rd_data(data_out[15:0]),
+ .hsync(hsync),
+ .vsync(vsync),
+ .r(r),
+ .g(g),
+ .b(b)
+ );
+
+ always @(posedge clk) begin
+ if (reset == 1) begin
+ state <= 1'b0;
+ end else begin
+ case (state)
+ 1'b0:
+ begin
+ if (en == 1 && wr == 0) begin
+ state <= 1'b1;
+ end
+ end
+ 1'b1:
+ begin
+ state <= 1'b0;
+ end
+ endcase
+ end
+ end
+
+ assign wt = (en == 1 && wr == 0 && state == 1'b0) ? 1 : 0;
+
+endmodule
Index: trunk/fpga/src/dsp/common/dspchrlo.init
===================================================================
--- trunk/fpga/src/dsp/common/dspchrlo.init (nonexistent)
+++ trunk/fpga/src/dsp/common/dspchrlo.init (revision 215)
@@ -0,0 +1,64 @@
+ defparam display_chr_lo.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_0C = 256'h09010C000309040002050403010201080300050C000D09030000000000000000;
+ defparam display_chr_lo.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_14 = 256'h0302050403010201080300000800080003050E090C0000030000000000000000;
+ defparam display_chr_lo.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_22 = 256'h0000000000000009040903020506090E05000000000000000000000000000000;
+ defparam display_chr_lo.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_26 = 256'h0000000000000000000000060F00000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_2A = 256'h000000000305030E05090303000405090C000001000000000000000000000000;
+ defparam display_chr_lo.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_2E = 256'h000000000000000000E050303050907000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_lo.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/common/dspatthi.init
===================================================================
--- trunk/fpga/src/dsp/common/dspatthi.init (nonexistent)
+++ trunk/fpga/src/dsp/common/dspatthi.init (revision 215)
@@ -0,0 +1,64 @@
+ defparam display_att_hi.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_hi.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/common/chrgenlo.init
===================================================================
--- trunk/fpga/src/dsp/common/chrgenlo.init (nonexistent)
+++ trunk/fpga/src/dsp/common/chrgenlo.init (revision 215)
@@ -0,0 +1,64 @@
+ defparam character_rom_lo.INIT_00 = 256'h000000007E818199BD8181A5817E000000000000000000000000000000000000;
+ defparam character_rom_lo.INIT_01 = 256'h00000000081C3E7F7F7F7F3600000000000000007EFFFFE7C3FFFFDBFF7E0000;
+ defparam character_rom_lo.INIT_02 = 256'h000000003C1899E7E7E73C3C180000000000000000081C3E7F3E1C0800000000;
+ defparam character_rom_lo.INIT_03 = 256'h000000000000183C3C18000000000000000000003C18187EFFFF7E3C18000000;
+ defparam character_rom_lo.INIT_04 = 256'h00000000003C664242663C0000000000FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF;
+ defparam character_rom_lo.INIT_05 = 256'h000000001E333333331E4C5870780000FFFFFFFFFFC399BDBD99C3FFFFFFFFFF;
+ defparam character_rom_lo.INIT_06 = 256'h00000000070F0E0C0C0C0CFCCCFC00000000000018187E183C666666663C0000;
+ defparam character_rom_lo.INIT_07 = 256'h000000001818DB3CE73CDB18180000000000000367E7E6C6C6C6C6FEC6FE0000;
+ defparam character_rom_lo.INIT_08 = 256'h00000000406070787C7F7C7870604000000000000103070F1F7F1F0F07030100;
+ defparam character_rom_lo.INIT_09 = 256'h0000000066660066666666666666000000000000183C7E181818187E3C180000;
+ defparam character_rom_lo.INIT_0A = 256'h0000003E63301C366363361C06633E0000000000D8D8D8D8D8DEDBDBDBFE0000;
+ defparam character_rom_lo.INIT_0B = 256'h0000007E183C7E181818187E3C180000000000007F7F7F7F0000000000000000;
+ defparam character_rom_lo.INIT_0C = 256'h00000000183C7E18181818181818000000000000181818181818187E3C180000;
+ defparam character_rom_lo.INIT_0D = 256'h0000000000000C067F060C000000000000000000000018307F30180000000000;
+ defparam character_rom_lo.INIT_0E = 256'h00000000000014367F361400000000000000000000007F030303030000000000;
+ defparam character_rom_lo.INIT_0F = 256'h0000000000081C1C3E3E7F7F0000000000000000007F7F3E3E1C1C0800000000;
+ defparam character_rom_lo.INIT_10 = 256'h000000001818001818183C3C3C18000000000000000000000000000000000000;
+ defparam character_rom_lo.INIT_11 = 256'h0000000036367F3636367F363600000000000000000000000000002466666600;
+ defparam character_rom_lo.INIT_12 = 256'h000000006163060C183063430000000000000018183E6361603E0343633E1818;
+ defparam character_rom_lo.INIT_13 = 256'h0000000000000000000000060C0C0C00000000006E3333333B6E1C36361C0000;
+ defparam character_rom_lo.INIT_14 = 256'h000000000C18303030303030180C00000000000030180C0C0C0C0C0C18300000;
+ defparam character_rom_lo.INIT_15 = 256'h00000000000018187E18180000000000000000000000663CFF3C660000000000;
+ defparam character_rom_lo.INIT_16 = 256'h00000000000000007F000000000000000000000C181818000000000000000000;
+ defparam character_rom_lo.INIT_17 = 256'h000000000103060C183060400000000000000000181800000000000000000000;
+ defparam character_rom_lo.INIT_18 = 256'h000000007E1818181818181E1C180000000000003E6363676B6B7363633E0000;
+ defparam character_rom_lo.INIT_19 = 256'h000000003E636060603C6060633E0000000000007F6303060C183060633E0000;
+ defparam character_rom_lo.INIT_1A = 256'h000000003E636060703F0303037F000000000000783030307F33363C38300000;
+ defparam character_rom_lo.INIT_1B = 256'h000000000C0C0C0C18306060637F0000000000003E636363633F0303061C0000;
+ defparam character_rom_lo.INIT_1C = 256'h000000001E306060607E6363633E0000000000003E636363633E6363633E0000;
+ defparam character_rom_lo.INIT_1D = 256'h000000000C181800000018180000000000000000001818000000181800000000;
+ defparam character_rom_lo.INIT_1E = 256'h0000000000007F00007F000000000000000000006030180C060C183060000000;
+ defparam character_rom_lo.INIT_1F = 256'h000000001818001818183063633E000000000000060C18306030180C06000000;
+ defparam character_rom_lo.INIT_20 = 256'h00000000636363637F6363361C080000000000003E033B7B7B7B63633E000000;
+ defparam character_rom_lo.INIT_21 = 256'h000000003C66430303030343663C0000000000003F666666663E6666663F0000;
+ defparam character_rom_lo.INIT_22 = 256'h000000007F664606161E1646667F0000000000001F36666666666666361F0000;
+ defparam character_rom_lo.INIT_23 = 256'h000000005C6663637B030343663C0000000000000F060606161E1646667F0000;
+ defparam character_rom_lo.INIT_24 = 256'h000000003C18181818181818183C00000000000063636363637F636363630000;
+ defparam character_rom_lo.INIT_25 = 256'h00000000676666361E1E363666670000000000001E3333333030303030780000;
+ defparam character_rom_lo.INIT_26 = 256'h0000000063636363636B7F7F77630000000000007F66460606060606060F0000;
+ defparam character_rom_lo.INIT_27 = 256'h000000001C36636363636363361C00000000000063636363737B7F6F67630000;
+ defparam character_rom_lo.INIT_28 = 256'h000070303E7B6B6363636363633E0000000000000F060606063E6666663F0000;
+ defparam character_rom_lo.INIT_29 = 256'h000000003E636360301C0663633E00000000000067666666363E6666663F0000;
+ defparam character_rom_lo.INIT_2A = 256'h000000003E6363636363636363630000000000003C1818181818185A7E7E0000;
+ defparam character_rom_lo.INIT_2B = 256'h0000000036367F6B6B6363636363000000000000081C36636363636363630000;
+ defparam character_rom_lo.INIT_2C = 256'h000000003C181818183C66666666000000000000636336361C1C363663630000;
+ defparam character_rom_lo.INIT_2D = 256'h000000003C0C0C0C0C0C0C0C0C3C0000000000007F6343060C183061637F0000;
+ defparam character_rom_lo.INIT_2E = 256'h000000003C30303030303030303C000000000000406070381C0E070301000000;
+ defparam character_rom_lo.INIT_2F = 256'h0000FF0000000000000000000000000000000000000000000000000063361C08;
+ defparam character_rom_lo.INIT_30 = 256'h000000006E3333333E301E000000000000000000000000000000000000180C0C;
+ defparam character_rom_lo.INIT_31 = 256'h000000003E63030303633E0000000000000000003B66666666361E0606070000;
+ defparam character_rom_lo.INIT_32 = 256'h000000003E6303037F633E0000000000000000006E33333333363C3030380000;
+ defparam character_rom_lo.INIT_33 = 256'h001E33303E33333333336E0000000000000000000F060606060F0626361C0000;
+ defparam character_rom_lo.INIT_34 = 256'h000000003C18181818181C00181800000000000067666666666E360606070000;
+ defparam character_rom_lo.INIT_35 = 256'h000000006766361E1E36660606070000003C6666606060606060700060600000;
+ defparam character_rom_lo.INIT_36 = 256'h000000006B6B6B6B6B7F370000000000000000003C18181818181818181C0000;
+ defparam character_rom_lo.INIT_37 = 256'h000000003E63636363633E0000000000000000006666666666663B0000000000;
+ defparam character_rom_lo.INIT_38 = 256'h007830303E33333333336E0000000000000F06063E66666666663B0000000000;
+ defparam character_rom_lo.INIT_39 = 256'h000000003E63301C06633E0000000000000000000F060606466E3B0000000000;
+ defparam character_rom_lo.INIT_3A = 256'h000000006E333333333333000000000000000000386C0C0C0C0C3F0C0C080000;
+ defparam character_rom_lo.INIT_3B = 256'h00000000367F6B6B636363000000000000000000183C66666666660000000000;
+ defparam character_rom_lo.INIT_3C = 256'h001F30607E63636363636300000000000000000063361C1C1C36630000000000;
+ defparam character_rom_lo.INIT_3D = 256'h0000000070181818180E181818700000000000007F63060C18337F0000000000;
+ defparam character_rom_lo.INIT_3E = 256'h000000000E18181818701818180E000000000000181818181800181818180000;
+ defparam character_rom_lo.INIT_3F = 256'h00000000007F636363361C08000000000000000000000000000000003B6E0000;
Index: trunk/fpga/src/dsp/common/dspchrhi.init
===================================================================
--- trunk/fpga/src/dsp/common/dspchrhi.init (nonexistent)
+++ trunk/fpga/src/dsp/common/dspchrhi.init (revision 215)
@@ -0,0 +1,64 @@
+ defparam display_chr_hi.INIT_00 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_01 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_02 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_03 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_04 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_05 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_06 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_07 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_08 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_09 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_0A = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_0B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_0C = 256'h2726262727262422272627262627262624222626272626252222222222222222;
+ defparam display_chr_hi.INIT_0D = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_0E = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_0F = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_10 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_11 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_12 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_13 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_14 = 256'h2727262726262726262422232322272227262626242223232222222222222222;
+ defparam display_chr_hi.INIT_15 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_16 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_17 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_18 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_19 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_1A = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_1B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_1C = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_1D = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_1E = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_1F = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_20 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_21 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_22 = 256'h2222222222222227272627272627262625222222222222222222222222222222;
+ defparam display_chr_hi.INIT_23 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_24 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_25 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_26 = 256'h2222222222222222222222262622222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_27 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_28 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_29 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_2A = 256'h2222222227262626262626252226262626272724222222222222222222222222;
+ defparam display_chr_hi.INIT_2B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_2C = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_2D = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_2E = 256'h2222222222222222226262727262624222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_2F = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_30 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_31 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_32 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_33 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_34 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_35 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_36 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_37 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_38 = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_39 = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_3A = 256'h2222222222222222222222222222222222222222222222222222222222222222;
+ defparam display_chr_hi.INIT_3B = 256'h0000000000000000000000000000000000000000000000002222222222222222;
+ defparam display_chr_hi.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_hi.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_hi.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_chr_hi.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/common/chrgenhi.init
===================================================================
--- trunk/fpga/src/dsp/common/chrgenhi.init (nonexistent)
+++ trunk/fpga/src/dsp/common/chrgenhi.init (revision 215)
@@ -0,0 +1,64 @@
+ defparam character_rom_hi.INIT_00 = 256'h000000006E333333333333003333000000003E60303C664303030343663C0000;
+ defparam character_rom_hi.INIT_01 = 256'h000000006E3333333E301E00361C0800000000003E6303037F633E000C183000;
+ defparam character_rom_hi.INIT_02 = 256'h000000006E3333333E301E00180C0600000000006E3333333E301E0033330000;
+ defparam character_rom_hi.INIT_03 = 256'h0000003C60303C660606663C00000000000000006E3333333E301E001C361C00;
+ defparam character_rom_hi.INIT_04 = 256'h000000003E6303037F633E0063630000000000003E6303037F633E00361C0800;
+ defparam character_rom_hi.INIT_05 = 256'h000000003C18181818181C0066660000000000003E6303037F633E00180C0600;
+ defparam character_rom_hi.INIT_06 = 256'h000000003C18181818181C00180C0600000000003C18181818181C00663C1800;
+ defparam character_rom_hi.INIT_07 = 256'h000000006363637F6363361C001C361C000000006363637F6363361C08636300;
+ defparam character_rom_hi.INIT_08 = 256'h00000000761B1B7E6C6E330000000000000000007F6606063E06667F00060C18;
+ defparam character_rom_hi.INIT_09 = 256'h000000003E63636363633E00361C08000000000073333333337F3333367C0000;
+ defparam character_rom_hi.INIT_0A = 256'h000000003E63636363633E00180C0600000000003E63636363633E0063630000;
+ defparam character_rom_hi.INIT_0B = 256'h000000006E33333333333300180C0600000000006E33333333333300331E0C00;
+ defparam character_rom_hi.INIT_0C = 256'h000000001C3663636363361C00636300001E30607E6363636363630063630000;
+ defparam character_rom_hi.INIT_0D = 256'h0000000018183C66060606663C181800000000003E6363636363636300636300;
+ defparam character_rom_hi.INIT_0E = 256'h000000001818187E187E183C66660000000000003F67060606060F0626361C00;
+ defparam character_rom_hi.INIT_0F = 256'h00000E1B18181818187E181818D8700000000000633333337B33231F33331F00;
+ defparam character_rom_hi.INIT_10 = 256'h000000003C18181818181C000C183000000000006E3333333E301E00060C1800;
+ defparam character_rom_hi.INIT_11 = 256'h000000006E33333333333300060C1800000000003E63636363633E00060C1800;
+ defparam character_rom_hi.INIT_12 = 256'h00000000636363737B7F6F6763003B6E000000006666666666663B003B6E0000;
+ defparam character_rom_hi.INIT_13 = 256'h0000000000000000003E001C36361C000000000000000000007E007C36363C00;
+ defparam character_rom_hi.INIT_14 = 256'h0000000000030303037F000000000000000000003E636303060C0C000C0C0000;
+ defparam character_rom_hi.INIT_15 = 256'h0000F83060C973060C183363430303000000000000606060607F000000000000;
+ defparam character_rom_hi.INIT_16 = 256'h00000000183C3C3C18181800181800000000F060FC5973660C18336343030300;
+ defparam character_rom_hi.INIT_17 = 256'h0000000000003366CC66330000000000000000000000CC663366CC0000000000;
+ defparam character_rom_hi.INIT_18 = 256'h55AA55AA55AA55AA55AA55AA55AA55AA22882288228822882288228822882288;
+ defparam character_rom_hi.INIT_19 = 256'h18181818181818181818181818181818EEBBEEBBEEBBEEBBEEBBEEBBEEBBEEBB;
+ defparam character_rom_hi.INIT_1A = 256'h18181818181818181F181F181818181818181818181818181F18181818181818;
+ defparam character_rom_hi.INIT_1B = 256'h6C6C6C6C6C6C6C6C7F000000000000006C6C6C6C6C6C6C6C6F6C6C6C6C6C6C6C;
+ defparam character_rom_hi.INIT_1C = 256'h6C6C6C6C6C6C6C6C6F606F6C6C6C6C6C18181818181818181F181F0000000000;
+ defparam character_rom_hi.INIT_1D = 256'h6C6C6C6C6C6C6C6C6F607F00000000006C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C;
+ defparam character_rom_hi.INIT_1E = 256'h00000000000000007F6C6C6C6C6C6C6C00000000000000007F606F6C6C6C6C6C;
+ defparam character_rom_hi.INIT_1F = 256'h18181818181818181F0000000000000000000000000000001F181F1818181818;
+ defparam character_rom_hi.INIT_20 = 256'h0000000000000000FF181818181818180000000000000000F818181818181818;
+ defparam character_rom_hi.INIT_21 = 256'h1818181818181818F8181818181818181818181818181818FF00000000000000;
+ defparam character_rom_hi.INIT_22 = 256'h1818181818181818FF181818181818180000000000000000FF00000000000000;
+ defparam character_rom_hi.INIT_23 = 256'h6C6C6C6C6C6C6C6CEC6C6C6C6C6C6C6C1818181818181818F818F81818181818;
+ defparam character_rom_hi.INIT_24 = 256'h6C6C6C6C6C6C6C6CEC0CFC00000000000000000000000000FC0CEC6C6C6C6C6C;
+ defparam character_rom_hi.INIT_25 = 256'h6C6C6C6C6C6C6C6CEF00FF00000000000000000000000000FF00EF6C6C6C6C6C;
+ defparam character_rom_hi.INIT_26 = 256'h0000000000000000FF00FF00000000006C6C6C6C6C6C6C6CEC0CEC6C6C6C6C6C;
+ defparam character_rom_hi.INIT_27 = 256'h0000000000000000FF00FF18181818186C6C6C6C6C6C6C6CEF00EF6C6C6C6C6C;
+ defparam character_rom_hi.INIT_28 = 256'h1818181818181818FF00FF00000000000000000000000000FF6C6C6C6C6C6C6C;
+ defparam character_rom_hi.INIT_29 = 256'h0000000000000000FC6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CFF00000000000000;
+ defparam character_rom_hi.INIT_2A = 256'h1818181818181818F818F800000000000000000000000000F818F81818181818;
+ defparam character_rom_hi.INIT_2B = 256'h6C6C6C6C6C6C6C6CFF6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CFC00000000000000;
+ defparam character_rom_hi.INIT_2C = 256'h00000000000000001F181818181818181818181818181818FF18FF1818181818;
+ defparam character_rom_hi.INIT_2D = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1818181818181818F800000000000000;
+ defparam character_rom_hi.INIT_2E = 256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFFFFF00000000000000;
+ defparam character_rom_hi.INIT_2F = 256'h000000000000000000FFFFFFFFFFFFFFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0;
+ defparam character_rom_hi.INIT_30 = 256'h00000303033F63633F633F0000000000000000006E3B1B1B1B3B6E0000000000;
+ defparam character_rom_hi.INIT_31 = 256'h000000003636363636367F0100000000000000000303030303030363637F0000;
+ defparam character_rom_hi.INIT_32 = 256'h000000000E1B1B1B1B1B7E0000000000000000007F63060C180C06637F000000;
+ defparam character_rom_hi.INIT_33 = 256'h000000001818181818183B6E000000000000000306063E666666666600000000;
+ defparam character_rom_hi.INIT_34 = 256'h000000001C3663637F6363361C000000000000007E183C6666663C187E000000;
+ defparam character_rom_hi.INIT_35 = 256'h000000003C666666667C30180C780000000000007736363636636363361C0000;
+ defparam character_rom_hi.INIT_36 = 256'h0000000003067ECFDBF37E60C00000000000000000007EDBDBDB7E0000000000;
+ defparam character_rom_hi.INIT_37 = 256'h0000000063636363636363633E00000000000000380C0606063E06060C380000;
+ defparam character_rom_hi.INIT_38 = 256'h00000000FF000018187E18180000000000000000007F00007F00007F00000000;
+ defparam character_rom_hi.INIT_39 = 256'h000000007E0030180C060C1830000000000000007E000C18306030180C000000;
+ defparam character_rom_hi.INIT_3A = 256'h000000000E1B1B1B18181818181818181818181818181818181818D8D8700000;
+ defparam character_rom_hi.INIT_3B = 256'h0000000000003B6E003B6E000000000000000000001818007E00181800000000;
+ defparam character_rom_hi.INIT_3C = 256'h0000000000000018180000000000000000000000000000000000001C36361C00;
+ defparam character_rom_hi.INIT_3D = 256'h00000000383C3636373030303030F00000000000000000180000000000000000;
+ defparam character_rom_hi.INIT_3E = 256'h0000000000000000001F13060C190E0000000000000000000036363636361B00;
+ defparam character_rom_hi.INIT_3F = 256'h0000000000000000000000000000000000000000003E3E3E3E3E3E3E00000000;
Index: trunk/fpga/src/dsp/common/dspmem.v
===================================================================
--- trunk/fpga/src/dsp/common/dspmem.v (nonexistent)
+++ trunk/fpga/src/dsp/common/dspmem.v (revision 215)
@@ -0,0 +1,175 @@
+//
+// dspmem.v -- display memory
+//
+
+
+module dspmem(rdwr_row, rdwr_col, wr_data, rd_data, en, wr,
+ clk, pixclk,
+ txtrow, txtcol, attcode, chrcode,
+ chrrow_in, chrcol_in, blank_in,
+ hsync_in, vsync_in, blink_in,
+ chrrow_out, chrcol_out, blank_out,
+ hsync_out, vsync_out, blink_out);
+ input [4:0] rdwr_row;
+ input [6:0] rdwr_col;
+ input [15:0] wr_data;
+ output [15:0] rd_data;
+ input en;
+ input wr;
+ input clk;
+ input pixclk;
+ input [4:0] txtrow;
+ input [6:0] txtcol;
+ output [7:0] attcode;
+ output [7:0] chrcode;
+ input [3:0] chrrow_in;
+ input [2:0] chrcol_in;
+ input blank_in;
+ input hsync_in;
+ input vsync_in;
+ input blink_in;
+ output reg [3:0] chrrow_out;
+ output reg [2:0] chrcol_out;
+ output reg blank_out;
+ output reg hsync_out;
+ output reg vsync_out;
+ output reg blink_out;
+
+ wire [11:0] rdwr_addr;
+ wire [3:0] rdwr_din_n3;
+ wire [3:0] rdwr_din_n2;
+ wire [3:0] rdwr_din_n1;
+ wire [3:0] rdwr_din_n0;
+ wire [3:0] rdwr_dout_n3;
+ wire [3:0] rdwr_dout_n2;
+ wire [3:0] rdwr_dout_n1;
+ wire [3:0] rdwr_dout_n0;
+
+ wire [11:0] rfsh_addr;
+ wire [3:0] rfsh_din_n3;
+ wire [3:0] rfsh_din_n2;
+ wire [3:0] rfsh_din_n1;
+ wire [3:0] rfsh_din_n0;
+ wire [3:0] rfsh_dout_n3;
+ wire [3:0] rfsh_dout_n2;
+ wire [3:0] rfsh_dout_n1;
+ wire [3:0] rfsh_dout_n0;
+
+ assign rdwr_addr[11:7] = rdwr_row[4:0];
+ assign rdwr_addr[6:0] = rdwr_col[6:0];
+ assign rdwr_din_n3 = wr_data[15:12];
+ assign rdwr_din_n2 = wr_data[11: 8];
+ assign rdwr_din_n1 = wr_data[ 7: 4];
+ assign rdwr_din_n0 = wr_data[ 3: 0];
+ assign rd_data[15:12] = rdwr_dout_n3;
+ assign rd_data[11: 8] = rdwr_dout_n2;
+ assign rd_data[ 7: 4] = rdwr_dout_n1;
+ assign rd_data[ 3: 0] = rdwr_dout_n0;
+
+ assign rfsh_addr[11:7] = txtrow[4:0];
+ assign rfsh_addr[6:0] = txtcol[6:0];
+ assign rfsh_din_n3 = 4'b0000;
+ assign rfsh_din_n2 = 4'b0000;
+ assign rfsh_din_n1 = 4'b0000;
+ assign rfsh_din_n0 = 4'b0000;
+ assign attcode[7:4] = rfsh_dout_n3;
+ assign attcode[3:0] = rfsh_dout_n2;
+ assign chrcode[7:4] = rfsh_dout_n1;
+ assign chrcode[3:0] = rfsh_dout_n0;
+
+ // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
+
+ RAMB16_S4_S4 display_att_hi (
+ .DOA(rdwr_dout_n3), // Port A 4-bit Data Output
+ .DOB(rfsh_dout_n3), // Port B 4-bit Data Output
+ .ADDRA(rdwr_addr), // Port A 12-bit Address Input
+ .ADDRB(rfsh_addr), // Port B 12-bit Address Input
+ .CLKA(clk), // Port A Clock
+ .CLKB(clk), // Port B Clock
+ .DIA(rdwr_din_n3), // Port A 4-bit Data Input
+ .DIB(rfsh_din_n3), // Port B 4-bit Data Input
+ .ENA(en), // Port A RAM Enable Input
+ .ENB(pixclk), // Port B RAM Enable Input
+ .SSRA(1'b0), // Port A Synchronous Set/Reset Input
+ .SSRB(1'b0), // Port B Synchronous Set/Reset Input
+ .WEA(wr), // Port A Write Enable Input
+ .WEB(1'b0) // Port B Write Enable Input
+ );
+
+ `include "dspatthi.init"
+
+ // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
+
+ RAMB16_S4_S4 display_att_lo (
+ .DOA(rdwr_dout_n2), // Port A 4-bit Data Output
+ .DOB(rfsh_dout_n2), // Port B 4-bit Data Output
+ .ADDRA(rdwr_addr), // Port A 12-bit Address Input
+ .ADDRB(rfsh_addr), // Port B 12-bit Address Input
+ .CLKA(clk), // Port A Clock
+ .CLKB(clk), // Port B Clock
+ .DIA(rdwr_din_n2), // Port A 4-bit Data Input
+ .DIB(rfsh_din_n2), // Port B 4-bit Data Input
+ .ENA(en), // Port A RAM Enable Input
+ .ENB(pixclk), // Port B RAM Enable Input
+ .SSRA(1'b0), // Port A Synchronous Set/Reset Input
+ .SSRB(1'b0), // Port B Synchronous Set/Reset Input
+ .WEA(wr), // Port A Write Enable Input
+ .WEB(1'b0) // Port B Write Enable Input
+ );
+
+ `include "dspattlo.init"
+
+ // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
+
+ RAMB16_S4_S4 display_chr_hi (
+ .DOA(rdwr_dout_n1), // Port A 4-bit Data Output
+ .DOB(rfsh_dout_n1), // Port B 4-bit Data Output
+ .ADDRA(rdwr_addr), // Port A 12-bit Address Input
+ .ADDRB(rfsh_addr), // Port B 12-bit Address Input
+ .CLKA(clk), // Port A Clock
+ .CLKB(clk), // Port B Clock
+ .DIA(rdwr_din_n1), // Port A 4-bit Data Input
+ .DIB(rfsh_din_n1), // Port B 4-bit Data Input
+ .ENA(en), // Port A RAM Enable Input
+ .ENB(pixclk), // Port B RAM Enable Input
+ .SSRA(1'b0), // Port A Synchronous Set/Reset Input
+ .SSRB(1'b0), // Port B Synchronous Set/Reset Input
+ .WEA(wr), // Port A Write Enable Input
+ .WEB(1'b0) // Port B Write Enable Input
+ );
+
+ `include "dspchrhi.init"
+
+ // RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
+
+ RAMB16_S4_S4 display_chr_lo (
+ .DOA(rdwr_dout_n0), // Port A 4-bit Data Output
+ .DOB(rfsh_dout_n0), // Port B 4-bit Data Output
+ .ADDRA(rdwr_addr), // Port A 12-bit Address Input
+ .ADDRB(rfsh_addr), // Port B 12-bit Address Input
+ .CLKA(clk), // Port A Clock
+ .CLKB(clk), // Port B Clock
+ .DIA(rdwr_din_n0), // Port A 4-bit Data Input
+ .DIB(rfsh_din_n0), // Port B 4-bit Data Input
+ .ENA(en), // Port A RAM Enable Input
+ .ENB(pixclk), // Port B RAM Enable Input
+ .SSRA(1'b0), // Port A Synchronous Set/Reset Input
+ .SSRB(1'b0), // Port B Synchronous Set/Reset Input
+ .WEA(wr), // Port A Write Enable Input
+ .WEB(1'b0) // Port B Write Enable Input
+ );
+
+ `include "dspchrlo.init"
+
+ always @(posedge clk) begin
+ if (pixclk == 1) begin
+ chrrow_out <= chrrow_in;
+ chrcol_out <= chrcol_in;
+ blank_out <= blank_in;
+ hsync_out <= hsync_in;
+ vsync_out <= vsync_in;
+ blink_out <= blink_in;
+ end
+ end
+
+endmodule
Index: trunk/fpga/src/dsp/common/chrgen.v
===================================================================
--- trunk/fpga/src/dsp/common/chrgen.v (nonexistent)
+++ trunk/fpga/src/dsp/common/chrgen.v (revision 215)
@@ -0,0 +1,79 @@
+//
+// chrgen.v -- character generator
+//
+
+
+module chrgen(clk, pixclk,
+ chrcode, chrrow, chrcol,
+ pixel,
+ attcode_in, blank_in, hsync_in, vsync_in, blink_in,
+ attcode_out, blank_out, hsync_out, vsync_out, blink_out);
+ input clk;
+ input pixclk;
+ input [7:0] chrcode;
+ input [3:0] chrrow;
+ input [2:0] chrcol;
+ output pixel;
+ input [7:0] attcode_in;
+ input blank_in;
+ input hsync_in;
+ input vsync_in;
+ input blink_in;
+ output reg [7:0] attcode_out;
+ output reg blank_out;
+ output reg hsync_out;
+ output reg vsync_out;
+ output reg blink_out;
+
+ wire [13:0] addr;
+ wire [0:0] pixel_lo;
+ wire [0:0] pixel_hi;
+
+ reg mux_ctrl;
+
+ assign addr[13:7] = chrcode[6:0];
+ assign addr[6:3] = chrrow[3:0];
+ assign addr[2:0] = chrcol[2:0];
+
+ assign pixel = (mux_ctrl == 0) ? pixel_lo[0] : pixel_hi[0];
+
+ // RAMB16_S1: Spartan-3 16kx1 Single-Port RAM
+
+ RAMB16_S1 character_rom_lo (
+ .DO(pixel_lo), // 1-bit Data Output
+ .ADDR(addr), // 14-bit Address Input
+ .CLK(clk), // Clock
+ .DI(1'b0), // 1-bit Data Input
+ .EN(pixclk), // RAM Enable Input
+ .SSR(1'b0), // Synchronous Set/Reset Input
+ .WE(1'b0) // Write Enable Input
+ );
+
+ `include "chrgenlo.init"
+
+ // RAMB16_S1: Spartan-3 16kx1 Single-Port RAM
+
+ RAMB16_S1 character_rom_hi (
+ .DO(pixel_hi), // 1-bit Data Output
+ .ADDR(addr), // 14-bit Address Input
+ .CLK(clk), // Clock
+ .DI(1'b0), // 1-bit Data Input
+ .EN(pixclk), // RAM Enable Input
+ .SSR(1'b0), // Synchronous Set/Reset Input
+ .WE(1'b0) // Write Enable Input
+ );
+
+ `include "chrgenhi.init"
+
+ always @(posedge clk) begin
+ if (pixclk == 1) begin
+ attcode_out[7:0] <= attcode_in[7:0];
+ blank_out <= blank_in;
+ hsync_out <= hsync_in;
+ vsync_out <= vsync_in;
+ blink_out <= blink_in;
+ mux_ctrl <= chrcode[7];
+ end
+ end
+
+endmodule
Index: trunk/fpga/src/dsp/common/timing.v
===================================================================
--- trunk/fpga/src/dsp/common/timing.v (nonexistent)
+++ trunk/fpga/src/dsp/common/timing.v (revision 215)
@@ -0,0 +1,98 @@
+//
+// timing.v -- timing generator
+//
+
+
+module timing(clk, pixclk,
+ txtrow, txtcol,
+ chrrow, chrcol,
+ blank, hsync, vsync, blink);
+ input clk;
+ output pixclk;
+ output [4:0] txtrow;
+ output [6:0] txtcol;
+ output [3:0] chrrow;
+ output [2:0] chrcol;
+ output blank;
+ output hsync;
+ output vsync;
+ output reg blink;
+
+ reg pclk;
+ reg [9:0] hcnt;
+ reg hblank, hsynch;
+ reg [9:0] vcnt;
+ reg vblank, vsynch;
+ reg [5:0] bcnt;
+
+ always @(posedge clk) begin
+ pclk <= ~pclk;
+ end
+
+ assign pixclk = pclk;
+
+ always @(posedge clk) begin
+ if (pclk == 1) begin
+ if (hcnt == 10'd799) begin
+ hcnt <= 10'd0;
+ hblank <= 1;
+ end else begin
+ hcnt <= hcnt + 1;
+ end
+ if (hcnt == 10'd639) begin
+ hblank <= 0;
+ end
+ if (hcnt == 10'd655) begin
+ hsynch <= 0;
+ end
+ if (hcnt == 10'd751) begin
+ hsynch <= 1;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ if (pclk == 1 && hcnt == 10'd799) begin
+ if (vcnt == 10'd524) begin
+ vcnt <= 10'd0;
+ vblank <= 1;
+ end else begin
+ vcnt <= vcnt + 1;
+ end
+ if (vcnt == 10'd479) begin
+ vblank <= 0;
+ end
+ if (vcnt == 10'd489) begin
+ vsynch <= 0;
+ end
+ if (vcnt == 10'd491) begin
+ vsynch <= 1;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin
+ if (bcnt == 6'd59) begin
+ bcnt <= 6'd0;
+ blink <= 1;
+ end else begin
+ bcnt <= bcnt + 1;
+ end
+ if (bcnt == 6'd29) begin
+ blink <= 0;
+ end
+ end
+ end
+
+ assign blank = hblank & vblank;
+
+ assign hsync = hsynch;
+ assign vsync = vsynch;
+
+ assign txtrow[4:0] = vcnt[8:4];
+ assign txtcol[6:0] = hcnt[9:3];
+ assign chrrow[3:0] = vcnt[3:0];
+ assign chrcol[2:0] = hcnt[2:0];
+
+endmodule
Index: trunk/fpga/src/dsp/common/dspattlo.init
===================================================================
--- trunk/fpga/src/dsp/common/dspattlo.init (nonexistent)
+++ trunk/fpga/src/dsp/common/dspattlo.init (revision 215)
@@ -0,0 +1,64 @@
+ defparam display_att_lo.INIT_00 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_01 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_02 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_03 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_04 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_05 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_06 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_07 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_08 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_09 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_0A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_0B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_0C = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_0D = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_0E = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_0F = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_10 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_11 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_12 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_13 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_14 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_15 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_16 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_17 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_18 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_19 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_1A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_1B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_1C = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_1D = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_1E = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_1F = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_20 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_21 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_22 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_23 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_24 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_25 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_26 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_27 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_28 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_29 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_2A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_2B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_2C = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_2D = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_2E = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_2F = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_30 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_31 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_32 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_33 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_34 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_35 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_36 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_37 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_38 = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_39 = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_3A = 256'h7777777777777777777777777777777777777777777777777777777777777777;
+ defparam display_att_lo.INIT_3B = 256'h0000000000000000000000000000000000000000000000007777777777777777;
+ defparam display_att_lo.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_lo.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_lo.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ defparam display_att_lo.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
Index: trunk/fpga/src/dsp/bpp9/pixel.v
===================================================================
--- trunk/fpga/src/dsp/bpp9/pixel.v (nonexistent)
+++ trunk/fpga/src/dsp/bpp9/pixel.v (revision 215)
@@ -0,0 +1,69 @@
+//
+// pixel.v -- last stage in display pipeline
+//
+
+
+module pixel(clk, pixclk, attcode,
+ pixel, blank, hsync_in, vsync_in, blink,
+ hsync, vsync, r, g, b);
+ input clk;
+ input pixclk;
+ input [7:0] attcode;
+ input pixel;
+ input blank;
+ input hsync_in;
+ input vsync_in;
+ input blink;
+ output reg hsync;
+ output reg vsync;
+ output reg [2:0] r;
+ output reg [2:0] g;
+ output reg [2:0] b;
+
+ wire blink_bit;
+ wire bg_red;
+ wire bg_green;
+ wire bg_blue;
+ wire inten_bit;
+ wire fg_red;
+ wire fg_green;
+ wire fg_blue;
+ wire foreground;
+ wire intensify;
+ wire red;
+ wire green;
+ wire blue;
+
+ assign blink_bit = attcode[7];
+ assign bg_red = attcode[6];
+ assign bg_green = attcode[5];
+ assign bg_blue = attcode[4];
+ assign inten_bit = attcode[3];
+ assign fg_red = attcode[2];
+ assign fg_green = attcode[1];
+ assign fg_blue = attcode[0];
+
+ assign foreground = pixel & ~(blink_bit & blink);
+ assign intensify = foreground & inten_bit;
+
+ assign red = (foreground ? fg_red : bg_red);
+ assign green = (foreground ? fg_green : bg_green);
+ assign blue = (foreground ? fg_blue : bg_blue);
+
+ always @(posedge clk) begin
+ if (pixclk == 1) begin
+ hsync <= hsync_in;
+ vsync <= vsync_in;
+ r[2] <= blank & red;
+ r[1] <= blank & intensify;
+ r[0] <= blank & red & intensify;
+ g[2] <= blank & green;
+ g[1] <= blank & intensify;
+ g[0] <= blank & green & intensify;
+ b[2] <= blank & blue;
+ b[1] <= blank & intensify;
+ b[0] <= blank & blue & intensify;
+ end
+ end
+
+endmodule
Index: trunk/fpga/src/dsp/bpp9/display.v
===================================================================
--- trunk/fpga/src/dsp/bpp9/display.v (nonexistent)
+++ trunk/fpga/src/dsp/bpp9/display.v (revision 215)
@@ -0,0 +1,122 @@
+//
+// display.v -- 30x80 character display, with attributes
+//
+
+
+module display(clk,
+ dsp_row, dsp_col, dsp_en, dsp_wr,
+ dsp_wr_data, dsp_rd_data,
+ hsync, vsync, r, g, b);
+ input clk;
+ input [4:0] dsp_row;
+ input [6:0] dsp_col;
+ input dsp_en;
+ input dsp_wr;
+ input [15:0] dsp_wr_data;
+ output [15:0] dsp_rd_data;
+ output hsync;
+ output vsync;
+ output [2:0] r;
+ output [2:0] g;
+ output [2:0] b;
+
+ wire pixclk;
+ wire [4:0] timing_txtrow;
+ wire [6:0] timing_txtcol;
+ wire [3:0] timing_chrrow;
+ wire [2:0] timing_chrcol;
+ wire timing_blank;
+ wire timing_hsync;
+ wire timing_vsync;
+ wire timing_blink;
+ wire [7:0] dspmem_attcode;
+ wire [7:0] dspmem_chrcode;
+ wire [3:0] dspmem_chrrow;
+ wire [2:0] dspmem_chrcol;
+ wire dspmem_blank;
+ wire dspmem_hsync;
+ wire dspmem_vsync;
+ wire dspmem_blink;
+ wire [7:0] chrgen_attcode;
+ wire chrgen_pixel;
+ wire chrgen_blank;
+ wire chrgen_hsync;
+ wire chrgen_vsync;
+ wire chrgen_blink;
+
+ timing timing1(
+ .clk(clk),
+ .pixclk(pixclk),
+ .txtrow(timing_txtrow[4:0]),
+ .txtcol(timing_txtcol[6:0]),
+ .chrrow(timing_chrrow[3:0]),
+ .chrcol(timing_chrcol[2:0]),
+ .blank(timing_blank),
+ .hsync(timing_hsync),
+ .vsync(timing_vsync),
+ .blink(timing_blink)
+ );
+
+ dspmem dspmem1(
+ .rdwr_row(dsp_row[4:0]),
+ .rdwr_col(dsp_col[6:0]),
+ .wr_data(dsp_wr_data[15:0]),
+ .rd_data(dsp_rd_data[15:0]),
+ .en(dsp_en),
+ .wr(dsp_wr),
+ .clk(clk),
+ .pixclk(pixclk),
+ .txtrow(timing_txtrow[4:0]),
+ .txtcol(timing_txtcol[6:0]),
+ .attcode(dspmem_attcode[7:0]),
+ .chrcode(dspmem_chrcode[7:0]),
+ .chrrow_in(timing_chrrow[3:0]),
+ .chrcol_in(timing_chrcol[2:0]),
+ .blank_in(timing_blank),
+ .hsync_in(timing_hsync),
+ .vsync_in(timing_vsync),
+ .blink_in(timing_blink),
+ .chrrow_out(dspmem_chrrow[3:0]),
+ .chrcol_out(dspmem_chrcol[2:0]),
+ .blank_out(dspmem_blank),
+ .hsync_out(dspmem_hsync),
+ .vsync_out(dspmem_vsync),
+ .blink_out(dspmem_blink)
+ );
+
+ chrgen chrgen1(
+ .clk(clk),
+ .pixclk(pixclk),
+ .chrcode(dspmem_chrcode[7:0]),
+ .chrrow(dspmem_chrrow[3:0]),
+ .chrcol(dspmem_chrcol[2:0]),
+ .pixel(chrgen_pixel),
+ .attcode_in(dspmem_attcode[7:0]),
+ .blank_in(dspmem_blank),
+ .hsync_in(dspmem_hsync),
+ .vsync_in(dspmem_vsync),
+ .blink_in(dspmem_blink),
+ .attcode_out(chrgen_attcode[7:0]),
+ .blank_out(chrgen_blank),
+ .hsync_out(chrgen_hsync),
+ .vsync_out(chrgen_vsync),
+ .blink_out(chrgen_blink)
+ );
+
+ pixel pixel1(
+ .clk(clk),
+ .pixclk(pixclk),
+ .attcode(chrgen_attcode[7:0]),
+ .pixel(chrgen_pixel),
+ .blank(chrgen_blank),
+ .hsync_in(chrgen_hsync),
+ .vsync_in(chrgen_vsync),
+ .blink(chrgen_blink),
+ .hsync(hsync),
+ .vsync(vsync),
+ .r(r[2:0]),
+ .g(g[2:0]),
+ .b(b[2:0])
+ );
+
+endmodule
Index: trunk/fpga/src/dsp/bpp9/dsp.v
===================================================================
--- trunk/fpga/src/dsp/bpp9/dsp.v (nonexistent)
+++ trunk/fpga/src/dsp/bpp9/dsp.v (revision 215)
@@ -0,0 +1,65 @@
+//
+// dsp.v -- character display interface
+//
+
+
+module dsp(clk, reset,
+ addr, en, wr, wt,
+ data_in, data_out,
+ hsync, vsync,
+ r, g, b);
+ // internal interface
+ input clk;
+ input reset;
+ input [13:2] addr;
+ input en;
+ input wr;
+ output wt;
+ input [15:0] data_in;
+ output [15:0] data_out;
+ // external interface
+ output hsync;
+ output vsync;
+ output [2:0] r;
+ output [2:0] g;
+ output [2:0] b;
+
+ reg state;
+
+ display display1(
+ .clk(clk),
+ .dsp_row(addr[13:9]),
+ .dsp_col(addr[8:2]),
+ .dsp_en(en),
+ .dsp_wr(wr),
+ .dsp_wr_data(data_in[15:0]),
+ .dsp_rd_data(data_out[15:0]),
+ .hsync(hsync),
+ .vsync(vsync),
+ .r(r[2:0]),
+ .g(g[2:0]),
+ .b(b[2:0])
+ );
+
+ always @(posedge clk) begin
+ if (reset == 1) begin
+ state <= 1'b0;
+ end else begin
+ case (state)
+ 1'b0:
+ begin
+ if (en == 1 && wr == 0) begin
+ state <= 1'b1;
+ end
+ end
+ 1'b1:
+ begin
+ state <= 1'b0;
+ end
+ endcase
+ end
+ end
+
+ assign wt = (en == 1 && wr == 0 && state == 1'b0) ? 1 : 0;
+
+endmodule
Index: trunk/fpga/boards/xsa-xst-3/eco32.bit
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/fpga/boards/xsa-xst-3/eco32.bit
===================================================================
--- trunk/fpga/boards/xsa-xst-3/eco32.bit (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/eco32.bit (revision 215)
trunk/fpga/boards/xsa-xst-3/eco32.bit
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/fpga/boards/xsa-xst-3/eco32.ucf
===================================================================
--- trunk/fpga/boards/xsa-xst-3/eco32.ucf (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/eco32.ucf (revision 215)
@@ -0,0 +1,176 @@
+#
+# eco32.ucf -- ECO32 user constraints for XSA-3S1000 + XST-3 board
+#
+
+#
+# clock and reset
+#
+NET "clk_in" PERIOD = 20.0ns HIGH 40%;
+NET "clk_in" LOC = "p8";
+NET "reset_inout_n" LOC = "d15";
+
+#
+# SDRAM
+#
+NET "sdram_a<0>" LOC = "b5";
+NET "sdram_a<1>" LOC = "a4";
+NET "sdram_a<2>" LOC = "b4";
+NET "sdram_a<3>" LOC = "e6";
+NET "sdram_a<4>" LOC = "e3";
+NET "sdram_a<5>" LOC = "c1";
+NET "sdram_a<6>" LOC = "e4";
+NET "sdram_a<7>" LOC = "d3";
+NET "sdram_a<8>" LOC = "c2";
+NET "sdram_a<9>" LOC = "a3";
+NET "sdram_a<10>" LOC = "b6";
+NET "sdram_a<11>" LOC = "c5";
+NET "sdram_a<12>" LOC = "c6";
+NET "sdram_ba<0>" LOC = "a7";
+NET "sdram_ba<1>" LOC = "c7";
+NET "sdram_cas_n" LOC = "a10";
+NET "sdram_cke" LOC = "d7";
+NET "sdram_clk" LOC = "e10";
+NET "sdram_cs_n" LOC = "b8";
+NET "sdram_dq<0>" LOC = "c15";
+NET "sdram_dq<1>" LOC = "d12";
+NET "sdram_dq<2>" LOC = "a14";
+NET "sdram_dq<3>" LOC = "b13";
+NET "sdram_dq<4>" LOC = "d11";
+NET "sdram_dq<5>" LOC = "a12";
+NET "sdram_dq<6>" LOC = "c11";
+NET "sdram_dq<7>" LOC = "d10";
+NET "sdram_dq<8>" LOC = "b11";
+NET "sdram_dq<9>" LOC = "b12";
+NET "sdram_dq<10>" LOC = "c12";
+NET "sdram_dq<11>" LOC = "b14";
+NET "sdram_dq<12>" LOC = "d14";
+NET "sdram_dq<13>" LOC = "c16";
+NET "sdram_dq<14>" LOC = "f12";
+NET "sdram_dq<15>" LOC = "f13";
+NET "sdram_fb" LOC = "n8";
+NET "sdram_ldqm" LOC = "c10";
+NET "sdram_ras_n" LOC = "a9";
+NET "sdram_udqm" LOC = "d9";
+NET "sdram_we_n" LOC = "b10";
+
+#
+# flash ROM
+#
+NET "flash_a<0>" LOC = "n5";
+NET "flash_a<1>" LOC = "k14";
+NET "flash_a<2>" LOC = "k13";
+NET "flash_a<3>" LOC = "k12";
+NET "flash_a<4>" LOC = "l14";
+NET "flash_a<5>" LOC = "m16";
+NET "flash_a<6>" LOC = "l13";
+NET "flash_a<7>" LOC = "n16";
+NET "flash_a<8>" LOC = "n14";
+NET "flash_a<9>" LOC = "p15";
+NET "flash_a<10>" LOC = "r16";
+NET "flash_a<11>" LOC = "p14";
+NET "flash_a<12>" LOC = "p13";
+NET "flash_a<13>" LOC = "n12";
+NET "flash_a<14>" LOC = "t14";
+NET "flash_a<15>" LOC = "r13";
+NET "flash_a<16>" LOC = "n10";
+NET "flash_a<17>" LOC = "m14";
+NET "flash_a<18>" LOC = "k3";
+NET "flash_a<19>" LOC = "k4";
+NET "flash_byte_n" LOC = "t8";
+NET "flash_ce_n" LOC = "r4";
+NET "flash_d<0>" LOC = "m11";
+NET "flash_d<1>" LOC = "n11";
+NET "flash_d<2>" LOC = "p10";
+NET "flash_d<3>" LOC = "r10";
+NET "flash_d<4>" LOC = "t7";
+NET "flash_d<5>" LOC = "r7";
+NET "flash_d<6>" LOC = "n6";
+NET "flash_d<7>" LOC = "m6";
+NET "flash_d<8>" LOC = "t4";
+NET "flash_d<9>" LOC = "r5";
+NET "flash_d<10>" LOC = "t5";
+NET "flash_d<11>" LOC = "p6";
+NET "flash_d<12>" LOC = "m7";
+NET "flash_d<13>" LOC = "r6";
+NET "flash_d<14>" LOC = "n7";
+NET "flash_d<15>" LOC = "p7";
+NET "flash_oe_n" LOC = "p5";
+NET "flash_rst_n" LOC = "p16";
+NET "flash_we_n" LOC = "m13";
+
+#
+# VGA display
+#
+NET "vga_hsync" LOC = "b7";
+NET "vga_vsync" LOC = "d8";
+NET "vga_r<0>" LOC = "c8";
+NET "vga_r<1>" LOC = "d6";
+NET "vga_r<2>" LOC = "b1";
+NET "vga_g<0>" LOC = "a8";
+NET "vga_g<1>" LOC = "a5";
+NET "vga_g<2>" LOC = "c3";
+NET "vga_b<0>" LOC = "c9";
+NET "vga_b<1>" LOC = "e7";
+NET "vga_b<2>" LOC = "d5";
+
+#
+# keyboard
+#
+NET "ps2_clk" LOC = "b16";
+NET "ps2_data" LOC = "e13";
+
+#
+# serial line 0
+#
+NET "rs232_0_rxd" LOC = "g5";
+NET "rs232_0_txd" LOC = "j2";
+
+#
+# serial line 1
+#
+NET "rs232_1_rxd" LOC = "d1";
+NET "rs232_1_txd" LOC = "f4";
+
+#
+# disk, ethernet, etc.
+#
+NET "ata_cs0_n" LOC = "g15";
+NET "ata_cs1_n" LOC = "g14";
+NET "ata_dmack_n" LOC = "k1";
+NET "ata_dmarq" LOC = "l4";
+NET "ata_intrq" LOC = "h15";
+NET "ata_iordy" LOC = "l2";
+NET "ether_cs_n" LOC = "g13";
+NET "pbus_a<0>" LOC = "l5";
+NET "pbus_a<1>" LOC = "n2";
+NET "pbus_a<2>" LOC = "m3";
+NET "pbus_a<3>" LOC = "n1";
+NET "pbus_a<4>" LOC = "t13";
+NET "pbus_d<0>" LOC = "p12";
+NET "pbus_d<10>" LOC = "f3";
+NET "pbus_d<11>" LOC = "f2";
+NET "pbus_d<12>" LOC = "g4";
+NET "pbus_d<13>" LOC = "g3";
+NET "pbus_d<14>" LOC = "g1";
+NET "pbus_d<15>" LOC = "h4";
+NET "pbus_d<1>" LOC = "j1";
+NET "pbus_d<2>" LOC = "h1";
+NET "pbus_d<3>" LOC = "h3";
+NET "pbus_d<4>" LOC = "g2";
+NET "pbus_d<5>" LOC = "k15";
+NET "pbus_d<6>" LOC = "k16";
+NET "pbus_d<7>" LOC = "f15";
+NET "pbus_d<8>" LOC = "e2";
+NET "pbus_d<9>" LOC = "e1";
+NET "pbus_read_n" LOC = "p2";
+NET "pbus_write_n" LOC = "r1";
+NET "slot1_cs_n" LOC = "e15";
+NET "slot2_cs_n" LOC = "d16";
+
+#
+# board I/O
+#
+NET "sw1_3" LOC = "k2";
+NET "sw1_4" LOC = "j4";
+NET "sw2_n" LOC = "e11";
+NET "sw3_n" LOC = "a13";
Index: trunk/fpga/boards/xsa-xst-3/eco32.xise
===================================================================
--- trunk/fpga/boards/xsa-xst-3/eco32.xise (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/eco32.xise (revision 215)
@@ -0,0 +1,441 @@
+
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