URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
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/eco32
- from Rev 215 to Rev 216
- ↔ Reverse comparison
Rev 215 → Rev 216
/trunk/fpga/src/eco32.v
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/trunk/fpga/boards/xsa-xst-3/eco32.xise
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/trunk/fpga/boards/xsa-xst-3/eco32.bit
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Index: trunk/fpga/boards/xsa-xst-3/eco32.ucf
===================================================================
--- trunk/fpga/boards/xsa-xst-3/eco32.ucf (revision 215)
+++ trunk/fpga/boards/xsa-xst-3/eco32.ucf (nonexistent)
@@ -1,176 +0,0 @@
-#
-# eco32.ucf -- ECO32 user constraints for XSA-3S1000 + XST-3 board
-#
-
-#
-# clock and reset
-#
-NET "clk_in" PERIOD = 20.0ns HIGH 40%;
-NET "clk_in" LOC = "p8";
-NET "reset_inout_n" LOC = "d15";
-
-#
-# SDRAM
-#
-NET "sdram_a<0>" LOC = "b5";
-NET "sdram_a<1>" LOC = "a4";
-NET "sdram_a<2>" LOC = "b4";
-NET "sdram_a<3>" LOC = "e6";
-NET "sdram_a<4>" LOC = "e3";
-NET "sdram_a<5>" LOC = "c1";
-NET "sdram_a<6>" LOC = "e4";
-NET "sdram_a<7>" LOC = "d3";
-NET "sdram_a<8>" LOC = "c2";
-NET "sdram_a<9>" LOC = "a3";
-NET "sdram_a<10>" LOC = "b6";
-NET "sdram_a<11>" LOC = "c5";
-NET "sdram_a<12>" LOC = "c6";
-NET "sdram_ba<0>" LOC = "a7";
-NET "sdram_ba<1>" LOC = "c7";
-NET "sdram_cas_n" LOC = "a10";
-NET "sdram_cke" LOC = "d7";
-NET "sdram_clk" LOC = "e10";
-NET "sdram_cs_n" LOC = "b8";
-NET "sdram_dq<0>" LOC = "c15";
-NET "sdram_dq<1>" LOC = "d12";
-NET "sdram_dq<2>" LOC = "a14";
-NET "sdram_dq<3>" LOC = "b13";
-NET "sdram_dq<4>" LOC = "d11";
-NET "sdram_dq<5>" LOC = "a12";
-NET "sdram_dq<6>" LOC = "c11";
-NET "sdram_dq<7>" LOC = "d10";
-NET "sdram_dq<8>" LOC = "b11";
-NET "sdram_dq<9>" LOC = "b12";
-NET "sdram_dq<10>" LOC = "c12";
-NET "sdram_dq<11>" LOC = "b14";
-NET "sdram_dq<12>" LOC = "d14";
-NET "sdram_dq<13>" LOC = "c16";
-NET "sdram_dq<14>" LOC = "f12";
-NET "sdram_dq<15>" LOC = "f13";
-NET "sdram_fb" LOC = "n8";
-NET "sdram_ldqm" LOC = "c10";
-NET "sdram_ras_n" LOC = "a9";
-NET "sdram_udqm" LOC = "d9";
-NET "sdram_we_n" LOC = "b10";
-
-#
-# flash ROM
-#
-NET "flash_a<0>" LOC = "n5";
-NET "flash_a<1>" LOC = "k14";
-NET "flash_a<2>" LOC = "k13";
-NET "flash_a<3>" LOC = "k12";
-NET "flash_a<4>" LOC = "l14";
-NET "flash_a<5>" LOC = "m16";
-NET "flash_a<6>" LOC = "l13";
-NET "flash_a<7>" LOC = "n16";
-NET "flash_a<8>" LOC = "n14";
-NET "flash_a<9>" LOC = "p15";
-NET "flash_a<10>" LOC = "r16";
-NET "flash_a<11>" LOC = "p14";
-NET "flash_a<12>" LOC = "p13";
-NET "flash_a<13>" LOC = "n12";
-NET "flash_a<14>" LOC = "t14";
-NET "flash_a<15>" LOC = "r13";
-NET "flash_a<16>" LOC = "n10";
-NET "flash_a<17>" LOC = "m14";
-NET "flash_a<18>" LOC = "k3";
-NET "flash_a<19>" LOC = "k4";
-NET "flash_byte_n" LOC = "t8";
-NET "flash_ce_n" LOC = "r4";
-NET "flash_d<0>" LOC = "m11";
-NET "flash_d<1>" LOC = "n11";
-NET "flash_d<2>" LOC = "p10";
-NET "flash_d<3>" LOC = "r10";
-NET "flash_d<4>" LOC = "t7";
-NET "flash_d<5>" LOC = "r7";
-NET "flash_d<6>" LOC = "n6";
-NET "flash_d<7>" LOC = "m6";
-NET "flash_d<8>" LOC = "t4";
-NET "flash_d<9>" LOC = "r5";
-NET "flash_d<10>" LOC = "t5";
-NET "flash_d<11>" LOC = "p6";
-NET "flash_d<12>" LOC = "m7";
-NET "flash_d<13>" LOC = "r6";
-NET "flash_d<14>" LOC = "n7";
-NET "flash_d<15>" LOC = "p7";
-NET "flash_oe_n" LOC = "p5";
-NET "flash_rst_n" LOC = "p16";
-NET "flash_we_n" LOC = "m13";
-
-#
-# VGA display
-#
-NET "vga_hsync" LOC = "b7";
-NET "vga_vsync" LOC = "d8";
-NET "vga_r<0>" LOC = "c8";
-NET "vga_r<1>" LOC = "d6";
-NET "vga_r<2>" LOC = "b1";
-NET "vga_g<0>" LOC = "a8";
-NET "vga_g<1>" LOC = "a5";
-NET "vga_g<2>" LOC = "c3";
-NET "vga_b<0>" LOC = "c9";
-NET "vga_b<1>" LOC = "e7";
-NET "vga_b<2>" LOC = "d5";
-
-#
-# keyboard
-#
-NET "ps2_clk" LOC = "b16";
-NET "ps2_data" LOC = "e13";
-
-#
-# serial line 0
-#
-NET "rs232_0_rxd" LOC = "g5";
-NET "rs232_0_txd" LOC = "j2";
-
-#
-# serial line 1
-#
-NET "rs232_1_rxd" LOC = "d1";
-NET "rs232_1_txd" LOC = "f4";
-
-#
-# disk, ethernet, etc.
-#
-NET "ata_cs0_n" LOC = "g15";
-NET "ata_cs1_n" LOC = "g14";
-NET "ata_dmack_n" LOC = "k1";
-NET "ata_dmarq" LOC = "l4";
-NET "ata_intrq" LOC = "h15";
-NET "ata_iordy" LOC = "l2";
-NET "ether_cs_n" LOC = "g13";
-NET "pbus_a<0>" LOC = "l5";
-NET "pbus_a<1>" LOC = "n2";
-NET "pbus_a<2>" LOC = "m3";
-NET "pbus_a<3>" LOC = "n1";
-NET "pbus_a<4>" LOC = "t13";
-NET "pbus_d<0>" LOC = "p12";
-NET "pbus_d<10>" LOC = "f3";
-NET "pbus_d<11>" LOC = "f2";
-NET "pbus_d<12>" LOC = "g4";
-NET "pbus_d<13>" LOC = "g3";
-NET "pbus_d<14>" LOC = "g1";
-NET "pbus_d<15>" LOC = "h4";
-NET "pbus_d<1>" LOC = "j1";
-NET "pbus_d<2>" LOC = "h1";
-NET "pbus_d<3>" LOC = "h3";
-NET "pbus_d<4>" LOC = "g2";
-NET "pbus_d<5>" LOC = "k15";
-NET "pbus_d<6>" LOC = "k16";
-NET "pbus_d<7>" LOC = "f15";
-NET "pbus_d<8>" LOC = "e2";
-NET "pbus_d<9>" LOC = "e1";
-NET "pbus_read_n" LOC = "p2";
-NET "pbus_write_n" LOC = "r1";
-NET "slot1_cs_n" LOC = "e15";
-NET "slot2_cs_n" LOC = "d16";
-
-#
-# board I/O
-#
-NET "sw1_3" LOC = "k2";
-NET "sw1_4" LOC = "j4";
-NET "sw2_n" LOC = "e11";
-NET "sw3_n" LOC = "a13";
Index: trunk/fpga/boards/xsa-xst-3/build/eco32.xise
===================================================================
--- trunk/fpga/boards/xsa-xst-3/build/eco32.xise (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/build/eco32.xise (revision 216)
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Index: trunk/fpga/boards/xsa-xst-3/build/eco32.bit
===================================================================
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Index: trunk/fpga/boards/xsa-xst-3/build/eco32.bit
===================================================================
--- trunk/fpga/boards/xsa-xst-3/build/eco32.bit (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/build/eco32.bit (revision 216)
trunk/fpga/boards/xsa-xst-3/build/eco32.bit
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+application/octet-stream
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Index: trunk/fpga/boards/xsa-xst-3/toplevel/eco32.v
===================================================================
--- trunk/fpga/boards/xsa-xst-3/toplevel/eco32.v (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/toplevel/eco32.v (revision 216)
@@ -0,0 +1,503 @@
+//
+// eco32.v -- ECO32 top-level description
+//
+
+
+module eco32(clk_in,
+ reset_inout_n,
+ sdram_clk,
+ sdram_fb,
+ sdram_cke,
+ sdram_cs_n,
+ sdram_ras_n,
+ sdram_cas_n,
+ sdram_we_n,
+ sdram_ba,
+ sdram_a,
+ sdram_udqm,
+ sdram_ldqm,
+ sdram_dq,
+ flash_ce_n,
+ flash_oe_n,
+ flash_we_n,
+ flash_rst_n,
+ flash_byte_n,
+ flash_a,
+ flash_d,
+ vga_hsync,
+ vga_vsync,
+ vga_r,
+ vga_g,
+ vga_b,
+ ps2_clk,
+ ps2_data,
+ rs232_0_rxd,
+ rs232_0_txd,
+ rs232_1_rxd,
+ rs232_1_txd,
+ pbus_d,
+ pbus_a,
+ pbus_read_n,
+ pbus_write_n,
+ ata_cs0_n,
+ ata_cs1_n,
+ ata_intrq,
+ ata_dmarq,
+ ata_dmack_n,
+ ata_iordy,
+ slot1_cs_n,
+ slot2_cs_n,
+ ether_cs_n,
+ sw1_3,
+ sw1_4,
+ sw2_n,
+ sw3_n);
+
+ // clock and reset
+ input clk_in;
+ inout reset_inout_n;
+ // SDRAM
+ output sdram_clk;
+ input sdram_fb;
+ output sdram_cke;
+ output sdram_cs_n;
+ output sdram_ras_n;
+ output sdram_cas_n;
+ output sdram_we_n;
+ output [1:0] sdram_ba;
+ output [12:0] sdram_a;
+ output sdram_udqm;
+ output sdram_ldqm;
+ inout [15:0] sdram_dq;
+ // flash ROM
+ output flash_ce_n;
+ output flash_oe_n;
+ output flash_we_n;
+ output flash_rst_n;
+ output flash_byte_n;
+ output [19:0] flash_a;
+ input [15:0] flash_d;
+ // VGA display
+ output vga_hsync;
+ output vga_vsync;
+ output [2:0] vga_r;
+ output [2:0] vga_g;
+ output [2:0] vga_b;
+ // keyboard
+ input ps2_clk;
+ input ps2_data;
+ // serial line 0
+ input rs232_0_rxd;
+ output rs232_0_txd;
+ // serial line 1
+ input rs232_1_rxd;
+ output rs232_1_txd;
+ // peripheral bus
+ inout [15:0] pbus_d;
+ output [4:0] pbus_a;
+ output pbus_read_n;
+ output pbus_write_n;
+ // ATA adapter
+ output ata_cs0_n;
+ output ata_cs1_n;
+ input ata_intrq;
+ input ata_dmarq;
+ output ata_dmack_n;
+ input ata_iordy;
+ // expansion slot 1
+ output slot1_cs_n;
+ // expansion slot 2
+ output slot2_cs_n;
+ // ethernet
+ output ether_cs_n;
+ // board I/O
+ input sw1_3;
+ input sw1_4;
+ input sw2_n;
+ input sw3_n;
+
+ // clk_reset
+ wire clk;
+ wire clk_ok;
+ wire reset;
+ // cpu
+ wire cpu_en;
+ wire cpu_wr;
+ wire [1:0] cpu_size;
+ wire [31:0] cpu_addr;
+ wire [31:0] cpu_data_in;
+ wire [31:0] cpu_data_out;
+ wire cpu_wt;
+ wire [15:0] cpu_irq;
+ // ram
+ wire ram_en;
+ wire ram_wr;
+ wire [1:0] ram_size;
+ wire [24:0] ram_addr;
+ wire [31:0] ram_data_in;
+ wire [31:0] ram_data_out;
+ wire ram_wt;
+ // rom
+ wire rom_en;
+ wire rom_wr;
+ wire [1:0] rom_size;
+ wire [20:0] rom_addr;
+ wire [31:0] rom_data_out;
+ wire rom_wt;
+ // tmr0
+ wire tmr0_en;
+ wire tmr0_wr;
+ wire [3:2] tmr0_addr;
+ wire [31:0] tmr0_data_in;
+ wire [31:0] tmr0_data_out;
+ wire tmr0_wt;
+ wire tmr0_irq;
+ // tmr1
+ wire tmr1_en;
+ wire tmr1_wr;
+ wire [3:2] tmr1_addr;
+ wire [31:0] tmr1_data_in;
+ wire [31:0] tmr1_data_out;
+ wire tmr1_wt;
+ wire tmr1_irq;
+ // dsp
+ wire dsp_en;
+ wire dsp_wr;
+ wire [13:2] dsp_addr;
+ wire [15:0] dsp_data_in;
+ wire [15:0] dsp_data_out;
+ wire dsp_wt;
+ // kbd
+ wire kbd_en;
+ wire kbd_wr;
+ wire kbd_addr;
+ wire [7:0] kbd_data_in;
+ wire [7:0] kbd_data_out;
+ wire kbd_wt;
+ wire kbd_irq;
+ // ser0
+ wire ser0_en;
+ wire ser0_wr;
+ wire [3:2] ser0_addr;
+ wire [7:0] ser0_data_in;
+ wire [7:0] ser0_data_out;
+ wire ser0_wt;
+ wire ser0_irq_r;
+ wire ser0_irq_t;
+ // ser1
+ wire ser1_en;
+ wire ser1_wr;
+ wire [3:2] ser1_addr;
+ wire [7:0] ser1_data_in;
+ wire [7:0] ser1_data_out;
+ wire ser1_wt;
+ wire ser1_irq_r;
+ wire ser1_irq_t;
+ // dsk
+ wire dsk_en;
+ wire dsk_wr;
+ wire [19:2] dsk_addr;
+ wire [31:0] dsk_data_in;
+ wire [31:0] dsk_data_out;
+ wire dsk_wt;
+ wire dsk_irq;
+ // bio
+ wire bio_en;
+ wire bio_wr;
+ wire bio_addr;
+ wire [31:0] bio_data_in;
+ wire [31:0] bio_data_out;
+ wire bio_wt;
+
+ clk_reset clk_reset1(
+ .clk_in(clk_in),
+ .reset_inout_n(reset_inout_n),
+ .sdram_clk(sdram_clk),
+ .sdram_fb(sdram_fb),
+ .clk(clk),
+ .clk_ok(clk_ok),
+ .reset(reset)
+ );
+
+ busctrl busctrl1(
+ // cpu
+ .cpu_en(cpu_en),
+ .cpu_wr(cpu_wr),
+ .cpu_size(cpu_size[1:0]),
+ .cpu_addr(cpu_addr[31:0]),
+ .cpu_data_in(cpu_data_in[31:0]),
+ .cpu_data_out(cpu_data_out[31:0]),
+ .cpu_wt(cpu_wt),
+ // ram
+ .ram_en(ram_en),
+ .ram_wr(ram_wr),
+ .ram_size(ram_size[1:0]),
+ .ram_addr(ram_addr[24:0]),
+ .ram_data_in(ram_data_in[31:0]),
+ .ram_data_out(ram_data_out[31:0]),
+ .ram_wt(ram_wt),
+ // rom
+ .rom_en(rom_en),
+ .rom_wr(rom_wr),
+ .rom_size(rom_size[1:0]),
+ .rom_addr(rom_addr[20:0]),
+ .rom_data_out(rom_data_out[31:0]),
+ .rom_wt(rom_wt),
+ // tmr0
+ .tmr0_en(tmr0_en),
+ .tmr0_wr(tmr0_wr),
+ .tmr0_addr(tmr0_addr[3:2]),
+ .tmr0_data_in(tmr0_data_in[31:0]),
+ .tmr0_data_out(tmr0_data_out[31:0]),
+ .tmr0_wt(tmr0_wt),
+ // tmr1
+ .tmr1_en(tmr1_en),
+ .tmr1_wr(tmr1_wr),
+ .tmr1_addr(tmr1_addr[3:2]),
+ .tmr1_data_in(tmr1_data_in[31:0]),
+ .tmr1_data_out(tmr1_data_out[31:0]),
+ .tmr1_wt(tmr1_wt),
+ // dsp
+ .dsp_en(dsp_en),
+ .dsp_wr(dsp_wr),
+ .dsp_addr(dsp_addr[13:2]),
+ .dsp_data_in(dsp_data_in[15:0]),
+ .dsp_data_out(dsp_data_out[15:0]),
+ .dsp_wt(dsp_wt),
+ // kbd
+ .kbd_en(kbd_en),
+ .kbd_wr(kbd_wr),
+ .kbd_addr(kbd_addr),
+ .kbd_data_in(kbd_data_in[7:0]),
+ .kbd_data_out(kbd_data_out[7:0]),
+ .kbd_wt(kbd_wt),
+ // ser0
+ .ser0_en(ser0_en),
+ .ser0_wr(ser0_wr),
+ .ser0_addr(ser0_addr[3:2]),
+ .ser0_data_in(ser0_data_in[7:0]),
+ .ser0_data_out(ser0_data_out[7:0]),
+ .ser0_wt(ser0_wt),
+ // ser1
+ .ser1_en(ser1_en),
+ .ser1_wr(ser1_wr),
+ .ser1_addr(ser1_addr[3:2]),
+ .ser1_data_in(ser1_data_in[7:0]),
+ .ser1_data_out(ser1_data_out[7:0]),
+ .ser1_wt(ser1_wt),
+ // dsk
+ .dsk_en(dsk_en),
+ .dsk_wr(dsk_wr),
+ .dsk_addr(dsk_addr[19:2]),
+ .dsk_data_in(dsk_data_in[31:0]),
+ .dsk_data_out(dsk_data_out[31:0]),
+ .dsk_wt(dsk_wt),
+ // bio
+ .bio_en(bio_en),
+ .bio_wr(bio_wr),
+ .bio_addr(bio_addr),
+ .bio_data_in(bio_data_in[31:0]),
+ .bio_data_out(bio_data_out[31:0]),
+ .bio_wt(bio_wt)
+ );
+
+ cpu cpu1(
+ .clk(clk),
+ .reset(reset),
+ .bus_en(cpu_en),
+ .bus_wr(cpu_wr),
+ .bus_size(cpu_size[1:0]),
+ .bus_addr(cpu_addr[31:0]),
+ .bus_data_in(cpu_data_in[31:0]),
+ .bus_data_out(cpu_data_out[31:0]),
+ .bus_wt(cpu_wt),
+ .irq(cpu_irq[15:0])
+ );
+
+ assign cpu_irq[15] = tmr1_irq;
+ assign cpu_irq[14] = tmr0_irq;
+ assign cpu_irq[13] = 1'b0;
+ assign cpu_irq[12] = 1'b0;
+ assign cpu_irq[11] = 1'b0;
+ assign cpu_irq[10] = 1'b0;
+ assign cpu_irq[ 9] = 1'b0;
+ assign cpu_irq[ 8] = dsk_irq;
+ assign cpu_irq[ 7] = 1'b0;
+ assign cpu_irq[ 6] = 1'b0;
+ assign cpu_irq[ 5] = 1'b0;
+ assign cpu_irq[ 4] = kbd_irq;
+ assign cpu_irq[ 3] = ser1_irq_r;
+ assign cpu_irq[ 2] = ser1_irq_t;
+ assign cpu_irq[ 1] = ser0_irq_r;
+ assign cpu_irq[ 0] = ser0_irq_t;
+
+ ram ram1(
+ .clk(clk),
+ .clk_ok(clk_ok),
+ .reset(reset),
+ .en(ram_en),
+ .wr(ram_wr),
+ .size(ram_size[1:0]),
+ .addr(ram_addr[24:0]),
+ .data_in(ram_data_in[31:0]),
+ .data_out(ram_data_out[31:0]),
+ .wt(ram_wt),
+ .sdram_cke(sdram_cke),
+ .sdram_cs_n(sdram_cs_n),
+ .sdram_ras_n(sdram_ras_n),
+ .sdram_cas_n(sdram_cas_n),
+ .sdram_we_n(sdram_we_n),
+ .sdram_ba(sdram_ba[1:0]),
+ .sdram_a(sdram_a[12:0]),
+ .sdram_udqm(sdram_udqm),
+ .sdram_ldqm(sdram_ldqm),
+ .sdram_dq(sdram_dq[15:0])
+ );
+
+ rom rom1(
+ .clk(clk),
+ .reset(reset),
+ .en(rom_en),
+ .wr(rom_wr),
+ .size(rom_size[1:0]),
+ .addr(rom_addr[20:0]),
+ .data_out(rom_data_out[31:0]),
+ .wt(rom_wt),
+ .ce_n(flash_ce_n),
+ .oe_n(flash_oe_n),
+ .we_n(flash_we_n),
+ .rst_n(flash_rst_n),
+ .byte_n(flash_byte_n),
+ .a(flash_a[19:0]),
+ .d(flash_d[15:0])
+ );
+
+ tmr tmr1_0(
+ .clk(clk),
+ .reset(reset),
+ .en(tmr0_en),
+ .wr(tmr0_wr),
+ .addr(tmr0_addr[3:2]),
+ .data_in(tmr0_data_in[31:0]),
+ .data_out(tmr0_data_out[31:0]),
+ .wt(tmr0_wt),
+ .irq(tmr0_irq)
+ );
+
+ tmr tmr1_1(
+ .clk(clk),
+ .reset(reset),
+ .en(tmr1_en),
+ .wr(tmr1_wr),
+ .addr(tmr1_addr[3:2]),
+ .data_in(tmr1_data_in[31:0]),
+ .data_out(tmr1_data_out[31:0]),
+ .wt(tmr1_wt),
+ .irq(tmr1_irq)
+ );
+
+ dsp dsp1(
+ .clk(clk),
+ .reset(reset),
+ .en(dsp_en),
+ .wr(dsp_wr),
+ .addr(dsp_addr[13:2]),
+ .data_in(dsp_data_in[15:0]),
+ .data_out(dsp_data_out[15:0]),
+ .wt(dsp_wt),
+ .hsync(vga_hsync),
+ .vsync(vga_vsync),
+ .r(vga_r[2:0]),
+ .g(vga_g[2:0]),
+ .b(vga_b[2:0])
+ );
+
+ kbd kbd1(
+ .clk(clk),
+ .reset(reset),
+ .en(kbd_en),
+ .wr(kbd_wr),
+ .addr(kbd_addr),
+ .data_in(kbd_data_in[7:0]),
+ .data_out(kbd_data_out[7:0]),
+ .wt(kbd_wt),
+ .irq(kbd_irq),
+ .ps2_clk(ps2_clk),
+ .ps2_data(ps2_data)
+ );
+
+ ser ser1_0(
+ .clk(clk),
+ .reset(reset),
+ .en(ser0_en),
+ .wr(ser0_wr),
+ .addr(ser0_addr[3:2]),
+ .data_in(ser0_data_in[7:0]),
+ .data_out(ser0_data_out[7:0]),
+ .wt(ser0_wt),
+ .irq_r(ser0_irq_r),
+ .irq_t(ser0_irq_t),
+ .rxd(rs232_0_rxd),
+ .txd(rs232_0_txd)
+ );
+
+ ser ser1_1(
+ .clk(clk),
+ .reset(reset),
+ .en(ser1_en),
+ .wr(ser1_wr),
+ .addr(ser1_addr[3:2]),
+ .data_in(ser1_data_in[7:0]),
+ .data_out(ser1_data_out[7:0]),
+ .wt(ser1_wt),
+ .irq_r(ser1_irq_r),
+ .irq_t(ser1_irq_t),
+ .rxd(rs232_1_rxd),
+ .txd(rs232_1_txd)
+ );
+
+ dsk dsk1(
+ .clk(clk),
+ .reset(reset),
+ .en(dsk_en),
+ .wr(dsk_wr),
+ .addr(dsk_addr[19:2]),
+ .data_in(dsk_data_in[31:0]),
+ .data_out(dsk_data_out[31:0]),
+ .wt(dsk_wt),
+ .irq(dsk_irq),
+ .ata_d(pbus_d[15:0]),
+ .ata_a(pbus_a[2:0]),
+ .ata_cs0_n(ata_cs0_n),
+ .ata_cs1_n(ata_cs1_n),
+ .ata_dior_n(pbus_read_n),
+ .ata_diow_n(pbus_write_n),
+ .ata_intrq(ata_intrq),
+ .ata_dmarq(ata_dmarq),
+ .ata_dmack_n(ata_dmack_n),
+ .ata_iordy(ata_iordy)
+ );
+
+ assign pbus_a[4:3] = 2'b00;
+ assign slot1_cs_n = 1;
+ assign slot2_cs_n = 1;
+ assign ether_cs_n = 1;
+
+ bio bio1(
+ .clk(clk),
+ .reset(reset),
+ .en(bio_en),
+ .wr(bio_wr),
+ .addr(bio_addr),
+ .data_in(bio_data_in[31:0]),
+ .data_out(bio_data_out[31:0]),
+ .wt(bio_wt),
+ .sw1_1(flash_a[19]),
+ .sw1_2(flash_a[18]),
+ .sw1_3(sw1_3),
+ .sw1_4(sw1_4),
+ .sw2_n(sw2_n),
+ .sw3_n(sw3_n)
+ );
+
+endmodule
Index: trunk/fpga/boards/xsa-xst-3/toplevel/eco32.ucf
===================================================================
--- trunk/fpga/boards/xsa-xst-3/toplevel/eco32.ucf (nonexistent)
+++ trunk/fpga/boards/xsa-xst-3/toplevel/eco32.ucf (revision 216)
@@ -0,0 +1,176 @@
+#
+# eco32.ucf -- ECO32 user constraints for XSA-3S1000 + XST-3 board
+#
+
+#
+# clock and reset
+#
+NET "clk_in" PERIOD = 20.0ns HIGH 40%;
+NET "clk_in" LOC = "p8";
+NET "reset_inout_n" LOC = "d15";
+
+#
+# SDRAM
+#
+NET "sdram_a<0>" LOC = "b5";
+NET "sdram_a<1>" LOC = "a4";
+NET "sdram_a<2>" LOC = "b4";
+NET "sdram_a<3>" LOC = "e6";
+NET "sdram_a<4>" LOC = "e3";
+NET "sdram_a<5>" LOC = "c1";
+NET "sdram_a<6>" LOC = "e4";
+NET "sdram_a<7>" LOC = "d3";
+NET "sdram_a<8>" LOC = "c2";
+NET "sdram_a<9>" LOC = "a3";
+NET "sdram_a<10>" LOC = "b6";
+NET "sdram_a<11>" LOC = "c5";
+NET "sdram_a<12>" LOC = "c6";
+NET "sdram_ba<0>" LOC = "a7";
+NET "sdram_ba<1>" LOC = "c7";
+NET "sdram_cas_n" LOC = "a10";
+NET "sdram_cke" LOC = "d7";
+NET "sdram_clk" LOC = "e10";
+NET "sdram_cs_n" LOC = "b8";
+NET "sdram_dq<0>" LOC = "c15";
+NET "sdram_dq<1>" LOC = "d12";
+NET "sdram_dq<2>" LOC = "a14";
+NET "sdram_dq<3>" LOC = "b13";
+NET "sdram_dq<4>" LOC = "d11";
+NET "sdram_dq<5>" LOC = "a12";
+NET "sdram_dq<6>" LOC = "c11";
+NET "sdram_dq<7>" LOC = "d10";
+NET "sdram_dq<8>" LOC = "b11";
+NET "sdram_dq<9>" LOC = "b12";
+NET "sdram_dq<10>" LOC = "c12";
+NET "sdram_dq<11>" LOC = "b14";
+NET "sdram_dq<12>" LOC = "d14";
+NET "sdram_dq<13>" LOC = "c16";
+NET "sdram_dq<14>" LOC = "f12";
+NET "sdram_dq<15>" LOC = "f13";
+NET "sdram_fb" LOC = "n8";
+NET "sdram_ldqm" LOC = "c10";
+NET "sdram_ras_n" LOC = "a9";
+NET "sdram_udqm" LOC = "d9";
+NET "sdram_we_n" LOC = "b10";
+
+#
+# flash ROM
+#
+NET "flash_a<0>" LOC = "n5";
+NET "flash_a<1>" LOC = "k14";
+NET "flash_a<2>" LOC = "k13";
+NET "flash_a<3>" LOC = "k12";
+NET "flash_a<4>" LOC = "l14";
+NET "flash_a<5>" LOC = "m16";
+NET "flash_a<6>" LOC = "l13";
+NET "flash_a<7>" LOC = "n16";
+NET "flash_a<8>" LOC = "n14";
+NET "flash_a<9>" LOC = "p15";
+NET "flash_a<10>" LOC = "r16";
+NET "flash_a<11>" LOC = "p14";
+NET "flash_a<12>" LOC = "p13";
+NET "flash_a<13>" LOC = "n12";
+NET "flash_a<14>" LOC = "t14";
+NET "flash_a<15>" LOC = "r13";
+NET "flash_a<16>" LOC = "n10";
+NET "flash_a<17>" LOC = "m14";
+NET "flash_a<18>" LOC = "k3";
+NET "flash_a<19>" LOC = "k4";
+NET "flash_byte_n" LOC = "t8";
+NET "flash_ce_n" LOC = "r4";
+NET "flash_d<0>" LOC = "m11";
+NET "flash_d<1>" LOC = "n11";
+NET "flash_d<2>" LOC = "p10";
+NET "flash_d<3>" LOC = "r10";
+NET "flash_d<4>" LOC = "t7";
+NET "flash_d<5>" LOC = "r7";
+NET "flash_d<6>" LOC = "n6";
+NET "flash_d<7>" LOC = "m6";
+NET "flash_d<8>" LOC = "t4";
+NET "flash_d<9>" LOC = "r5";
+NET "flash_d<10>" LOC = "t5";
+NET "flash_d<11>" LOC = "p6";
+NET "flash_d<12>" LOC = "m7";
+NET "flash_d<13>" LOC = "r6";
+NET "flash_d<14>" LOC = "n7";
+NET "flash_d<15>" LOC = "p7";
+NET "flash_oe_n" LOC = "p5";
+NET "flash_rst_n" LOC = "p16";
+NET "flash_we_n" LOC = "m13";
+
+#
+# VGA display
+#
+NET "vga_hsync" LOC = "b7";
+NET "vga_vsync" LOC = "d8";
+NET "vga_r<0>" LOC = "c8";
+NET "vga_r<1>" LOC = "d6";
+NET "vga_r<2>" LOC = "b1";
+NET "vga_g<0>" LOC = "a8";
+NET "vga_g<1>" LOC = "a5";
+NET "vga_g<2>" LOC = "c3";
+NET "vga_b<0>" LOC = "c9";
+NET "vga_b<1>" LOC = "e7";
+NET "vga_b<2>" LOC = "d5";
+
+#
+# keyboard
+#
+NET "ps2_clk" LOC = "b16";
+NET "ps2_data" LOC = "e13";
+
+#
+# serial line 0
+#
+NET "rs232_0_rxd" LOC = "g5";
+NET "rs232_0_txd" LOC = "j2";
+
+#
+# serial line 1
+#
+NET "rs232_1_rxd" LOC = "d1";
+NET "rs232_1_txd" LOC = "f4";
+
+#
+# disk, ethernet, etc.
+#
+NET "ata_cs0_n" LOC = "g15";
+NET "ata_cs1_n" LOC = "g14";
+NET "ata_dmack_n" LOC = "k1";
+NET "ata_dmarq" LOC = "l4";
+NET "ata_intrq" LOC = "h15";
+NET "ata_iordy" LOC = "l2";
+NET "ether_cs_n" LOC = "g13";
+NET "pbus_a<0>" LOC = "l5";
+NET "pbus_a<1>" LOC = "n2";
+NET "pbus_a<2>" LOC = "m3";
+NET "pbus_a<3>" LOC = "n1";
+NET "pbus_a<4>" LOC = "t13";
+NET "pbus_d<0>" LOC = "p12";
+NET "pbus_d<10>" LOC = "f3";
+NET "pbus_d<11>" LOC = "f2";
+NET "pbus_d<12>" LOC = "g4";
+NET "pbus_d<13>" LOC = "g3";
+NET "pbus_d<14>" LOC = "g1";
+NET "pbus_d<15>" LOC = "h4";
+NET "pbus_d<1>" LOC = "j1";
+NET "pbus_d<2>" LOC = "h1";
+NET "pbus_d<3>" LOC = "h3";
+NET "pbus_d<4>" LOC = "g2";
+NET "pbus_d<5>" LOC = "k15";
+NET "pbus_d<6>" LOC = "k16";
+NET "pbus_d<7>" LOC = "f15";
+NET "pbus_d<8>" LOC = "e2";
+NET "pbus_d<9>" LOC = "e1";
+NET "pbus_read_n" LOC = "p2";
+NET "pbus_write_n" LOC = "r1";
+NET "slot1_cs_n" LOC = "e15";
+NET "slot2_cs_n" LOC = "d16";
+
+#
+# board I/O
+#
+NET "sw1_3" LOC = "k2";
+NET "sw1_4" LOC = "j4";
+NET "sw2_n" LOC = "e11";
+NET "sw3_n" LOC = "a13";
Index: trunk/fpga/boards/s3e-500/build/eco32.xise
===================================================================
--- trunk/fpga/boards/s3e-500/build/eco32.xise (nonexistent)
+++ trunk/fpga/boards/s3e-500/build/eco32.xise (revision 216)
@@ -0,0 +1,146 @@
+
+
+
+
+
+
+
+
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+
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+
Index: trunk/fpga/boards/s3e-500/toplevel/eco32.v
===================================================================
--- trunk/fpga/boards/s3e-500/toplevel/eco32.v (nonexistent)
+++ trunk/fpga/boards/s3e-500/toplevel/eco32.v (revision 216)
@@ -0,0 +1,490 @@
+//
+// eco32.v -- ECO32 top-level description
+//
+
+
+module eco32(clk_in,
+ reset_in,
+ sdram_ck_p,
+ sdram_ck_n,
+ sdram_cke,
+ sdram_cs_n,
+ sdram_ras_n,
+ sdram_cas_n,
+ sdram_we_n,
+ sdram_ba,
+ sdram_a,
+ sdram_udm,
+ sdram_ldm,
+ sdram_udqs,
+ sdram_ldqs,
+ sdram_dq,
+ flash_ce_n,
+ flash_oe_n,
+ flash_we_n,
+ flash_byte_n,
+ flash_a,
+ flash_d,
+ vga_hsync,
+ vga_vsync,
+ vga_r,
+ vga_g,
+ vga_b,
+ ps2_clk,
+ ps2_data,
+ rs232_0_rxd,
+ rs232_0_txd,
+ rs232_1_rxd,
+ rs232_1_txd,
+ spi_sck,
+ spi_mosi,
+ dac_cs_n,
+ dac_clr_n,
+ amp_cs_n,
+ amp_shdn,
+ ad_conv,
+ sw,
+ led,
+ lcd_e,
+ lcd_rw,
+ lcd_rs,
+ spi_ss_b,
+ fpga_init_b);
+ // clock and reset
+ input clk_in;
+ input reset_in;
+ // SDRAM
+ output sdram_ck_p;
+ output sdram_ck_n;
+ output sdram_cke;
+ output sdram_cs_n;
+ output sdram_ras_n;
+ output sdram_cas_n;
+ output sdram_we_n;
+ output [1:0] sdram_ba;
+ output [12:0] sdram_a;
+ output sdram_udm;
+ output sdram_ldm;
+ inout sdram_udqs;
+ inout sdram_ldqs;
+ inout [15:0] sdram_dq;
+ // flash ROM
+ output flash_ce_n;
+ output flash_oe_n;
+ output flash_we_n;
+ output flash_byte_n;
+ output [23:0] flash_a;
+ input [15:0] flash_d;
+ // VGA display
+ output vga_hsync;
+ output vga_vsync;
+ output vga_r;
+ output vga_g;
+ output vga_b;
+ // keyboard
+ input ps2_clk;
+ input ps2_data;
+ // serial line 0
+ input rs232_0_rxd;
+ output rs232_0_txd;
+ // serial line 1
+ input rs232_1_rxd;
+ output rs232_1_txd;
+ // SPI bus controller
+ output spi_sck;
+ output spi_mosi;
+ output dac_cs_n;
+ output dac_clr_n;
+ output amp_cs_n;
+ output amp_shdn;
+ output ad_conv;
+ // board I/O
+ input [3:0] sw;
+ output [7:0] led;
+ output lcd_e;
+ output lcd_rw;
+ output lcd_rs;
+ output spi_ss_b;
+ output fpga_init_b;
+
+ // clk_reset
+ wire ddr_clk_0;
+ wire ddr_clk_90;
+ wire ddr_clk_180;
+ wire ddr_clk_270;
+ wire ddr_clk_ok;
+ wire clk;
+ wire reset;
+ // cpu
+ wire cpu_en;
+ wire cpu_wr;
+ wire [1:0] cpu_size;
+ wire [31:0] cpu_addr;
+ wire [31:0] cpu_data_in;
+ wire [31:0] cpu_data_out;
+ wire cpu_wt;
+ wire [15:0] cpu_irq;
+ // ram
+ wire ram_en;
+ wire ram_wr;
+ wire [1:0] ram_size;
+ wire [25:0] ram_addr;
+ wire [31:0] ram_data_in;
+ wire [31:0] ram_data_out;
+ wire ram_wt;
+ // rom
+ wire rom_en;
+ wire rom_wr;
+ wire [1:0] rom_size;
+ wire [23:0] rom_addr;
+ wire [31:0] rom_data_out;
+ wire rom_wt;
+ // tmr
+ wire tmr_en;
+ wire tmr_wr;
+ wire tmr_addr;
+ wire [31:0] tmr_data_in;
+ wire [31:0] tmr_data_out;
+ wire tmr_wt;
+ wire tmr_irq;
+ // dsp
+ wire dsp_en;
+ wire dsp_wr;
+ wire [13:2] dsp_addr;
+ wire [15:0] dsp_data_in;
+ wire [15:0] dsp_data_out;
+ wire dsp_wt;
+ // kbd
+ wire kbd_en;
+ wire kbd_wr;
+ wire kbd_addr;
+ wire [7:0] kbd_data_in;
+ wire [7:0] kbd_data_out;
+ wire kbd_wt;
+ wire kbd_irq;
+ // ser0
+ wire ser0_en;
+ wire ser0_wr;
+ wire [3:2] ser0_addr;
+ wire [7:0] ser0_data_in;
+ wire [7:0] ser0_data_out;
+ wire ser0_wt;
+ wire ser0_irq_r;
+ wire ser0_irq_t;
+ // ser1
+ wire ser1_en;
+ wire ser1_wr;
+ wire [3:2] ser1_addr;
+ wire [7:0] ser1_data_in;
+ wire [7:0] ser1_data_out;
+ wire ser1_wt;
+ wire ser1_irq_r;
+ wire ser1_irq_t;
+ // fms
+ wire fms_en;
+ wire fms_wr;
+ wire [11:2] fms_addr;
+ wire [31:0] fms_data_in;
+ wire [31:0] fms_data_out;
+ wire fms_wt;
+ // spi
+ wire [15:0] dac_sample_l;
+ wire [15:0] dac_sample_r;
+ wire dac_next;
+ // bio
+ wire bio_en;
+ wire bio_wr;
+ wire bio_addr;
+ wire [31:0] bio_data_in;
+ wire [31:0] bio_data_out;
+ wire bio_wt;
+ wire spi_en;
+
+ clk_reset clk_reset1(
+ .clk_in(clk_in),
+ .reset_in(reset_in),
+ .ddr_clk_0(ddr_clk_0),
+ .ddr_clk_90(ddr_clk_90),
+ .ddr_clk_180(ddr_clk_180),
+ .ddr_clk_270(ddr_clk_270),
+ .ddr_clk_ok(ddr_clk_ok),
+ .clk(clk),
+ .reset(reset)
+ );
+
+ busctrl busctrl1(
+ // cpu
+ .cpu_en(cpu_en),
+ .cpu_wr(cpu_wr),
+ .cpu_size(cpu_size[1:0]),
+ .cpu_addr(cpu_addr[31:0]),
+ .cpu_data_in(cpu_data_in[31:0]),
+ .cpu_data_out(cpu_data_out[31:0]),
+ .cpu_wt(cpu_wt),
+ // ram
+ .ram_en(ram_en),
+ .ram_wr(ram_wr),
+ .ram_size(ram_size[1:0]),
+ .ram_addr(ram_addr[25:0]),
+ .ram_data_in(ram_data_in[31:0]),
+ .ram_data_out(ram_data_out[31:0]),
+ .ram_wt(ram_wt),
+ // rom
+ .rom_en(rom_en),
+ .rom_wr(rom_wr),
+ .rom_size(rom_size[1:0]),
+ .rom_addr(rom_addr[23:0]),
+ .rom_data_out(rom_data_out[31:0]),
+ .rom_wt(rom_wt),
+ // tmr
+ .tmr_en(tmr_en),
+ .tmr_wr(tmr_wr),
+ .tmr_addr(tmr_addr),
+ .tmr_data_in(tmr_data_in[31:0]),
+ .tmr_data_out(tmr_data_out[31:0]),
+ .tmr_wt(tmr_wt),
+ // dsp
+ .dsp_en(dsp_en),
+ .dsp_wr(dsp_wr),
+ .dsp_addr(dsp_addr[13:2]),
+ .dsp_data_in(dsp_data_in[15:0]),
+ .dsp_data_out(dsp_data_out[15:0]),
+ .dsp_wt(dsp_wt),
+ // kbd
+ .kbd_en(kbd_en),
+ .kbd_wr(kbd_wr),
+ .kbd_addr(kbd_addr),
+ .kbd_data_in(kbd_data_in[7:0]),
+ .kbd_data_out(kbd_data_out[7:0]),
+ .kbd_wt(kbd_wt),
+ // ser0
+ .ser0_en(ser0_en),
+ .ser0_wr(ser0_wr),
+ .ser0_addr(ser0_addr[3:2]),
+ .ser0_data_in(ser0_data_in[7:0]),
+ .ser0_data_out(ser0_data_out[7:0]),
+ .ser0_wt(ser0_wt),
+ // ser1
+ .ser1_en(ser1_en),
+ .ser1_wr(ser1_wr),
+ .ser1_addr(ser1_addr[3:2]),
+ .ser1_data_in(ser1_data_in[7:0]),
+ .ser1_data_out(ser1_data_out[7:0]),
+ .ser1_wt(ser1_wt),
+ // fms
+ .fms_en(fms_en),
+ .fms_wr(fms_wr),
+ .fms_addr(fms_addr[11:2]),
+ .fms_data_in(fms_data_in[31:0]),
+ .fms_data_out(fms_data_out[31:0]),
+ .fms_wt(fms_wt),
+ // bio
+ .bio_en(bio_en),
+ .bio_wr(bio_wr),
+ .bio_addr(bio_addr),
+ .bio_data_in(bio_data_in[31:0]),
+ .bio_data_out(bio_data_out[31:0]),
+ .bio_wt(bio_wt)
+ );
+
+ cpu cpu1(
+ .clk(clk),
+ .reset(reset),
+ .bus_en(cpu_en),
+ .bus_wr(cpu_wr),
+ .bus_size(cpu_size[1:0]),
+ .bus_addr(cpu_addr[31:0]),
+ .bus_data_in(cpu_data_in[31:0]),
+ .bus_data_out(cpu_data_out[31:0]),
+ .bus_wt(cpu_wt),
+ .irq(cpu_irq[15:0])
+ );
+
+ assign cpu_irq[15] = 1'b0;
+ assign cpu_irq[14] = tmr_irq;
+ assign cpu_irq[13] = 1'b0;
+ assign cpu_irq[12] = 1'b0;
+ assign cpu_irq[11] = 1'b0;
+ assign cpu_irq[10] = 1'b0;
+ assign cpu_irq[ 9] = 1'b0;
+ assign cpu_irq[ 8] = 1'b0; //dsk_irq;
+ assign cpu_irq[ 7] = 1'b0;
+ assign cpu_irq[ 6] = 1'b0;
+ assign cpu_irq[ 5] = 1'b0;
+ assign cpu_irq[ 4] = kbd_irq;
+ assign cpu_irq[ 3] = ser1_irq_r;
+ assign cpu_irq[ 2] = ser1_irq_t;
+ assign cpu_irq[ 1] = ser0_irq_r;
+ assign cpu_irq[ 0] = ser0_irq_t;
+
+ ram ram1(
+ .ddr_clk_0(ddr_clk_0),
+ .ddr_clk_90(ddr_clk_90),
+ .ddr_clk_180(ddr_clk_180),
+ .ddr_clk_270(ddr_clk_270),
+ .ddr_clk_ok(ddr_clk_ok),
+ .clk(clk),
+ .reset(reset),
+ .en(ram_en),
+ .wr(ram_wr),
+ .size(ram_size[1:0]),
+ .addr(ram_addr[25:0]),
+ .data_in(ram_data_in[31:0]),
+ .data_out(ram_data_out[31:0]),
+ .wt(ram_wt),
+ .sdram_ck_p(sdram_ck_p),
+ .sdram_ck_n(sdram_ck_n),
+ .sdram_cke(sdram_cke),
+ .sdram_cs_n(sdram_cs_n),
+ .sdram_ras_n(sdram_ras_n),
+ .sdram_cas_n(sdram_cas_n),
+ .sdram_we_n(sdram_we_n),
+ .sdram_ba(sdram_ba[1:0]),
+ .sdram_a(sdram_a[12:0]),
+ .sdram_udm(sdram_udm),
+ .sdram_ldm(sdram_ldm),
+ .sdram_udqs(sdram_udqs),
+ .sdram_ldqs(sdram_ldqs),
+ .sdram_dq(sdram_dq[15:0])
+ );
+
+ rom rom1(
+ .clk(clk),
+ .reset(reset),
+ .en(rom_en),
+ .wr(rom_wr),
+ .size(rom_size[1:0]),
+ .addr(rom_addr[23:0]),
+ .data_out(rom_data_out[31:0]),
+ .wt(rom_wt),
+ .spi_en(spi_en),
+ .ce_n(flash_ce_n),
+ .oe_n(flash_oe_n),
+ .we_n(flash_we_n),
+ .byte_n(flash_byte_n),
+ .a(flash_a[23:0]),
+ .d(flash_d[15:0])
+ );
+
+ tmr tmr1(
+ .clk(clk),
+ .reset(reset),
+ .en(tmr_en),
+ .wr(tmr_wr),
+ .addr(tmr_addr),
+ .data_in(tmr_data_in[31:0]),
+ .data_out(tmr_data_out[31:0]),
+ .wt(tmr_wt),
+ .irq(tmr_irq)
+ );
+
+ dsp dsp1(
+ .clk(clk),
+ .reset(reset),
+ .en(dsp_en),
+ .wr(dsp_wr),
+ .addr(dsp_addr[13:2]),
+ .data_in(dsp_data_in[15:0]),
+ .data_out(dsp_data_out[15:0]),
+ .wt(dsp_wt),
+ .hsync(vga_hsync),
+ .vsync(vga_vsync),
+ .r(vga_r),
+ .g(vga_g),
+ .b(vga_b)
+ );
+
+ kbd kbd1(
+ .clk(clk),
+ .reset(reset),
+ .en(kbd_en),
+ .wr(kbd_wr),
+ .addr(kbd_addr),
+ .data_in(kbd_data_in[7:0]),
+ .data_out(kbd_data_out[7:0]),
+ .wt(kbd_wt),
+ .irq(kbd_irq),
+ .ps2_clk(ps2_clk),
+ .ps2_data(ps2_data)
+ );
+
+ ser ser1_0(
+ .clk(clk),
+ .reset(reset),
+ .en(ser0_en),
+ .wr(ser0_wr),
+ .addr(ser0_addr[3:2]),
+ .data_in(ser0_data_in[7:0]),
+ .data_out(ser0_data_out[7:0]),
+ .wt(ser0_wt),
+ .irq_r(ser0_irq_r),
+ .irq_t(ser0_irq_t),
+ .rxd(rs232_0_rxd),
+ .txd(rs232_0_txd)
+ );
+
+ ser ser1_1(
+ .clk(clk),
+ .reset(reset),
+ .en(ser1_en),
+ .wr(ser1_wr),
+ .addr(ser1_addr[3:2]),
+ .data_in(ser1_data_in[7:0]),
+ .data_out(ser1_data_out[7:0]),
+ .wt(ser1_wt),
+ .irq_r(ser1_irq_r),
+ .irq_t(ser1_irq_t),
+ .rxd(rs232_1_rxd),
+ .txd(rs232_1_txd)
+ );
+
+ fms fms1(
+ .clk(clk),
+ .reset(reset),
+ .en(fms_en),
+ .wr(fms_wr),
+ .addr(fms_addr[11:2]),
+ .data_in(fms_data_in[31:0]),
+ .data_out(fms_data_out[31:0]),
+ .wt(fms_wt),
+ .next(dac_next),
+ .sample_l(dac_sample_l[15:0]),
+ .sample_r(dac_sample_r[15:0])
+ );
+
+ spi spi1(
+ .clk(clk),
+ .reset(reset),
+ .spi_en(spi_en),
+ .dac_sample_l(dac_sample_l[15:0]),
+ .dac_sample_r(dac_sample_r[15:0]),
+ .dac_next(dac_next),
+ .spi_sck(spi_sck),
+ .spi_mosi(spi_mosi),
+ .dac_cs_n(dac_cs_n),
+ .dac_clr_n(dac_clr_n),
+ .amp_cs_n(amp_cs_n),
+ .amp_shdn(amp_shdn),
+ .ad_conv(ad_conv)
+ );
+
+ bio bio1(
+ .clk(clk),
+ .reset(reset),
+ .en(bio_en),
+ .wr(bio_wr),
+ .addr(bio_addr),
+ .data_in(bio_data_in[31:0]),
+ .data_out(bio_data_out[31:0]),
+ .wt(bio_wt),
+ .spi_en(spi_en),
+ .sw(sw[3:0]),
+ .led(led[7:0]),
+ .lcd_e(lcd_e),
+ .lcd_rw(lcd_rw),
+ .lcd_rs(lcd_rs),
+ .spi_ss_b(spi_ss_b),
+ .fpga_init_b(fpga_init_b)
+ );
+
+endmodule
Index: trunk/fpga/boards/s3e-500/toplevel/eco32.ucf
===================================================================
--- trunk/fpga/boards/s3e-500/toplevel/eco32.ucf (nonexistent)
+++ trunk/fpga/boards/s3e-500/toplevel/eco32.ucf (revision 216)
@@ -0,0 +1,296 @@
+#
+# eco32.ucf -- ECO32 user constraints for S3E starter kit board
+#
+
+#
+# clock and reset
+#
+NET "clk_in"
+ PERIOD = 20.0ns HIGH 40%;
+NET "clk_in"
+ LOC = "C9" | IOSTANDARD = LVCMOS33;
+NET "reset_in"
+ LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
+
+#
+# DDR SDRAM
+#
+NET "sdram_ck_p"
+ LOC = "J5" | IOSTANDARD = SSTL2_I;
+NET "sdram_ck_n"
+ LOC = "J4" | IOSTANDARD = SSTL2_I;
+NET "sdram_cke"
+ LOC = "K3" | IOSTANDARD = SSTL2_I;
+NET "sdram_cs_n"
+ LOC = "K4" | IOSTANDARD = SSTL2_I;
+NET "sdram_ras_n"
+ LOC = "C1" | IOSTANDARD = SSTL2_I;
+NET "sdram_cas_n"
+ LOC = "C2" | IOSTANDARD = SSTL2_I;
+NET "sdram_we_n"
+ LOC = "D1" | IOSTANDARD = SSTL2_I;
+NET "sdram_ba<1>"
+ LOC = "K6" | IOSTANDARD = SSTL2_I;
+NET "sdram_ba<0>"
+ LOC = "K5" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<12>"
+ LOC = "P2" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<11>"
+ LOC = "N5" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<10>"
+ LOC = "T2" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<9>"
+ LOC = "N4" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<8>"
+ LOC = "H2" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<7>"
+ LOC = "H1" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<6>"
+ LOC = "H3" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<5>"
+ LOC = "H4" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<4>"
+ LOC = "F4" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<3>"
+ LOC = "P1" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<2>"
+ LOC = "R2" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<1>"
+ LOC = "R3" | IOSTANDARD = SSTL2_I;
+NET "sdram_a<0>"
+ LOC = "T1" | IOSTANDARD = SSTL2_I;
+NET "sdram_udm"
+ LOC = "J1" | IOSTANDARD = SSTL2_I;
+NET "sdram_ldm"
+ LOC = "J2" | IOSTANDARD = SSTL2_I;
+NET "sdram_udqs"
+ LOC = "G3" | IOSTANDARD = SSTL2_I;
+NET "sdram_ldqs"
+ LOC = "L6" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<15>"
+ LOC = "H5" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<14>"
+ LOC = "H6" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<13>"
+ LOC = "G5" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<12>"
+ LOC = "G6" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<11>"
+ LOC = "F2" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<10>"
+ LOC = "F1" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<9>"
+ LOC = "E1" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<8>"
+ LOC = "E2" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<7>"
+ LOC = "M6" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<6>"
+ LOC = "M5" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<5>"
+ LOC = "M4" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<4>"
+ LOC = "M3" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<3>"
+ LOC = "L4" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<2>"
+ LOC = "L3" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<1>"
+ LOC = "L1" | IOSTANDARD = SSTL2_I;
+NET "sdram_dq<0>"
+ LOC = "L2" | IOSTANDARD = SSTL2_I;
+
+#
+# prohibit VREF pins
+#
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+
+#
+# parallel NOR flash ROM
+#
+NET "flash_ce_n"
+ LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_oe_n"
+ LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_we_n"
+ LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_byte_n"
+ LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<23>"
+ LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<22>"
+ LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<21>"
+ LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<20>"
+ LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<19>"
+ LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<18>"
+ LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<17>"
+ LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<16>"
+ LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<15>"
+ LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<14>"
+ LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<13>"
+ LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<12>"
+ LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<11>"
+ LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<10>"
+ LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<9>"
+ LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<8>"
+ LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<7>"
+ LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<6>"
+ LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<5>"
+ LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<4>"
+ LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<3>"
+ LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<2>"
+ LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<1>"
+ LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_a<0>"
+ LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<15>"
+ LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<14>"
+ LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<13>"
+ LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<12>"
+ LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<11>"
+ LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<10>"
+ LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<9>"
+ LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<8>"
+ LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<7>"
+ LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<6>"
+ LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<5>"
+ LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<4>"
+ LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<3>"
+ LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<2>"
+ LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<1>"
+ LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "flash_d<0>"
+ LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+
+#
+# VGA display
+#
+NET "vga_hsync"
+ LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
+NET "vga_vsync"
+ LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
+NET "vga_r"
+ LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
+NET "vga_g"
+ LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
+NET "vga_b"
+ LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST;
+
+#
+# keyboard
+#
+NET "ps2_clk"
+ LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
+NET "ps2_data"
+ LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
+
+#
+# serial line 0
+#
+NET "rs232_0_rxd"
+ LOC = "R7" | IOSTANDARD = LVTTL;
+NET "rs232_0_txd"
+ LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+
+#
+# serial line 1
+#
+NET "rs232_1_rxd"
+ LOC = "U8" | IOSTANDARD = LVTTL;
+NET "rs232_1_txd"
+ LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+
+#
+# SPI bus controller
+#
+NET "spi_sck"
+ LOC = "U16" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+NET "spi_mosi"
+ LOC = "T4" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+NET "dac_cs_n"
+ LOC = "N8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
+NET "dac_clr_n"
+ LOC = "P8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
+NET "amp_cs_n"
+ LOC = "N7" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+NET "amp_shdn"
+ LOC = "P7" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+NET "ad_conv"
+ LOC = "P11" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+
+#
+# board I/O
+#
+NET "sw<3>"
+ LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
+NET "sw<2>"
+ LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
+NET "sw<1>"
+ LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
+NET "sw<0>"
+ LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
+NET "led<7>"
+ LOC = "F9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<6>"
+ LOC = "E9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<5>"
+ LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<4>"
+ LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<3>"
+ LOC = "F11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<2>"
+ LOC = "E11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<1>"
+ LOC = "E12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "led<0>"
+ LOC = "F12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW;
+NET "lcd_e"
+ LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "lcd_rw"
+ LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "lcd_rs"
+ LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;
+NET "spi_ss_b"
+ LOC = "U3" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW;
+NET "fpga_init_b"
+ LOC = "T3" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW;