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/trunk/fpga/src/ram/sdramcntl.vhd
File deleted
/trunk/fpga/src/ram/ram.v
File deleted
/trunk/fpga/src/ram/sdr/ram.v
0,0 → 1,332
// |
// ram.v -- main memory, using SDRAM |
// |
|
|
module ram(clk, clk_ok, reset, |
en, wr, size, addr, |
data_in, data_out, wt, |
sdram_cke, sdram_cs_n, |
sdram_ras_n, sdram_cas_n, |
sdram_we_n, sdram_ba, sdram_a, |
sdram_udqm, sdram_ldqm, sdram_dq); |
// internal interface signals |
input clk; |
input clk_ok; |
input reset; |
input en; |
input wr; |
input [1:0] size; |
input [24:0] addr; |
input [31:0] data_in; |
output reg [31:0] data_out; |
output reg wt; |
// SDRAM interface signals |
output sdram_cke; |
output sdram_cs_n; |
output sdram_ras_n; |
output sdram_cas_n; |
output sdram_we_n; |
output [1:0] sdram_ba; |
output [12:0] sdram_a; |
output sdram_udqm; |
output sdram_ldqm; |
inout [15:0] sdram_dq; |
|
reg [3:0] state; |
reg a0; |
reg cntl_read; |
reg cntl_write; |
wire cntl_done; |
wire [23:0] cntl_addr; |
reg [15:0] cntl_din; |
wire [15:0] cntl_dout; |
|
wire sd_out_en; |
wire [15:0] sd_out; |
|
//-------------------------------------------------------------- |
|
sdramCntl sdramCntl1( |
// clock |
.clk(clk), |
.clk_ok(clk_ok), |
// host side |
.rd(cntl_read & ~cntl_done), |
.wr(cntl_write & ~cntl_done), |
.done(cntl_done), |
.hAddr(cntl_addr), |
.hDIn(cntl_din), |
.hDOut(cntl_dout), |
// SDRAM side |
.cke(sdram_cke), |
.ce_n(sdram_cs_n), |
.ras_n(sdram_ras_n), |
.cas_n(sdram_cas_n), |
.we_n(sdram_we_n), |
.ba(sdram_ba), |
.sAddr(sdram_a), |
.sDIn(sdram_dq), |
.sDOut(sd_out), |
.sDOutEn(sd_out_en), |
.dqmh(sdram_udqm), |
.dqml(sdram_ldqm) |
); |
|
assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz; |
|
//-------------------------------------------------------------- |
|
// the SDRAM is organized in 16-bit halfwords |
// address line 0 is controlled by the state machine |
// (this is necessary for word accesses) |
assign cntl_addr[23:1] = addr[24:2]; |
assign cntl_addr[0] = a0; |
|
// state machine for SDRAM access |
always @(posedge clk) begin |
if (reset == 1) begin |
state <= 4'b0000; |
wt <= 1; |
end else begin |
case (state) |
4'b0000: |
// wait for access |
begin |
if (en == 1) begin |
// access |
if (wr == 1) begin |
// write |
if (size[1] == 1) begin |
// write word |
state <= 4'b0001; |
end else begin |
if (size[0] == 1) begin |
// write halfword |
state <= 4'b0101; |
end else begin |
// write byte |
state <= 4'b0111; |
end |
end |
end else begin |
// read |
if (size[1] == 1) begin |
// read word |
state <= 4'b0011; |
end else begin |
if (size[0] == 1) begin |
// read halfword |
state <= 4'b0110; |
end else begin |
// read byte |
state <= 4'b1001; |
end |
end |
end |
end |
end |
4'b0001: |
// write word, upper 16 bits |
begin |
if (cntl_done == 1) begin |
state <= 4'b0010; |
end |
end |
4'b0010: |
// write word, lower 16 bits |
begin |
if (cntl_done == 1) begin |
state <= 4'b1111; |
wt <= 0; |
end |
end |
4'b0011: |
// read word, upper 16 bits |
begin |
if (cntl_done == 1) begin |
state <= 4'b0100; |
data_out[31:16] <= cntl_dout; |
end |
end |
4'b0100: |
// read word, lower 16 bits |
begin |
if (cntl_done == 1) begin |
state <= 4'b1111; |
data_out[15:0] <= cntl_dout; |
wt <= 0; |
end |
end |
4'b0101: |
// write halfword |
begin |
if (cntl_done == 1) begin |
state <= 4'b1111; |
wt <= 0; |
end |
end |
4'b0110: |
// read halfword |
begin |
if (cntl_done == 1) begin |
state <= 4'b1111; |
data_out[31:16] <= 16'h0000; |
data_out[15:0] <= cntl_dout; |
wt <= 0; |
end |
end |
4'b0111: |
// write byte (read halfword cycle) |
begin |
if (cntl_done == 1) begin |
state <= 4'b1000; |
data_out[31:16] <= 16'h0000; |
data_out[15:0] <= cntl_dout; |
end |
end |
4'b1000: |
// write byte (write halfword cycle) |
begin |
if (cntl_done == 1) begin |
state <= 4'b1111; |
wt <= 0; |
end |
end |
4'b1001: |
// read byte |
begin |
if (cntl_done == 1) begin |
state <= 4'b1111; |
data_out[31:8] <= 24'h000000; |
if (addr[0] == 0) begin |
data_out[7:0] <= cntl_dout[15:8]; |
end else begin |
data_out[7:0] <= cntl_dout[7:0]; |
end |
wt <= 0; |
end |
end |
4'b1111: |
// end of bus cycle |
begin |
state <= 4'b0000; |
wt <= 1; |
end |
default: |
// all other states: reset |
begin |
state <= 4'b0000; |
wt <= 1; |
end |
endcase |
end |
end |
|
// output of state machine |
always @(*) begin |
case (state) |
4'b0000: |
// wait for access |
begin |
a0 = 1'bx; |
cntl_read = 0; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
4'b0001: |
// write word, upper 16 bits |
begin |
a0 = 1'b0; |
cntl_read = 0; |
cntl_write = 1; |
cntl_din = data_in[31:16]; |
end |
4'b0010: |
// write word, lower 16 bits |
begin |
a0 = 1'b1; |
cntl_read = 0; |
cntl_write = 1; |
cntl_din = data_in[15:0]; |
end |
4'b0011: |
// read word, upper 16 bits |
begin |
a0 = 1'b0; |
cntl_read = 1; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
4'b0100: |
// read word, lower 16 bits |
begin |
a0 = 1'b1; |
cntl_read = 1; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
4'b0101: |
// write halfword |
begin |
a0 = addr[1]; |
cntl_read = 0; |
cntl_write = 1; |
cntl_din = data_in[15:0]; |
end |
4'b0110: |
// read halfword |
begin |
a0 = addr[1]; |
cntl_read = 1; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
4'b0111: |
// write byte (read halfword cycle) |
begin |
a0 = addr[1]; |
cntl_read = 1; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
4'b1000: |
// write byte (write halfword cycle) |
begin |
a0 = addr[1]; |
cntl_read = 0; |
cntl_write = 1; |
if (addr[0] == 0) begin |
cntl_din = { data_in[7:0], data_out[7:0] }; |
end else begin |
cntl_din = { data_out[15:8], data_in[7:0] }; |
end |
end |
4'b1001: |
// read byte |
begin |
a0 = addr[1]; |
cntl_read = 1; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
4'b1111: |
// end of bus cycle |
begin |
a0 = 1'bx; |
cntl_read = 0; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
default: |
// all other states: reset |
begin |
a0 = 1'bx; |
cntl_read = 0; |
cntl_write = 0; |
cntl_din = 16'hxxxx; |
end |
endcase |
end |
|
endmodule |
/trunk/fpga/src/ram/sdr/sdramcntl.vhd
0,0 → 1,596
-------------------------------------------------------------------- |
-- Company : XESS Corp. |
-- Engineer : Dave Vanden Bout |
-- Creation Date : 05/17/2005 |
-- Copyright : 2005, XESS Corp |
-- Tool Versions : WebPACK 6.3.03i |
-- |
-- Description: |
-- SDRAM controller |
-- |
-- Revision: |
-- n.a. (because of hacking by Hellwig Geisse) |
-- |
-- Additional Comments: |
-- 1.4.0: |
-- Added generic parameter to enable/disable independent active rows in each bank. |
-- 1.3.0: |
-- Modified to allow independently active rows in each bank. |
-- 1.2.0: |
-- Modified to allow pipelining of read/write operations. |
-- 1.1.0: |
-- Initial release. |
-- |
-- License: |
-- This code can be freely distributed and modified as long as |
-- this header is not removed. |
-------------------------------------------------------------------- |
|
library IEEE, UNISIM; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.numeric_std.all; |
|
entity sdramCntl is |
port( |
-- host side |
clk : in std_logic; -- master clock |
clk_ok : in std_logic; -- true if clock is stable |
rd : in std_logic; -- initiate read operation |
wr : in std_logic; -- initiate write operation |
done : out std_logic; -- read or write operation is done |
hAddr : in std_logic_vector(23 downto 0); -- address from host to SDRAM |
hDIn : in std_logic_vector(15 downto 0); -- data from host to SDRAM |
hDOut : out std_logic_vector(15 downto 0); -- data from SDRAM to host |
|
-- SDRAM side |
cke : out std_logic; -- clock-enable to SDRAM |
ce_n : out std_logic; -- chip-select to SDRAM |
ras_n : out std_logic; -- SDRAM row address strobe |
cas_n : out std_logic; -- SDRAM column address strobe |
we_n : out std_logic; -- SDRAM write enable |
ba : out std_logic_vector(1 downto 0); -- SDRAM bank address |
sAddr : out std_logic_vector(12 downto 0); -- SDRAM row/column address |
sDIn : in std_logic_vector(15 downto 0); -- data from SDRAM |
sDOut : out std_logic_vector(15 downto 0); -- data to SDRAM |
sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut |
dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true |
dqml : out std_logic -- enable lower-byte of SDRAM databus if true |
); |
end sdramCntl; |
|
|
architecture arch of sdramCntl is |
|
constant YES : std_logic := '1'; |
constant NO : std_logic := '0'; |
|
-- select one of two integers based on a Boolean |
function int_select(s : in boolean; a : in integer; b : in integer) return integer is |
begin |
if s then |
return a; |
else |
return b; |
end if; |
return a; |
end function int_select; |
|
constant OUTPUT : std_logic := '1'; -- direction of dataflow w.r.t. this controller |
constant INPUT : std_logic := '0'; |
constant NOP : std_logic := '0'; -- no operation |
constant READ : std_logic := '1'; -- read operation |
constant WRITE : std_logic := '1'; -- write operation |
|
-- SDRAM timing parameters |
constant Tinit : natural := 200; -- min initialization interval (us) |
constant Tras : natural := 45; -- min interval between active to precharge commands (ns) |
constant Trcd : natural := 20; -- min interval between active and R/W commands (ns) |
constant Tref : natural := 64_000_000; -- maximum refresh interval (ns) |
constant Trfc : natural := 66; -- duration of refresh operation (ns) |
constant Trp : natural := 20; -- min precharge command duration (ns) |
constant Twr : natural := 15; -- write recovery time (ns) |
constant Txsr : natural := 75; -- exit self-refresh time (ns) |
|
-- SDRAM timing parameters converted into clock cycles (based on FREQ = 50_000) |
constant NORM : natural := 1_000_000; -- normalize ns * KHz |
constant INIT_CYCLES : natural := 1+((Tinit*50_000)/1000); -- SDRAM power-on initialization interval |
constant RAS_CYCLES : natural := 1+((Tras*50_000)/NORM); -- active-to-precharge interval |
constant RCD_CYCLES : natural := 1+((Trcd*50_000)/NORM); -- active-to-R/W interval |
constant REF_CYCLES : natural := 1+(((Tref/8192)*50_000)/NORM); -- interval between row refreshes |
constant RFC_CYCLES : natural := 1+((Trfc*50_000)/NORM); -- refresh operation interval |
constant RP_CYCLES : natural := 1+((Trp*50_000)/NORM); -- precharge operation interval |
constant WR_CYCLES : natural := 1+((Twr*50_000)/NORM); -- write recovery time |
constant XSR_CYCLES : natural := 1+((Txsr*50_000)/NORM); -- exit self-refresh time |
constant MODE_CYCLES : natural := 2; -- mode register setup time |
constant CAS_CYCLES : natural := 3; -- CAS latency |
constant RFSH_OPS : natural := 8; -- number of refresh operations needed to init SDRAM |
|
-- timer registers that count down times for various SDRAM operations |
signal timer_r, timer_x : natural range 0 to INIT_CYCLES; -- current SDRAM op time |
signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES; -- active-to-precharge time |
signal wrTimer_r, wrTimer_x : natural range 0 to WR_CYCLES; -- write-to-precharge time |
signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES; -- time between row refreshes |
signal rfshCntr_r, rfshCntr_x : natural range 0 to 8192; -- counts refreshes that are neede |
signal nopCntr_r, nopCntr_x : natural range 0 to 10000; -- counts consecutive NOP operations |
|
signal doSelfRfsh : std_logic; -- active when the NOP counter hits zero and self-refresh can start |
|
-- states of the SDRAM controller state machine |
type cntlState is ( |
INITWAIT, -- initialization - waiting for power-on initialization to complete |
INITPCHG, -- initialization - initial precharge of SDRAM banks |
INITSETMODE, -- initialization - set SDRAM mode |
INITRFSH, -- initialization - do initial refreshes |
RW, -- read/write/refresh the SDRAM |
ACTIVATE, -- open a row of the SDRAM for reading/writing |
REFRESHROW, -- refresh a row of the SDRAM |
SELFREFRESH -- keep SDRAM in self-refresh mode with CKE low |
); |
signal state_r, state_x : cntlState; -- state register and next state |
|
-- commands that are sent to the SDRAM to make it perform certain operations |
-- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml) |
subtype sdramCmd is unsigned(5 downto 0); |
constant NOP_CMD : sdramCmd := "011100"; |
constant ACTIVE_CMD : sdramCmd := "001100"; |
constant READ_CMD : sdramCmd := "010100"; |
constant WRITE_CMD : sdramCmd := "010000"; |
constant PCHG_CMD : sdramCmd := "001011"; |
constant MODE_CMD : sdramCmd := "000011"; |
constant RFSH_CMD : sdramCmd := "000111"; |
|
-- SDRAM mode register |
-- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS |
subtype sdramMode is std_logic_vector(12 downto 0); |
constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000"; |
|
-- the host address is decomposed into these sets of SDRAM address components |
constant ROW_LEN : natural := 13; -- number of row address bits |
constant COL_LEN : natural := 9; -- number of column address bits |
signal bank : std_logic_vector(ba'range); -- bank address bits |
signal row : std_logic_vector(ROW_LEN - 1 downto 0); -- row address within bank |
signal col : std_logic_vector(sAddr'range); -- column address within row |
|
-- registers that store the currently active row in each bank of the SDRAM |
constant NUM_ACTIVE_ROWS : integer := 1; |
type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range); |
signal activeRow_r, activeRow_x : activeRowType; |
signal activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1); -- indicates that some row in a bank is active |
signal bankIndex : natural range 0 to NUM_ACTIVE_ROWS-1; -- bank address bits |
signal activeBank_r, activeBank_x : std_logic_vector(ba'range); -- indicates the bank with the active row |
signal doActivate : std_logic; -- indicates when a new row in a bank needs to be activated |
|
-- there is a command bit embedded within the SDRAM column address |
constant CMDBIT_POS : natural := 10; -- position of command bit |
constant AUTO_PCHG_ON : std_logic := '1'; -- CMDBIT value to auto-precharge the bank |
constant AUTO_PCHG_OFF : std_logic := '0'; -- CMDBIT value to disable auto-precharge |
constant ONE_BANK : std_logic := '0'; -- CMDBIT value to select one bank |
constant ALL_BANKS : std_logic := '1'; -- CMDBIT value to select all banks |
|
-- status signals that indicate when certain operations are in progress |
signal wrInProgress : std_logic; -- write operation in progress |
signal rdInProgress : std_logic; -- read operation in progress |
signal activateInProgress : std_logic; -- row activation is in progress |
|
-- these registers track the progress of read and write operations |
signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0); -- pipeline of read ops in progress |
signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0); -- pipeline of write ops (only need 1 cycle) |
|
-- registered outputs to host |
signal hDOut_r, hDOut_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM and sent to the host |
|
-- registered outputs to SDRAM |
signal cke_r, cke_x : std_logic; -- clock enable |
signal cmd_r, cmd_x : sdramCmd; -- SDRAM command bits |
signal ba_r, ba_x : std_logic_vector(ba'range); -- SDRAM bank address bits |
signal sAddr_r, sAddr_x : std_logic_vector(sAddr'range); -- SDRAM row/column address |
signal sData_r, sData_x : std_logic_vector(sDOut'range); -- SDRAM out databus |
signal sDataDir_r, sDataDir_x : std_logic; -- SDRAM databus direction control bit |
|
begin |
|
----------------------------------------------------------- |
-- attach some internal signals to the I/O ports |
----------------------------------------------------------- |
|
-- attach registered SDRAM control signals to SDRAM input pins |
(ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r; -- SDRAM operation control bits |
cke <= cke_r; -- SDRAM clock enable |
ba <= ba_r; -- SDRAM bank address |
sAddr <= sAddr_r; -- SDRAM address |
sDOut <= sData_r; -- SDRAM output data bus |
sDOutEn <= YES when sDataDir_r = OUTPUT else NO; -- output databus enable |
|
-- attach some port signals |
hDOut <= hDOut_r; -- data back to host |
|
|
----------------------------------------------------------- |
-- compute the next state and outputs |
----------------------------------------------------------- |
|
combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r, |
activeFlag_r, activeRow_r, activeBank_r, |
rdPipeline_r, wrPipeline_r, |
nopCntr_r, rfshCntr_r, timer_r, rasTimer_r, |
wrTimer_r, refTimer_r, cmd_r, cke_r) |
begin |
|
----------------------------------------------------------- |
-- setup default values for signals |
----------------------------------------------------------- |
|
cke_x <= YES; -- enable SDRAM clock |
cmd_x <= NOP_CMD; -- set SDRAM command to no-operation |
sDataDir_x <= INPUT; -- accept data from the SDRAM |
sData_x <= hDIn(sData_x'range); -- output data from host to SDRAM |
state_x <= state_r; -- reload these registers and flags |
activeFlag_x <= activeFlag_r; -- with their existing values |
activeRow_x <= activeRow_r; |
activeBank_x <= activeBank_r; |
rfshCntr_x <= rfshCntr_r; |
|
----------------------------------------------------------- |
-- setup default value for the SDRAM address |
----------------------------------------------------------- |
|
-- extract bank field from host address |
ba_x <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN); |
bank <= ba_x; |
bankIndex <= 0; |
-- extract row, column fields from host address |
row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN); |
-- extend column (if needed) until it is as large as the (SDRAM address bus - 1) |
col <= (others => '0'); -- set it to all zeroes |
col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0); |
-- by default, set SDRAM address to the column address with interspersed |
-- command bit set to disable auto-precharge |
sAddr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF |
& col(CMDBIT_POS-1 downto 0); |
|
----------------------------------------------------------- |
-- manage the read and write operation pipelines |
----------------------------------------------------------- |
|
-- determine if read operations are in progress by the presence of |
-- READ flags in the read pipeline |
if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then |
rdInProgress <= YES; |
else |
rdInProgress <= NO; |
end if; |
|
-- enter NOPs into the read and write pipeline shift registers by default |
rdPipeline_x <= NOP & rdPipeline_r(rdPipeline_r'high downto 1); |
wrPipeline_x(0) <= NOP; |
|
-- transfer data from SDRAM to the host data register if a read flag has exited the pipeline |
-- (the transfer occurs 1 cycle before we tell the host the read operation is done) |
if rdPipeline_r(1) = READ then |
-- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase |
hDOut_x <= sDIn(hDOut'range); |
else |
-- retain contents of host data registers if no data from the SDRAM has arrived yet |
hDOut_x <= hDOut_r; |
end if; |
|
done <= rdPipeline_r(0) or wrPipeline_r(0); -- a read or write operation is done |
|
----------------------------------------------------------- |
-- manage row activation |
----------------------------------------------------------- |
|
-- request a row activation operation if the row of the current address |
-- does not match the currently active row in the bank, or if no row |
-- in the bank is currently active |
if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then |
doActivate <= YES; |
else |
doActivate <= NO; |
end if; |
|
----------------------------------------------------------- |
-- manage self-refresh |
----------------------------------------------------------- |
|
-- enter self-refresh if neither a read or write is requested for 10000 consecutive cycles. |
if (rd = YES) or (wr = YES) then |
-- any read or write resets NOP counter and exits self-refresh state |
nopCntr_x <= 0; |
doSelfRfsh <= NO; |
elsif nopCntr_r /= 10000 then |
-- increment NOP counter whenever there is no read or write operation |
nopCntr_x <= nopCntr_r + 1; |
doSelfRfsh <= NO; |
else |
-- start self-refresh when counter hits maximum NOP count and leave counter unchanged |
nopCntr_x <= nopCntr_r; |
doSelfRfsh <= YES; |
end if; |
|
----------------------------------------------------------- |
-- update the timers |
----------------------------------------------------------- |
|
-- row activation timer |
if rasTimer_r /= 0 then |
-- decrement a non-zero timer and set the flag |
-- to indicate the row activation is still inprogress |
rasTimer_x <= rasTimer_r - 1; |
activateInProgress <= YES; |
else |
-- on timeout, keep the timer at zero and reset the flag |
-- to indicate the row activation operation is done |
rasTimer_x <= rasTimer_r; |
activateInProgress <= NO; |
end if; |
|
-- write operation timer |
if wrTimer_r /= 0 then |
-- decrement a non-zero timer and set the flag |
-- to indicate the write operation is still inprogress |
wrTimer_x <= wrTimer_r - 1; |
wrInPRogress <= YES; |
else |
-- on timeout, keep the timer at zero and reset the flag that |
-- indicates a write operation is in progress |
wrTimer_x <= wrTimer_r; |
wrInPRogress <= NO; |
end if; |
|
-- refresh timer |
if refTimer_r /= 0 then |
refTimer_x <= refTimer_r - 1; |
else |
-- on timeout, reload the timer with the interval between row refreshes |
-- and increment the counter for the number of row refreshes that are needed |
refTimer_x <= REF_CYCLES; |
rfshCntr_x <= rfshCntr_r + 1; |
end if; |
|
-- main timer for sequencing SDRAM operations |
if timer_r /= 0 then |
-- decrement the timer and do nothing else since the previous operation has not completed yet. |
timer_x <= timer_r - 1; |
else |
-- the previous operation has completed once the timer hits zero |
timer_x <= timer_r; -- by default, leave the timer at zero |
|
----------------------------------------------------------- |
-- compute the next state and outputs |
----------------------------------------------------------- |
case state_r is |
|
----------------------------------------------------------- |
-- let clock stabilize and then wait for the SDRAM to initialize |
----------------------------------------------------------- |
when INITWAIT => |
-- wait for SDRAM power-on initialization once the clock is stable |
timer_x <= INIT_CYCLES; -- set timer for initialization duration |
state_x <= INITPCHG; |
|
----------------------------------------------------------- |
-- precharge all SDRAM banks after power-on initialization |
----------------------------------------------------------- |
when INITPCHG => |
cmd_x <= PCHG_CMD; |
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks |
timer_x <= RP_CYCLES; -- set timer for precharge operation duration |
rfshCntr_x <= RFSH_OPS; -- set counter for refresh ops needed after precharge |
state_x <= INITRFSH; |
|
----------------------------------------------------------- |
-- refresh the SDRAM a number of times after initial precharge |
----------------------------------------------------------- |
when INITRFSH => |
cmd_x <= RFSH_CMD; |
timer_x <= RFC_CYCLES; -- set timer to refresh operation duration |
rfshCntr_x <= rfshCntr_r - 1; -- decrement refresh operation counter |
if rfshCntr_r = 1 then |
state_x <= INITSETMODE; -- set the SDRAM mode once all refresh ops are done |
end if; |
|
----------------------------------------------------------- |
-- set the mode register of the SDRAM |
----------------------------------------------------------- |
when INITSETMODE => |
cmd_x <= MODE_CMD; |
sAddr_x <= MODE; -- output mode register bits on the SDRAM address bits |
timer_x <= MODE_CYCLES; -- set timer for mode setting operation duration |
state_x <= RW; |
|
----------------------------------------------------------- |
-- process read/write/refresh operations after initialization is done |
----------------------------------------------------------- |
when RW => |
----------------------------------------------------------- |
-- highest priority operation: row refresh |
-- do a refresh operation if the refresh counter is non-zero |
----------------------------------------------------------- |
if rfshCntr_r /= 0 then |
-- wait for any row activations, writes or reads to finish before doing a precharge |
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then |
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM |
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks |
timer_x <= RP_CYCLES; -- set timer for this operation |
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation |
state_x <= REFRESHROW; -- refresh the SDRAM after the precharge |
end if; |
----------------------------------------------------------- |
-- do a host-initiated read operation |
----------------------------------------------------------- |
elsif rd = YES then |
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row. |
-- This gives extra time for the row activation circuitry. |
if (true) then |
-- activate a new row if the current read is outside the active row or bank |
if doActivate = YES then |
-- activate new row only if all previous activations, writes, reads are done |
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then |
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM |
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank |
timer_x <= RP_CYCLES; -- set timer for this operation |
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation |
state_x <= ACTIVATE; -- activate the new row after the precharge is done |
end if; |
-- read from the currently active row if no previous read operation |
-- is in progress or if pipeline reads are enabled |
-- we can always initiate a read even if a write is already in progress |
elsif (rdInProgress = NO) then |
cmd_x <= READ_CMD; -- initiate a read of the SDRAM |
-- insert a flag into the pipeline shift register that will exit the end |
-- of the shift register when the data from the SDRAM is available |
rdPipeline_x <= READ & rdPipeline_r(rdPipeline_r'high downto 1); |
end if; |
end if; |
----------------------------------------------------------- |
-- do a host-initiated write operation |
----------------------------------------------------------- |
elsif wr = YES then |
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row. |
-- This gives extra time for the row activation circuitry. |
if (true) then |
-- activate a new row if the current write is outside the active row or bank |
if doActivate = YES then |
-- activate new row only if all previous activations, writes, reads are done |
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then |
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM |
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank |
timer_x <= RP_CYCLES; -- set timer for this operation |
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation |
state_x <= ACTIVATE; -- activate the new row after the precharge is done |
end if; |
-- write to the currently active row if no previous read operations are in progress |
elsif rdInProgress = NO then |
cmd_x <= WRITE_CMD; -- initiate the write operation |
sDataDir_x <= OUTPUT; -- turn on drivers to send data to SDRAM |
-- set timer so precharge doesn't occur too soon after write operation |
wrTimer_x <= WR_CYCLES; |
-- insert a flag into the 1-bit pipeline shift register that will exit on the |
-- next cycle. The write into SDRAM is not actually done by that time, but |
-- this doesn't matter to the host |
wrPipeline_x(0) <= WRITE; |
end if; |
end if; |
----------------------------------------------------------- |
-- do a host-initiated self-refresh operation |
----------------------------------------------------------- |
elsif doSelfRfsh = YES then |
-- wait until all previous activations, writes, reads are done |
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then |
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM |
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks |
timer_x <= RP_CYCLES; -- set timer for this operation |
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation |
state_x <= SELFREFRESH; -- self-refresh the SDRAM after the precharge |
end if; |
----------------------------------------------------------- |
-- no operation |
----------------------------------------------------------- |
else |
state_x <= RW; -- continue to look for SDRAM operations to execute |
end if; |
|
----------------------------------------------------------- |
-- activate a row of the SDRAM |
----------------------------------------------------------- |
when ACTIVATE => |
cmd_x <= ACTIVE_CMD; |
sAddr_x <= (others => '0'); -- output the address for the row to be activated |
sAddr_x(row'range) <= row; |
activeBank_x <= bank; |
activeRow_x(bankIndex) <= row; -- store the new active SDRAM row address |
activeFlag_x(bankIndex) <= YES; -- the SDRAM is now active |
rasTimer_x <= RAS_CYCLES; -- minimum time before another precharge can occur |
timer_x <= RCD_CYCLES; -- minimum time before a read/write operation can occur |
state_x <= RW; -- return to do read/write operation that initiated this activation |
|
----------------------------------------------------------- |
-- refresh a row of the SDRAM |
----------------------------------------------------------- |
when REFRESHROW => |
cmd_x <= RFSH_CMD; |
timer_x <= RFC_CYCLES; -- refresh operation interval |
rfshCntr_x <= rfshCntr_r - 1; -- decrement the number of needed row refreshes |
state_x <= RW; -- process more SDRAM operations after refresh is done |
|
----------------------------------------------------------- |
-- place the SDRAM into self-refresh and keep it there until further notice |
----------------------------------------------------------- |
when SELFREFRESH => |
if (doSelfRfsh = YES) then |
-- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock |
cmd_x <= RFSH_CMD; -- output the refresh command; this is only needed on the first clock cycle |
cke_x <= NO; -- disable the SDRAM clock |
else |
-- else exit self-refresh mode and start processing read and write operations |
cke_x <= YES; -- restart the SDRAM clock |
rfshCntr_x <= 0; -- no refreshes are needed immediately after leaving self-refresh |
activeFlag_x <= (others => NO); -- self-refresh deactivates all rows |
timer_x <= XSR_CYCLES; -- wait this long until read and write operations can resume |
state_x <= RW; |
end if; |
|
----------------------------------------------------------- |
-- unknown state |
----------------------------------------------------------- |
when others => |
state_x <= INITWAIT; -- reset state if in erroneous state |
|
end case; |
end if; |
end process combinatorial; |
|
|
----------------------------------------------------------- |
-- update registers on the appropriate clock edge |
----------------------------------------------------------- |
|
update : process(clk_ok, clk) |
begin |
|
if clk_ok = NO then |
-- asynchronous reset |
state_r <= INITWAIT; |
activeFlag_r <= (others => NO); |
rfshCntr_r <= 0; |
timer_r <= 0; |
refTimer_r <= REF_CYCLES; |
rasTimer_r <= 0; |
wrTimer_r <= 0; |
nopCntr_r <= 0; |
rdPipeline_r <= (others => '0'); |
wrPipeline_r <= (others => '0'); |
cke_r <= NO; |
cmd_r <= NOP_CMD; |
ba_r <= (others => '0'); |
sAddr_r <= (others => '0'); |
sData_r <= (others => '0'); |
sDataDir_r <= INPUT; |
hDOut_r <= (others => '0'); |
elsif rising_edge(clk) then |
state_r <= state_x; |
activeBank_r <= activeBank_x; |
activeRow_r <= activeRow_x; |
activeFlag_r <= activeFlag_x; |
rfshCntr_r <= rfshCntr_x; |
timer_r <= timer_x; |
refTimer_r <= refTimer_x; |
rasTimer_r <= rasTimer_x; |
wrTimer_r <= wrTimer_x; |
nopCntr_r <= nopCntr_x; |
rdPipeline_r <= rdPipeline_x; |
wrPipeline_r <= wrPipeline_x; |
cke_r <= cke_x; |
cmd_r <= cmd_x; |
ba_r <= ba_x; |
sAddr_r <= sAddr_x; |
sData_r <= sData_x; |
sDataDir_r <= sDataDir_x; |
hDOut_r <= hDOut_x; |
end if; |
|
end process update; |
|
end arch; |
/trunk/fpga/src/ram/ddr/ddr_sdram.v
0,0 → 1,752
//////////////////////////////////////////////////////////////////////////// |
// |
// Create Date: 02/11/07 |
// Last Change: 01/22/12 |
// Design Name: DDR SDRAM memory controller |
// Module Name: ddr_sdram |
// Description: memory controller for DDR SDRAM |
// hard coded for 8 Meg x 16 x 4 banks |
// |
// Revision: |
// Revision 0.01 - File Created |
// |
// Development platform: Spartan-3E Starter kit |
// |
// Copyright (C) 2007, Rick Huang |
// |
// Modifications by Hellwig Geisse, 2012 |
// - sd_CK_P and sd_CK_N supplied by this module |
// - DDR output registers for sd_CK_P and sd_CK_N added |
// - sd_CLK_O deleted |
// - debug output deleted |
// - burst mode sections of the state machine deleted |
// (have been commented out already) |
// - additional states SD_RD_DONE_1 and SD_WR_DONE_1 inserted |
// (in order to stretch the wACK_O signal, which is to be |
// recognized by external circuits clocked with 50 MHz) |
// - four "write byte" signals added to interface |
// (to allow 8 and 16 bit write operations too) |
// - mask registers UDM_reg_O and LDM_reg_O deleted |
// - DDR output registers for sd_UDM_O and sd_LDM_O added |
// - data_sample_en and its associated multiplexer removed |
// (apparently a debugging vehicle) |
// |
// This library is free software; you can redistribute it and/or |
// modify it under the terms of the GNU Lesser General Public |
// License as published by the Free Software Foundation; either |
// version 2.1 of the License, or (at your option) any later version. |
// |
// This library is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
// Lesser General Public License for more details. |
// |
// You should have received a copy of the GNU Lesser General Public |
// License along with this library; if not, write to the Free Software |
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
// MA 02110-1301 USA |
// |
//////////////////////////////////////////////////////////////////////////// |
|
module ddr_sdram(sd_CK_P, sd_CK_N, |
sd_A_O, sd_BA_O, sd_D_IO, |
sd_RAS_O, sd_CAS_O, sd_WE_O, |
sd_UDM_O, sd_LDM_O, |
sd_UDQS_IO, sd_LDQS_IO, |
sd_CS_O, sd_CKE_O, |
clk0, clk90, |
clk180, clk270, |
reset, |
wADR_I, wSTB_I, wWE_I, wWRB_I, |
wDAT_I, wDAT_O, wACK_O); |
// interface to DDR SDRAM memory |
output sd_CK_P; |
output sd_CK_N; |
output [12:0] sd_A_O; |
output [1:0] sd_BA_O; |
inout [15:0] sd_D_IO; |
output sd_RAS_O; |
output sd_CAS_O; |
output sd_WE_O; |
output sd_UDM_O; |
output sd_LDM_O; |
inout sd_UDQS_IO; |
inout sd_LDQS_IO; |
output sd_CS_O; |
output sd_CKE_O; |
// internal interface signals |
input clk0; |
input clk90; |
input clk180; |
input clk270; |
input reset; |
// A[25:24] = bank[1:0] |
// A[23:11] = row[12:0] |
// A[10: 2] = col[9:1] |
// (a specific combination of the 2+13+9=24 bits adresses |
// a 32-bit word which is transmitted as a burst of two |
// consecutive 16-bit halfwords in one clock cycle) |
input [25:2] wADR_I; |
input wSTB_I; |
input wWE_I; |
input [3:0] wWRB_I; |
input [31:0] wDAT_I; |
output [31:0] wDAT_O; |
output wACK_O; |
|
// Local data storage |
reg [5:0] sd_state; |
reg [3:0] init_state; |
reg [5:0] wait_count; |
reg [14:0] init_wait_count; |
reg [12:0] sd_A_O; |
reg [1:0] sd_BA_O; |
reg [12:0] mode_reg; |
reg sd_RAS_O; |
reg sd_CAS_O; |
reg sd_WE_O; |
reg sd_CS_O; |
reg sd_CKE_O; |
reg wACK_O; |
|
reg [9:0] refresh_counter; |
reg [3:0] refresh_queue; // Number of refresh command to queue |
reg refresh_now; |
reg refresh_ack; |
|
reg [31:0] D_rd_reg; |
reg DQS_state; |
reg DQS_oe; // 1 for output |
reg D_oe; // 1 for output enable |
|
reg [31:0] D_wr_reg; // Data write buffer |
reg [3:0] D_mask_reg; // data mask buffer |
|
|
/*************************************************** |
* SD ram clock source |
***************************************************/ |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), |
.INIT(1'b0), |
.SRTYPE("SYNC") |
) ODDR2_inst_CK_P ( |
.Q(sd_CK_P), |
.C0(clk180), |
.C1(clk0), |
.CE(1'b1), |
.D0(1'b1), |
.D1(1'b0), |
.R(1'b0), |
.S(1'b0) |
); |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), |
.INIT(1'b0), |
.SRTYPE("SYNC") |
) ODDR2_inst_CK_N ( |
.Q(sd_CK_N), |
.C0(clk0), |
.C1(clk180), |
.CE(1'b1), |
.D0(1'b1), |
.D1(1'b0), |
.R(1'b0), |
.S(1'b0) |
); |
|
/*************************************************** |
* De-duplex of the data path |
* For some reason, for read, the output is CL=2.5, not CL=2 |
* Thus, catching of the data is 1/2 a cycle late. |
* Flip the clk0 and clk180, 1/2 cycle delay catched |
* on data_mux_latch |
***************************************************/ |
|
// Data from SDRAM will be loaded at {data_mux_out[31:0]} |
wire [31:0] data_mux_out; |
wire [15:0] iddr_conn; |
wire [15:0] oddr_conn; |
|
|
generate |
genvar i; |
|
for(i=0;i<16;i=i+1) |
begin : iou |
IDDR2 #( |
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" |
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1 |
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1 |
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset |
) IDDR2_inst ( |
.Q0(data_mux_out[i]), // C0 clock |
.Q1(data_mux_out[i+16]), // C1 clock |
.C0(clk180), |
.C1(clk0), |
.CE(1'b1), // Always enabled |
.D(iddr_conn[i]), // 1-bit DDR data input |
.R(1'b0), // 1-bit reset input |
.S(1'b0) // 1-bit set input |
); |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" |
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 |
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset |
) ODDR2_inst ( |
.Q(oddr_conn[i]), // 1-bit DDR output data |
.C0(clk90), // 1-bit clock input |
.C1(clk270), // 1-bit clock input |
.CE(1'b1), // 1-bit clock enable input |
.D0(D_wr_reg[i]), // (associated with C0) |
.D1(D_wr_reg[i+16]), // (associated with C1) |
.R(1'b0), // 1-bit reset input |
.S(1'b0) // 1-bit set input |
); |
|
IOBUF #( |
.DRIVE(4), // Specify the output drive strength |
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay |
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" |
.IOSTANDARD("DEFAULT"), // Specify the I/O standard |
.SLEW("SLOW") // Specify the output slew rate |
) IOBUF_inst ( |
.O(iddr_conn[i]), // Buffer output |
.IO(sd_D_IO[i]), // Buffer inout port (connect directly to top-level port) |
.I(oddr_conn[i]), // Buffer input |
.T(~D_oe) // 3-state enable input |
); |
end |
endgenerate |
|
|
wire sd_UDQS_O; |
wire sd_LDQS_O; |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), |
.INIT(1'b0), |
.SRTYPE("SYNC") |
) ODDR2_inst_UDQS ( |
.Q(sd_UDQS_O), |
.C0(clk180), |
.C1(clk0), |
.CE(1'b1), |
.D0(DQS_state), |
.D1(1'b0), |
.R(1'b0), |
.S(1'b0) |
); |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), |
.INIT(1'b0), |
.SRTYPE("SYNC") |
) ODDR2_inst_LDQS ( |
.Q(sd_LDQS_O), |
.C0(clk180), |
.C1(clk0), |
.CE(1'b1), |
.D0(DQS_state), |
.D1(1'b0), |
.R(1'b0), |
.S(1'b0) |
); |
|
IOBUF #( |
.DRIVE(4), |
.IBUF_DELAY_VALUE("0"), |
.IFD_DELAY_VALUE("AUTO"), |
.IOSTANDARD("DEFAULT"), |
.SLEW("SLOW") |
) IOBUF_inst_UDQS ( |
// .O() intentionally not connected |
.IO(sd_UDQS_IO), |
.I(sd_UDQS_O), |
.T(~DQS_oe) |
); |
|
IOBUF #( |
.DRIVE(4), |
.IBUF_DELAY_VALUE("0"), |
.IFD_DELAY_VALUE("AUTO"), |
.IOSTANDARD("DEFAULT"), |
.SLEW("SLOW") |
) IOBUF_inst_LDQS ( |
// .O() intentionally not connected |
.IO(sd_LDQS_IO), |
.I(sd_LDQS_O), |
.T(~DQS_oe) |
); |
|
|
reg [31:0] data_mux_latch; |
always @ (posedge clk180) |
begin |
data_mux_latch <= data_mux_out; |
end |
|
/*************************************************** |
* Data bus flow direction control |
***************************************************/ |
|
assign wDAT_O = D_rd_reg[31:0]; |
|
// Mask output |
|
wire UDM_conn; |
wire LDM_conn; |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), |
.INIT(1'b0), |
.SRTYPE("SYNC") |
) ODDR2_inst_UDM ( |
.Q(UDM_conn), |
.C0(clk90), |
.C1(clk270), |
.CE(1'b1), |
.D0(~D_mask_reg[1]), |
.D1(~D_mask_reg[3]), |
.R(1'b0), |
.S(1'b0) |
); |
|
ODDR2 #( |
.DDR_ALIGNMENT("NONE"), |
.INIT(1'b0), |
.SRTYPE("SYNC") |
) ODDR2_inst_LDM ( |
.Q(LDM_conn), |
.C0(clk90), |
.C1(clk270), |
.CE(1'b1), |
.D0(~D_mask_reg[0]), |
.D1(~D_mask_reg[2]), |
.R(1'b0), |
.S(1'b0) |
); |
|
IOBUF #( |
.DRIVE(4), |
.IBUF_DELAY_VALUE("0"), |
.IFD_DELAY_VALUE("AUTO"), |
.IOSTANDARD("DEFAULT"), |
.SLEW("SLOW") |
) IOBUF_inst_UDM ( |
// .O() intentionally not connected |
.IO(sd_UDM_O), |
.I(UDM_conn), |
.T(1'b0) |
); |
|
IOBUF #( |
.DRIVE(4), |
.IBUF_DELAY_VALUE("0"), |
.IFD_DELAY_VALUE("AUTO"), |
.IOSTANDARD("DEFAULT"), |
.SLEW("SLOW") |
) IOBUF_inst_LDM ( |
// .O() intentionally not connected |
.IO(sd_LDM_O), |
.I(LDM_conn), |
.T(1'b0) |
); |
|
|
/*************************************************** |
* Main tx/rx state machine |
***************************************************/ |
|
/* Timing */ |
parameter WAIT_TIME = 5'd5; |
parameter INIT_WAIT = 15'h3000; |
parameter INIT_CLK_EN_WAIT = 15'h10; |
parameter WAIT_CMD_MAX = 6'b100000; |
parameter REFRESH_WAIT = WAIT_CMD_MAX - 6'd7; |
parameter ACCESS_WAIT = WAIT_CMD_MAX - 6'd1; |
parameter CAS_WAIT = WAIT_CMD_MAX - 6'd3; |
parameter AVG_REFRESH_DUR = 10'd700; |
|
/* Main state machine */ |
parameter SD_IDLE = 0, |
SD_INIT = 1, |
SD_INIT_WAIT = 2, |
SD_PRECHG_ALL = 3, |
SD_PRECHG_ALL1 = 4, |
SD_AUTO_REF = 5, |
SD_AUTO_REF1 = 6, |
SD_AUTO_REF_ACK = 7, |
SD_LD_MODE = 8, |
SD_LD_MODE1 = 9, |
SD_RD_START = 10, |
SD_RD_COL = 11, |
SD_RD_CAS_WAIT = 12, |
SD_RD_LATCH = 13, |
SD_RD_LATCH1 = 14, |
SD_RD_DONE = 15, |
SD_WR_START = 16, |
SD_WR_COL = 17, |
SD_WR_CAS_WAIT = 18, |
SD_WR_LATCH = 19, |
SD_WR_LATCH1 = 20, |
SD_WR_DONE = 21, |
SD_RD_DONE_1 = 22, |
SD_WR_DONE_1 = 23; |
|
/* Initialization state machine */ |
parameter SI_START = 0, |
SI_PRECHG = 1, |
SI_LOAD_EX_MODE = 2, |
SI_LOAD_MODE = 3, |
SI_LOAD_MODE2 = 4, |
SI_PRECHG2 = 5, |
SI_AUTO_REF = 6, |
SI_AUTO_REF2 = 7, |
SI_DONE = 8; |
|
|
always @ (posedge clk0) |
begin |
if(reset) |
begin |
sd_state <= SD_INIT; |
init_state <= SI_START; |
end else |
begin |
wait_count <= wait_count + 1; |
|
case (sd_state) |
SD_INIT: // Initialize, wait until INIT_WAIT |
begin |
case (init_state) |
SI_START: |
begin |
sd_state <= SD_INIT_WAIT; |
init_state <= SI_PRECHG; |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
sd_CS_O <= 1; |
sd_CKE_O <= 0; |
init_wait_count <= 16'd0; |
end |
SI_PRECHG: |
begin |
sd_state <= SD_PRECHG_ALL; |
init_state <= SI_LOAD_EX_MODE; |
end |
SI_LOAD_EX_MODE: |
begin |
// Normal operation |
mode_reg <= 13'b0000000000000; |
sd_BA_O <= 2'b01; |
sd_state <= SD_LD_MODE; |
init_state <= SI_LOAD_MODE; |
end |
SI_LOAD_MODE: |
begin |
// CAS = 2, Reset DLL, Burst = 2, sequential |
mode_reg <= {6'b000010, 3'b010, 1'b0, 3'b001}; |
sd_BA_O <= 2'b00; |
sd_state <= SD_LD_MODE; |
init_state <= SI_LOAD_MODE2; |
end |
SI_LOAD_MODE2: |
begin |
// CAS = 2, NO Reset DLL, Burst = 2, sequential |
mode_reg <= {6'b000000, 3'b010, 1'b0, 3'b001}; |
sd_BA_O <= 2'b00; |
sd_state <= SD_LD_MODE; |
init_state <= SI_PRECHG2; |
end |
SI_PRECHG2: |
begin |
sd_state <= SD_PRECHG_ALL; |
init_state <= SI_AUTO_REF; |
end |
SI_AUTO_REF: |
begin |
sd_state <= SD_AUTO_REF; |
init_state <= SI_AUTO_REF2; |
end |
SI_AUTO_REF2: |
begin |
sd_state <= SD_AUTO_REF; |
init_state <= SI_DONE; |
end |
SI_DONE: |
begin |
init_state <= SI_DONE; |
sd_state <= SD_IDLE; |
end |
default: |
init_state <= SI_START; |
endcase |
end |
// ** Waiting for SDRAM waking up ***************************** |
SD_INIT_WAIT: |
begin |
init_wait_count <= init_wait_count + 1; |
if(init_wait_count == INIT_WAIT) |
begin |
sd_state <= SD_INIT; |
end |
if(init_wait_count == INIT_CLK_EN_WAIT) |
begin |
sd_CKE_O <= 1; // Wake up the SDRAM |
end |
end |
// ** Precharge command *************************************** |
SD_PRECHG_ALL: |
begin |
sd_state <= SD_PRECHG_ALL1; |
sd_RAS_O <= 0; |
sd_CAS_O <= 1; |
sd_WE_O <= 0; |
sd_CS_O <= 0; |
sd_A_O[10] <= 1; // Command for precharge all |
end |
SD_PRECHG_ALL1: |
begin |
sd_CS_O <= 1; |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
sd_state <= SD_IDLE; // Precharge takes 15nS before next command |
end |
// ** Load mode register ************************************** |
SD_LD_MODE: |
begin |
sd_state <= SD_LD_MODE1; |
sd_RAS_O <= 0; |
sd_CAS_O <= 0; |
sd_WE_O <= 0; |
sd_CS_O <= 0; |
sd_A_O[12:0] <= mode_reg; |
end |
SD_LD_MODE1: |
begin |
sd_CS_O <= 1; |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; // Load Mode takes 12nS |
sd_state <= SD_IDLE; // Add wait if needed |
end |
// ** Auto refresh command ************************************ |
SD_AUTO_REF: |
begin |
sd_state <= SD_AUTO_REF1; |
sd_RAS_O <= 0; |
sd_CAS_O <= 0; |
sd_WE_O <= 1; |
sd_CS_O <= 0; |
wait_count <= REFRESH_WAIT; |
end |
SD_AUTO_REF1: |
begin |
sd_CS_O <= 1; // Issue NOP during wait |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
if(wait_count[5] == 1) // Time up, return to idle |
begin |
sd_state <= SD_AUTO_REF_ACK; |
refresh_ack <= 1; |
end |
end |
SD_AUTO_REF_ACK: // Interlocking state |
begin |
sd_state <= SD_IDLE; |
refresh_ack <= 0; |
end |
// ** Read cycle ********************************************** |
SD_RD_START: |
begin |
sd_state <= SD_RD_COL; |
sd_RAS_O <= 0; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
sd_CS_O <= 0; |
sd_BA_O[1:0] <= wADR_I[25:24]; |
sd_A_O[12:0] <= wADR_I[23:11]; |
wait_count <= ACCESS_WAIT; |
D_oe <= 0; // Not driving the bus |
DQS_state <= 0; |
end |
SD_RD_COL: |
begin |
if(wait_count[5] != 1) |
begin |
sd_CS_O <= 1; // NOP command during access wait |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
end else |
begin |
sd_CS_O <= 0; // Access column |
sd_RAS_O <= 1; |
sd_CAS_O <= 0; |
sd_WE_O <= 1; |
sd_state <= SD_RD_CAS_WAIT; |
sd_A_O[9:1] <= wADR_I[10:2]; |
sd_A_O[10] <= 1; // Use auto-precharge |
sd_A_O[0] <= 0; |
wait_count <= CAS_WAIT; |
DQS_oe <= 0; // Set DQS for input |
end |
end |
SD_RD_CAS_WAIT: |
begin // Wait until DQS signal there is data |
if(wait_count[5] != 1) |
begin |
sd_CS_O <= 1; // NOP command during access wait |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
end else |
begin |
sd_state <= SD_RD_LATCH; |
end |
end |
SD_RD_LATCH: |
begin |
D_rd_reg <= data_mux_latch[31:0]; |
wACK_O <= 1; |
sd_state <= SD_RD_DONE; |
end |
SD_RD_DONE: |
begin |
wACK_O <= 1; |
sd_state <= SD_RD_DONE_1; |
DQS_state <= 0; |
DQS_oe <= 1; // Set DQS back to output |
end |
SD_RD_DONE_1: |
begin |
wACK_O <= 0; |
sd_state <= SD_IDLE; |
end |
// ** Write cycle ********************************************* |
SD_WR_START: |
begin // Open the bank - ACTIVE command |
sd_state <= SD_WR_COL; |
sd_RAS_O <= 0; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
sd_CS_O <= 0; |
sd_BA_O[1:0] <= wADR_I[25:24]; |
sd_A_O[12:0] <= wADR_I[23:11]; |
D_wr_reg <= wDAT_I; |
D_mask_reg <= wWRB_I; |
wait_count <= ACCESS_WAIT; |
DQS_state <= 0; |
end |
SD_WR_COL: |
begin |
if(wait_count[5] != 1) |
begin |
sd_CS_O <= 1; // NOP command during access wait |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
end else |
begin |
sd_CS_O <= 0; // Access column |
sd_RAS_O <= 1; |
sd_CAS_O <= 0; |
sd_WE_O <= 0; |
DQS_oe <= 1; |
sd_state <= SD_WR_CAS_WAIT; |
sd_A_O[9:1] <= wADR_I[10:2]; |
sd_A_O[10] <= 1; // Use auto-precharge |
sd_A_O[0] <= 0; |
end |
end |
SD_WR_CAS_WAIT: |
begin // Wait until DQS signal there is data |
sd_state <= SD_WR_LATCH; |
DQS_state <= 1; // Start with DQS low |
D_oe <= 1; // Drive the data bus |
sd_CS_O <= 1; |
sd_RAS_O <= 1; |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
end |
SD_WR_LATCH: |
begin |
sd_state <= SD_WR_LATCH1; |
DQS_state <= 0; |
end |
SD_WR_LATCH1: |
begin |
sd_state <= SD_WR_DONE; |
DQS_state <= 0; |
wACK_O <= 1; |
end |
SD_WR_DONE: |
begin |
D_oe <= 0; |
wACK_O <= 1; |
sd_state <= SD_WR_DONE_1; |
end |
SD_WR_DONE_1: |
begin |
wACK_O <= 0; |
sd_state <= SD_IDLE; |
end |
// Wishbone transfer is done during idle time |
SD_IDLE: /* Idle/sleep process */ |
begin |
sd_RAS_O <= 1; // Set for NOP by default |
sd_CAS_O <= 1; |
sd_WE_O <= 1; |
sd_CS_O <= 1; |
if(init_state != SI_DONE) // If still in init cycle, go back and work |
sd_state <= SD_INIT; |
else if(wSTB_I && !wWE_I) // Start of a read command |
sd_state <= SD_RD_START; |
else if(wSTB_I && wWE_I) // Start of a write command |
sd_state <= SD_WR_START; |
else if(refresh_now) // Refresh is the last command |
sd_state <= SD_AUTO_REF; |
end |
|
default: |
sd_state <= SD_IDLE; |
endcase |
end |
end |
|
/* Seperate always block for refresh timer */ |
/* The idea is to queue as many as 8 refresh command as possible if the bus is |
* free */ |
always @ (posedge clk0) |
begin |
if(refresh_ack) |
begin |
refresh_now <= 0; |
refresh_queue <= refresh_queue + 4'd1; |
end else |
if(reset) |
begin |
refresh_counter <= 0; |
refresh_queue <= 4'd0; |
end else |
begin |
refresh_counter <= refresh_counter + 1; |
if(refresh_counter == AVG_REFRESH_DUR) |
begin |
refresh_counter <= 0; |
if(refresh_queue != 4'd0) |
refresh_queue <= refresh_queue - 4'd1; |
end |
if(refresh_queue != 4'd7) |
refresh_now <= 1; |
end |
end |
|
endmodule |
/trunk/fpga/src/ram/ddr/ram.v
0,0 → 1,191
// |
// ram_2.v -- main memory, using DDR SDRAM |
// |
|
|
module ram(ddr_clk_0, ddr_clk_90, ddr_clk_180, |
ddr_clk_270, ddr_clk_ok, clk, reset, |
en, wr, size, addr, |
data_in, data_out, wt, |
sdram_ck_p, sdram_ck_n, sdram_cke, |
sdram_cs_n, sdram_ras_n, sdram_cas_n, |
sdram_we_n, sdram_ba, sdram_a, |
sdram_udm, sdram_ldm, |
sdram_udqs, sdram_ldqs, sdram_dq); |
// internal interface signals |
input ddr_clk_0; |
input ddr_clk_90; |
input ddr_clk_180; |
input ddr_clk_270; |
input ddr_clk_ok; |
input clk; |
input reset; |
input en; |
input wr; |
input [1:0] size; |
input [25:0] addr; |
input [31:0] data_in; |
output reg [31:0] data_out; |
output wt; |
// DDR SDRAM interface signals |
output sdram_ck_p; |
output sdram_ck_n; |
output sdram_cke; |
output sdram_cs_n; |
output sdram_ras_n; |
output sdram_cas_n; |
output sdram_we_n; |
output [1:0] sdram_ba; |
output [12:0] sdram_a; |
output sdram_udm; |
output sdram_ldm; |
inout sdram_udqs; |
inout sdram_ldqs; |
inout [15:0] sdram_dq; |
|
wire [31:0] do; |
reg [31:0] di; |
reg [3:0] wb; |
wire ack; |
|
ddr_sdram ddr_sdram1( |
.sd_CK_P(sdram_ck_p), |
.sd_CK_N(sdram_ck_n), |
.sd_A_O(sdram_a[12:0]), |
.sd_BA_O(sdram_ba[1:0]), |
.sd_D_IO(sdram_dq[15:0]), |
.sd_RAS_O(sdram_ras_n), |
.sd_CAS_O(sdram_cas_n), |
.sd_WE_O(sdram_we_n), |
.sd_UDM_O(sdram_udm), |
.sd_LDM_O(sdram_ldm), |
.sd_UDQS_IO(sdram_udqs), |
.sd_LDQS_IO(sdram_ldqs), |
.sd_CS_O(sdram_cs_n), |
.sd_CKE_O(sdram_cke), |
.clk0(ddr_clk_0), |
.clk90(ddr_clk_90), |
.clk180(ddr_clk_180), |
.clk270(ddr_clk_270), |
.reset(~ddr_clk_ok), |
.wADR_I(addr[25:2]), |
.wSTB_I(en), |
.wWE_I(wr), |
.wWRB_I(wb[3:0]), |
.wDAT_I(di[31:0]), |
.wDAT_O(do[31:0]), |
.wACK_O(ack) |
); |
|
// read multiplexer |
always @(*) begin |
case (size[1:0]) |
2'b00: |
// byte |
begin |
data_out[31:24] = 8'hxx; |
data_out[23:16] = 8'hxx; |
data_out[15: 8] = 8'hxx; |
if (addr[1] == 0) begin |
if (addr[0] == 0) begin |
data_out[ 7: 0] = do[31:24]; |
end else begin |
data_out[ 7: 0] = do[23:16]; |
end |
end else begin |
if (addr[0] == 0) begin |
data_out[ 7: 0] = do[15: 8]; |
end else begin |
data_out[ 7: 0] = do[ 7: 0]; |
end |
end |
end |
2'b01: |
// halfword |
begin |
data_out[31:24] = 8'hxx; |
data_out[23:16] = 8'hxx; |
if (addr[1] == 0) begin |
data_out[15: 8] = do[31:24]; |
data_out[ 7: 0] = do[23:16]; |
end else begin |
data_out[15: 8] = do[15: 8]; |
data_out[ 7: 0] = do[ 7: 0]; |
end |
end |
2'b10: |
// word |
begin |
data_out[31:24] = do[31:24]; |
data_out[23:16] = do[23:16]; |
data_out[15: 8] = do[15: 8]; |
data_out[ 7: 0] = do[ 7: 0]; |
end |
default: |
// illegal |
begin |
data_out[31:24] = 8'hxx; |
data_out[23:16] = 8'hxx; |
data_out[15: 8] = 8'hxx; |
data_out[ 7: 0] = 8'hxx; |
end |
endcase |
end |
|
// write multiplexer & data masks |
always @(*) begin |
case (size[1:0]) |
2'b00: |
// byte |
begin |
di[31:24] = data_in[ 7: 0]; |
di[23:16] = data_in[ 7: 0]; |
di[15: 8] = data_in[ 7: 0]; |
di[ 7: 0] = data_in[ 7: 0]; |
wb[3] = ~addr[1] & ~addr[0]; |
wb[2] = ~addr[1] & addr[0]; |
wb[1] = addr[1] & ~addr[0]; |
wb[0] = addr[1] & addr[0]; |
end |
2'b01: |
// halfword |
begin |
di[31:24] = data_in[15: 8]; |
di[23:16] = data_in[ 7: 0]; |
di[15: 8] = data_in[15: 8]; |
di[ 7: 0] = data_in[ 7: 0]; |
wb[3] = ~addr[1]; |
wb[2] = ~addr[1]; |
wb[1] = addr[1]; |
wb[0] = addr[1]; |
end |
2'b10: |
// word |
begin |
di[31:24] = data_in[31:24]; |
di[23:16] = data_in[23:16]; |
di[15: 8] = data_in[15: 8]; |
di[ 7: 0] = data_in[ 7: 0]; |
wb[3] = 1'b1; |
wb[2] = 1'b1; |
wb[1] = 1'b1; |
wb[0] = 1'b1; |
end |
default: |
// illegal |
begin |
di[31:24] = 8'hxx; |
di[23:16] = 8'hxx; |
di[15: 8] = 8'hxx; |
di[ 7: 0] = 8'hxx; |
wb[3] = 1'b0; |
wb[2] = 1'b0; |
wb[1] = 1'b0; |
wb[0] = 1'b0; |
end |
endcase |
end |
|
assign wt = ~ack; |
|
endmodule |
/trunk/fpga/boards/xsa-xst-3/build/eco32.xise
31,11 → 31,11
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> |
</file> |
<file xil_pn:name="../../../src/ram/ram.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ram/sdr/ram.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> |
</file> |
<file xil_pn:name="../../../src/ram/sdramcntl.vhd" xil_pn:type="FILE_VHDL"> |
<file xil_pn:name="../../../src/ram/sdr/sdramcntl.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
/trunk/fpga/boards/xsa-xst-3/build/eco32.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream