URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
Compare Revisions
- This comparison shows the changes necessary to convert path
/eco32
- from Rev 224 to Rev 225
- ↔ Reverse comparison
Rev 224 → Rev 225
/trunk/fpga/boards/xsa-xst-3/build/eco32.xise
19,13 → 19,13
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> |
</file> |
<file xil_pn:name="../../../src/clk_reset/clk_reset.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../clk_rst/clk_rst.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> |
</file> |
<file xil_pn:name="../../../src/busctrl/busctrl.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> |
</file> |
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
117,7 → 117,7
</file> |
<file xil_pn:name="../../../src/bio/bio.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> |
</file> |
<file xil_pn:name="../toplevel/eco32.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
/trunk/fpga/boards/xsa-xst-3/build/eco32.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/fpga/boards/xsa-xst-3/toplevel/eco32.v
116,7 → 116,7
input sw2_n; |
input sw3_n; |
|
// clk_reset |
// clk_rst |
wire clk; |
wire clk_ok; |
wire reset; |
209,7 → 209,7
wire [31:0] bio_data_out; |
wire bio_wt; |
|
clk_reset clk_reset1( |
clk_rst clk_rst1( |
.clk_in(clk_in), |
.reset_inout_n(reset_inout_n), |
.sdram_clk(sdram_clk), |
/trunk/fpga/boards/s3e-500/toplevel/eco32.v
107,7 → 107,7
output spi_ss_b; |
output fpga_init_b; |
|
// clk_reset |
// clk_rst |
wire ddr_clk_0; |
wire ddr_clk_90; |
wire ddr_clk_180; |
200,7 → 200,7
wire bio_wt; |
wire spi_en; |
|
clk_reset clk_reset1( |
clk_rst clk_rst1( |
.clk_in(clk_in), |
.reset_in(reset_in), |
.ddr_clk_0(ddr_clk_0), |