OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32
    from Rev 227 to Rev 228
    ↔ Reverse comparison
  •

Rev 227 → Rev 228

/trunk/fpga/boards/s3e-500/build/eco32.xise
9,130 → 9,412
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
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<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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<property xil_pn:name="Implementation Top File" xil_pn:value="../toplevel/eco32.v" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
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<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="eco32" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="eco32_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="eco32_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="eco32_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="eco32_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="eco32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-22T13:31:56" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="684A826A6B3D8F1FBA3BD7B547FE3B82" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
139,8 → 421,19
 
<libraries/>
 
<partitions>
<partition xil_pn:name="/eco32"/>
</partitions>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
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<file xil_pn:name="../../../src/dsp/common/chrgenlo.init" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../src/dsp/common/chrgenhi.init" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../src/dsp/common/dspatthi.init" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../src/dsp/common/dspattlo.init" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../src/dsp/common/dspchrhi.init" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../src/dsp/common/dspchrlo.init" xil_pn:type="FILE_VERILOG"/>
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</project>
/trunk/fpga/boards/s3e-500/build/eco32.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/fpga/boards/s3e-500/build/eco32.bit
trunk/fpga/boards/s3e-500/build/eco32.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/fpga/boards/s3e-500/toplevel/eco32.v =================================================================== --- trunk/fpga/boards/s3e-500/toplevel/eco32.v (revision 227) +++ trunk/fpga/boards/s3e-500/toplevel/eco32.v (revision 228) @@ -139,14 +139,22 @@ wire [23:0] rom_addr; wire [31:0] rom_data_out; wire rom_wt; - // tmr - wire tmr_en; - wire tmr_wr; - wire tmr_addr; - wire [31:0] tmr_data_in; - wire [31:0] tmr_data_out; - wire tmr_wt; - wire tmr_irq; + // tmr0 + wire tmr0_en; + wire tmr0_wr; + wire [3:2] tmr0_addr; + wire [31:0] tmr0_data_in; + wire [31:0] tmr0_data_out; + wire tmr0_wt; + wire tmr0_irq; + // tmr1 + wire tmr1_en; + wire tmr1_wr; + wire [3:2] tmr1_addr; + wire [31:0] tmr1_data_in; + wire [31:0] tmr1_data_out; + wire tmr1_wt; + wire tmr1_irq; // dsp wire dsp_en; wire dsp_wr; @@ -236,13 +244,20 @@ .rom_addr(rom_addr[23:0]), .rom_data_out(rom_data_out[31:0]), .rom_wt(rom_wt), - // tmr - .tmr_en(tmr_en), - .tmr_wr(tmr_wr), - .tmr_addr(tmr_addr), - .tmr_data_in(tmr_data_in[31:0]), - .tmr_data_out(tmr_data_out[31:0]), - .tmr_wt(tmr_wt), + // tmr0 + .tmr0_en(tmr0_en), + .tmr0_wr(tmr0_wr), + .tmr0_addr(tmr0_addr[3:2]), + .tmr0_data_in(tmr0_data_in[31:0]), + .tmr0_data_out(tmr0_data_out[31:0]), + .tmr0_wt(tmr0_wt), + // tmr1 + .tmr1_en(tmr1_en), + .tmr1_wr(tmr1_wr), + .tmr1_addr(tmr1_addr[3:2]), + .tmr1_data_in(tmr1_data_in[31:0]), + .tmr1_data_out(tmr1_data_out[31:0]), + .tmr1_wt(tmr1_wt), // dsp .dsp_en(dsp_en), .dsp_wr(dsp_wr), @@ -300,8 +315,8 @@ .irq(cpu_irq[15:0]) ); - assign cpu_irq[15] = 1'b0; - assign cpu_irq[14] = tmr_irq; + assign cpu_irq[15] = tmr1_irq; + assign cpu_irq[14] = tmr0_irq; assign cpu_irq[13] = 1'b0; assign cpu_irq[12] = 1'b0; assign cpu_irq[11] = 1'b0; @@ -366,18 +381,30 @@ .d(flash_d[15:0]) ); - tmr tmr1( + tmr tmr1_0( .clk(clk), .reset(reset), - .en(tmr_en), - .wr(tmr_wr), - .addr(tmr_addr), - .data_in(tmr_data_in[31:0]), - .data_out(tmr_data_out[31:0]), - .wt(tmr_wt), - .irq(tmr_irq) + .en(tmr0_en), + .wr(tmr0_wr), + .addr(tmr0_addr[3:2]), + .data_in(tmr0_data_in[31:0]), + .data_out(tmr0_data_out[31:0]), + .wt(tmr0_wt), + .irq(tmr0_irq) ); + tmr tmr1_1( + .clk(clk), + .reset(reset), + .en(tmr1_en), + .wr(tmr1_wr), + .addr(tmr1_addr[3:2]), + .data_in(tmr1_data_in[31:0]), + .data_out(tmr1_data_out[31:0]), + .wt(tmr1_wt), + .irq(tmr1_irq) + ); + dsp dsp1( .clk(clk), .reset(reset),
/trunk/fpga/boards/s3e-500/Makefile
1,5 → 1,5
#
# Makefile for FPGA implementations of ECO32
# Makefile for ECO32 on Digilent S3E starter kit board
#
 
BUILD = ../../../build
6,11 → 6,9
 
.PHONY: all install clean
 
all:
#all: xsa-xst-3/eco32.bit
all: build/eco32.bit
 
install:
#install: xsa-xst-3/eco32.bit
install: build/eco32.bit
# $(BUILD)/bin/bit2exo 0x180000 \
# xsa-xst-3/eco32.bit xsa-xst-3/eco32.exo
# mkdir -p $(BUILD)/eco32/xsa-xst-3
18,11 → 16,9
# cp xsa-xst-3/eco32.exo $(BUILD)/eco32/xsa-xst-3
 
clean:
# mv xsa-xst-3/eco32.ucf .
# mv xsa-xst-3/eco32.xise .
# mv xsa-xst-3/eco32.bit .
# rm -rf xsa-xst-3/*
# mv eco32.ucf xsa-xst-3
# mv eco32.xise xsa-xst-3
# mv eco32.bit xsa-xst-3
mv build/eco32.xise .
mv build/eco32.bit .
rm -rf build/*
mv eco32.xise build
mv eco32.bit build
rm -f *~
/trunk/fpga/boards/s3e-500/busctrl/busctrl.v
9,8 → 9,10
ram_data_in, ram_data_out, ram_wt,
rom_en, rom_wr, rom_size, rom_addr,
rom_data_out, rom_wt,
tmr_en, tmr_wr, tmr_addr,
tmr_data_in, tmr_data_out, tmr_wt,
tmr0_en, tmr0_wr, tmr0_addr,
tmr0_data_in, tmr0_data_out, tmr0_wt,
tmr1_en, tmr1_wr, tmr1_addr,
tmr1_data_in, tmr1_data_out, tmr1_wt,
dsp_en, dsp_wr, dsp_addr,
dsp_data_in, dsp_data_out, dsp_wt,
kbd_en, kbd_wr, kbd_addr,
46,13 → 48,20
output [23:0] rom_addr;
input [31:0] rom_data_out;
input rom_wt;
// tmr
output tmr_en;
output tmr_wr;
output tmr_addr;
output [31:0] tmr_data_in;
input [31:0] tmr_data_out;
input tmr_wt;
// tmr0
output tmr0_en;
output tmr0_wr;
output [3:2] tmr0_addr;
output [31:0] tmr0_data_in;
input [31:0] tmr0_data_out;
input tmr0_wt;
// tmr1
output tmr1_en;
output tmr1_wr;
output [3:2] tmr1_addr;
output [31:0] tmr1_data_in;
input [31:0] tmr1_data_out;
input tmr1_wt;
// dsp
output dsp_en;
output dsp_wr;
114,8 → 123,12
// I/O: architectural limit = 256 MB
assign i_o_en =
(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0;
assign tmr_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h00) ? 1 : 0;
assign tmr0_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h00
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
assign tmr1_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h00
&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
assign dsp_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0;
assign kbd_en =
137,7 → 150,8
assign cpu_wt =
(ram_en == 1) ? ram_wt :
(rom_en == 1) ? rom_wt :
(tmr_en == 1) ? tmr_wt :
(tmr0_en == 1) ? tmr0_wt :
(tmr1_en == 1) ? tmr1_wt :
(dsp_en == 1) ? dsp_wt :
(kbd_en == 1) ? kbd_wt :
(ser0_en == 1) ? ser0_wt :
148,7 → 162,8
assign cpu_data_in[31:0] =
(ram_en == 1) ? ram_data_out[31:0] :
(rom_en == 1) ? rom_data_out[31:0] :
(tmr_en == 1) ? tmr_data_out[31:0] :
(tmr0_en == 1) ? tmr0_data_out[31:0] :
(tmr1_en == 1) ? tmr1_data_out[31:0] :
(dsp_en == 1) ? { 16'h0000, dsp_data_out[15:0] } :
(kbd_en == 1) ? { 24'h000000, kbd_data_out[7:0] } :
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } :
168,11 → 183,16
assign rom_size[1:0] = cpu_size[1:0];
assign rom_addr[23:0] = cpu_addr[23:0];
 
// to tmr
assign tmr_wr = cpu_wr;
assign tmr_addr = cpu_addr[2];
assign tmr_data_in[31:0] = cpu_data_out[31:0];
// to tmr0
assign tmr0_wr = cpu_wr;
assign tmr0_addr[3:2] = cpu_addr[3:2];
assign tmr0_data_in[31:0] = cpu_data_out[31:0];
 
// to tmr1
assign tmr1_wr = cpu_wr;
assign tmr1_addr[3:2] = cpu_addr[3:2];
assign tmr1_data_in[31:0] = cpu_data_out[31:0];
 
// to dsp
assign dsp_wr = cpu_wr;
assign dsp_addr[13:2] = cpu_addr[13:2];

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