URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
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/eco32
- from Rev 229 to Rev 230
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Rev 229 → Rev 230
/trunk/fpga/boards/xsa-xst-3/clk_rst/clk_rst.v
File deleted
/trunk/fpga/boards/xsa-xst-3/toplevel/eco32.ucf
File deleted
/trunk/fpga/boards/xsa-xst-3/toplevel/eco32.v
File deleted
/trunk/fpga/boards/xsa-xst-3/bio/bio.v
File deleted
/trunk/fpga/boards/xsa-xst-3/busctrl/busctrl.v
File deleted
/trunk/fpga/boards/xsa-xst-3/src/clk_rst/clk_rst.v
0,0 → 1,99
// |
// clk_rst.v -- clock and reset generator |
// |
|
|
module clk_rst(clk_in, reset_inout_n, |
sdram_clk, sdram_fb, |
clk, clk_ok, reset); |
input clk_in; |
inout reset_inout_n; |
output sdram_clk; |
input sdram_fb; |
output clk; |
output clk_ok; |
output reset; |
|
wire clk_in_buf; |
wire int_clk; |
wire int_locked; |
wire ext_rst_n; |
wire ext_fb; |
wire ext_locked; |
|
reg reset_p_n; |
reg reset_s_n; |
reg [23:0] reset_counter; |
wire reset_counting; |
|
//------------------------------------------------------------ |
|
IBUFG clk_in_buffer( |
.I(clk_in), |
.O(clk_in_buf) |
); |
|
DCM int_dcm( |
.CLKIN(clk_in_buf), |
.CLKFB(clk), |
.RST(1'b0), |
.CLK0(int_clk), |
.LOCKED(int_locked) |
); |
|
BUFG int_clk_buffer( |
.I(int_clk), |
.O(clk) |
); |
|
//------------------------------------------------------------ |
|
SRL16 ext_dll_rst_gen( |
.CLK(clk_in_buf), |
.D(int_locked), |
.Q(ext_rst_n), |
.A0(1'b1), |
.A1(1'b1), |
.A2(1'b1), |
.A3(1'b1) |
); |
|
defparam ext_dll_rst_gen.INIT = 16'h0000; |
|
//------------------------------------------------------------ |
|
IBUFG ext_fb_buffer( |
.I(sdram_fb), |
.O(ext_fb) |
); |
|
DCM ext_dcm( |
.CLKIN(clk_in_buf), |
.CLKFB(ext_fb), |
.RST(~ext_rst_n), |
.CLK0(sdram_clk), |
.LOCKED(ext_locked) |
); |
|
assign clk_ok = int_locked & ext_locked; |
|
//------------------------------------------------------------ |
|
assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1; |
assign reset_inout_n = (reset_counter[23] == 0) ? 1'b0 : 1'bz; |
|
always @(posedge clk_in_buf) begin |
reset_p_n <= reset_inout_n; |
reset_s_n <= reset_p_n; |
if (reset_counting == 1) begin |
reset_counter <= reset_counter + 1; |
end else begin |
if (~reset_s_n | ~clk_ok) begin |
reset_counter <= 24'h000000; |
end |
end |
end |
|
assign reset = reset_counting; |
|
endmodule |
/trunk/fpga/boards/xsa-xst-3/src/bio/bio.v
0,0 → 1,80
// |
// bio.v -- board specific I/O |
// |
|
|
module bio(clk, reset, |
en, wr, addr, |
data_in, data_out, |
wt, |
sw1_1, sw1_2, |
sw1_3, sw1_4, |
sw2_n, sw3_n); |
// internal interface |
input clk; |
input reset; |
input en; |
input wr; |
input addr; |
input [31:0] data_in; |
output [31:0] data_out; |
output wt; |
// external interface |
input sw1_1; |
input sw1_2; |
input sw1_3; |
input sw1_4; |
input sw2_n; |
input sw3_n; |
|
reg [31:0] bio_out; |
wire [31:0] bio_in; |
|
reg sw1_1_p; |
reg sw1_1_s; |
reg sw1_2_p; |
reg sw1_2_s; |
reg sw1_3_p; |
reg sw1_3_s; |
reg sw1_4_p; |
reg sw1_4_s; |
reg sw2_p_n; |
reg sw2_s_n; |
reg sw3_p_n; |
reg sw3_s_n; |
|
always @(posedge clk) begin |
if (reset) begin |
bio_out[31:0] <= 32'h0; |
end else begin |
if (en & wr & ~addr) begin |
bio_out[31:0] <= data_in[31:0]; |
end |
end |
end |
|
assign data_out[31:0] = |
(addr == 0) ? bio_out[31:0] : bio_in[31:0]; |
assign wt = 0; |
|
always @(posedge clk) begin |
sw1_1_p <= sw1_1; |
sw1_1_s <= sw1_1_p; |
sw1_2_p <= sw1_2; |
sw1_2_s <= sw1_2_p; |
sw1_3_p <= sw1_3; |
sw1_3_s <= sw1_3_p; |
sw1_4_p <= sw1_4; |
sw1_4_s <= sw1_4_p; |
sw2_p_n <= sw2_n; |
sw2_s_n <= sw2_p_n; |
sw3_p_n <= sw3_n; |
sw3_s_n <= sw3_p_n; |
end |
|
assign bio_in[31:0] = |
{ 26'h0, |
~sw3_s_n, ~sw2_s_n, |
sw1_4_s, sw1_3_s, sw1_2_s, sw1_1_s }; |
|
endmodule |
/trunk/fpga/boards/xsa-xst-3/src/toplevel/eco32.v
0,0 → 1,503
// |
// eco32.v -- ECO32 top-level description |
// |
|
|
module eco32(clk_in, |
reset_inout_n, |
sdram_clk, |
sdram_fb, |
sdram_cke, |
sdram_cs_n, |
sdram_ras_n, |
sdram_cas_n, |
sdram_we_n, |
sdram_ba, |
sdram_a, |
sdram_udqm, |
sdram_ldqm, |
sdram_dq, |
flash_ce_n, |
flash_oe_n, |
flash_we_n, |
flash_rst_n, |
flash_byte_n, |
flash_a, |
flash_d, |
vga_hsync, |
vga_vsync, |
vga_r, |
vga_g, |
vga_b, |
ps2_clk, |
ps2_data, |
rs232_0_rxd, |
rs232_0_txd, |
rs232_1_rxd, |
rs232_1_txd, |
pbus_d, |
pbus_a, |
pbus_read_n, |
pbus_write_n, |
ata_cs0_n, |
ata_cs1_n, |
ata_intrq, |
ata_dmarq, |
ata_dmack_n, |
ata_iordy, |
slot1_cs_n, |
slot2_cs_n, |
ether_cs_n, |
sw1_3, |
sw1_4, |
sw2_n, |
sw3_n); |
|
// clock and reset |
input clk_in; |
inout reset_inout_n; |
// SDRAM |
output sdram_clk; |
input sdram_fb; |
output sdram_cke; |
output sdram_cs_n; |
output sdram_ras_n; |
output sdram_cas_n; |
output sdram_we_n; |
output [1:0] sdram_ba; |
output [12:0] sdram_a; |
output sdram_udqm; |
output sdram_ldqm; |
inout [15:0] sdram_dq; |
// flash ROM |
output flash_ce_n; |
output flash_oe_n; |
output flash_we_n; |
output flash_rst_n; |
output flash_byte_n; |
output [19:0] flash_a; |
input [15:0] flash_d; |
// VGA display |
output vga_hsync; |
output vga_vsync; |
output [2:0] vga_r; |
output [2:0] vga_g; |
output [2:0] vga_b; |
// keyboard |
input ps2_clk; |
input ps2_data; |
// serial line 0 |
input rs232_0_rxd; |
output rs232_0_txd; |
// serial line 1 |
input rs232_1_rxd; |
output rs232_1_txd; |
// peripheral bus |
inout [15:0] pbus_d; |
output [4:0] pbus_a; |
output pbus_read_n; |
output pbus_write_n; |
// ATA adapter |
output ata_cs0_n; |
output ata_cs1_n; |
input ata_intrq; |
input ata_dmarq; |
output ata_dmack_n; |
input ata_iordy; |
// expansion slot 1 |
output slot1_cs_n; |
// expansion slot 2 |
output slot2_cs_n; |
// ethernet |
output ether_cs_n; |
// board I/O |
input sw1_3; |
input sw1_4; |
input sw2_n; |
input sw3_n; |
|
// clk_rst |
wire clk; |
wire clk_ok; |
wire reset; |
// cpu |
wire cpu_en; |
wire cpu_wr; |
wire [1:0] cpu_size; |
wire [31:0] cpu_addr; |
wire [31:0] cpu_data_in; |
wire [31:0] cpu_data_out; |
wire cpu_wt; |
wire [15:0] cpu_irq; |
// ram |
wire ram_en; |
wire ram_wr; |
wire [1:0] ram_size; |
wire [24:0] ram_addr; |
wire [31:0] ram_data_in; |
wire [31:0] ram_data_out; |
wire ram_wt; |
// rom |
wire rom_en; |
wire rom_wr; |
wire [1:0] rom_size; |
wire [20:0] rom_addr; |
wire [31:0] rom_data_out; |
wire rom_wt; |
// tmr0 |
wire tmr0_en; |
wire tmr0_wr; |
wire [3:2] tmr0_addr; |
wire [31:0] tmr0_data_in; |
wire [31:0] tmr0_data_out; |
wire tmr0_wt; |
wire tmr0_irq; |
// tmr1 |
wire tmr1_en; |
wire tmr1_wr; |
wire [3:2] tmr1_addr; |
wire [31:0] tmr1_data_in; |
wire [31:0] tmr1_data_out; |
wire tmr1_wt; |
wire tmr1_irq; |
// dsp |
wire dsp_en; |
wire dsp_wr; |
wire [13:2] dsp_addr; |
wire [15:0] dsp_data_in; |
wire [15:0] dsp_data_out; |
wire dsp_wt; |
// kbd |
wire kbd_en; |
wire kbd_wr; |
wire kbd_addr; |
wire [7:0] kbd_data_in; |
wire [7:0] kbd_data_out; |
wire kbd_wt; |
wire kbd_irq; |
// ser0 |
wire ser0_en; |
wire ser0_wr; |
wire [3:2] ser0_addr; |
wire [7:0] ser0_data_in; |
wire [7:0] ser0_data_out; |
wire ser0_wt; |
wire ser0_irq_r; |
wire ser0_irq_t; |
// ser1 |
wire ser1_en; |
wire ser1_wr; |
wire [3:2] ser1_addr; |
wire [7:0] ser1_data_in; |
wire [7:0] ser1_data_out; |
wire ser1_wt; |
wire ser1_irq_r; |
wire ser1_irq_t; |
// dsk |
wire dsk_en; |
wire dsk_wr; |
wire [19:2] dsk_addr; |
wire [31:0] dsk_data_in; |
wire [31:0] dsk_data_out; |
wire dsk_wt; |
wire dsk_irq; |
// bio |
wire bio_en; |
wire bio_wr; |
wire bio_addr; |
wire [31:0] bio_data_in; |
wire [31:0] bio_data_out; |
wire bio_wt; |
|
clk_rst clk_rst1( |
.clk_in(clk_in), |
.reset_inout_n(reset_inout_n), |
.sdram_clk(sdram_clk), |
.sdram_fb(sdram_fb), |
.clk(clk), |
.clk_ok(clk_ok), |
.reset(reset) |
); |
|
busctrl busctrl1( |
// cpu |
.cpu_en(cpu_en), |
.cpu_wr(cpu_wr), |
.cpu_size(cpu_size[1:0]), |
.cpu_addr(cpu_addr[31:0]), |
.cpu_data_in(cpu_data_in[31:0]), |
.cpu_data_out(cpu_data_out[31:0]), |
.cpu_wt(cpu_wt), |
// ram |
.ram_en(ram_en), |
.ram_wr(ram_wr), |
.ram_size(ram_size[1:0]), |
.ram_addr(ram_addr[24:0]), |
.ram_data_in(ram_data_in[31:0]), |
.ram_data_out(ram_data_out[31:0]), |
.ram_wt(ram_wt), |
// rom |
.rom_en(rom_en), |
.rom_wr(rom_wr), |
.rom_size(rom_size[1:0]), |
.rom_addr(rom_addr[20:0]), |
.rom_data_out(rom_data_out[31:0]), |
.rom_wt(rom_wt), |
// tmr0 |
.tmr0_en(tmr0_en), |
.tmr0_wr(tmr0_wr), |
.tmr0_addr(tmr0_addr[3:2]), |
.tmr0_data_in(tmr0_data_in[31:0]), |
.tmr0_data_out(tmr0_data_out[31:0]), |
.tmr0_wt(tmr0_wt), |
// tmr1 |
.tmr1_en(tmr1_en), |
.tmr1_wr(tmr1_wr), |
.tmr1_addr(tmr1_addr[3:2]), |
.tmr1_data_in(tmr1_data_in[31:0]), |
.tmr1_data_out(tmr1_data_out[31:0]), |
.tmr1_wt(tmr1_wt), |
// dsp |
.dsp_en(dsp_en), |
.dsp_wr(dsp_wr), |
.dsp_addr(dsp_addr[13:2]), |
.dsp_data_in(dsp_data_in[15:0]), |
.dsp_data_out(dsp_data_out[15:0]), |
.dsp_wt(dsp_wt), |
// kbd |
.kbd_en(kbd_en), |
.kbd_wr(kbd_wr), |
.kbd_addr(kbd_addr), |
.kbd_data_in(kbd_data_in[7:0]), |
.kbd_data_out(kbd_data_out[7:0]), |
.kbd_wt(kbd_wt), |
// ser0 |
.ser0_en(ser0_en), |
.ser0_wr(ser0_wr), |
.ser0_addr(ser0_addr[3:2]), |
.ser0_data_in(ser0_data_in[7:0]), |
.ser0_data_out(ser0_data_out[7:0]), |
.ser0_wt(ser0_wt), |
// ser1 |
.ser1_en(ser1_en), |
.ser1_wr(ser1_wr), |
.ser1_addr(ser1_addr[3:2]), |
.ser1_data_in(ser1_data_in[7:0]), |
.ser1_data_out(ser1_data_out[7:0]), |
.ser1_wt(ser1_wt), |
// dsk |
.dsk_en(dsk_en), |
.dsk_wr(dsk_wr), |
.dsk_addr(dsk_addr[19:2]), |
.dsk_data_in(dsk_data_in[31:0]), |
.dsk_data_out(dsk_data_out[31:0]), |
.dsk_wt(dsk_wt), |
// bio |
.bio_en(bio_en), |
.bio_wr(bio_wr), |
.bio_addr(bio_addr), |
.bio_data_in(bio_data_in[31:0]), |
.bio_data_out(bio_data_out[31:0]), |
.bio_wt(bio_wt) |
); |
|
cpu cpu1( |
.clk(clk), |
.reset(reset), |
.bus_en(cpu_en), |
.bus_wr(cpu_wr), |
.bus_size(cpu_size[1:0]), |
.bus_addr(cpu_addr[31:0]), |
.bus_data_in(cpu_data_in[31:0]), |
.bus_data_out(cpu_data_out[31:0]), |
.bus_wt(cpu_wt), |
.irq(cpu_irq[15:0]) |
); |
|
assign cpu_irq[15] = tmr1_irq; |
assign cpu_irq[14] = tmr0_irq; |
assign cpu_irq[13] = 1'b0; |
assign cpu_irq[12] = 1'b0; |
assign cpu_irq[11] = 1'b0; |
assign cpu_irq[10] = 1'b0; |
assign cpu_irq[ 9] = 1'b0; |
assign cpu_irq[ 8] = dsk_irq; |
assign cpu_irq[ 7] = 1'b0; |
assign cpu_irq[ 6] = 1'b0; |
assign cpu_irq[ 5] = 1'b0; |
assign cpu_irq[ 4] = kbd_irq; |
assign cpu_irq[ 3] = ser1_irq_r; |
assign cpu_irq[ 2] = ser1_irq_t; |
assign cpu_irq[ 1] = ser0_irq_r; |
assign cpu_irq[ 0] = ser0_irq_t; |
|
ram ram1( |
.clk(clk), |
.clk_ok(clk_ok), |
.reset(reset), |
.en(ram_en), |
.wr(ram_wr), |
.size(ram_size[1:0]), |
.addr(ram_addr[24:0]), |
.data_in(ram_data_in[31:0]), |
.data_out(ram_data_out[31:0]), |
.wt(ram_wt), |
.sdram_cke(sdram_cke), |
.sdram_cs_n(sdram_cs_n), |
.sdram_ras_n(sdram_ras_n), |
.sdram_cas_n(sdram_cas_n), |
.sdram_we_n(sdram_we_n), |
.sdram_ba(sdram_ba[1:0]), |
.sdram_a(sdram_a[12:0]), |
.sdram_udqm(sdram_udqm), |
.sdram_ldqm(sdram_ldqm), |
.sdram_dq(sdram_dq[15:0]) |
); |
|
rom rom1( |
.clk(clk), |
.reset(reset), |
.en(rom_en), |
.wr(rom_wr), |
.size(rom_size[1:0]), |
.addr(rom_addr[20:0]), |
.data_out(rom_data_out[31:0]), |
.wt(rom_wt), |
.ce_n(flash_ce_n), |
.oe_n(flash_oe_n), |
.we_n(flash_we_n), |
.rst_n(flash_rst_n), |
.byte_n(flash_byte_n), |
.a(flash_a[19:0]), |
.d(flash_d[15:0]) |
); |
|
tmr tmr1_0( |
.clk(clk), |
.reset(reset), |
.en(tmr0_en), |
.wr(tmr0_wr), |
.addr(tmr0_addr[3:2]), |
.data_in(tmr0_data_in[31:0]), |
.data_out(tmr0_data_out[31:0]), |
.wt(tmr0_wt), |
.irq(tmr0_irq) |
); |
|
tmr tmr1_1( |
.clk(clk), |
.reset(reset), |
.en(tmr1_en), |
.wr(tmr1_wr), |
.addr(tmr1_addr[3:2]), |
.data_in(tmr1_data_in[31:0]), |
.data_out(tmr1_data_out[31:0]), |
.wt(tmr1_wt), |
.irq(tmr1_irq) |
); |
|
dsp dsp1( |
.clk(clk), |
.reset(reset), |
.en(dsp_en), |
.wr(dsp_wr), |
.addr(dsp_addr[13:2]), |
.data_in(dsp_data_in[15:0]), |
.data_out(dsp_data_out[15:0]), |
.wt(dsp_wt), |
.hsync(vga_hsync), |
.vsync(vga_vsync), |
.r(vga_r[2:0]), |
.g(vga_g[2:0]), |
.b(vga_b[2:0]) |
); |
|
kbd kbd1( |
.clk(clk), |
.reset(reset), |
.en(kbd_en), |
.wr(kbd_wr), |
.addr(kbd_addr), |
.data_in(kbd_data_in[7:0]), |
.data_out(kbd_data_out[7:0]), |
.wt(kbd_wt), |
.irq(kbd_irq), |
.ps2_clk(ps2_clk), |
.ps2_data(ps2_data) |
); |
|
ser ser1_0( |
.clk(clk), |
.reset(reset), |
.en(ser0_en), |
.wr(ser0_wr), |
.addr(ser0_addr[3:2]), |
.data_in(ser0_data_in[7:0]), |
.data_out(ser0_data_out[7:0]), |
.wt(ser0_wt), |
.irq_r(ser0_irq_r), |
.irq_t(ser0_irq_t), |
.rxd(rs232_0_rxd), |
.txd(rs232_0_txd) |
); |
|
ser ser1_1( |
.clk(clk), |
.reset(reset), |
.en(ser1_en), |
.wr(ser1_wr), |
.addr(ser1_addr[3:2]), |
.data_in(ser1_data_in[7:0]), |
.data_out(ser1_data_out[7:0]), |
.wt(ser1_wt), |
.irq_r(ser1_irq_r), |
.irq_t(ser1_irq_t), |
.rxd(rs232_1_rxd), |
.txd(rs232_1_txd) |
); |
|
dsk dsk1( |
.clk(clk), |
.reset(reset), |
.en(dsk_en), |
.wr(dsk_wr), |
.addr(dsk_addr[19:2]), |
.data_in(dsk_data_in[31:0]), |
.data_out(dsk_data_out[31:0]), |
.wt(dsk_wt), |
.irq(dsk_irq), |
.ata_d(pbus_d[15:0]), |
.ata_a(pbus_a[2:0]), |
.ata_cs0_n(ata_cs0_n), |
.ata_cs1_n(ata_cs1_n), |
.ata_dior_n(pbus_read_n), |
.ata_diow_n(pbus_write_n), |
.ata_intrq(ata_intrq), |
.ata_dmarq(ata_dmarq), |
.ata_dmack_n(ata_dmack_n), |
.ata_iordy(ata_iordy) |
); |
|
assign pbus_a[4:3] = 2'b00; |
assign slot1_cs_n = 1; |
assign slot2_cs_n = 1; |
assign ether_cs_n = 1; |
|
bio bio1( |
.clk(clk), |
.reset(reset), |
.en(bio_en), |
.wr(bio_wr), |
.addr(bio_addr), |
.data_in(bio_data_in[31:0]), |
.data_out(bio_data_out[31:0]), |
.wt(bio_wt), |
.sw1_1(flash_a[19]), |
.sw1_2(flash_a[18]), |
.sw1_3(sw1_3), |
.sw1_4(sw1_4), |
.sw2_n(sw2_n), |
.sw3_n(sw3_n) |
); |
|
endmodule |
/trunk/fpga/boards/xsa-xst-3/src/toplevel/eco32.ucf
0,0 → 1,176
# |
# eco32.ucf -- ECO32 user constraints for XSA-3S1000 + XST-3 board |
# |
|
# |
# clock and reset |
# |
NET "clk_in" PERIOD = 20.0ns HIGH 40%; |
NET "clk_in" LOC = "p8"; |
NET "reset_inout_n" LOC = "d15"; |
|
# |
# SDRAM |
# |
NET "sdram_a<0>" LOC = "b5"; |
NET "sdram_a<1>" LOC = "a4"; |
NET "sdram_a<2>" LOC = "b4"; |
NET "sdram_a<3>" LOC = "e6"; |
NET "sdram_a<4>" LOC = "e3"; |
NET "sdram_a<5>" LOC = "c1"; |
NET "sdram_a<6>" LOC = "e4"; |
NET "sdram_a<7>" LOC = "d3"; |
NET "sdram_a<8>" LOC = "c2"; |
NET "sdram_a<9>" LOC = "a3"; |
NET "sdram_a<10>" LOC = "b6"; |
NET "sdram_a<11>" LOC = "c5"; |
NET "sdram_a<12>" LOC = "c6"; |
NET "sdram_ba<0>" LOC = "a7"; |
NET "sdram_ba<1>" LOC = "c7"; |
NET "sdram_cas_n" LOC = "a10"; |
NET "sdram_cke" LOC = "d7"; |
NET "sdram_clk" LOC = "e10"; |
NET "sdram_cs_n" LOC = "b8"; |
NET "sdram_dq<0>" LOC = "c15"; |
NET "sdram_dq<1>" LOC = "d12"; |
NET "sdram_dq<2>" LOC = "a14"; |
NET "sdram_dq<3>" LOC = "b13"; |
NET "sdram_dq<4>" LOC = "d11"; |
NET "sdram_dq<5>" LOC = "a12"; |
NET "sdram_dq<6>" LOC = "c11"; |
NET "sdram_dq<7>" LOC = "d10"; |
NET "sdram_dq<8>" LOC = "b11"; |
NET "sdram_dq<9>" LOC = "b12"; |
NET "sdram_dq<10>" LOC = "c12"; |
NET "sdram_dq<11>" LOC = "b14"; |
NET "sdram_dq<12>" LOC = "d14"; |
NET "sdram_dq<13>" LOC = "c16"; |
NET "sdram_dq<14>" LOC = "f12"; |
NET "sdram_dq<15>" LOC = "f13"; |
NET "sdram_fb" LOC = "n8"; |
NET "sdram_ldqm" LOC = "c10"; |
NET "sdram_ras_n" LOC = "a9"; |
NET "sdram_udqm" LOC = "d9"; |
NET "sdram_we_n" LOC = "b10"; |
|
# |
# flash ROM |
# |
NET "flash_a<0>" LOC = "n5"; |
NET "flash_a<1>" LOC = "k14"; |
NET "flash_a<2>" LOC = "k13"; |
NET "flash_a<3>" LOC = "k12"; |
NET "flash_a<4>" LOC = "l14"; |
NET "flash_a<5>" LOC = "m16"; |
NET "flash_a<6>" LOC = "l13"; |
NET "flash_a<7>" LOC = "n16"; |
NET "flash_a<8>" LOC = "n14"; |
NET "flash_a<9>" LOC = "p15"; |
NET "flash_a<10>" LOC = "r16"; |
NET "flash_a<11>" LOC = "p14"; |
NET "flash_a<12>" LOC = "p13"; |
NET "flash_a<13>" LOC = "n12"; |
NET "flash_a<14>" LOC = "t14"; |
NET "flash_a<15>" LOC = "r13"; |
NET "flash_a<16>" LOC = "n10"; |
NET "flash_a<17>" LOC = "m14"; |
NET "flash_a<18>" LOC = "k3"; |
NET "flash_a<19>" LOC = "k4"; |
NET "flash_byte_n" LOC = "t8"; |
NET "flash_ce_n" LOC = "r4"; |
NET "flash_d<0>" LOC = "m11"; |
NET "flash_d<1>" LOC = "n11"; |
NET "flash_d<2>" LOC = "p10"; |
NET "flash_d<3>" LOC = "r10"; |
NET "flash_d<4>" LOC = "t7"; |
NET "flash_d<5>" LOC = "r7"; |
NET "flash_d<6>" LOC = "n6"; |
NET "flash_d<7>" LOC = "m6"; |
NET "flash_d<8>" LOC = "t4"; |
NET "flash_d<9>" LOC = "r5"; |
NET "flash_d<10>" LOC = "t5"; |
NET "flash_d<11>" LOC = "p6"; |
NET "flash_d<12>" LOC = "m7"; |
NET "flash_d<13>" LOC = "r6"; |
NET "flash_d<14>" LOC = "n7"; |
NET "flash_d<15>" LOC = "p7"; |
NET "flash_oe_n" LOC = "p5"; |
NET "flash_rst_n" LOC = "p16"; |
NET "flash_we_n" LOC = "m13"; |
|
# |
# VGA display |
# |
NET "vga_hsync" LOC = "b7"; |
NET "vga_vsync" LOC = "d8"; |
NET "vga_r<0>" LOC = "c8"; |
NET "vga_r<1>" LOC = "d6"; |
NET "vga_r<2>" LOC = "b1"; |
NET "vga_g<0>" LOC = "a8"; |
NET "vga_g<1>" LOC = "a5"; |
NET "vga_g<2>" LOC = "c3"; |
NET "vga_b<0>" LOC = "c9"; |
NET "vga_b<1>" LOC = "e7"; |
NET "vga_b<2>" LOC = "d5"; |
|
# |
# keyboard |
# |
NET "ps2_clk" LOC = "b16"; |
NET "ps2_data" LOC = "e13"; |
|
# |
# serial line 0 |
# |
NET "rs232_0_rxd" LOC = "g5"; |
NET "rs232_0_txd" LOC = "j2"; |
|
# |
# serial line 1 |
# |
NET "rs232_1_rxd" LOC = "d1"; |
NET "rs232_1_txd" LOC = "f4"; |
|
# |
# disk, ethernet, etc. |
# |
NET "ata_cs0_n" LOC = "g15"; |
NET "ata_cs1_n" LOC = "g14"; |
NET "ata_dmack_n" LOC = "k1"; |
NET "ata_dmarq" LOC = "l4"; |
NET "ata_intrq" LOC = "h15"; |
NET "ata_iordy" LOC = "l2"; |
NET "ether_cs_n" LOC = "g13"; |
NET "pbus_a<0>" LOC = "l5"; |
NET "pbus_a<1>" LOC = "n2"; |
NET "pbus_a<2>" LOC = "m3"; |
NET "pbus_a<3>" LOC = "n1"; |
NET "pbus_a<4>" LOC = "t13"; |
NET "pbus_d<0>" LOC = "p12"; |
NET "pbus_d<10>" LOC = "f3"; |
NET "pbus_d<11>" LOC = "f2"; |
NET "pbus_d<12>" LOC = "g4"; |
NET "pbus_d<13>" LOC = "g3"; |
NET "pbus_d<14>" LOC = "g1"; |
NET "pbus_d<15>" LOC = "h4"; |
NET "pbus_d<1>" LOC = "j1"; |
NET "pbus_d<2>" LOC = "h1"; |
NET "pbus_d<3>" LOC = "h3"; |
NET "pbus_d<4>" LOC = "g2"; |
NET "pbus_d<5>" LOC = "k15"; |
NET "pbus_d<6>" LOC = "k16"; |
NET "pbus_d<7>" LOC = "f15"; |
NET "pbus_d<8>" LOC = "e2"; |
NET "pbus_d<9>" LOC = "e1"; |
NET "pbus_read_n" LOC = "p2"; |
NET "pbus_write_n" LOC = "r1"; |
NET "slot1_cs_n" LOC = "e15"; |
NET "slot2_cs_n" LOC = "d16"; |
|
# |
# board I/O |
# |
NET "sw1_3" LOC = "k2"; |
NET "sw1_4" LOC = "j4"; |
NET "sw2_n" LOC = "e11"; |
NET "sw3_n" LOC = "a13"; |
/trunk/fpga/boards/xsa-xst-3/src/busctrl/busctrl.v
0,0 → 1,225
// |
// busctrl.v -- bus controller |
// |
|
|
module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr, |
cpu_data_out, cpu_data_in, cpu_wt, |
ram_en, ram_wr, ram_size, ram_addr, |
ram_data_in, ram_data_out, ram_wt, |
rom_en, rom_wr, rom_size, rom_addr, |
rom_data_out, rom_wt, |
tmr0_en, tmr0_wr, tmr0_addr, |
tmr0_data_in, tmr0_data_out, tmr0_wt, |
tmr1_en, tmr1_wr, tmr1_addr, |
tmr1_data_in, tmr1_data_out, tmr1_wt, |
dsp_en, dsp_wr, dsp_addr, |
dsp_data_in, dsp_data_out, dsp_wt, |
kbd_en, kbd_wr, kbd_addr, |
kbd_data_in, kbd_data_out, kbd_wt, |
ser0_en, ser0_wr, ser0_addr, |
ser0_data_in, ser0_data_out, ser0_wt, |
ser1_en, ser1_wr, ser1_addr, |
ser1_data_in, ser1_data_out, ser1_wt, |
dsk_en, dsk_wr, dsk_addr, |
dsk_data_in, dsk_data_out, dsk_wt, |
bio_en, bio_wr, bio_addr, |
bio_data_in, bio_data_out, bio_wt); |
// cpu |
input cpu_en; |
input cpu_wr; |
input [1:0] cpu_size; |
input [31:0] cpu_addr; |
input [31:0] cpu_data_out; |
output [31:0] cpu_data_in; |
output cpu_wt; |
// ram |
output ram_en; |
output ram_wr; |
output [1:0] ram_size; |
output [24:0] ram_addr; |
output [31:0] ram_data_in; |
input [31:0] ram_data_out; |
input ram_wt; |
// rom |
output rom_en; |
output rom_wr; |
output [1:0] rom_size; |
output [20:0] rom_addr; |
input [31:0] rom_data_out; |
input rom_wt; |
// tmr0 |
output tmr0_en; |
output tmr0_wr; |
output [3:2] tmr0_addr; |
output [31:0] tmr0_data_in; |
input [31:0] tmr0_data_out; |
input tmr0_wt; |
// tmr1 |
output tmr1_en; |
output tmr1_wr; |
output [3:2] tmr1_addr; |
output [31:0] tmr1_data_in; |
input [31:0] tmr1_data_out; |
input tmr1_wt; |
// dsp |
output dsp_en; |
output dsp_wr; |
output [13:2] dsp_addr; |
output [15:0] dsp_data_in; |
input [15:0] dsp_data_out; |
input dsp_wt; |
// kbd |
output kbd_en; |
output kbd_wr; |
output kbd_addr; |
output [7:0] kbd_data_in; |
input [7:0] kbd_data_out; |
input kbd_wt; |
// ser0 |
output ser0_en; |
output ser0_wr; |
output [3:2] ser0_addr; |
output [7:0] ser0_data_in; |
input [7:0] ser0_data_out; |
input ser0_wt; |
// ser1 |
output ser1_en; |
output ser1_wr; |
output [3:2] ser1_addr; |
output [7:0] ser1_data_in; |
input [7:0] ser1_data_out; |
input ser1_wt; |
// dsk |
output dsk_en; |
output dsk_wr; |
output [19:2] dsk_addr; |
output [31:0] dsk_data_in; |
input [31:0] dsk_data_out; |
input dsk_wt; |
// bio |
output bio_en; |
output bio_wr; |
output bio_addr; |
output [31:0] bio_data_in; |
input [31:0] bio_data_out; |
input bio_wt; |
|
wire i_o_en; |
|
// |
// address decoder |
// |
// RAM: architectural limit = 512 MB |
// board limit = 32 MB |
assign ram_en = |
(cpu_en == 1 && cpu_addr[31:29] == 3'b000 |
&& cpu_addr[28:25] == 4'b0000) ? 1 : 0; |
// ROM: architectural limit = 256 MB |
// board limit = 2 MB |
assign rom_en = |
(cpu_en == 1 && cpu_addr[31:28] == 4'b0010 |
&& cpu_addr[27:21] == 7'b0000000) ? 1 : 0; |
// I/O: architectural limit = 256 MB |
assign i_o_en = |
(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0; |
assign tmr0_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
assign tmr1_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00 |
&& cpu_addr[19:12] == 8'h01) ? 1 : 0; |
assign dsp_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0; |
assign kbd_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h02) ? 1 : 0; |
assign ser0_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h03 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
assign ser1_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h03 |
&& cpu_addr[19:12] == 8'h01) ? 1 : 0; |
assign dsk_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0; |
assign bio_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h10 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
|
// to cpu |
assign cpu_wt = |
(ram_en == 1) ? ram_wt : |
(rom_en == 1) ? rom_wt : |
(tmr0_en == 1) ? tmr0_wt : |
(tmr1_en == 1) ? tmr1_wt : |
(dsp_en == 1) ? dsp_wt : |
(kbd_en == 1) ? kbd_wt : |
(ser0_en == 1) ? ser0_wt : |
(ser1_en == 1) ? ser1_wt : |
(dsk_en == 1) ? dsk_wt : |
(bio_en == 1) ? bio_wt : |
1; |
assign cpu_data_in[31:0] = |
(ram_en == 1) ? ram_data_out[31:0] : |
(rom_en == 1) ? rom_data_out[31:0] : |
(tmr0_en == 1) ? tmr0_data_out[31:0] : |
(tmr1_en == 1) ? tmr1_data_out[31:0] : |
(dsp_en == 1) ? { 16'h0000, dsp_data_out[15:0] } : |
(kbd_en == 1) ? { 24'h000000, kbd_data_out[7:0] } : |
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } : |
(ser1_en == 1) ? { 24'h000000, ser1_data_out[7:0] } : |
(dsk_en == 1) ? dsk_data_out[31:0] : |
(bio_en == 1) ? bio_data_out[31:0] : |
32'h00000000; |
|
// to ram |
assign ram_wr = cpu_wr; |
assign ram_size[1:0] = cpu_size[1:0]; |
assign ram_addr[24:0] = cpu_addr[24:0]; |
assign ram_data_in[31:0] = cpu_data_out[31:0]; |
|
// to rom |
assign rom_wr = cpu_wr; |
assign rom_size[1:0] = cpu_size[1:0]; |
assign rom_addr[20:0] = cpu_addr[20:0]; |
|
// to tmr0 |
assign tmr0_wr = cpu_wr; |
assign tmr0_addr[3:2] = cpu_addr[3:2]; |
assign tmr0_data_in[31:0] = cpu_data_out[31:0]; |
|
// to tmr1 |
assign tmr1_wr = cpu_wr; |
assign tmr1_addr[3:2] = cpu_addr[3:2]; |
assign tmr1_data_in[31:0] = cpu_data_out[31:0]; |
|
// to dsp |
assign dsp_wr = cpu_wr; |
assign dsp_addr[13:2] = cpu_addr[13:2]; |
assign dsp_data_in[15:0] = cpu_data_out[15:0]; |
|
// to kbd |
assign kbd_wr = cpu_wr; |
assign kbd_addr = cpu_addr[2]; |
assign kbd_data_in[7:0] = cpu_data_out[7:0]; |
|
// to ser0 |
assign ser0_wr = cpu_wr; |
assign ser0_addr[3:2] = cpu_addr[3:2]; |
assign ser0_data_in[7:0] = cpu_data_out[7:0]; |
|
// to ser1 |
assign ser1_wr = cpu_wr; |
assign ser1_addr[3:2] = cpu_addr[3:2]; |
assign ser1_data_in[7:0] = cpu_data_out[7:0]; |
|
// to dsk |
assign dsk_wr = cpu_wr; |
assign dsk_addr[19:2] = cpu_addr[19:2]; |
assign dsk_data_in[31:0] = cpu_data_out[31:0]; |
|
// to bio |
assign bio_wr = cpu_wr; |
assign bio_addr = cpu_addr[2]; |
assign bio_data_in[31:0] = cpu_data_out[31:0]; |
|
endmodule |
/trunk/fpga/boards/s3e-500/clk_rst/clk_rst.v
File deleted
/trunk/fpga/boards/s3e-500/toplevel/eco32.v
File deleted
/trunk/fpga/boards/s3e-500/toplevel/eco32.ucf
File deleted
/trunk/fpga/boards/s3e-500/bio/bio.v
File deleted
/trunk/fpga/boards/s3e-500/spi/spi.v
File deleted
/trunk/fpga/boards/s3e-500/busctrl/busctrl.v
File deleted
/trunk/fpga/boards/s3e-500/src/clk_rst/clk_rst.v
0,0 → 1,146
// |
// clk_rst.v -- clock and reset generator |
// |
|
|
module clk_rst(clk_in, reset_in, |
ddr_clk_0, ddr_clk_90, ddr_clk_180, |
ddr_clk_270, ddr_clk_ok, clk, reset); |
input clk_in; |
input reset_in; |
output ddr_clk_0; |
output ddr_clk_90; |
output ddr_clk_180; |
output ddr_clk_270; |
output ddr_clk_ok; |
output clk; |
output reset; |
|
wire clk50_in; |
wire clk50_out; |
wire clk50_ok; |
wire clk100_out; |
wire clk100_in; |
wire clk100_0; |
wire clk100_90; |
wire clk100_180; |
wire clk100_270; |
wire clk100_ok; |
|
reg reset_p; |
reg reset_s; |
reg [23:0] reset_counter; |
wire reset_counting; |
|
//------------------------------------------------------------ |
|
IBUFG clk_in_buffer( |
.I(clk_in), |
.O(clk50_in) |
); |
|
DCM_SP dcm50( |
.RST(1'b0), |
.CLKIN(clk50_in), |
.CLKFB(clk), |
.CLK0(clk50_out), |
.CLK2X(clk100_out), |
.LOCKED(clk50_ok), |
.PSCLK(1'b0), |
.PSEN(1'b0), |
.PSINCDEC(1'b0) |
); |
|
defparam dcm50.CLKDV_DIVIDE = 2.0; |
defparam dcm50.CLKFX_DIVIDE = 1; |
defparam dcm50.CLKFX_MULTIPLY = 4; |
defparam dcm50.CLKIN_DIVIDE_BY_2 = "FALSE"; |
defparam dcm50.CLKIN_PERIOD = 20.0; |
defparam dcm50.CLKOUT_PHASE_SHIFT = "NONE"; |
defparam dcm50.CLK_FEEDBACK = "1X"; |
defparam dcm50.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; |
defparam dcm50.DLL_FREQUENCY_MODE = "LOW"; |
defparam dcm50.DUTY_CYCLE_CORRECTION = "TRUE"; |
defparam dcm50.PHASE_SHIFT = 0; |
defparam dcm50.STARTUP_WAIT = "FALSE"; |
|
BUFG clk50_buffer( |
.I(clk50_out), |
.O(clk) |
); |
|
BUFG clk100_buffer( |
.I(clk100_out), |
.O(clk100_in) |
); |
|
//------------------------------------------------------------ |
|
DCM_SP dcm100( |
.RST(~clk50_ok), |
.CLKIN(clk100_in), |
.CLKFB(ddr_clk_0), |
.CLK0(clk100_0), |
.CLK90(clk100_90), |
.CLK180(clk100_180), |
.CLK270(clk100_270), |
.LOCKED(clk100_ok), |
.PSCLK(1'b0), |
.PSEN(1'b0), |
.PSINCDEC(1'b0) |
); |
|
defparam dcm100.CLKDV_DIVIDE = 2.0; |
defparam dcm100.CLKFX_DIVIDE = 1; |
defparam dcm100.CLKFX_MULTIPLY = 4; |
defparam dcm100.CLKIN_DIVIDE_BY_2 = "FALSE"; |
defparam dcm100.CLKIN_PERIOD = 10.0; |
defparam dcm100.CLKOUT_PHASE_SHIFT = "NONE"; |
defparam dcm100.CLK_FEEDBACK = "1X"; |
defparam dcm100.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; |
defparam dcm100.DLL_FREQUENCY_MODE = "LOW"; |
defparam dcm100.DUTY_CYCLE_CORRECTION = "TRUE"; |
defparam dcm100.PHASE_SHIFT = 0; |
defparam dcm100.STARTUP_WAIT = "FALSE"; |
|
BUFG clk100_0_buffer( |
.I(clk100_0), |
.O(ddr_clk_0) |
); |
|
BUFG clk100_90_buffer( |
.I(clk100_90), |
.O(ddr_clk_90) |
); |
|
BUFG clk100_180_buffer( |
.I(clk100_180), |
.O(ddr_clk_180) |
); |
|
BUFG clk100_270_buffer( |
.I(clk100_270), |
.O(ddr_clk_270) |
); |
|
assign ddr_clk_ok = clk100_ok; |
|
//------------------------------------------------------------ |
|
assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1; |
|
always @(posedge clk) begin |
reset_p <= reset_in; |
reset_s <= reset_p; |
if (reset_s | ~clk50_ok | ~clk100_ok) begin |
reset_counter <= 24'h000000; |
end else begin |
if (reset_counting == 1) begin |
reset_counter <= reset_counter + 1; |
end |
end |
end |
|
assign reset = reset_counting; |
|
endmodule |
/trunk/fpga/boards/s3e-500/src/bio/bio.v
0,0 → 1,64
// |
// bio.v -- board specific I/O |
// |
|
|
module bio(clk, reset, |
en, wr, addr, |
data_in, data_out, |
wt, spi_en, |
sw, led, |
lcd_e, lcd_rw, lcd_rs, |
spi_ss_b, fpga_init_b); |
// internal interface |
input clk; |
input reset; |
input en; |
input wr; |
input addr; |
input [31:0] data_in; |
output [31:0] data_out; |
output wt; |
output spi_en; |
// external interface |
input [3:0] sw; |
output [7:0] led; |
output lcd_e; |
output lcd_rw; |
output lcd_rs; |
output spi_ss_b; |
output fpga_init_b; |
|
reg [31:0] bio_out; |
wire [31:0] bio_in; |
|
always @(posedge clk) begin |
if (reset) begin |
bio_out[31:0] <= 32'h0; |
end else begin |
if (en & wr & ~addr) begin |
bio_out[31:0] <= data_in[31:0]; |
end |
end |
end |
|
assign data_out[31:0] = |
(addr == 0) ? bio_out[31:0] : bio_in[31:0]; |
assign wt = 0; |
assign spi_en = bio_out[31]; |
|
assign bio_in[31:0] = { 28'h0, sw[3:0] }; |
|
assign led[7:0] = bio_out[7:0]; |
|
// disable the character LCD screen |
// it may be enabled if spi_en = 1 |
assign lcd_e = 0; |
assign lcd_rw = 0; |
assign lcd_rs = 0; |
|
// disable SPI serial and platform flash ROMs |
assign spi_ss_b = 1; |
assign fpga_init_b = 0; |
|
endmodule |
/trunk/fpga/boards/s3e-500/src/toplevel/eco32.v
0,0 → 1,517
// |
// eco32.v -- ECO32 top-level description |
// |
|
|
module eco32(clk_in, |
reset_in, |
sdram_ck_p, |
sdram_ck_n, |
sdram_cke, |
sdram_cs_n, |
sdram_ras_n, |
sdram_cas_n, |
sdram_we_n, |
sdram_ba, |
sdram_a, |
sdram_udm, |
sdram_ldm, |
sdram_udqs, |
sdram_ldqs, |
sdram_dq, |
flash_ce_n, |
flash_oe_n, |
flash_we_n, |
flash_byte_n, |
flash_a, |
flash_d, |
vga_hsync, |
vga_vsync, |
vga_r, |
vga_g, |
vga_b, |
ps2_clk, |
ps2_data, |
rs232_0_rxd, |
rs232_0_txd, |
rs232_1_rxd, |
rs232_1_txd, |
spi_sck, |
spi_mosi, |
dac_cs_n, |
dac_clr_n, |
amp_cs_n, |
amp_shdn, |
ad_conv, |
sw, |
led, |
lcd_e, |
lcd_rw, |
lcd_rs, |
spi_ss_b, |
fpga_init_b); |
// clock and reset |
input clk_in; |
input reset_in; |
// SDRAM |
output sdram_ck_p; |
output sdram_ck_n; |
output sdram_cke; |
output sdram_cs_n; |
output sdram_ras_n; |
output sdram_cas_n; |
output sdram_we_n; |
output [1:0] sdram_ba; |
output [12:0] sdram_a; |
output sdram_udm; |
output sdram_ldm; |
inout sdram_udqs; |
inout sdram_ldqs; |
inout [15:0] sdram_dq; |
// flash ROM |
output flash_ce_n; |
output flash_oe_n; |
output flash_we_n; |
output flash_byte_n; |
output [23:0] flash_a; |
input [15:0] flash_d; |
// VGA display |
output vga_hsync; |
output vga_vsync; |
output vga_r; |
output vga_g; |
output vga_b; |
// keyboard |
input ps2_clk; |
input ps2_data; |
// serial line 0 |
input rs232_0_rxd; |
output rs232_0_txd; |
// serial line 1 |
input rs232_1_rxd; |
output rs232_1_txd; |
// SPI bus controller |
output spi_sck; |
output spi_mosi; |
output dac_cs_n; |
output dac_clr_n; |
output amp_cs_n; |
output amp_shdn; |
output ad_conv; |
// board I/O |
input [3:0] sw; |
output [7:0] led; |
output lcd_e; |
output lcd_rw; |
output lcd_rs; |
output spi_ss_b; |
output fpga_init_b; |
|
// clk_rst |
wire ddr_clk_0; |
wire ddr_clk_90; |
wire ddr_clk_180; |
wire ddr_clk_270; |
wire ddr_clk_ok; |
wire clk; |
wire reset; |
// cpu |
wire cpu_en; |
wire cpu_wr; |
wire [1:0] cpu_size; |
wire [31:0] cpu_addr; |
wire [31:0] cpu_data_in; |
wire [31:0] cpu_data_out; |
wire cpu_wt; |
wire [15:0] cpu_irq; |
// ram |
wire ram_en; |
wire ram_wr; |
wire [1:0] ram_size; |
wire [25:0] ram_addr; |
wire [31:0] ram_data_in; |
wire [31:0] ram_data_out; |
wire ram_wt; |
// rom |
wire rom_en; |
wire rom_wr; |
wire [1:0] rom_size; |
wire [23:0] rom_addr; |
wire [31:0] rom_data_out; |
wire rom_wt; |
// tmr0 |
wire tmr0_en; |
wire tmr0_wr; |
wire [3:2] tmr0_addr; |
wire [31:0] tmr0_data_in; |
wire [31:0] tmr0_data_out; |
wire tmr0_wt; |
wire tmr0_irq; |
// tmr1 |
wire tmr1_en; |
wire tmr1_wr; |
wire [3:2] tmr1_addr; |
wire [31:0] tmr1_data_in; |
wire [31:0] tmr1_data_out; |
wire tmr1_wt; |
wire tmr1_irq; |
// dsp |
wire dsp_en; |
wire dsp_wr; |
wire [13:2] dsp_addr; |
wire [15:0] dsp_data_in; |
wire [15:0] dsp_data_out; |
wire dsp_wt; |
// kbd |
wire kbd_en; |
wire kbd_wr; |
wire kbd_addr; |
wire [7:0] kbd_data_in; |
wire [7:0] kbd_data_out; |
wire kbd_wt; |
wire kbd_irq; |
// ser0 |
wire ser0_en; |
wire ser0_wr; |
wire [3:2] ser0_addr; |
wire [7:0] ser0_data_in; |
wire [7:0] ser0_data_out; |
wire ser0_wt; |
wire ser0_irq_r; |
wire ser0_irq_t; |
// ser1 |
wire ser1_en; |
wire ser1_wr; |
wire [3:2] ser1_addr; |
wire [7:0] ser1_data_in; |
wire [7:0] ser1_data_out; |
wire ser1_wt; |
wire ser1_irq_r; |
wire ser1_irq_t; |
// fms |
wire fms_en; |
wire fms_wr; |
wire [11:2] fms_addr; |
wire [31:0] fms_data_in; |
wire [31:0] fms_data_out; |
wire fms_wt; |
// spi |
wire [15:0] dac_sample_l; |
wire [15:0] dac_sample_r; |
wire dac_next; |
// bio |
wire bio_en; |
wire bio_wr; |
wire bio_addr; |
wire [31:0] bio_data_in; |
wire [31:0] bio_data_out; |
wire bio_wt; |
wire spi_en; |
|
clk_rst clk_rst1( |
.clk_in(clk_in), |
.reset_in(reset_in), |
.ddr_clk_0(ddr_clk_0), |
.ddr_clk_90(ddr_clk_90), |
.ddr_clk_180(ddr_clk_180), |
.ddr_clk_270(ddr_clk_270), |
.ddr_clk_ok(ddr_clk_ok), |
.clk(clk), |
.reset(reset) |
); |
|
busctrl busctrl1( |
// cpu |
.cpu_en(cpu_en), |
.cpu_wr(cpu_wr), |
.cpu_size(cpu_size[1:0]), |
.cpu_addr(cpu_addr[31:0]), |
.cpu_data_in(cpu_data_in[31:0]), |
.cpu_data_out(cpu_data_out[31:0]), |
.cpu_wt(cpu_wt), |
// ram |
.ram_en(ram_en), |
.ram_wr(ram_wr), |
.ram_size(ram_size[1:0]), |
.ram_addr(ram_addr[25:0]), |
.ram_data_in(ram_data_in[31:0]), |
.ram_data_out(ram_data_out[31:0]), |
.ram_wt(ram_wt), |
// rom |
.rom_en(rom_en), |
.rom_wr(rom_wr), |
.rom_size(rom_size[1:0]), |
.rom_addr(rom_addr[23:0]), |
.rom_data_out(rom_data_out[31:0]), |
.rom_wt(rom_wt), |
// tmr0 |
.tmr0_en(tmr0_en), |
.tmr0_wr(tmr0_wr), |
.tmr0_addr(tmr0_addr[3:2]), |
.tmr0_data_in(tmr0_data_in[31:0]), |
.tmr0_data_out(tmr0_data_out[31:0]), |
.tmr0_wt(tmr0_wt), |
// tmr1 |
.tmr1_en(tmr1_en), |
.tmr1_wr(tmr1_wr), |
.tmr1_addr(tmr1_addr[3:2]), |
.tmr1_data_in(tmr1_data_in[31:0]), |
.tmr1_data_out(tmr1_data_out[31:0]), |
.tmr1_wt(tmr1_wt), |
// dsp |
.dsp_en(dsp_en), |
.dsp_wr(dsp_wr), |
.dsp_addr(dsp_addr[13:2]), |
.dsp_data_in(dsp_data_in[15:0]), |
.dsp_data_out(dsp_data_out[15:0]), |
.dsp_wt(dsp_wt), |
// kbd |
.kbd_en(kbd_en), |
.kbd_wr(kbd_wr), |
.kbd_addr(kbd_addr), |
.kbd_data_in(kbd_data_in[7:0]), |
.kbd_data_out(kbd_data_out[7:0]), |
.kbd_wt(kbd_wt), |
// ser0 |
.ser0_en(ser0_en), |
.ser0_wr(ser0_wr), |
.ser0_addr(ser0_addr[3:2]), |
.ser0_data_in(ser0_data_in[7:0]), |
.ser0_data_out(ser0_data_out[7:0]), |
.ser0_wt(ser0_wt), |
// ser1 |
.ser1_en(ser1_en), |
.ser1_wr(ser1_wr), |
.ser1_addr(ser1_addr[3:2]), |
.ser1_data_in(ser1_data_in[7:0]), |
.ser1_data_out(ser1_data_out[7:0]), |
.ser1_wt(ser1_wt), |
// fms |
.fms_en(fms_en), |
.fms_wr(fms_wr), |
.fms_addr(fms_addr[11:2]), |
.fms_data_in(fms_data_in[31:0]), |
.fms_data_out(fms_data_out[31:0]), |
.fms_wt(fms_wt), |
// bio |
.bio_en(bio_en), |
.bio_wr(bio_wr), |
.bio_addr(bio_addr), |
.bio_data_in(bio_data_in[31:0]), |
.bio_data_out(bio_data_out[31:0]), |
.bio_wt(bio_wt) |
); |
|
cpu cpu1( |
.clk(clk), |
.reset(reset), |
.bus_en(cpu_en), |
.bus_wr(cpu_wr), |
.bus_size(cpu_size[1:0]), |
.bus_addr(cpu_addr[31:0]), |
.bus_data_in(cpu_data_in[31:0]), |
.bus_data_out(cpu_data_out[31:0]), |
.bus_wt(cpu_wt), |
.irq(cpu_irq[15:0]) |
); |
|
assign cpu_irq[15] = tmr1_irq; |
assign cpu_irq[14] = tmr0_irq; |
assign cpu_irq[13] = 1'b0; |
assign cpu_irq[12] = 1'b0; |
assign cpu_irq[11] = 1'b0; |
assign cpu_irq[10] = 1'b0; |
assign cpu_irq[ 9] = 1'b0; |
assign cpu_irq[ 8] = 1'b0; //dsk_irq; |
assign cpu_irq[ 7] = 1'b0; |
assign cpu_irq[ 6] = 1'b0; |
assign cpu_irq[ 5] = 1'b0; |
assign cpu_irq[ 4] = kbd_irq; |
assign cpu_irq[ 3] = ser1_irq_r; |
assign cpu_irq[ 2] = ser1_irq_t; |
assign cpu_irq[ 1] = ser0_irq_r; |
assign cpu_irq[ 0] = ser0_irq_t; |
|
ram ram1( |
.ddr_clk_0(ddr_clk_0), |
.ddr_clk_90(ddr_clk_90), |
.ddr_clk_180(ddr_clk_180), |
.ddr_clk_270(ddr_clk_270), |
.ddr_clk_ok(ddr_clk_ok), |
.clk(clk), |
.reset(reset), |
.en(ram_en), |
.wr(ram_wr), |
.size(ram_size[1:0]), |
.addr(ram_addr[25:0]), |
.data_in(ram_data_in[31:0]), |
.data_out(ram_data_out[31:0]), |
.wt(ram_wt), |
.sdram_ck_p(sdram_ck_p), |
.sdram_ck_n(sdram_ck_n), |
.sdram_cke(sdram_cke), |
.sdram_cs_n(sdram_cs_n), |
.sdram_ras_n(sdram_ras_n), |
.sdram_cas_n(sdram_cas_n), |
.sdram_we_n(sdram_we_n), |
.sdram_ba(sdram_ba[1:0]), |
.sdram_a(sdram_a[12:0]), |
.sdram_udm(sdram_udm), |
.sdram_ldm(sdram_ldm), |
.sdram_udqs(sdram_udqs), |
.sdram_ldqs(sdram_ldqs), |
.sdram_dq(sdram_dq[15:0]) |
); |
|
rom rom1( |
.clk(clk), |
.reset(reset), |
.en(rom_en), |
.wr(rom_wr), |
.size(rom_size[1:0]), |
.addr(rom_addr[23:0]), |
.data_out(rom_data_out[31:0]), |
.wt(rom_wt), |
.spi_en(spi_en), |
.ce_n(flash_ce_n), |
.oe_n(flash_oe_n), |
.we_n(flash_we_n), |
.byte_n(flash_byte_n), |
.a(flash_a[23:0]), |
.d(flash_d[15:0]) |
); |
|
tmr tmr1_0( |
.clk(clk), |
.reset(reset), |
.en(tmr0_en), |
.wr(tmr0_wr), |
.addr(tmr0_addr[3:2]), |
.data_in(tmr0_data_in[31:0]), |
.data_out(tmr0_data_out[31:0]), |
.wt(tmr0_wt), |
.irq(tmr0_irq) |
); |
|
tmr tmr1_1( |
.clk(clk), |
.reset(reset), |
.en(tmr1_en), |
.wr(tmr1_wr), |
.addr(tmr1_addr[3:2]), |
.data_in(tmr1_data_in[31:0]), |
.data_out(tmr1_data_out[31:0]), |
.wt(tmr1_wt), |
.irq(tmr1_irq) |
); |
|
dsp dsp1( |
.clk(clk), |
.reset(reset), |
.en(dsp_en), |
.wr(dsp_wr), |
.addr(dsp_addr[13:2]), |
.data_in(dsp_data_in[15:0]), |
.data_out(dsp_data_out[15:0]), |
.wt(dsp_wt), |
.hsync(vga_hsync), |
.vsync(vga_vsync), |
.r(vga_r), |
.g(vga_g), |
.b(vga_b) |
); |
|
kbd kbd1( |
.clk(clk), |
.reset(reset), |
.en(kbd_en), |
.wr(kbd_wr), |
.addr(kbd_addr), |
.data_in(kbd_data_in[7:0]), |
.data_out(kbd_data_out[7:0]), |
.wt(kbd_wt), |
.irq(kbd_irq), |
.ps2_clk(ps2_clk), |
.ps2_data(ps2_data) |
); |
|
ser ser1_0( |
.clk(clk), |
.reset(reset), |
.en(ser0_en), |
.wr(ser0_wr), |
.addr(ser0_addr[3:2]), |
.data_in(ser0_data_in[7:0]), |
.data_out(ser0_data_out[7:0]), |
.wt(ser0_wt), |
.irq_r(ser0_irq_r), |
.irq_t(ser0_irq_t), |
.rxd(rs232_0_rxd), |
.txd(rs232_0_txd) |
); |
|
ser ser1_1( |
.clk(clk), |
.reset(reset), |
.en(ser1_en), |
.wr(ser1_wr), |
.addr(ser1_addr[3:2]), |
.data_in(ser1_data_in[7:0]), |
.data_out(ser1_data_out[7:0]), |
.wt(ser1_wt), |
.irq_r(ser1_irq_r), |
.irq_t(ser1_irq_t), |
.rxd(rs232_1_rxd), |
.txd(rs232_1_txd) |
); |
|
fms fms1( |
.clk(clk), |
.reset(reset), |
.en(fms_en), |
.wr(fms_wr), |
.addr(fms_addr[11:2]), |
.data_in(fms_data_in[31:0]), |
.data_out(fms_data_out[31:0]), |
.wt(fms_wt), |
.next(dac_next), |
.sample_l(dac_sample_l[15:0]), |
.sample_r(dac_sample_r[15:0]) |
); |
|
spi spi1( |
.clk(clk), |
.reset(reset), |
.spi_en(spi_en), |
.dac_sample_l(dac_sample_l[15:0]), |
.dac_sample_r(dac_sample_r[15:0]), |
.dac_next(dac_next), |
.spi_sck(spi_sck), |
.spi_mosi(spi_mosi), |
.dac_cs_n(dac_cs_n), |
.dac_clr_n(dac_clr_n), |
.amp_cs_n(amp_cs_n), |
.amp_shdn(amp_shdn), |
.ad_conv(ad_conv) |
); |
|
bio bio1( |
.clk(clk), |
.reset(reset), |
.en(bio_en), |
.wr(bio_wr), |
.addr(bio_addr), |
.data_in(bio_data_in[31:0]), |
.data_out(bio_data_out[31:0]), |
.wt(bio_wt), |
.spi_en(spi_en), |
.sw(sw[3:0]), |
.led(led[7:0]), |
.lcd_e(lcd_e), |
.lcd_rw(lcd_rw), |
.lcd_rs(lcd_rs), |
.spi_ss_b(spi_ss_b), |
.fpga_init_b(fpga_init_b) |
); |
|
endmodule |
/trunk/fpga/boards/s3e-500/src/toplevel/eco32.ucf
0,0 → 1,296
# |
# eco32.ucf -- ECO32 user constraints for S3E starter kit board |
# |
|
# |
# clock and reset |
# |
NET "clk_in" |
PERIOD = 20.0ns HIGH 40%; |
NET "clk_in" |
LOC = "C9" | IOSTANDARD = LVCMOS33; |
NET "reset_in" |
LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; |
|
# |
# DDR SDRAM |
# |
NET "sdram_ck_p" |
LOC = "J5" | IOSTANDARD = SSTL2_I; |
NET "sdram_ck_n" |
LOC = "J4" | IOSTANDARD = SSTL2_I; |
NET "sdram_cke" |
LOC = "K3" | IOSTANDARD = SSTL2_I; |
NET "sdram_cs_n" |
LOC = "K4" | IOSTANDARD = SSTL2_I; |
NET "sdram_ras_n" |
LOC = "C1" | IOSTANDARD = SSTL2_I; |
NET "sdram_cas_n" |
LOC = "C2" | IOSTANDARD = SSTL2_I; |
NET "sdram_we_n" |
LOC = "D1" | IOSTANDARD = SSTL2_I; |
NET "sdram_ba<1>" |
LOC = "K6" | IOSTANDARD = SSTL2_I; |
NET "sdram_ba<0>" |
LOC = "K5" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<12>" |
LOC = "P2" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<11>" |
LOC = "N5" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<10>" |
LOC = "T2" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<9>" |
LOC = "N4" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<8>" |
LOC = "H2" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<7>" |
LOC = "H1" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<6>" |
LOC = "H3" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<5>" |
LOC = "H4" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<4>" |
LOC = "F4" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<3>" |
LOC = "P1" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<2>" |
LOC = "R2" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<1>" |
LOC = "R3" | IOSTANDARD = SSTL2_I; |
NET "sdram_a<0>" |
LOC = "T1" | IOSTANDARD = SSTL2_I; |
NET "sdram_udm" |
LOC = "J1" | IOSTANDARD = SSTL2_I; |
NET "sdram_ldm" |
LOC = "J2" | IOSTANDARD = SSTL2_I; |
NET "sdram_udqs" |
LOC = "G3" | IOSTANDARD = SSTL2_I; |
NET "sdram_ldqs" |
LOC = "L6" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<15>" |
LOC = "H5" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<14>" |
LOC = "H6" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<13>" |
LOC = "G5" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<12>" |
LOC = "G6" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<11>" |
LOC = "F2" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<10>" |
LOC = "F1" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<9>" |
LOC = "E1" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<8>" |
LOC = "E2" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<7>" |
LOC = "M6" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<6>" |
LOC = "M5" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<5>" |
LOC = "M4" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<4>" |
LOC = "M3" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<3>" |
LOC = "L4" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<2>" |
LOC = "L3" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<1>" |
LOC = "L1" | IOSTANDARD = SSTL2_I; |
NET "sdram_dq<0>" |
LOC = "L2" | IOSTANDARD = SSTL2_I; |
|
# |
# prohibit VREF pins |
# |
CONFIG PROHIBIT = D2; |
CONFIG PROHIBIT = G4; |
CONFIG PROHIBIT = J6; |
CONFIG PROHIBIT = L5; |
CONFIG PROHIBIT = R4; |
|
# |
# parallel NOR flash ROM |
# |
NET "flash_ce_n" |
LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_oe_n" |
LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_we_n" |
LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_byte_n" |
LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<23>" |
LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<22>" |
LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<21>" |
LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<20>" |
LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<19>" |
LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<18>" |
LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<17>" |
LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<16>" |
LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<15>" |
LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<14>" |
LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<13>" |
LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<12>" |
LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<11>" |
LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<10>" |
LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<9>" |
LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<8>" |
LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<7>" |
LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<6>" |
LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<5>" |
LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<4>" |
LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<3>" |
LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<2>" |
LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<1>" |
LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_a<0>" |
LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<15>" |
LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<14>" |
LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<13>" |
LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<12>" |
LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<11>" |
LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<10>" |
LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<9>" |
LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<8>" |
LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<7>" |
LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<6>" |
LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<5>" |
LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<4>" |
LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<3>" |
LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<2>" |
LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<1>" |
LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "flash_d<0>" |
LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
|
# |
# VGA display |
# |
NET "vga_hsync" |
LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; |
NET "vga_vsync" |
LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; |
NET "vga_r" |
LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; |
NET "vga_g" |
LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; |
NET "vga_b" |
LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST; |
|
# |
# keyboard |
# |
NET "ps2_clk" |
LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; |
NET "ps2_data" |
LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; |
|
# |
# serial line 0 |
# |
NET "rs232_0_rxd" |
LOC = "R7" | IOSTANDARD = LVTTL; |
NET "rs232_0_txd" |
LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
|
# |
# serial line 1 |
# |
NET "rs232_1_rxd" |
LOC = "U8" | IOSTANDARD = LVTTL; |
NET "rs232_1_txd" |
LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
|
# |
# SPI bus controller |
# |
NET "spi_sck" |
LOC = "U16" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
NET "spi_mosi" |
LOC = "T4" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
NET "dac_cs_n" |
LOC = "N8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; |
NET "dac_clr_n" |
LOC = "P8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; |
NET "amp_cs_n" |
LOC = "N7" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
NET "amp_shdn" |
LOC = "P7" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
NET "ad_conv" |
LOC = "P11" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
|
# |
# board I/O |
# |
NET "sw<3>" |
LOC = "N17" | IOSTANDARD = LVTTL | PULLUP; |
NET "sw<2>" |
LOC = "H18" | IOSTANDARD = LVTTL | PULLUP; |
NET "sw<1>" |
LOC = "L14" | IOSTANDARD = LVTTL | PULLUP; |
NET "sw<0>" |
LOC = "L13" | IOSTANDARD = LVTTL | PULLUP; |
NET "led<7>" |
LOC = "F9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<6>" |
LOC = "E9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<5>" |
LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<4>" |
LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<3>" |
LOC = "F11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<2>" |
LOC = "E11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<1>" |
LOC = "E12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "led<0>" |
LOC = "F12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; |
NET "lcd_e" |
LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "lcd_rw" |
LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "lcd_rs" |
LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
NET "spi_ss_b" |
LOC = "U3" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW; |
NET "fpga_init_b" |
LOC = "T3" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; |
/trunk/fpga/boards/s3e-500/src/spi/spi.v
0,0 → 1,136
// |
// spi.v -- SPI bus controller |
// |
|
|
module spi(clk, reset, spi_en, |
dac_sample_l, dac_sample_r, dac_next, |
spi_sck, spi_mosi, |
dac_cs_n, dac_clr_n, |
amp_cs_n, amp_shdn, |
ad_conv); |
// internal interface |
input clk; |
input reset; |
input spi_en; |
// DAC controller interface |
input [15:0] dac_sample_l; |
input [15:0] dac_sample_r; |
output dac_next; |
// external interface |
output spi_sck; |
output spi_mosi; |
output dac_cs_n; |
output dac_clr_n; |
output amp_cs_n; |
output amp_shdn; |
output ad_conv; |
|
//------------------------------------------------------------ |
|
// |
// SPI timing and clock generator |
// |
|
reg [9:0] timing; |
|
always @(posedge clk) begin |
if (reset) begin |
timing <= 10'h0; |
end else begin |
if (spi_en == 1'b0 && timing == 10'h0) begin |
// put SPI on hold in state 0 if disabled |
timing <= timing; |
end else begin |
// else step through the command cycle |
timing <= timing + 1; |
end |
end |
end |
|
assign spi_sck = timing[0]; |
|
//------------------------------------------------------------ |
|
// |
// DAC controller |
// |
|
reg dac_ld; |
reg [47:0] dac_sr; |
wire dac_shift; |
|
assign dac_next = (timing[9:0] == 10'h001) ? 1 : 0; |
|
always @(posedge clk) begin |
if (reset) begin |
dac_ld <= 1'b1; |
end else begin |
if (timing[9:0] == 10'h001) begin |
dac_ld <= 1'b0; |
end |
if (timing[9:0] == 10'h031) begin |
dac_ld <= 1'b1; |
end |
if (timing[9:0] == 10'h033) begin |
dac_ld <= 1'b0; |
end |
if (timing[9:0] == 10'h063) begin |
dac_ld <= 1'b1; |
end |
end |
end |
|
assign dac_shift = spi_sck & ~dac_ld; |
|
always @(posedge clk) begin |
if (reset) begin |
dac_sr <= 48'h0; |
end else begin |
if (dac_next) begin |
dac_sr[47:44] <= 4'b0011; |
dac_sr[43:40] <= 4'b0000; |
dac_sr[39:24] <= { ~dac_sample_l[15], |
dac_sample_l[14:0] }; |
dac_sr[23:20] <= 4'b0011; |
dac_sr[19:16] <= 4'b0001; |
dac_sr[15: 0] <= { ~dac_sample_r[15], |
dac_sample_r[14:0] }; |
end else begin |
if (dac_shift) begin |
dac_sr[47:1] <= dac_sr[46:0]; |
dac_sr[0] <= 1'b0; |
end |
end |
end |
end |
|
assign dac_cs_n = dac_ld; |
assign dac_clr_n = ~reset; |
|
//------------------------------------------------------------ |
|
// |
// amplifier controller |
// |
|
assign amp_cs_n = 1; |
assign amp_shdn = reset; |
|
//------------------------------------------------------------ |
|
// |
// ADC controller |
// |
|
assign ad_conv = 0; |
|
//------------------------------------------------------------ |
|
// |
// SPI data output |
// |
|
assign spi_mosi = dac_sr[47]; |
|
endmodule |
/trunk/fpga/boards/s3e-500/src/busctrl/busctrl.v
0,0 → 1,226
// |
// busctrl.v -- bus controller |
// |
|
|
module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr, |
cpu_data_out, cpu_data_in, cpu_wt, |
ram_en, ram_wr, ram_size, ram_addr, |
ram_data_in, ram_data_out, ram_wt, |
rom_en, rom_wr, rom_size, rom_addr, |
rom_data_out, rom_wt, |
tmr0_en, tmr0_wr, tmr0_addr, |
tmr0_data_in, tmr0_data_out, tmr0_wt, |
tmr1_en, tmr1_wr, tmr1_addr, |
tmr1_data_in, tmr1_data_out, tmr1_wt, |
dsp_en, dsp_wr, dsp_addr, |
dsp_data_in, dsp_data_out, dsp_wt, |
kbd_en, kbd_wr, kbd_addr, |
kbd_data_in, kbd_data_out, kbd_wt, |
ser0_en, ser0_wr, ser0_addr, |
ser0_data_in, ser0_data_out, ser0_wt, |
ser1_en, ser1_wr, ser1_addr, |
ser1_data_in, ser1_data_out, ser1_wt, |
fms_en, fms_wr, fms_addr, |
fms_data_in, fms_data_out, fms_wt, |
bio_en, bio_wr, bio_addr, |
bio_data_in, bio_data_out, bio_wt); |
// cpu |
input cpu_en; |
input cpu_wr; |
input [1:0] cpu_size; |
input [31:0] cpu_addr; |
input [31:0] cpu_data_out; |
output [31:0] cpu_data_in; |
output cpu_wt; |
// ram |
output ram_en; |
output ram_wr; |
output [1:0] ram_size; |
output [25:0] ram_addr; |
output [31:0] ram_data_in; |
input [31:0] ram_data_out; |
input ram_wt; |
// rom |
output rom_en; |
output rom_wr; |
output [1:0] rom_size; |
output [23:0] rom_addr; |
input [31:0] rom_data_out; |
input rom_wt; |
// tmr0 |
output tmr0_en; |
output tmr0_wr; |
output [3:2] tmr0_addr; |
output [31:0] tmr0_data_in; |
input [31:0] tmr0_data_out; |
input tmr0_wt; |
// tmr1 |
output tmr1_en; |
output tmr1_wr; |
output [3:2] tmr1_addr; |
output [31:0] tmr1_data_in; |
input [31:0] tmr1_data_out; |
input tmr1_wt; |
// dsp |
output dsp_en; |
output dsp_wr; |
output [13:2] dsp_addr; |
output [15:0] dsp_data_in; |
input [15:0] dsp_data_out; |
input dsp_wt; |
// kbd |
output kbd_en; |
output kbd_wr; |
output kbd_addr; |
output [7:0] kbd_data_in; |
input [7:0] kbd_data_out; |
input kbd_wt; |
// ser0 |
output ser0_en; |
output ser0_wr; |
output [3:2] ser0_addr; |
output [7:0] ser0_data_in; |
input [7:0] ser0_data_out; |
input ser0_wt; |
// ser1 |
output ser1_en; |
output ser1_wr; |
output [3:2] ser1_addr; |
output [7:0] ser1_data_in; |
input [7:0] ser1_data_out; |
input ser1_wt; |
// fms |
output fms_en; |
output fms_wr; |
output [11:2] fms_addr; |
output [31:0] fms_data_in; |
input [31:0] fms_data_out; |
input fms_wt; |
// bio |
output bio_en; |
output bio_wr; |
output bio_addr; |
output [31:0] bio_data_in; |
input [31:0] bio_data_out; |
input bio_wt; |
|
wire i_o_en; |
|
// |
// address decoder |
// |
// RAM: architectural limit = 512 MB |
// board limit = 64 MB |
assign ram_en = |
(cpu_en == 1 && cpu_addr[31:29] == 3'b000 |
&& cpu_addr[28:26] == 3'b000) ? 1 : 0; |
// ROM: architectural limit = 256 MB |
// board limit = 16 MB |
assign rom_en = |
(cpu_en == 1 && cpu_addr[31:28] == 4'b0010 |
&& cpu_addr[27:24] == 4'b0000) ? 1 : 0; |
// I/O: architectural limit = 256 MB |
assign i_o_en = |
(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0; |
assign tmr0_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
assign tmr1_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h00 |
&& cpu_addr[19:12] == 8'h01) ? 1 : 0; |
assign dsp_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0; |
assign kbd_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h02) ? 1 : 0; |
assign ser0_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h03 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
assign ser1_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h03 |
&& cpu_addr[19:12] == 8'h01) ? 1 : 0; |
assign fms_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h05 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
assign bio_en = |
(i_o_en == 1 && cpu_addr[27:20] == 8'h10 |
&& cpu_addr[19:12] == 8'h00) ? 1 : 0; |
|
// to cpu |
assign cpu_wt = |
(ram_en == 1) ? ram_wt : |
(rom_en == 1) ? rom_wt : |
(tmr0_en == 1) ? tmr0_wt : |
(tmr1_en == 1) ? tmr1_wt : |
(dsp_en == 1) ? dsp_wt : |
(kbd_en == 1) ? kbd_wt : |
(ser0_en == 1) ? ser0_wt : |
(ser1_en == 1) ? ser1_wt : |
(fms_en == 1) ? fms_wt : |
(bio_en == 1) ? bio_wt : |
1; |
assign cpu_data_in[31:0] = |
(ram_en == 1) ? ram_data_out[31:0] : |
(rom_en == 1) ? rom_data_out[31:0] : |
(tmr0_en == 1) ? tmr0_data_out[31:0] : |
(tmr1_en == 1) ? tmr1_data_out[31:0] : |
(dsp_en == 1) ? { 16'h0000, dsp_data_out[15:0] } : |
(kbd_en == 1) ? { 24'h000000, kbd_data_out[7:0] } : |
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } : |
(ser1_en == 1) ? { 24'h000000, ser1_data_out[7:0] } : |
(fms_en == 1) ? fms_data_out[31:0] : |
(bio_en == 1) ? bio_data_out[31:0] : |
32'h00000000; |
|
// to ram |
assign ram_wr = cpu_wr; |
assign ram_size[1:0] = cpu_size[1:0]; |
assign ram_addr[25:0] = cpu_addr[25:0]; |
assign ram_data_in[31:0] = cpu_data_out[31:0]; |
|
// to rom |
assign rom_wr = cpu_wr; |
assign rom_size[1:0] = cpu_size[1:0]; |
assign rom_addr[23:0] = cpu_addr[23:0]; |
|
// to tmr0 |
assign tmr0_wr = cpu_wr; |
assign tmr0_addr[3:2] = cpu_addr[3:2]; |
assign tmr0_data_in[31:0] = cpu_data_out[31:0]; |
|
// to tmr1 |
assign tmr1_wr = cpu_wr; |
assign tmr1_addr[3:2] = cpu_addr[3:2]; |
assign tmr1_data_in[31:0] = cpu_data_out[31:0]; |
|
// to dsp |
assign dsp_wr = cpu_wr; |
assign dsp_addr[13:2] = cpu_addr[13:2]; |
assign dsp_data_in[15:0] = cpu_data_out[15:0]; |
|
// to kbd |
assign kbd_wr = cpu_wr; |
assign kbd_addr = cpu_addr[2]; |
assign kbd_data_in[7:0] = cpu_data_out[7:0]; |
|
// to ser0 |
assign ser0_wr = cpu_wr; |
assign ser0_addr[3:2] = cpu_addr[3:2]; |
assign ser0_data_in[7:0] = cpu_data_out[7:0]; |
|
// to ser1 |
assign ser1_wr = cpu_wr; |
assign ser1_addr[3:2] = cpu_addr[3:2]; |
assign ser1_data_in[7:0] = cpu_data_out[7:0]; |
|
// to fms |
assign fms_wr = cpu_wr; |
assign fms_addr[11:2] = cpu_addr[11:2]; |
assign fms_data_in[31:0] = cpu_data_out[31:0]; |
|
// to bio |
assign bio_wr = cpu_wr; |
assign bio_addr = cpu_addr[2]; |
assign bio_data_in[31:0] = cpu_data_out[31:0]; |
|
endmodule |