URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
Compare Revisions
- This comparison shows the changes necessary to convert path
/eco32
- from Rev 290 to Rev 291
- ↔ Reverse comparison
Rev 290 → Rev 291
/trunk/fpga/mc/src/ram/ddr/ram.v
46,6 → 46,26
inout sdram_ldqs; |
inout [15:0] sdram_dq; |
|
//---------------------------------------------------- |
|
// This is a hack. The synthesizer detected setup timing |
// violations on wDAT_I that resulted from crossing the |
// 50 MHz to 100 MHz clock domain border. The circuit would |
// have functioned perfectly ok, because the signals are |
// used only on the following 100 MHz clock edge, a fact |
// that the synthesizer was unable to deduce. Instead of |
// tolerating formal errors during synthesis, I tried to |
// insert a register that is clocked with the trailing |
// edge of the 50 MHz clock. Surprisingly, this worked. |
|
reg [31:0] data_in_buf; |
|
always @(negedge clk) begin |
data_in_buf[31:0] <= data_in[31:0]; |
end |
|
//---------------------------------------------------- |
|
ddr_sdram ddr_sdram_1( |
.sd_CK_P(sdram_ck_p), |
.sd_CK_N(sdram_ck_n), |
70,7 → 90,7
.wSTB_I(stb), |
.wWE_I(we), |
.wWRB_I(4'b1111), |
.wDAT_I(data_in[31:0]), |
.wDAT_I(data_in_buf[31:0]), |
.wDAT_O(data_out[31:0]), |
.wACK_O(ack) |
); |
/trunk/fpga/mc/boards/xsa-xst-3/build/eco32.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/fpga/mc/boards/s3e-500/build/eco32.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/fpga/mc/boards/s3e-500/doc/README
9,7 → 9,7
c) git clone git://git.zerfleddert.de/usb-driver |
d) cd usb-driver |
e) make |
f) ./setup_pcusb /opt/Xilinx/14.5/ISE_DS/ISE/ |
f) ./setup_pcusb /opt/Xilinx/14.7/ISE_DS/ISE/ |
|
2. The configuration bitstring for the FPGA is stored in the |
"Platform Flash PROM" (XCF04S). The board must therefore be |
17,7 → 17,7
|
3. Here is the command which burns the configuration bitstring |
into the Platform Flash PROM: |
/opt/Xilinx/14.5/ISE_DS/ISE/bin/lin/impact -batch ./program.cmd |
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/impact -batch ./program.cmd |
|
4. The machine monitor is stored in the "StrataFlash Parallel NOR |
Flash PROM" (28F128J3), starting at address 0x000000. The ECO32 |
44,7 → 44,7
- add linefeed on (the programmer sends CR, but not LF) |
- local echo off (the programmer does echo itself) |
d) Here is the command that loads the FPGA with the programmer: |
/opt/Xilinx/14.5/ISE_DS/ISE/bin/lin/impact -batch ./flash-500.cmd |
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/impact -batch ./flash-500.cmd |
If the download succeeds, you should see the message "PicoBlaze NOR |
FLASH Programmer v1.00" on the computer which is connected via the |
serial line to the starter board, as well as a menue of commands |