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    /encore/trunk/fpmult/src
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/fpmult_generic.vhdl File deleted \ No newline at end of file
/fpmult_comp.vhdl
1,14 → 1,15
library ieee;
use ieee.std_logic_1164.all;
use work.fp_generic.all;
 
package fpmult_comp is
type fpmult_in_type is record
a:std_logic_vector(22 downto 0);
b:std_logic_vector(22 downto 0);
a:fp_type;
b:fp_type;
end record;
 
type fpmult_out_type is record
p:std_logic_vector(22 downto 0);
p:fp_type;
end record;
 
component fpmult is
/fpmult_stageN_comp.vhdl
1,29 → 1,28
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_generic.all;
 
package fpmult_stageN_comp is
type fpmult_stageN_in_type is record
a:fp_type;
b:fp_type;
 
p_sign:fp_sign_type;
p_exp:fp_exp_type;
p_mantissa:fp_long_mantissa_type;
end record;
 
alias fpmult_stageN_out_type is fpmult_stageN_in_type;
 
component fpmult_stageN is
generic(
N:integer
);
port(
clk:in std_logic;
d:in fpmult_stageN_in_type;
q:out fpmult_stageN_out_type
);
end component;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
 
package fpmult_stageN_comp is
type fpmult_stageN_in_type is record
a:fp_type;
b:fp_type;
 
p_sign:fp_sign_type;
p_exp:fp_exp_type;
p_mantissa:fp_long_mantissa_type;
end record;
 
alias fpmult_stageN_out_type is fpmult_stageN_in_type;
 
component fpmult_stageN is
generic(
N:integer
);
port(
clk:in std_logic;
d:in fpmult_stageN_in_type;
q:out fpmult_stageN_out_type
);
end component;
end package;
/fpmult_stage0_comp.vhdl
1,23 → 1,22
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_generic.all;
use work.fpmult_stageN_comp.all;
 
package fpmult_stage0_comp is
type fpmult_stage0_in_type is record
a:fp_type;
b:fp_type;
end record;
 
alias fpmult_stage0_out_type is fpmult_stageN_in_type;
 
component fpmult_stage0 is
port(
clk:in std_logic;
d:in fpmult_stage0_in_type;
q:out fpmult_stage0_out_type
);
end component;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_stageN_comp.all;
 
package fpmult_stage0_comp is
type fpmult_stage0_in_type is record
a:fp_type;
b:fp_type;
end record;
 
alias fpmult_stage0_out_type is fpmult_stageN_in_type;
 
component fpmult_stage0 is
port(
clk:in std_logic;
d:in fpmult_stage0_in_type;
q:out fpmult_stage0_out_type
);
end component;
end package;
/fp_generic.vhdl
1,89 → 1,99
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package fp_generic is
 
subtype fp_type is std_logic_vector(31 downto 0);
subtype fp_sign_type is std_logic;
subtype fp_exp_type is unsigned(7 downto 0);
subtype fp_mantissa_type is unsigned(23 downto 0);
subtype fp_long_mantissa_type is unsigned(47 downto 0);
 
subtype fp_error_type is std_logic_vector(5 downto 0);
constant FP_ERR_INVALID:fp_error_type:="000001";
constant FP_ERR_DIVBYZERO:fp_error_type:="000100";
constant FP_ERR_OVERFLOW:fp_error_type:="001000";
constant FP_ERR_UNDERFLOW:fp_error_type:="010000";
constant FP_ERR_INEXACT:fp_error_type:="100000";
 
function fp_sign(fp:fp_type) return fp_sign_type;
function fp_exp(fp:fp_type) return fp_exp_type;
function fp_mantissa(fp:fp_type) return fp_mantissa_type;
 
function fp_is_normal(fp:fp_type) return boolean;
function fp_is_zero(fp:fp_type) return boolean;
function fp_is_subnormal(fp:fp_type) return boolean;
function fp_is_infinite(fp:fp_type) return boolean;
function fp_is_nan(fp:fp_type) return boolean;
function fp_is_signalling(fp:fp_type) return boolean;
function fp_is_quiet(fp:fp_type) return boolean;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
end package;
 
package body fp_generic is
 
function fp_sign(fp:fp_type) return fp_sign_type is
begin
return fp(31);
end function fp_sign;
 
function fp_exp(fp:fp_type) return fp_exp_type is
begin
return unsigned(fp(30 downto 23));
end function fp_exp;
 
function fp_mantissa(fp:fp_type) return fp_mantissa_type is
begin
return unsigned("1"&fp(22 downto 0)); -- Prepend implied '1' bit of IEEE-754 mantissa in order to return a 24 bit entity
end function fp_mantissa;
 
function fp_is_normal(fp:fp_type) return boolean is
variable e:fp_exp_type;
begin
e:=fp_exp(fp);
 
return (e/=(others=>'0')) and (e/=(others=>'1'));
end function fp_is_normal;
 
function fp_is_zero(fp:fp_type) return boolean is
begin
return (unsigned(fp_exp(fp))=0) and (unsigned(fp_mantissa(fp))=0);
end function fp_is_zero;
 
function fp_is_subnormal(fp:fp_type) return boolean is
begin
return (fp_exp(fp)=(others=>'0')) and (fp_mantissa(fp)/=(others=>'0'));
end function fp_is_subnormal;
 
function fp_is_infinite(fp:fp_type) return boolean is
begin
return (fp_exp(fp)=(others=>'1')) and (fp_mantissa(fp)=(others=>'0'));
end function fp_is_infinite;
 
function fp_is_nan(fp:fp_type) return boolean is
begin
return (fp_exp(fp)=(others=>'1')) and (fp_mantissa(fp)/=(others=>'0'));
end function fp_is_nan;
 
function fp_is_signalling(fp:fp_type) return boolean is
begin
return fp_is_nan(fp) and fp_mantissa(fp)(22)='0';
end function fp_is_signalling;
 
function fp_is_quiet(fp:fp_type) return boolean is
begin
return fp_is_nan(fp) and fp_mantissa(fp)(22)='1';
end function fp_is_quiet;
 
end package body fp_generic;
package fp_generic is
 
subtype fp_type is std_logic_vector(31 downto 0);
subtype fp_sign_type is std_logic;
subtype fp_exp_type is unsigned(7 downto 0);
subtype fp_mantissa_type is unsigned(23 downto 0);
subtype fp_long_mantissa_type is unsigned(47 downto 0);
 
subtype fp_error_type is std_logic_vector(5 downto 0);
constant FP_ERR_INVALID:fp_error_type:="000001";
constant FP_ERR_DIVBYZERO:fp_error_type:="000100";
constant FP_ERR_OVERFLOW:fp_error_type:="001000";
constant FP_ERR_UNDERFLOW:fp_error_type:="010000";
constant FP_ERR_INEXACT:fp_error_type:="100000";
 
function fp_sign(fp:fp_type) return fp_sign_type;
function fp_exp(fp:fp_type) return fp_exp_type;
function fp_mantissa(fp:fp_type) return fp_mantissa_type;
 
function fp_is_normal(fp:fp_type) return boolean;
function fp_is_zero(fp:fp_type) return boolean;
function fp_is_subnormal(fp:fp_type) return boolean;
function fp_is_infinite(fp:fp_type) return boolean;
function fp_is_nan(fp:fp_type) return boolean;
function fp_is_signalling(fp:fp_type) return boolean;
function fp_is_quiet(fp:fp_type) return boolean;
 
end package;
 
package body fp_generic is
 
function fp_sign(fp:fp_type) return fp_sign_type is
begin
return fp(31);
end function fp_sign;
 
function fp_exp(fp:fp_type) return fp_exp_type is
begin
return(resize((unsigned(fp) srl 23),8));
end function fp_exp;
 
function fp_mantissa(fp:fp_type) return fp_mantissa_type is
begin
return(fp_mantissa_type("1"&fp(22 downto 0))); -- Prepend implied '1' bit of IEEE-754 mantissa in order to return a 24 bit entity
end function fp_mantissa;
 
function fp_exp_is_min(exp:fp_exp_type) return boolean is
begin
return (exp=0);
end function fp_exp_is_min;
 
function fp_exp_is_max(exp:fp_exp_type) return boolean is
begin
return (exp=255);
end function fp_exp_is_max;
 
function fp_is_normal(fp:fp_type) return boolean is
variable exp:fp_exp_type;
begin
exp:=fp_exp(fp);
 
return not fp_exp_is_min(exp) and not fp_exp_is_max(exp);
end function fp_is_normal;
 
function fp_is_zero(fp:fp_type) return boolean is
begin
return (fp_exp(fp)=0) and (fp_mantissa(fp)=0);
end function fp_is_zero;
 
function fp_is_subnormal(fp:fp_type) return boolean is
begin
return (fp_exp(fp)=0) and (fp_mantissa(fp)/=0);
end function fp_is_subnormal;
 
function fp_is_infinite(fp:fp_type) return boolean is
begin
return (fp_exp_is_max(fp_exp(fp))) and (fp_mantissa(fp)=0);
end function fp_is_infinite;
 
function fp_is_nan(fp:fp_type) return boolean is
begin
return (fp_exp_is_max(fp_exp(fp))) and (fp_mantissa(fp)/=0);
end function fp_is_nan;
 
function fp_is_signalling(fp:fp_type) return boolean is
begin
return fp_is_nan(fp) and fp_mantissa(fp)(22)='0';
end function fp_is_signalling;
 
function fp_is_quiet(fp:fp_type) return boolean is
begin
return fp_is_nan(fp) and fp_mantissa(fp)(22)='1';
end function fp_is_quiet;
 
end package body fp_generic;
/test_fpmult.vhdl
0,0 → 1,30
library ieee;
use ieee.std_logic_1164.all;
use work.fp_generic.all;
use work.fpmult_comp.all;
 
entity test_fpmult is
end;
 
architecture testbench of test_fpmult is
signal clk:std_logic:='0';
signal d:fpmult_in_type;
signal q:fpmult_out_type;
begin
 
dut:fpmult port map(clk,d,q);
 
clock:process
begin
wait for 10 ns; clk <= not clk;
end process clock;
 
stimulus:process
begin
d.a<="00111111110110010100011101010101"; -- 0x3FD94755 -> 1.69748938
d.b<="00111111101101110110110011100001"; -- 0x3FB76CE1 -> 1.43301022
wait;
end process stimulus;
 
end testbench;
 
/fpmult.vhdl
1,94 → 1,43
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.fpmult_comp.all;
use work.fpmult_stage0_comp.all;
use work.fpmult_stageN_comp.all;
use work.fpmult_stage23_comp.all;
 
entity fpmult is
port(
clk:in std_logic;
 
a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
p:out std_logic_vector(31 downto 0);
 
p_s00:out std_logic_vector(23 downto 1);
p_s01:out std_logic_vector(25 downto 1);
p_s02:out std_logic_vector(26 downto 2);
p_s03:out std_logic_vector(27 downto 3);
p_s04:out std_logic_vector(28 downto 4);
p_s05:out std_logic_vector(29 downto 5);
p_s06:out std_logic_vector(30 downto 6);
p_s07:out std_logic_vector(31 downto 7);
p_s08:out std_logic_vector(32 downto 8);
p_s09:out std_logic_vector(33 downto 9);
p_s10:out std_logic_vector(34 downto 10);
p_s11:out std_logic_vector(35 downto 11);
p_s12:out std_logic_vector(36 downto 12);
p_s13:out std_logic_vector(37 downto 13);
p_s14:out std_logic_vector(38 downto 14);
p_s15:out std_logic_vector(39 downto 15);
p_s16:out std_logic_vector(40 downto 16);
p_s17:out std_logic_vector(41 downto 17);
p_s18:out std_logic_vector(42 downto 18);
p_s19:out std_logic_vector(43 downto 19);
p_s20:out std_logic_vector(44 downto 20);
p_s21:out std_logic_vector(45 downto 21);
p_s22:out std_logic_vector(46 downto 22)
);
end;
 
architecture structural of fpmult is
signal fpmult_stage0_in:fpmult_stage0_in_type;
signal fpmult_stage0_out:fpmult_stage0_out_type;
signal fpmult_stage23_in:fpmult_stage23_in_type;
signal fpmult_stage23_out:fpmult_stage23_out_type;
type fpmult_stageN_in_array_type is array(23 downto 1) of fpmult_stageN_in_type;
type fpmult_stageN_out_array_type is array(22 downto 1) of fpmult_stageN_out_type;
signal fpmult_stageN_in_array:fpmult_stageN_in_array_type;
signal fpmult_stageN_out_array:fpmult_stageN_out_array_type;
begin
fpmult_stage0_in.a<=a;
fpmult_stage0_in.b<=b;
 
stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
 
fpmult_stageN_in_array(1)<=fpmult_stage0_out;
pipeline:for N in 22 downto 1 generate
stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
end generate pipeline;
 
fpmult_stage23_in<=fpmult_stageN_out_array(22);
 
stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
 
p<=fpmult_stage23_out.p;
p_s00<=std_logic_vector(fpmult_stage0_out.p_mantissa(23 downto 1));
p_s01<=std_logic_vector(fpmult_stageN_out_array(1).p_mantissa(25 downto 1));
p_s02<=std_logic_vector(fpmult_stageN_out_array(2).p_mantissa(26 downto 2));
p_s03<=std_logic_vector(fpmult_stageN_out_array(3).p_mantissa(27 downto 3));
p_s04<=std_logic_vector(fpmult_stageN_out_array(4).p_mantissa(28 downto 4));
p_s05<=std_logic_vector(fpmult_stageN_out_array(5).p_mantissa(29 downto 5));
p_s06<=std_logic_vector(fpmult_stageN_out_array(6).p_mantissa(30 downto 6));
p_s07<=std_logic_vector(fpmult_stageN_out_array(7).p_mantissa(31 downto 7));
p_s08<=std_logic_vector(fpmult_stageN_out_array(8).p_mantissa(32 downto 8));
p_s09<=std_logic_vector(fpmult_stageN_out_array(9).p_mantissa(33 downto 9));
p_s10<=std_logic_vector(fpmult_stageN_out_array(10).p_mantissa(34 downto 10));
p_s11<=std_logic_vector(fpmult_stageN_out_array(11).p_mantissa(35 downto 11));
p_s12<=std_logic_vector(fpmult_stageN_out_array(12).p_mantissa(36 downto 12));
p_s13<=std_logic_vector(fpmult_stageN_out_array(13).p_mantissa(37 downto 13));
p_s14<=std_logic_vector(fpmult_stageN_out_array(14).p_mantissa(38 downto 14));
p_s15<=std_logic_vector(fpmult_stageN_out_array(15).p_mantissa(39 downto 15));
p_s16<=std_logic_vector(fpmult_stageN_out_array(16).p_mantissa(40 downto 16));
p_s17<=std_logic_vector(fpmult_stageN_out_array(17).p_mantissa(41 downto 17));
p_s18<=std_logic_vector(fpmult_stageN_out_array(18).p_mantissa(42 downto 18));
p_s19<=std_logic_vector(fpmult_stageN_out_array(19).p_mantissa(43 downto 19));
p_s20<=std_logic_vector(fpmult_stageN_out_array(20).p_mantissa(44 downto 20));
p_s21<=std_logic_vector(fpmult_stageN_out_array(21).p_mantissa(45 downto 21));
p_s22<=std_logic_vector(fpmult_stageN_out_array(22).p_mantissa(46 downto 22));
end;
library ieee;
use ieee.std_logic_1164.all;
use work.fpmult_comp.all;
use work.fpmult_stage0_comp.all;
use work.fpmult_stageN_comp.all;
use work.fpmult_stage23_comp.all;
 
entity fpmult is
port(
clk:in std_logic;
d:in fpmult_in_type;
q:out fpmult_out_type
);
end;
 
architecture structural of fpmult is
signal fpmult_stage0_in:fpmult_stage0_in_type;
signal fpmult_stage0_out:fpmult_stage0_out_type;
signal fpmult_stage23_in:fpmult_stage23_in_type;
signal fpmult_stage23_out:fpmult_stage23_out_type;
type fpmult_stageN_in_array_type is array(23 downto 1) of fpmult_stageN_in_type;
type fpmult_stageN_out_array_type is array(22 downto 1) of fpmult_stageN_out_type;
signal fpmult_stageN_in_array:fpmult_stageN_in_array_type;
signal fpmult_stageN_out_array:fpmult_stageN_out_array_type;
begin
fpmult_stage0_in.a<=d.a;
fpmult_stage0_in.b<=d.b;
 
stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
 
fpmult_stageN_in_array(1)<=fpmult_stage0_out;
pipeline:for N in 22 downto 1 generate
stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
end generate pipeline;
 
fpmult_stage23_in<=fpmult_stageN_out_array(22);
 
stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
 
q.p<=fpmult_stage23_out.p;
end;
/fpmult_stage0.vhdl
25,6 → 25,15
begin
comb:process(d,r)
variable v:reg_type;
variable a_is_normal,b_is_normal:boolean;
variable a_is_subnormal,b_is_subnormal:boolean;
variable a_is_zero,b_is_zero:boolean;
variable a_is_infinite,b_is_infinite:boolean;
variable a_is_nan,b_is_nan:boolean;
variable is_normal:boolean;
variable is_zero:boolean;
variable is_infinite:boolean;
variable is_nan:boolean;
begin
-- sample register outputs
v:=r;
33,6 → 42,32
v.a:=d.a;
v.b:=d.b;
 
a_is_normal:=fp_is_normal(v.a);
b_is_normal:=fp_is_normal(v.b);
a_is_subnormal:=fp_is_subnormal(v.a);
b_is_subnormal:=fp_is_subnormal(v.b);
a_is_zero:=fp_is_zero(v.a);
b_is_zero:=fp_is_zero(v.b);
a_is_infinite:=fp_is_infinite(v.a);
b_is_infinite:=fp_is_infinite(v.b);
a_is_nan:=fp_is_nan(v.a);
b_is_nan:=fp_is_nan(v.b);
 
if a_is_normal or b_is_normal then
if a_is_normal and b_is_normal then
is_normal:=true;
end if;
if a_is_zero or b_is_zero then
is_zero:=true;
end if;
if a_is_infinite or b_is_infinite then
is_infinite:=true;
end if;
if a_is_nan or b_is_nan then
is_nan:=true;
end if;
end if;
v.p_sign:=fp_sign(d.a) xor fp_sign(d.b);
v.p_exp:=fp_exp(d.a) + fp_exp(d.b) - 127;
if fp_mantissa(d.b)(0)='1' then
/fpmult_stage23_comp.vhdl
1,22 → 1,21
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_generic.all;
use work.fpmult_stageN_comp.all;
 
package fpmult_stage23_comp is
alias fpmult_stage23_in_type is fpmult_stageN_out_type;
 
type fpmult_stage23_out_type is record
p:fp_type;
end record;
 
component fpmult_stage23 is
port(
clk:in std_logic;
d:in fpmult_stage23_in_type;
q:out fpmult_stage23_out_type
);
end component;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_stageN_comp.all;
 
package fpmult_stage23_comp is
alias fpmult_stage23_in_type is fpmult_stageN_out_type;
 
type fpmult_stage23_out_type is record
p:fp_type;
end record;
 
component fpmult_stage23 is
port(
clk:in std_logic;
d:in fpmult_stage23_in_type;
q:out fpmult_stage23_out_type
);
end component;
end package;

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