URL
https://opencores.org/ocsvn/esoc/esoc/trunk
Subversion Repositories esoc
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/esoc/trunk
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Rev 25 → Rev 26
/Sources/altera/esoc.qsf
0,0 → 1,68
# Copyright (C) 1991-2008 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
|
|
# The default values for assignments are stored in the file |
# esoc_assignment_defaults.qdf |
# If this file doesn't exist, and for assignments not listed, see file |
# assignment_defaults.qdf |
|
# Altera recommends that you do not modify this file. This |
# file is updated automatically by the Quartus II software |
# and any changes you make may be lost or overwritten. |
|
|
set_global_assignment -name FAMILY "Stratix II" |
set_global_assignment -name DEVICE AUTO |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:50:18 NOVEMBER 04, 2013" |
set_global_assignment -name LAST_QUARTUS_VERSION 8.1 |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_ram_8kx80/esoc_ram_8kx80.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_fifo_nkx80/esoc_fifo_128x80.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_pll1_c3/esoc_pll1_c3.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_pll2_c3/esoc_pll2_c3.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_rom_nkx32/esoc_rom_2kx32.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_port_mac/esoc_port_mac.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_fifo_nkx16/esoc_fifo_256x16.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_ram_4kx1/esoc_ram_4kx1.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_fifo_nkx32/esoc_fifo_256x32.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_fifo_nkx112/esoc_fifo_256x112.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_fifo_nkx32x64/esoc_fifo_2kx32x64.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/altera/esoc_fifo_nkx32x64/esoc_fifo_2kx64x32.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/package_hash10_24b.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/package_esoc_configuration.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_storage.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_processor_control.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_processor_outbound.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_processor_inbound.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_processor_search.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_processor.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_mal_clock.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_mal_outbound.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_mal_inbound.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_mal_control.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_mal.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port_interface.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_port.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_clk_en_gen.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_search_engine_sa_store.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_search_engine_control.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_search_engine_sa.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_search_engine_da.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_search_engine.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_bus_arbiter.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_reset.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc_control.vhd" -library work |
set_global_assignment -name VHDL_FILE "C:/data/temp/1. eSoc/2. Sources/esoc.ews/design.hdl/esoc.vhd" -library work |
set_global_assignment -name TOP_LEVEL_ENTITY esoc |
/Sources/altera/esoc_fifo_16kx32.qip
--- Sources/altera/esoc.qpf (nonexistent)
+++ Sources/altera/esoc.qpf (revision 26)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "8.1"
+DATE = "12:50:18 November 04, 2013"
+
+
+# Revisions
+
+PROJECT_REVISION = "esoc"