OpenCores
URL https://opencores.org/ocsvn/esoc/esoc/trunk

Subversion Repositories esoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /esoc/trunk
    from Rev 52 to Rev 53
    ↔ Reverse comparison
  •

Rev 52 → Rev 53

/Sources/logixa/esoc_port_mal_clock.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_mal_clock
-- Last modified : Mon Apr 14 12:49:01 2014.
/Sources/logixa/esoc_search_engine_sa_store.vhd
1,46 → 1,22
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_search_engine_sa_store
-- Last modified : Mon Apr 14 12:50:14 2014.
-- Last modified : Tue Aug 19 08:05:17 2014.
--------------------------------------------------------------------------------
 
 
66,7 → 42,7
 
--------------------------------------------------------------------------------
-- Object : Architecture work.esoc_search_engine_sa_store.esoc_search_engine_sa_store
-- Last modified : Mon Apr 14 12:50:14 2014.
-- Last modified : Tue Aug 19 08:05:17 2014.
--------------------------------------------------------------------------------
 
 
96,7 → 72,7
-- define unused bits to avoid inferred latch warning during analysis & synthesis
search_sa_store_d(esoc_search_entry_valid) <= '0';
search_sa_store_d(esoc_search_entry_update) <= '0';
search_sa_store_d(esoc_search_entry_aging) <= '0';
search_sa_store_d(esoc_search_entry_unused2 downto esoc_search_entry_unused1) <= (others => '0');
case store_sa_state is
/Sources/logixa/esoc_search_engine_control.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_search_engine_control
-- Last modified : Mon Apr 14 12:49:59 2014.
/Sources/logixa/esoc_search_engine.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_search_engine
-- Last modified : Mon Apr 14 12:49:54 2014.
/Sources/logixa/esoc_port_mal_inbound.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_mal_inbound
-- Last modified : Mon Apr 14 12:49:11 2014.
/Sources/logixa/esoc_port_mal_outbound.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_mal_outbound
-- Last modified : Mon Apr 14 12:49:17 2014.
/Sources/logixa/esoc_search_engine_da.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_search_engine_da
-- Last modified : Mon Apr 14 12:50:04 2014.
/Sources/logixa/esoc_bus_arbiter.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_bus_arbiter
-- Last modified : Mon Apr 14 12:48:27 2014.
/Sources/logixa/esoc_port_processor_inbound.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_processor_inbound
-- Last modified : Mon Apr 14 12:49:30 2014.
/Sources/logixa/esoc_port_processor_outbound.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_processor_outbound
-- Last modified : Mon Apr 14 12:49:34 2014.
/Sources/logixa/esoc_port_interface.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_interface
-- Last modified : Mon Apr 14 12:51:18 2014.
/Sources/logixa/esoc_port_processor_search.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_processor_search
-- Last modified : Mon Apr 14 12:49:39 2014.
/Sources/logixa/esoc_port_storage.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_storage
-- Last modified : Mon Apr 14 12:49:43 2014.
/Sources/logixa/esoc_port_mal_control.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_mal_control
-- Last modified : Mon Apr 14 12:49:06 2014.
/Sources/logixa/esoc_port_mal.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_mal
-- Last modified : Mon Apr 14 12:48:57 2014.
/Sources/logixa/esoc_search_engine_sa.vhd
1,46 → 1,22
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_search_engine_sa
-- Last modified : Mon Apr 14 12:50:09 2014.
-- Last modified : Tue Aug 19 08:05:17 2014.
--------------------------------------------------------------------------------
 
 
73,7 → 49,7
 
--------------------------------------------------------------------------------
-- Object : Architecture work.esoc_search_engine_sa.esoc_search_engine_sa
-- Last modified : Mon Apr 14 12:50:09 2014.
-- Last modified : Tue Aug 19 08:05:17 2014.
--------------------------------------------------------------------------------
 
 
171,7 → 147,7
search_table_address_i <= std_logic_vector(to_unsigned(to_integer(unsigned(search_table_address_i))-1,search_table_address_i'length));
search_key_i(esoc_search_entry_valid) <= '1';
search_key_i(esoc_search_entry_update) <= '1';
search_key_i(esoc_search_entry_aging) <= '1';
search_table_wren <= '1';
search_state <= idle;
208,7 → 184,7
end if;
search_key_i(esoc_search_entry_valid) <= '1';
search_key_i(esoc_search_entry_update) <= '1';
search_key_i(esoc_search_entry_aging) <= '1';
search_state <= idle;
end if;
end if;
257,8 → 233,8
-- update the entry or even invalidate the entry
if search_table_q(esoc_search_entry_valid) = '1' then
search_key_i <= search_table_q;
search_key_i(esoc_search_entry_valid) <= search_table_q(esoc_search_entry_update);
search_key_i(esoc_search_entry_update) <= '0';
search_key_i(esoc_search_entry_valid) <= search_table_q(esoc_search_entry_aging);
search_key_i(esoc_search_entry_aging) <= '0';
search_table_wren <= '1';
end if;
/Sources/logixa/esoc_control.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_control
-- Last modified : Thu Apr 17 12:55:38 2014.
/Sources/logixa/esoc.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc
-- Last modified : Mon Apr 14 12:48:20 2014.
/Sources/logixa/esoc_reset.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_reset
-- Last modified : Mon Apr 14 12:49:49 2014.
/Sources/logixa/package_esoc_configuration.vhd
134,7 → 134,7
-- Entity ESoC Search Engine
-- Record in MAC/VLAN Learning table
constant esoc_search_entry_valid : integer := 79; -- Position of entry valid flag in table entry, length is 1 bit
constant esoc_search_entry_update : integer := 78; -- Position of update flag for aging protocol in table entry, length is 1 bit
constant esoc_search_entry_aging : integer := 78; -- Position of update flag for aging protocol in table entry, length is 1 bit
constant esoc_search_entry_unused2 : integer := 77; --
constant esoc_search_entry_unused1 : integer := 76; --
constant esoc_search_entry_destination : integer := 60; -- Position of destination ports in table entry, length is 16 bit
/Sources/logixa/esoc_port_processor_control.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_processor_control
-- Last modified : Mon Apr 14 12:49:26 2014.
/Sources/logixa/esoc_port_processor.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port_processor
-- Last modified : Mon Apr 14 12:49:21 2014.
/Sources/logixa/esoc_port.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_port
-- Last modified : Mon Apr 14 12:48:46 2014.
/Sources/logixa/esoc_clk_en_gen.vhd
1,43 → 1,19
--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
--
-- Ease library : work
-- HDL library : work
-- Host name : S212065
-- User name : df768
-- Time stamp : Tue Aug 19 08:05:18 2014
--
-- Designed by : L.Maarsen
-- Company : LogiXA
-- Project info : eSoC
--
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
 
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_clk_en_gen
-- Last modified : Mon Apr 14 12:48:32 2014.

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