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/testbench/tb-arp_responder.vhdl
0,0 → 1,298
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use work.arp_package.all;
 
entity tb_arp_responder is
--empty
end tb_arp_responder;
 
 
architecture beh of tb_arp_responder is
 
COMPONENT arp_responder
PORT(
ARESET : IN std_logic;
MY_MAC : IN std_logic_vector(47 downto 0);
MY_IPV4 : IN std_logic_vector(31 downto 0);
CLK_RX : IN std_logic;
DATA_VALID_RX : IN std_logic;
DATA_RX : IN std_logic_vector(7 downto 0);
CLK_TX : IN std_logic;
DATA_ACK_TX : IN std_logic;
DATA_VALID_TX : OUT std_logic;
DATA_TX : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
constant severity_c : severity_level := failure;
 
--Inputs
signal ARESET : std_logic := '0';
signal MY_MAC : std_logic_vector(47 downto 0) := x"00_01_42_00_5F_FF";
signal MY_IPV4 : std_logic_vector(31 downto 0) := x"C0_A8_01_02";
signal CLK_RX : std_logic := '0';
signal DATA_VALID_RX : std_logic := '0';
signal DATA_RX : std_logic_vector(7 downto 0) := (others => '0');
signal CLK_TX : std_logic := '0';
signal TB_CLK : std_logic := '0';
signal DATA_ACK_TX : std_logic := '0';
--Outputs
signal DATA_VALID_TX : std_logic;
signal DATA_TX : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 8 ns;
constant TB_CLK_SKEW : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: arp_responder PORT MAP (
ARESET => ARESET,
MY_MAC => MY_MAC,
MY_IPV4 => MY_IPV4,
CLK_RX => CLK_RX,
DATA_VALID_RX => DATA_VALID_RX,
DATA_RX => DATA_RX,
CLK_TX => CLK_TX,
DATA_ACK_TX => DATA_ACK_TX,
DATA_VALID_TX => DATA_VALID_TX,
DATA_TX => DATA_TX
);
 
----Testbench Clock Generator:
tb_clk_gen : process
begin
TB_CLK <= '0';
wait for CLK_period/2;
TB_CLK <= '1';
wait for CLK_period/2;
end process;
 
CLK_RX <= transport TB_CLK after TB_CLK_SKEW;
CLK_TX <= not(CLK_RX);
 
-- Stimulus process
stim_proc: process
 
--
-- wait for the rising edge of tb_ck
--
procedure wait_tb_clk(num_cyc : integer := 1) is
begin
for i in 1 to num_cyc loop
wait until TB_CLK'event and TB_CLK = '1';
end loop;
end wait_tb_clk;
--
-- wait for the rising edge of rx clk
--
procedure wait_rx_clk(num_cyc : integer := 1) is
begin
for i in 1 to num_cyc loop
wait until CLK_RX'event and CLK_RX = '1';
end loop;
end wait_rx_clk;
 
--
-- wait for the rising edge of tx clk
--
procedure wait_tx_clk(num_cyc : integer := 1) is
begin
for i in 1 to num_cyc loop
wait until CLK_TX'event and CLK_TX = '1';
end loop;
end wait_tx_clk;
 
--
-- Generate a valid ARP request
--
procedure gen_valid_arp_req is
begin
-- Set the Data Valid flag
DATA_VALID_RX <= '1';
 
-- Generate BDCST DA
for i in 0 to 5 loop
DATA_RX <= MAC_BDCST_ADDR(i);
wait_tb_clk;
end loop;
-- Generate SA
for i in 0 to 5 loop
DATA_RX <= CMP_A_MAC_ADDR(i);
wait_tb_clk;
end loop;
-- Generate ARP E_TYPE
for i in 0 to 1 loop
DATA_RX <= E_TYPE_ARP(i);
wait_tb_clk;
end loop;
 
-- Generate Ethernet H_TYPE
for i in 0 to 1 loop
DATA_RX <= H_TYPE_ETH(i);
wait_tb_clk;
end loop;
 
-- Generate IPV4 P_TYPE
for i in 0 to 1 loop
DATA_RX <= P_TYPE_IPV4(i);
wait_tb_clk;
end loop;
 
-- Generate Ethernet H_LEN
DATA_RX <= H_TYPE_ETH_LEN;
wait_tb_clk;
 
-- Generate IPV4 P_LEN
DATA_RX <= P_TYPE_IPV4_LEN;
wait_tb_clk;
 
-- Generate OPER for ARP Request
for i in 0 to 1 loop
DATA_RX <= ARP_OPER_REQ(i);
wait_tb_clk;
end loop;
 
-- Generate SHA
for i in 0 to 5 loop
DATA_RX <= CMP_A_MAC_ADDR(i);
wait_tb_clk;
end loop;
 
-- Generate SPA
for i in 0 to 3 loop
DATA_RX <= CMP_A_IPV4_ADDR(i);
wait_tb_clk;
end loop;
 
-- Generate THA
for i in 0 to 5 loop
DATA_RX <= MY_MAC((47-i*8) downto (40-i*8));
wait_tb_clk;
end loop;
 
-- Generate TPA
for i in 0 to 3 loop
DATA_RX <= MY_IPV4((31-i*8) downto (24-i*8));
wait_tb_clk;
end loop;
 
-- Remove the Data Valid flag
DATA_VALID_RX <= '0';
 
-- End of Generated ARP Packet
end gen_valid_arp_req;
 
--
-- Generate a valid ARP request
--
procedure gen_valid_eth_pkt(payload_size_bytes : integer := 46) is
begin
-- Set the Data Valid flag
DATA_VALID_RX <= '1';
 
-- Generate BDCST DA
for i in 0 to 5 loop
DATA_RX <= MY_MAC((47-i*8) downto (40-i*8));
wait_tb_clk;
end loop;
-- Generate SA
for i in 0 to 5 loop
DATA_RX <= CMP_A_MAC_ADDR(i);
wait_tb_clk;
end loop;
-- Generate E_TYPE for IPV4
for i in 0 to 1 loop
DATA_RX <= P_TYPE_IPV4(i);
wait_tb_clk;
end loop;
 
-- Generate Payload
for i in 1 to payload_size_bytes loop
-- Incrementing bytes for payload
DATA_RX <= conv_std_logic_vector((i-1),8);
wait_tb_clk;
end loop;
 
-- Generate fake FCS
for i in 1 to 4 loop
-- Incrementing bytes for FCS (x"F0",x"F1",etc)
DATA_RX <= conv_std_logic_vector(240+(i-1),8);
wait_tb_clk;
end loop;
 
-- Remove the Data Valid flag
DATA_VALID_RX <= '0';
 
-- End of Generated Ethernet Packet
end gen_valid_eth_pkt;
 
--
-- Receive an ARP response
--
procedure rec_arp_resp(wait_data_ack_tx : integer := 10) is
begin
-- Handle the response
wait until DATA_VALID_TX = '1';
wait_tx_clk(wait_data_ack_tx);
DATA_ACK_TX <= '1';
wait_tx_clk;
DATA_ACK_TX <= '0';
wait until DATA_VALID_TX = '0';
end rec_arp_resp;
 
--
-- Reset the Testbench
--
procedure reset_tb(time : integer := 10) is
begin
-- hold reset state
wait_tb_clk;
ARESET <= '1';
wait_tb_clk(time);
ARESET <= '0';
end reset_tb;
 
-------------------------------------------------------------
----- BEGIN PROCESS -----------------------------------------
-------------------------------------------------------------
begin
 
reset_tb;
gen_valid_arp_req;
rec_arp_resp;
wait_tb_clk(10);
gen_valid_eth_pkt(46);
wait_tb_clk(10);
gen_valid_arp_req;
rec_arp_resp;
wait_tb_clk(10);
gen_valid_arp_req;
rec_arp_resp;
wait_tb_clk(10);
gen_valid_eth_pkt(46);
wait_tb_clk(10);
gen_valid_eth_pkt(76);
wait_tb_clk(10);
 
-- stop the simulation once you're done
wait_tb_clk(50);
assert false
report "End of Simulation"
severity severity_c;
 
end process;
 
 
end beh;
 
 
/testbench/tb-ed.vhdl
0,0 → 1,73
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
 
entity tb_edge_detector is
--empty
end tb_edge_detector;
 
 
architecture beh of tb_edge_detector is
 
component edge_detector
port(
din : in std_logic;
clk : in std_logic;
rst_n : in std_logic;
dout : out std_logic
);
end component edge_detector;
 
 
--signal declaration
 
signal clk_net : std_logic;
signal rst_n_net : std_logic;
signal din_net : std_logic;
signal dout_net : std_logic;
 
begin
inst_1: edge_detector
port map(
din => din_net,
clk => clk_net,
rst_n => rst_n_net,
dout => dout_net
);
 
clk_p : process
begin
clk_net <= '0';
wait for 2 ns;
clk_net <= '1';
wait for 2 ns;
end process clk_p;
 
input_data : process
begin
din_net <= '0';
wait for 7 ns;
din_net <= '1';
wait for 10 ns;
din_net <= '0';
wait for 20 ns;
end process input_data;
 
test_bench : process
begin
 
rst_n_net <= '0';
wait for 1 ns;
rst_n_net <= '1';
wait for 100 ns;
 
assert false
report "End of Simulation"
severity failure;
 
end process test_bench;
 
end beh;
 
 
/testbench
testbench Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: rtl/arp_responder.vhdl =================================================================== --- rtl/arp_responder.vhdl (nonexistent) +++ rtl/arp_responder.vhdl (revision 2) @@ -0,0 +1,432 @@ +---------------------------------------------------------------------------------- +-- Company: Eastern Washington University, Cheney, WA +-- Engineer: Justin Wagner +-- +-- Create Date: 7/Oct/2011 +-- Design Name: +-- Module Name: arp_responder - rtl +-- Project Name: +-- Target Devices: n/a +-- Tool versions: +-- Description: Project for Job application to XR Trading +-- +-- Dependencies: arp_package.vhdl (Definitions of various constants) +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use work.arp_package.all; + +entity arp_responder is +Port ( ARESET : in STD_LOGIC; + MY_MAC : in std_logic_vector(47 downto 0); --my MAC address + MY_IPV4 : in std_logic_vector(31 downto 0); --my IPV4 address + CLK_RX : in STD_LOGIC; + DATA_VALID_RX : in STD_LOGIC; + DATA_RX : in std_logic_vector(7 downto 0); + CLK_TX : in STD_LOGIC; + DATA_ACK_TX : in STD_LOGIC; + DATA_VALID_TX : out STD_LOGIC; + DATA_TX : out std_logic_vector(7 downto 0) + ); +end arp_responder; +---------------------------------------------------------------------------------- +architecture rtl of arp_responder is + -- Edge Detector used to find positive edge of DATA_VALID_RX + component edge_detector + port( + din : in std_logic; + clk : in std_logic; + rst_n : in std_logic; + dout : out std_logic + ); + end component edge_detector; + + --the following declares the various states for the machine + type state_type is (IDLE, + CHECK_DA, CHECK_SA, CHECK_E_TYPE, CHECK_H_TYPE, CHECK_P_TYPE, + CHECK_H_LEN, CHECK_P_LEN, CHECK_OPER, CHECK_SHA, CHECK_SPA, + CHECK_THA, CHECK_TPA, + GEN_DA, GEN_SA, GEN_E_TYPE, GEN_H_TYPE, GEN_P_TYPE, + GEN_H_LEN, GEN_P_LEN, GEN_OPER, GEN_SHA, GEN_SPA, + GEN_THA, GEN_TPA); + + signal SA_mem, next_SA_mem : HA_mem_type; + signal SPA_mem, next_SPA_mem : PA_mem_type; + signal next_state, state : state_type; + signal next_counter, counter : std_logic_vector(3 downto 0); + signal posedge_DATA_VALID_RX : std_logic; + signal next_DATA_VALID_TX : std_logic; + signal next_DATA_TX : std_logic_vector(7 downto 0); + +begin + + -- A positive edge detector for the DATA_VALID_RX signal + ed_1: edge_detector + port map( + din => DATA_VALID_RX, + clk => CLK_RX, + rst_n => not(ARESET), + dout => posedge_DATA_VALID_RX + ); + +---------------------------------------------------------------------------------- +-- This process describes the flow from one state to another in the FSM----------- +-- It also describes what the outputs should be at each state--------------------- +---------------------------------------------------------------------------------- +combo:process(state, posedge_DATA_VALID_RX, counter, SA_mem, SPA_mem, DATA_ACK_TX, + MY_MAC, MY_IPV4) +begin +-- Hold Values by Default +-- These values will hold true in every state unless a state explicitly defines +-- a different value for any of these signals. + next_DATA_TX <= (others => '0'); + next_DATA_VALID_TX <= '0'; + next_counter <= counter; + next_SA_mem <= SA_mem; + next_SPA_mem <= SPA_mem; + +------------------------------------------------------------------ +--State Machine Start...Please see ASM chart for State Diagram---- + case state is + + when IDLE => + if (posedge_DATA_VALID_RX ='1') then + next_state <= CHECK_DA; + else + next_state <= IDLE; + end if; + next_SA_mem <= ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0')); + next_SPA_mem <= ((others => '0'),(others => '0'),(others => '0'),(others => '0')); + next_counter <= (others => '0'); + + when CHECK_DA => + -- Validate that the DA is a Broadcast, if not return to IDLE + next_counter <= counter + 1; + if (DATA_RX = MAC_BDCST_ADDR(conv_integer(counter))) then + if (counter < 5) then + next_state <= CHECK_DA; + else + next_state <= CHECK_SA; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when CHECK_SA => + -- Lets store the SA so we can respond to it later + next_counter <= counter + 1; + next_state <= CHECK_SA; + next_SA_mem(conv_integer(counter)) <= DATA_RX; + if (counter >= 5) then + next_state <= CHECK_E_TYPE; + next_counter <= (others => '0'); + end if; + + when CHECK_E_TYPE => + -- Verify that the E_TYPE is the ARP ETYPE + next_counter <= counter + 1; + if (DATA_RX = E_TYPE_ARP(conv_integer(counter))) then + next_state <= CHECK_E_TYPE; + if (counter >= 1) then + next_state <= CHECK_H_TYPE; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when CHECK_H_TYPE => + -- Verify that the H_TYPE is the Ethernet HTYPE + next_counter <= counter + 1; + if (DATA_RX = H_TYPE_ETH(conv_integer(counter))) then + next_state <= CHECK_H_TYPE; + if (counter >= 1) then + next_state <= CHECK_P_TYPE; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when CHECK_P_TYPE => + -- Verify that the P_TYPE is the IPV4 PTYPE + next_counter <= counter + 1; + if (DATA_RX = P_TYPE_IPV4(conv_integer(counter))) then + next_state <= CHECK_P_TYPE; + if (counter >= 1) then + next_state <= CHECK_H_LEN; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when CHECK_H_LEN => + -- Verify that the H_LEN is the Ethernet Length + next_counter <= (others => '0'); + if (DATA_RX = H_TYPE_ETH_LEN) then + next_state <= CHECK_P_LEN; + else + next_state <= IDLE; + end if; + + when CHECK_P_LEN => + -- Verify that the P_LEN is the IPV4 Length + next_counter <= (others => '0'); + if (DATA_RX = P_TYPE_IPV4_LEN) then + next_state <= CHECK_OPER; + else + next_state <= IDLE; + end if; + + when CHECK_OPER => + -- Verify that we received an ARP Request + next_counter <= counter + 1; + if (DATA_RX = ARP_OPER_REQ(conv_integer(counter))) then + next_state <= CHECK_OPER; + if (counter >= 1) then + next_state <= CHECK_SHA; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when CHECK_SHA => + -- Ignore the SHA field since we already retrieved this + -- from the Ethernet header + next_counter <= counter + 1; + next_state <= CHECK_SHA; + if (counter >= 5) then + next_counter <= (others => '0'); + next_state <= CHECK_SPA; + end if; + + when CHECK_SPA => + -- Lets store the SPA so we can respond to it later + next_counter <= counter + 1; + next_state <= CHECK_SPA; + next_SPA_mem(conv_integer(counter)) <= DATA_RX; + if (counter >= 3) then + next_state <= CHECK_THA; + next_counter <= (others => '0'); + end if; + + when CHECK_THA => + -- Make sure we are the destination Hardware Address + next_counter <= counter + 1; + if (DATA_RX = MY_MAC((47-(conv_integer(counter)*8)) downto (40-(conv_integer(counter)*8)))) then + next_state <= CHECK_THA; + if (counter >= 5) then + next_state <= CHECK_TPA; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when CHECK_TPA => + -- Make sure we are the destination Protocol Address + next_counter <= counter + 1; + if (DATA_RX = MY_IPV4((31-(conv_integer(counter)*8)) downto (24-(conv_integer(counter)*8)))) then + next_state <= CHECK_TPA; + if (counter >= 3) then + next_state <= GEN_DA; + next_counter <= (others => '0'); + end if; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + -- GENERATE AN ARP RESPONSE + + when GEN_DA => + -- Generate the DA for the response + next_DATA_VALID_TX <= '1'; + next_DATA_TX <= SA_mem(conv_integer(counter)); + if (DATA_ACK_TX = '0' AND counter = 0) then + next_counter <= (others => '0'); + else + next_counter <= counter + 1; + end if; + if (counter < 5) then + next_state <= GEN_DA; + else + next_state <= GEN_SA; + next_counter <= (others => '0'); + end if; + + when GEN_SA => + -- Generate the DA for the response + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= MY_MAC((47-(conv_integer(counter)*8)) downto (40-(conv_integer(counter)*8))); + if (counter < 5) then + next_state <= GEN_SA; + else + next_state <= GEN_E_TYPE; + next_counter <= (others => '0'); + end if; + + when GEN_E_TYPE => + -- Generate the E_TYPE for the response + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= E_TYPE_ARP(conv_integer(counter)); + if (counter < 1) then + next_state <= GEN_E_TYPE; + else + next_state <= GEN_H_TYPE; + next_counter <= (others => '0'); + end if; + + when GEN_H_TYPE => + -- Generate the H_TYPE for the response + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= H_TYPE_ETH(conv_integer(counter)); + if (counter < 1) then + next_state <= GEN_H_TYPE; + else + next_state <= GEN_P_TYPE; + next_counter <= (others => '0'); + end if; + + when GEN_P_TYPE => + -- Generate the P_TYPE for the response + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= P_TYPE_IPV4(conv_integer(counter)); + if (counter < 1) then + next_state <= GEN_P_TYPE; + else + next_state <= GEN_H_LEN; + next_counter <= (others => '0'); + end if; + + when GEN_H_LEN => + next_DATA_VALID_TX <= '1'; + next_DATA_TX <= H_TYPE_ETH_LEN; + next_state <= GEN_P_LEN; + + when GEN_P_LEN => + next_DATA_VALID_TX <= '1'; + next_DATA_TX <= P_TYPE_IPV4_LEN; + next_state <= GEN_OPER; + + when GEN_OPER => + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= ARP_OPER_RESP(conv_integer(counter)); + if (counter < 1) then + next_state <= GEN_OPER; + else + next_state <= GEN_SHA; + next_counter <= (others => '0'); + end if; + + when GEN_SHA => + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= MY_MAC((47-(conv_integer(counter)*8)) downto (40-(conv_integer(counter)*8))); + if (counter < 5) then + next_state <= GEN_SHA; + else + next_state <= GEN_SPA; + next_counter <= (others => '0'); + end if; + + when GEN_SPA => + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= MY_IPV4((31-(conv_integer(counter)*8)) downto (24-(conv_integer(counter)*8))); + if (counter < 3) then + next_state <= GEN_SPA; + else + next_state <= GEN_THA; + next_counter <= (others => '0'); + end if; + + when GEN_THA => + -- Generate the THA for the response + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= SA_mem(conv_integer(counter)); + if (counter < 5) then + next_state <= GEN_THA; + else + next_state <= GEN_TPA; + next_counter <= (others => '0'); + end if; + + when GEN_TPA => + -- Generate the TPA for the response + next_DATA_VALID_TX <= '1'; + next_counter <= counter + 1; + next_DATA_TX <= SPA_mem(conv_integer(counter)); + if (counter < 3) then + next_state <= GEN_TPA; + else + next_state <= IDLE; + next_counter <= (others => '0'); + end if; + + when others => + next_state <= IDLE; + + end case; + +end process combo; +---------------------------------------------------------------------------------- +--Sequential Logic Processes-------------------------------------------------------- +---------------------------------------------------------------------------------- +seq_RX:process(CLK_RX, ARESET) +begin + + if (ARESET='1') then --resetting the board + state <= IDLE; + counter <= (others => '0'); + SA_mem <= ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0')); + SPA_mem <= ((others => '0'),(others => '0'),(others => '0'),(others => '0')); + + -- move next state values into registers on clock edge + elsif (CLK_RX'event and CLK_RX ='1') then + state <= next_state; + counter <= next_counter; + SA_mem <= next_SA_mem; + SPA_mem <= next_SPA_mem; + + else + NULL; + end if; + +end process seq_RX; + +seq_TX:process(CLK_TX, ARESET) +begin + + if (ARESET='1') then --resetting the board + DATA_VALID_TX <= '0'; + DATA_TX <= (others => '0'); + -- move next state values into registers on clock edge + elsif (CLK_TX'event and CLK_TX ='1') then + DATA_VALID_TX <= next_DATA_VALID_TX; + DATA_TX <= next_DATA_TX; + else + NULL; + end if; + +end process seq_TX; + +end rtl; Index: rtl/arp_package.vhdl =================================================================== --- rtl/arp_package.vhdl (nonexistent) +++ rtl/arp_package.vhdl (revision 2) @@ -0,0 +1,27 @@ +-- +-- author: Justin Wagner +-- file: arp_package.vhdl +-- comment: package for ARP +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +package arp_package is + type HA_mem_type is array (0 to 5) of std_logic_vector(7 downto 0); + type PA_mem_type is array (0 to 3) of std_logic_vector(7 downto 0); + type TYPE_mem_type is array (0 to 1) of std_logic_vector(7 downto 0); + + constant MAC_BDCST_ADDR : HA_mem_type := ((x"FF"),(x"FF"),(x"FF"),(x"FF"),(x"FF"),(x"FF")); + constant CMP_A_MAC_ADDR : HA_mem_type := ((x"00"),(x"01"),(x"42"),(x"00"),(x"5F"),(x"68")); + constant CMP_A_IPV4_ADDR : PA_mem_type := ((x"C0"),(x"A8"),(x"01"),(x"01")); + constant E_TYPE_ARP : TYPE_mem_type := ((x"08"),(x"06")); + constant H_TYPE_ETH : TYPE_mem_type := ((x"00"),(x"01")); + constant P_TYPE_IPV4 : TYPE_mem_type := ((x"08"),(x"00")); + constant ARP_OPER_REQ : TYPE_mem_type := ((x"00"),(x"01")); + constant ARP_OPER_RESP : TYPE_mem_type := ((x"00"),(x"02")); + constant H_TYPE_ETH_LEN : std_logic_vector(7 downto 0) := x"06"; + constant P_TYPE_IPV4_LEN : std_logic_vector(7 downto 0) := x"04"; +end arp_package; + Index: rtl/edge_detector.vhdl =================================================================== --- rtl/edge_detector.vhdl (nonexistent) +++ rtl/edge_detector.vhdl (revision 2) @@ -0,0 +1,66 @@ +-- +-- author: Claudio Talarico +-- file: ed-mealy-rtl.vhd +-- comments: edge detector (Mealy FSM) +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity edge_detector is +port ( din : in std_logic; + clk : in std_logic; + rst_n : in std_logic; + dout : out std_logic + ); + +end edge_detector; + +architecture rtl of edge_detector is +type state_t is (zero, one); +signal state, next_state : state_t; +signal pulse : std_logic; + +begin + + the_machine: process(din,state) + begin + + -- defaults + next_state <= zero; + pulse <= '0'; + + case state is + when zero => + if (din = '0') then + next_state <= zero; + else + next_state <= one; + pulse <= '1'; + end if; + when one => + if (din = '0') then + next_state <= zero; + -- We only want a positive edge detector JRW + pulse <= '0'; + else + next_state <= one; + end if; + when others => + -- do nothing + end case; + end process the_machine; + + the_registers: process(clk, rst_n) + begin + if (rst_n = '0') then + state <= zero; + elsif (clk='1' and clk'event) then + state <= next_state; + end if; + end process the_registers; + + --dummy assignment + dout <= pulse; +end rtl; + Index: rtl =================================================================== --- rtl (nonexistent) +++ rtl (revision 2)
rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: README.txt =================================================================== --- README.txt (nonexistent) +++ README.txt (revision 2) @@ -0,0 +1,4 @@ +RTL Code is found under the rtl folder +Testbench Code is found under the testbench folder + +Main ARP Responder Block is in rtl/arp_responder.vhdl

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