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/MAC_rx_FF.v
0,0 → 1,734
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_FF.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2008/08/17 11:41:30 maverickist
// no message
//
// Revision 1.5 2006/06/25 04:58:56 maverickist
// no message
//
// Revision 1.4 2006/05/28 05:09:20 maverickist
// no message
//
// Revision 1.3 2006/01/19 14:07:54 maverickist
// verification is complete.
//
// Revision 1.3 2005/12/16 06:44:16 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2 2005/12/13 12:15:37 Administrator
// no message
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_rx_FF (
Reset ,
Clk_MAC ,
Clk_SYS ,
//MAC_rx_ctrl interface
Fifo_data ,
Fifo_data_en ,
Fifo_full ,
Fifo_data_err ,
Fifo_data_end ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface
Rx_mac_ra ,
Rx_mac_rd ,
Rx_mac_data ,
Rx_mac_BE ,
Rx_mac_sop ,
Rx_mac_pa,
Rx_mac_eop
);
input Reset ;
input Clk_MAC ;
input Clk_SYS ;
//MAC_rx_ctrl interface
input [7:0] Fifo_data ;
input Fifo_data_en ;
output Fifo_full ;
input Fifo_data_err ;
input Fifo_data_end ;
//CPU
input RX_APPEND_CRC ;
input [4:0] Rx_Hwmark ;
input [4:0] Rx_Lwmark ;
//user interface
output Rx_mac_ra ;//
input Rx_mac_rd ;
output [31:0] Rx_mac_data ;
output [1:0] Rx_mac_BE ;
output Rx_mac_pa ;
output Rx_mac_sop ;
output Rx_mac_eop ;
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter State_byte3 =4'd0;
parameter State_byte2 =4'd1;
parameter State_byte1 =4'd2;
parameter State_byte0 =4'd3;
parameter State_be0 =4'd4;
parameter State_be3 =4'd5;
parameter State_be2 =4'd6;
parameter State_be1 =4'd7;
parameter State_err_end =4'd8;
parameter State_idle =4'd9;
 
parameter SYS_read =3'd0;
parameter SYS_pause =3'd1;
parameter SYS_wait_end =3'd2;
parameter SYS_idle =3'd3;
parameter FF_emtpy_err =3'd4;
 
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
 
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
reg [35:0] Din;
reg [35:0] Din_tmp;
reg [35:0] Din_tmp_reg;
wire[35:0] Dout;
reg Wr_en;
reg Wr_en_tmp;
reg Wr_en_ptr;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
reg Full;
reg Almost_full;
reg Empty /* synthesis syn_keep=1 */;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
reg [7:0] Fifo_data_byte0;
reg [7:0] Fifo_data_byte1;
reg [7:0] Fifo_data_byte2;
reg [7:0] Fifo_data_byte3;
reg Fifo_data_en_dl1;
reg [7:0] Fifo_data_dl1;
reg Rx_mac_sop_tmp ;
reg Rx_mac_sop ;
reg Rx_mac_ra ;
reg Rx_mac_pa ;
 
 
 
reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0] Next_state_SYS ;
reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
reg Packet_number_sub ;
wire Packet_number_add_edge;
reg Packet_number_add_dl1;
reg Packet_number_add_dl2;
reg Packet_number_add ;
reg Packet_number_add_tmp ;
reg Packet_number_add_tmp_dl1;
reg Packet_number_add_tmp_dl2;
 
reg Rx_mac_sop_tmp_dl1;
reg [35:0] Dout_dl1;
reg [4:0] Fifo_data_count;
reg Rx_mac_pa_tmp ;
reg Add_wr_jump_tmp ;
reg Add_wr_jump_tmp_pl1 ;
reg Add_wr_jump ;
reg Add_wr_jump_rd_pl1 ;
reg [4:0] Rx_Hwmark_pl ;
reg [4:0] Rx_Lwmark_pl ;
reg Addr_freshed_ptr ;
integer i ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Current_state <=State_idle;
else
Current_state <=Next_state;
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
case (Current_state)
State_idle:
if (Fifo_data_en)
Next_state =State_byte3;
else
Next_state =Current_state;
State_byte3:
if (Fifo_data_en)
Next_state =State_byte2;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be1;
else
Next_state =Current_state;
State_byte2:
if (Fifo_data_en)
Next_state =State_byte1;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be2;
else
Next_state =Current_state;
State_byte1:
if (Fifo_data_en)
Next_state =State_byte0;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be3;
else
Next_state =Current_state;
State_byte0:
if (Fifo_data_en)
Next_state =State_byte3;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be0;
else
Next_state =Current_state;
State_be1:
Next_state =State_idle;
State_be2:
Next_state =State_idle;
State_be3:
Next_state =State_idle;
State_be0:
Next_state =State_idle;
State_err_end:
Next_state =State_idle;
default:
Next_state =State_idle;
endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_reg <=0;
else if (Current_state==State_idle)
Add_wr_reg <=Add_wr;
//
 
always @ (posedge Reset or posedge Clk_MAC)
if (Reset)
Add_wr_gray <=0;
else
begin
Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
end
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_ungray =0;
else
begin
Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
end
assign Add_wr_pluse=Add_wr+1;
assign Add_wr_pluse4=Add_wr+4;
assign Add_wr_pluse3=Add_wr+3;
assign Add_wr_pluse2=Add_wr+2;
 
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Full <=0;
else if (Add_wr_pluse==Add_rd_ungray)
Full <=1;
else
Full <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Almost_full <=0;
else if (Add_wr_pluse4==Add_rd_ungray||
Add_wr_pluse3==Add_rd_ungray||
Add_wr_pluse2==Add_rd_ungray||
Add_wr_pluse==Add_rd_ungray
)
Almost_full <=1;
else
Almost_full <=0;
 
assign Fifo_full =Almost_full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr <=0;
else if (Current_state==State_err_end)
Add_wr <=Add_wr_reg;
else if (Wr_en&&!Full)
Add_wr <=Add_wr +1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump_tmp <=0;
else if (Current_state==State_err_end)
Add_wr_jump_tmp <=1;
else
Add_wr_jump_tmp <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump_tmp_pl1 <=0;
else
Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_jump <=0;
else if (Current_state==State_err_end)
Add_wr_jump <=1;
else if (Add_wr_jump_tmp_pl1)
Add_wr_jump <=0;
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_en_dl1 <=0;
else
Fifo_data_en_dl1 <=Fifo_data_en;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_dl1 <=0;
else
Fifo_data_dl1 <=Fifo_data;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte3 <=0;
else if (Current_state==State_byte3&&Fifo_data_en_dl1)
Fifo_data_byte3 <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte2 <=0;
else if (Current_state==State_byte2&&Fifo_data_en_dl1)
Fifo_data_byte2 <=Fifo_data_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte1 <=0;
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
Fifo_data_byte1 <=Fifo_data_dl1;
 
always @ (* )
case (Current_state)
State_be0:
Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
State_be1:
Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
State_be2:
Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
State_be3:
Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
default:
Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
endcase
always @ (*)
if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3||
(Current_state==State_byte0&&Fifo_data_en))
Wr_en_tmp =1;
else
Wr_en_tmp =0;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Din_tmp_reg <=0;
else if(Wr_en_tmp)
Din_tmp_reg <=Din_tmp;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Wr_en_ptr <=0;
else if(Current_state==State_idle)
Wr_en_ptr <=0;
else if(Wr_en_tmp)
Wr_en_ptr <=1;
 
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Wr_en <=0;
Din <=0;
end
else if(RX_APPEND_CRC)
begin
Wr_en <=Wr_en_tmp;
Din <=Din_tmp;
end
else
begin
Wr_en <=Wr_en_tmp&&Wr_en_ptr;
Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
end
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add_tmp <=0;
else if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3)
Packet_number_add_tmp <=1;
else
Packet_number_add_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Packet_number_add_tmp_dl1 <=0;
Packet_number_add_tmp_dl2 <=0;
end
else
begin
Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
end
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add <=0;
else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
Packet_number_add <=1;
else
Packet_number_add <=0;
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Current_state_SYS <=SYS_idle;
else
Current_state_SYS <=Next_state_SYS;
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
case (Current_state_SYS)
SYS_idle:
if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
Next_state_SYS =SYS_read;
else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_read:
if (Dout[35])
Next_state_SYS =SYS_wait_end;
else if (!Rx_mac_rd)
Next_state_SYS =SYS_pause;
else if (Empty)
Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_pause:
if (Rx_mac_rd)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
FF_emtpy_err:
if (!Empty)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
SYS_wait_end:
if (!Rx_mac_rd)
Next_state_SYS =SYS_idle;
else
Next_state_SYS =Current_state_SYS;
default:
Next_state_SYS =SYS_idle;
endcase
//gen Rx_mac_ra
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Packet_number_add_dl1 <=0;
Packet_number_add_dl2 <=0;
end
else
begin
Packet_number_add_dl1 <=Packet_number_add;
Packet_number_add_dl2 <=Packet_number_add_dl1;
end
assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
Packet_number_sub =1;
else
Packet_number_sub =0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_inFF <=0;
else if (Packet_number_add_edge&&!Packet_number_sub)
Packet_number_inFF <=Packet_number_inFF + 1;
else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
Packet_number_inFF <=Packet_number_inFF - 1;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Fifo_data_count <=0;
else
Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_Hwmark_pl <=0;
Rx_Lwmark_pl <=0;
end
else
begin
Rx_Hwmark_pl <=Rx_Hwmark;
Rx_Lwmark_pl <=Rx_Lwmark;
end
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_ra <=0;
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
Rx_mac_ra <=0;
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
Rx_mac_ra <=1;
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd <=0;
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
Add_rd <=Add_rd + 1;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd_pl1 <=0;
else
Add_rd_pl1 <=Add_rd;
always @ (*)
if (Add_rd_pl1==Add_rd)
Addr_freshed_ptr =0;
else
Addr_freshed_ptr =1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
if (Reset)
Add_rd_gray <=0;
else
begin
Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
end
//
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_jump_rd_pl1 <=0;
else
Add_wr_jump_rd_pl1 <=Add_wr_jump;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_ungray =0;
else if (!Add_wr_jump_rd_pl1)
begin
Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
end
//empty signal gen
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Empty <=1;
else if (Add_rd==Add_wr_ungray)
Empty <=1;
else
Empty <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Dout_dl1 <=0;
else
Dout_dl1 <=Dout;
 
assign Rx_mac_data =Dout_dl1[31:0];
assign Rx_mac_BE =Dout_dl1[33:32];
assign Rx_mac_eop =Dout_dl1[35];
 
//aligned to Addr_rd
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa_tmp <=0;
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
Rx_mac_pa_tmp <=1;
else
Rx_mac_pa_tmp <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa <=0;
else
Rx_mac_pa <=Rx_mac_pa_tmp;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_sop_tmp <=0;
else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
Rx_mac_sop_tmp <=1;
else
Rx_mac_sop_tmp <=0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_mac_sop_tmp_dl1 <=0;
Rx_mac_sop <=0;
end
else
begin
Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
end
 
 
 
//******************************************************************************
 
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a (Din ),
.wren_a (Wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (Clk_MAC ),
.clock_b (Clk_SYS ),
.q_b (Dout ));
 
endmodule
 
 
 
 
 
/MAC_rx_ctrl.v
0,0 → 1,533
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2006/01/19 14:07:54 maverickist
// verification is complete.
//
// Revision 1.3 2005/12/16 06:44:17 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2 2005/12/13 12:15:37 Administrator
// no message
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_rx_ctrl (
Reset ,
Clk ,
//RMII interface
MCrs_dv , //
MRxD , //
MRxErr , //
//CRC_chk interface
CRC_en ,
CRC_init ,
CRC_err ,
//MAC_rx_add_chk interface
MAC_add_en ,
MAC_rx_add_chk_err ,
//broadcast_filter
broadcast_ptr ,
broadcast_drop ,
//flow_control signals
pause_quanta ,
pause_quanta_val ,
//MAC_rx_FF interface
Fifo_data ,
Fifo_data_en ,
Fifo_data_err ,
Fifo_data_end ,
Fifo_full ,
//RMON interface
Rx_pkt_type_rmon ,
Rx_pkt_length_rmon ,
Rx_apply_rmon ,
Rx_pkt_err_type_rmon ,
//CPU
RX_IFG_SET ,
RX_MAX_LENGTH,
RX_MIN_LENGTH
);
 
input Reset ;
input Clk ;
//RMII interface
input MCrs_dv ;
input [7:0] MRxD ;
input MRxErr ;
//CRC_chk interface
output CRC_en ;
output CRC_init;
input CRC_err ;
//MAC_rx_add_chk interface
output MAC_add_en ;
input MAC_rx_add_chk_err ;
//broadcast_filter
output broadcast_ptr ;
input broadcast_drop ;
//flow_control signals
output [15:0] pause_quanta ;
output pause_quanta_val ;
//MAC_rx_FF interface
output [7:0] Fifo_data ;
output Fifo_data_en ;
output Fifo_data_err ;
output Fifo_data_end ;
input Fifo_full;
//RMON interface
output [15:0] Rx_pkt_length_rmon ;
output Rx_apply_rmon ;
output [2:0] Rx_pkt_err_type_rmon ;
output [2:0] Rx_pkt_type_rmon ;
//CPU
input [5:0] RX_IFG_SET ;
input [15:0] RX_MAX_LENGTH ;// 1518
input [6:0] RX_MIN_LENGTH ;// 64
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter State_idle =4'd00;
parameter State_preamble =4'd01;
parameter State_SFD =4'd02;
parameter State_data =4'd03;
parameter State_checkCRC =4'd04;
parameter State_OkEnd =4'd07;
parameter State_drop =4'd08;
parameter State_ErrEnd =4'd09;
parameter State_CRCErrEnd =4'd10;
parameter State_FFFullDrop =4'd11;
parameter State_FFFullErrEnd =4'd12;
parameter State_IFG =4'd13;
 
parameter Pause_idle =4'd0;
parameter Pause_pre_syn =4'd1;
parameter Pause_quanta_hi =4'd2;
parameter Pause_quanta_lo =4'd3;
parameter Pause_syn =4'd4;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
reg [3:0] Pause_current /* synthesis syn_keep=1 */;
reg [3:0] Pause_next;
reg [5:0] IFG_counter;
reg Crs_dv ;
reg [7:0] RxD ;
reg [7:0] RxD_dl1 ;
reg RxErr ;
reg [15:0] Frame_length_counter;
reg Too_long;
reg Too_short;
reg Fifo_data_en;
reg Fifo_data_end;
reg Fifo_data_err;
reg CRC_en;
reg CRC_init;
reg Rx_apply_rmon;
reg Rx_apply_rmon_tmp;
reg Rx_apply_rmon_tmp_pl1;
reg [2:0] Rx_pkt_err_type_rmon;
reg MAC_add_en;
reg [2:0] Rx_pkt_type_rmon;
reg [7:0] pause_quanta_h ;
reg [15:0] pause_quanta ;
reg pause_quanta_val ;
reg pause_quanta_val_tmp;
reg pause_frame_ptr ;
reg broadcast_ptr ;
//******************************************************************************
//delay signals
//******************************************************************************
always @ (posedge Reset or posedge Clk)
if (Reset)
begin
Crs_dv <=0;
RxD <=0;
RxErr <=0;
end
else
begin
Crs_dv <=MCrs_dv ;
RxD <=MRxD ;
RxErr <=MRxErr ;
end
 
always @ (posedge Reset or posedge Clk)
if (Reset)
RxD_dl1 <=0;
else
RxD_dl1 <=RxD;
//******************************************************************************
//State_machine
//******************************************************************************
always @ (posedge Reset or posedge Clk)
if (Reset)
Current_state <=State_idle;
else
Current_state <=Next_state;
always @ (*)
case (Current_state)
State_idle:
if (Crs_dv&&RxD==8'h55)
Next_state =State_preamble;
else
Next_state =Current_state;
State_preamble:
if (!Crs_dv)
Next_state =State_ErrEnd;
else if (RxErr)
Next_state =State_drop;
else if (RxD==8'hd5)
Next_state =State_SFD;
else if (RxD==8'h55)
Next_state =Current_state;
else
Next_state =State_drop;
State_SFD:
if (!Crs_dv)
Next_state =State_ErrEnd;
else if (RxErr)
Next_state =State_drop;
else
Next_state =State_data;
State_data:
if (!Crs_dv&&!Too_short&&!Too_long)
Next_state =State_checkCRC;
else if (!Crs_dv&&(Too_short||Too_long))
Next_state =State_ErrEnd;
else if (Fifo_full)
Next_state =State_FFFullErrEnd;
else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop)
Next_state =State_drop;
else
Next_state =State_data;
State_checkCRC:
if (CRC_err)
Next_state =State_CRCErrEnd;
else
Next_state =State_OkEnd;
State_drop:
if (!Crs_dv)
Next_state =State_ErrEnd;
else
Next_state =Current_state;
State_OkEnd:
Next_state =State_IFG;
State_ErrEnd:
Next_state =State_IFG;
State_CRCErrEnd:
Next_state =State_IFG;
State_FFFullDrop:
if (!Crs_dv)
Next_state =State_IFG;
else
Next_state =Current_state;
State_FFFullErrEnd:
Next_state =State_FFFullDrop;
State_IFG:
if (IFG_counter==RX_IFG_SET-4) //remove some additional time
Next_state =State_idle;
else
Next_state =Current_state;
default:
Next_state =State_idle;
endcase
always @ (posedge Reset or posedge Clk)
if (Reset)
IFG_counter <=0;
else if (Current_state!=State_IFG)
IFG_counter <=0;
else
IFG_counter <=IFG_counter + 1;
//******************************************************************************
//gen fifo interface signals
//******************************************************************************
 
assign Fifo_data =RxD_dl1;
 
always @(Current_state)
if (Current_state==State_data)
Fifo_data_en =1;
else
Fifo_data_en =0;
always @(Current_state)
if (Current_state==State_ErrEnd||Current_state==State_OkEnd
||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Fifo_data_end =1;
else
Fifo_data_end =0;
 
always @(Current_state)
if (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Fifo_data_err =1;
else
Fifo_data_err =0;
 
//******************************************************************************
//CRC_chk interface
//******************************************************************************
 
always @(Current_state)
if (Current_state==State_data)
CRC_en =1;
else
CRC_en =0;
always @(Current_state)
if (Current_state==State_SFD)
CRC_init =1;
else
CRC_init =0;
//******************************************************************************
//gen rmon signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Frame_length_counter <=0;
else if (Current_state==State_SFD)
Frame_length_counter <=1;
else if (Current_state==State_data)
Frame_length_counter <=Frame_length_counter+ 1'b1;
always @ (Frame_length_counter or RX_MIN_LENGTH)
if (Frame_length_counter<RX_MIN_LENGTH)
Too_short =1;
else
Too_short =0;
always @ (*)
if (Frame_length_counter>RX_MAX_LENGTH)
Too_long =1;
else
Too_long =0;
assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_apply_rmon_tmp <=0;
else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Rx_apply_rmon_tmp <=1;
else
Rx_apply_rmon_tmp <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_apply_rmon_tmp_pl1 <=0;
else
Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_apply_rmon <=0;
else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Rx_apply_rmon <=1;
else if (Rx_apply_rmon_tmp_pl1)
Rx_apply_rmon <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_pkt_err_type_rmon <=0;
else if (Current_state==State_CRCErrEnd)
Rx_pkt_err_type_rmon <=3'b001 ;//
else if (Current_state==State_FFFullErrEnd)
Rx_pkt_err_type_rmon <=3'b010 ;//
else if (Current_state==State_ErrEnd)
Rx_pkt_err_type_rmon <=3'b011 ;//
else if(Current_state==State_OkEnd)
Rx_pkt_err_type_rmon <=3'b100 ;
 
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_pkt_type_rmon <=0;
else if (Current_state==State_OkEnd&&pause_frame_ptr)
Rx_pkt_type_rmon <=3'b100 ;//
else if(Current_state==State_SFD&&Next_state==State_data)
Rx_pkt_type_rmon <={1'b0,MRxD[7:6]};
 
always @ (posedge Clk or posedge Reset)
if (Reset)
broadcast_ptr <=0;
else if(Current_state==State_IFG)
broadcast_ptr <=0;
else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)
broadcast_ptr <=1;
 
//******************************************************************************
//MAC add checker signals
//******************************************************************************
always @ (Frame_length_counter or Fifo_data_en)
if(Frame_length_counter>=1&&Frame_length_counter<=6)
MAC_add_en <=Fifo_data_en;
else
MAC_add_en <=0;
 
//******************************************************************************
//flow control signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Pause_current <=Pause_idle;
else
Pause_current <=Pause_next;
always @ (*)
case (Pause_current)
Pause_idle :
if(Current_state==State_SFD)
Pause_next =Pause_pre_syn;
else
Pause_next =Pause_current;
Pause_pre_syn:
case (Frame_length_counter)
16'd1: if (RxD_dl1==8'h01)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd2: if (RxD_dl1==8'h80)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd3: if (RxD_dl1==8'hc2)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd4: if (RxD_dl1==8'h00)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd5: if (RxD_dl1==8'h00)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd6: if (RxD_dl1==8'h01)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd13: if (RxD_dl1==8'h88)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd14: if (RxD_dl1==8'h08)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd15: if (RxD_dl1==8'h00)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd16: if (RxD_dl1==8'h01)
Pause_next =Pause_quanta_hi;
else
Pause_next =Pause_idle;
default: Pause_next =Pause_current;
endcase
Pause_quanta_hi :
Pause_next =Pause_quanta_lo;
Pause_quanta_lo :
Pause_next =Pause_syn;
Pause_syn :
if (Current_state==State_IFG)
Pause_next =Pause_idle;
else
Pause_next =Pause_current;
default
Pause_next =Pause_idle;
endcase
 
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_h <=0;
else if(Pause_current==Pause_quanta_hi)
pause_quanta_h <=RxD_dl1;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta <=0;
else if(Pause_current==Pause_quanta_lo)
pause_quanta <={pause_quanta_h,RxD_dl1};
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_val_tmp <=0;
else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)
pause_quanta_val_tmp <=1;
else
pause_quanta_val_tmp <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_val <=0;
else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)
pause_quanta_val <=1;
else
pause_quanta_val <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_frame_ptr <=0;
else if(Pause_current==Pause_syn)
pause_frame_ptr <=1;
else
pause_frame_ptr <=0;
endmodule
/CRC_chk.v
0,0 → 1,126
//////////////////////////////////////////////////////////////////////
//// ////
//// CRC_chk.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:16 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module CRC_chk(
Reset ,
Clk ,
CRC_data ,
CRC_init ,
CRC_en ,
//From CPU
CRC_chk_en ,
CRC_err
);
input Reset ;
input Clk ;
input[7:0] CRC_data ;
input CRC_init ;
input CRC_en ;
//From CPU
input CRC_chk_en ;
output CRC_err ;
//******************************************************************************
//internal signals
//******************************************************************************
reg [31:0] CRC_reg;
wire[31:0] Next_CRC;
//******************************************************************************
//input data width is 8bit, and the first bit is bit[0]
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
 
always @ (posedge Clk or posedge Reset)
if (Reset)
CRC_reg <=32'hffffffff;
else if (CRC_init)
CRC_reg <=32'hffffffff;
else if (CRC_en)
CRC_reg <=NextCRC(CRC_data,CRC_reg);
 
assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
 
endmodule
/MAC_rx_add_chk.v
0,0 → 1,153
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_add_chk.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:17 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_rx_add_chk (
Reset ,
Clk ,
Init ,
data ,
MAC_add_en ,
MAC_rx_add_chk_err ,
//From CPU
MAC_rx_add_chk_en ,
MAC_add_prom_data ,
MAC_add_prom_add ,
MAC_add_prom_wr
 
);
input Reset ;
input Clk ;
input Init ;
input [7:0] data ;
input MAC_add_en ;
output MAC_rx_add_chk_err ;
//From CPU
input MAC_rx_add_chk_en ;
input [7:0] MAC_add_prom_data ;
input [2:0] MAC_add_prom_add ;
input MAC_add_prom_wr ;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg [2:0] addr_rd;
wire[2:0] addr_wr;
wire[7:0] din;
wire[7:0] dout;
wire wr_en;
 
reg MAC_rx_add_chk_err;
reg MAC_add_prom_wr_dl1;
reg MAC_add_prom_wr_dl2;
reg [7:0] data_dl1 ;
reg MAC_add_en_dl1 ;
//******************************************************************************
//write data from cpu to prom
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
data_dl1 <=0;
MAC_add_en_dl1 <=0;
end
else
begin
data_dl1 <=data;
MAC_add_en_dl1 <=MAC_add_en;
end
 
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
MAC_add_prom_wr_dl1 <=0;
MAC_add_prom_wr_dl2 <=0;
end
else
begin
MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
end
assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
assign addr_wr =MAC_add_prom_add;
assign din =MAC_add_prom_data;
 
//******************************************************************************
//mac add verify
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
addr_rd <=0;
else if (Init)
addr_rd <=0;
else if (MAC_add_en)
addr_rd <=addr_rd + 1;
always @ (posedge Clk or posedge Reset)
if (Reset)
MAC_rx_add_chk_err <=0;
else if (Init)
MAC_rx_add_chk_err <=0;
else if (MAC_rx_add_chk_en&&MAC_add_en_dl1&&dout!=data_dl1)
MAC_rx_add_chk_err <=1;
 
//******************************************************************************
//a port for read ,b port for write .
//******************************************************************************
duram #(8,3,"M512","DUAL_PORT") U_duram(
.data_a (din ),
.wren_a (wr_en ),
.address_a (addr_wr ),
.address_b (addr_rd ),
.clock_a (Clk ),
.clock_b (Clk ),
.q_b (dout ));
 
endmodule
/Broadcast_filter.v
0,0 → 1,104
//////////////////////////////////////////////////////////////////////
//// ////
//// Broadcast_filter.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:16 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module Broadcast_filter (
Reset ,
Clk ,
//MAC_rx_ctrl ,
broadcast_ptr ,
broadcast_drop ,
//FromCPU ,
broadcast_filter_en ,
broadcast_bucket_depth ,
broadcast_bucket_interval
);
input Reset ;
input Clk ;
//MAC_rx_ctrl
input broadcast_ptr ;
output broadcast_drop ;
//FromCPU ;
input broadcast_filter_en ;
input [15:0] broadcast_bucket_depth ;
input [15:0] broadcast_bucket_interval ;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg [15:0] time_counter ;
reg [15:0] broadcast_counter ;
reg broadcast_drop ;
//******************************************************************************
//
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
time_counter <=0;
else if (time_counter==broadcast_bucket_interval)
time_counter <=0;
else
time_counter <=time_counter+1;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
broadcast_counter <=0;
else if (time_counter==broadcast_bucket_interval)
broadcast_counter <=0;
else if (broadcast_ptr&&broadcast_counter!=broadcast_bucket_depth)
broadcast_counter <=broadcast_counter+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
broadcast_drop <=0;
else if(broadcast_filter_en&&broadcast_counter==broadcast_bucket_depth)
broadcast_drop <=1;
else
broadcast_drop <=0;
 
endmodule

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