URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac/tags/rel_22/sim/rtl_sim/bin
- from Rev 335 to Rev 338
- ↔ Reverse comparison
Rev 335 → Rev 338
/sim_file_list.lst
0,0 → 1,14
../../../bench/verilog/tb_ethernet.v |
../../../bench/verilog/tb_eth_defines.v |
../../../bench/verilog/eth_phy.v |
../../../bench/verilog/eth_phy_defines.v |
../../../bench/verilog/wb_bus_mon.v |
../../../bench/verilog/wb_slave_behavioral.v |
../../../bench/verilog/wb_master32.v |
../../../bench/verilog/wb_master_behavioral.v |
../../../../../lib/artisan/art_hssp_256x32_bist.v |
../../../../../lib/artisan/art_hssp_256x32/art_hssp_256x32.v |
../../../../../bist/rtl/verilog/bist.v |
../../../../../bist/rtl/verilog/bist_sp_top.v |
|
|
sim_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_file_list.lst
===================================================================
--- rtl_file_list.lst (nonexistent)
+++ rtl_file_list.lst (revision 338)
@@ -0,0 +1,26 @@
+../../../rtl/verilog/eth_crc.v
+../../../rtl/verilog/eth_defines.v
+../../../rtl/verilog/eth_maccontrol.v
+../../../rtl/verilog/eth_macstatus.v
+../../../rtl/verilog/eth_miim.v
+../../../rtl/verilog/eth_outputcontrol.v
+../../../rtl/verilog/eth_random.v
+../../../rtl/verilog/eth_receivecontrol.v
+../../../rtl/verilog/eth_register.v
+../../../rtl/verilog/eth_registers.v
+../../../rtl/verilog/eth_rxcounters.v
+../../../rtl/verilog/eth_rxethmac.v
+../../../rtl/verilog/eth_rxstatem.v
+../../../rtl/verilog/eth_shiftreg.v
+../../../rtl/verilog/timescale.v
+../../../rtl/verilog/eth_top.v
+../../../rtl/verilog/eth_transmitcontrol.v
+../../../rtl/verilog/eth_txcounters.v
+../../../rtl/verilog/eth_txethmac.v
+../../../rtl/verilog/eth_txstatem.v
+../../../rtl/verilog/eth_clockgen.v
+../../../rtl/verilog/eth_spram_256x32.v
+../../../rtl/verilog/eth_wishbone.v
+../../../rtl/verilog/eth_fifo.v
+../../../rtl/verilog/eth_rxaddrcheck.v
+../../../rtl/verilog/xilinx_dist_ram_16x32.v
rtl_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncelab.args
===================================================================
--- ncelab.args (nonexistent)
+++ ncelab.args (revision 338)
@@ -0,0 +1,7 @@
+-snapshot worklib.ethernet:fun
+-cdslib ../bin/cds.lib
+-logfile ../log/ncelab.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93 worklib.tb_ethernet
ncelab.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncelab_xilinx.args
===================================================================
--- ncelab_xilinx.args (nonexistent)
+++ ncelab_xilinx.args (revision 338)
@@ -0,0 +1,9 @@
+-snapshot worklib.ethernet:fun
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncelab_xilinx.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93
+worklib.tb_ethernet worklib.glbl
ncelab_xilinx.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim_waves.rc
===================================================================
--- ncsim_waves.rc (nonexistent)
+++ ncsim_waves.rc (revision 338)
@@ -0,0 +1,7 @@
+set dump_level all
+
+database -open waves -shm -into ../out/waves.shm
+probe -create -database waves tb_ethernet -shm -all -depth $dump_level
+
+run
+quit
ncsim_waves.rc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: INCA_libs/worklib/dir_keeper
===================================================================
Index: xilinx_file_list.lst
===================================================================
--- xilinx_file_list.lst (nonexistent)
+++ xilinx_file_list.lst (revision 338)
@@ -0,0 +1,4 @@
+../../../../../lib/xilinx/lib/glbl/glbl.v
+../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+../../../../../lib/xilinx/lib/unisims/RAMB4_S16.v
+../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
xilinx_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: artisan_file_list.lst
===================================================================
--- artisan_file_list.lst (nonexistent)
+++ artisan_file_list.lst (revision 338)
@@ -0,0 +1,8 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncvlog_artisan.log
+-update
+-messages
+../../../../../../lib/artisan/art_hsdp_256x40.v
+../../../../../../lib/artisan/art_hddp_8192x64.v
+
artisan_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim.rc
===================================================================
--- ncsim.rc (nonexistent)
+++ ncsim.rc (revision 338)
@@ -0,0 +1,2 @@
+run
+quit
ncsim.rc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run_sim
===================================================================
--- run_sim (nonexistent)
+++ run_sim (revision 338)
@@ -0,0 +1,47 @@
+#!/bin/csh -f
+
+set arg_num = $#argv; # number of arguments
+
+if ($arg_num < 1) then
+ echo " "
+ echo "Missing required ATS argument:"
+ echo " '-r' for regression"
+ echo " "
+ exit
+endif
+
+set cur_arg = 1
+set arg_chk = 0
+
+set regression = 0
+
+while ($cur_arg <= $arg_num)
+ if ("$argv[$cur_arg]" == "-r") then
+ @ regression = 1
+ @ arg_chk = $arg_chk + 1
+ endif
+
+ if ($arg_chk != $cur_arg) then
+ echo " "
+ echo "Invalid argument $argv[$cur_arg]"
+ echo " "
+ exit
+ endif
+
+ @ cur_arg = $cur_arg + 1
+end
+
+if ($regression == 0) then
+ echo " "
+ echo "Missing required ATS argument:"
+ echo " '-r' for regression"
+ echo " "
+ exit
+else
+ echo " "
+ echo "ATS running ethernet script with following argument:"
+ echo " '-r' for regression"
+ echo " "
+ ../run/run_eth_sim_regr.scr -r
+endif
+
run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: cds.lib
===================================================================
--- cds.lib (nonexistent)
+++ cds.lib (revision 338)
@@ -0,0 +1,2 @@
+define worklib ../bin/INCA_libs/worklib
+include $CDS_INST_DIR/tools/inca/files/cds.lib
cds.lib
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: hdl.var
===================================================================
--- hdl.var (nonexistent)
+++ hdl.var (revision 338)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Sat Aug 4 10:51:23 2001
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)
hdl.var
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property