URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac/tags/rel_24/sim/rtl_sim/ncsim_sim/bin
- from Rev 335 to Rev 338
- ↔ Reverse comparison
Rev 335 → Rev 338
/sim_file_list.lst
0,0 → 1,10
../../../../bench/verilog/tb_ethernet.v |
../../../../bench/verilog/tb_eth_defines.v |
../../../../bench/verilog/eth_phy.v |
../../../../bench/verilog/eth_phy_defines.v |
../../../../bench/verilog/wb_bus_mon.v |
../../../../bench/verilog/wb_slave_behavioral.v |
../../../../bench/verilog/wb_master32.v |
../../../../bench/verilog/wb_master_behavioral.v |
../../../../../../lib/vs_rams/018/vs_hdsp_256x32/vs_hdsp_256x32.v |
|
/xilinx_file_list.lst
0,0 → 1,4
../../../../../../lib/xilinx/lib/glbl/glbl.v |
../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v |
../../../../../../lib/xilinx/lib/unisims/RAMB4_S16.v |
../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v |
/artisan_file_list.lst
0,0 → 1,8
-cdslib ../bin/cds.lib |
-hdlvar ../bin/hdl.var |
-logfile ../log/ncvlog_artisan.log |
-update |
-messages |
../../../../../../lib/artisan/art_hsdp_256x40.v |
../../../../../../lib/artisan/art_hddp_8192x64.v |
|
/rtl_file_list.lst
0,0 → 1,25
../../../../rtl/verilog/eth_crc.v |
../../../../rtl/verilog/eth_defines.v |
../../../../rtl/verilog/eth_maccontrol.v |
../../../../rtl/verilog/eth_macstatus.v |
../../../../rtl/verilog/eth_miim.v |
../../../../rtl/verilog/eth_outputcontrol.v |
../../../../rtl/verilog/eth_random.v |
../../../../rtl/verilog/eth_receivecontrol.v |
../../../../rtl/verilog/eth_register.v |
../../../../rtl/verilog/eth_registers.v |
../../../../rtl/verilog/eth_rxcounters.v |
../../../../rtl/verilog/eth_rxethmac.v |
../../../../rtl/verilog/eth_rxstatem.v |
../../../../rtl/verilog/eth_shiftreg.v |
../../../../rtl/verilog/timescale.v |
../../../../rtl/verilog/eth_top.v |
../../../../rtl/verilog/eth_transmitcontrol.v |
../../../../rtl/verilog/eth_txcounters.v |
../../../../rtl/verilog/eth_txethmac.v |
../../../../rtl/verilog/eth_txstatem.v |
../../../../rtl/verilog/eth_clockgen.v |
../../../../rtl/verilog/eth_spram_256x32.v |
../../../../rtl/verilog/eth_wishbone.v |
../../../../rtl/verilog/eth_fifo.v |
../../../../rtl/verilog/eth_rxaddrcheck.v |
/INCA_libs/worklib/dir_keeper
--- ncelab.args (nonexistent)
+++ ncelab.args (revision 338)
@@ -0,0 +1,7 @@
+-snapshot worklib.ethernet:fun
+-cdslib ../bin/cds.lib
+-logfile ../log/ncelab.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93 worklib.tb_ethernet
/ncsim_waves.rc
0,0 → 1,7
set dump_level all |
|
database -open waves -shm -into ../out/waves.shm |
probe -create -database waves tb_ethernet -shm -all -depth $dump_level |
|
run |
quit |
/ncelab_xilinx.args
0,0 → 1,9
-snapshot worklib.ethernet:fun |
-cdslib ../bin/cds.lib |
-hdlvar ../bin/hdl.var |
-logfile ../log/ncelab_xilinx.log |
-access +wc |
-messages |
-no_tchk_msg |
-v93 |
worklib.tb_ethernet worklib.glbl |
/ncsim.rc
0,0 → 1,2
run |
quit |
/cds.lib
0,0 → 1,2
define worklib ../bin/INCA_libs/worklib |
include $CDS_INST_DIR/tools/inca/files/cds.lib |
/hdl.var
0,0 → 1,9
# |
# hdl.var: Defines variables used by the INCA tools. |
# Created by ncprep on Sat Aug 4 10:51:23 2001 |
# |
|
softinclude $CDS_INST_DIR/tools/inca/files/hdl.var |
|
define LIB_MAP ( $LIB_MAP, + => worklib ) |
define VIEW_MAP ( $VIEW_MAP, .v => v) |