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URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

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  • This comparison shows the changes necessary to convert path 
    /ethmac10g/tags/V10/bench
    from Rev 40 to Rev 72
    ↔ Reverse comparison
  •

Rev 40 → Rev 72

/debug_large.do
0,0 → 1,119
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_CLK
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/RESET
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_START
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_UNDERRUN
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/TX_ACK
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_tb/U_top_module/TXD
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_tb/U_top_module/TXC
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/FC_TRANS_PAUSEDATA
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/FC_TRANS_PAUSEVAL
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/FC_TX_PAUSEDATA
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/FC_TX_PAUSEVALID
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/FRAME_START
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/reset_int
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/DELAY_ACK
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_REG
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL1
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL2
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL3
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL4
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL5
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL6
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL7
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL8
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL9
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL10
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL11
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL12
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL13
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL14
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DEL15
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL1
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL2
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL3
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL4
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL5
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL6
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL7
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL8
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL9
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL10
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL11
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL12
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL13
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL14
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_DEL15
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/OVERFLOW_VALID
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/OVERFLOW_DATA
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_REG
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TX_DATA_VALID_DELAY
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/CRC_32_64
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/BYTE_COUNTER
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/frame_start_del
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/transmit_pause_frame_del
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/transmit_pause_frame
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/append_start_pause
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/append_start_pause_del
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/transmit_pause_frame_valid
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/reset_err_pause
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/load_CRC8
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/tx_data_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/start_CRC8
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/START_CRC8_DEL
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/append_end_frame
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/insert_error
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_tx_data_valid
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_tx_data
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_CRC64
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_valid
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/load_final_CRC
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/final_byte_count
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/byte_count_reg
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/CRC_OUT
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/append_reg
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/length_register
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/tx_undderrun_int
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/MAX_FRAME_SIZE
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/vlan_enabled_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/jumbo_enabled_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/tx_enabled_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/fcs_enabled_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/reset_tx_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/read_ifg_int
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/apply_pause_delay
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_pause_frame
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXD_PAUSE_DEL0
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXD_PAUSE_DEL1
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXD_PAUSE_DEL2
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXC_PAUSE_DEL0
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXC_PAUSE_DEL1
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/TXC_PAUSE_DEL2
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/PAUSEVAL_DEL
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/PAUSEVAL_DEL1
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/PAUSEVAL_DEL2
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/RESET_ERR_PAUSE
add wave -noupdate -format Logic /TransmitTop_tb/U_top_module/set_pause_stats
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/store_transmit_pause_value
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/pause_frame_counter
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/shift_pause_data
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/shift_pause_valid
add wave -noupdate -format Literal /TransmitTop_tb/U_top_module/shift_pause_valid_del
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {480 ns} 0}
WaveRestoreZoom {225 ns} {617 ns}
configure wave -namecolwidth 403
configure wave -valuecolwidth 182
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
/TransmitTop_CRC_tb.v
0,0 → 1,157
`include "TransmitTop.v"
module TransmitTop_min_frame_tb();
 
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
 
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
 
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
 
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
 
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
 
reg START_TX_BITS;
 
// Initialize all variables
initial begin
 
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET= 1; // Assert the reset
#10 RESET= 0; // De-assert the reset
#15 TX_START = 1;
// TX_DATA = 64'h0000560000000000;
TX_DATA_VALID = 8'hFF;
D_START = 1;
#20 TX_START = 0;
//#1800 TX_DATA_VALID = 8'h07;
#60 TX_DATA_VALID = 8'h07;
// #1960 TX_DATA_VALID = 8'h07;
// TX_DATA = 64'h0000000000000011;
#10 TX_DATA_VALID = 8'h00;
D_START = 0;
//next frame
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
 
#1000 $finish; // Terminate simulation
end
 
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
 
 
 
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
 
end
 
 
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
 
 
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
 
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
 
 
 
 
endmodule
/debug_pause.do
0,0 → 1,122
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/TX_CLK
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/RESET
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/TX_START
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/TX_UNDERRUN
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/TX_ACK
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TXD
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TXC
add wave -noupdate -format Literal -radix unsigned /TransmitTopPause_tb/U_top_module/FC_TRANS_PAUSEDATA
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/FC_TRANS_PAUSEVAL
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/FC_TX_PAUSEDATA
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/FC_TX_PAUSEVALID
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/FRAME_START
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/reset_int
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/DELAY_ACK
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_REG
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_REG
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL1
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL1
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL2
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL3
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL4
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL5
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL6
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL7
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL8
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL9
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL10
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL11
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL12
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL13
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL14
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DEL15
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/OVERFLOW_VALID
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/shift_pause_data
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/load_CRC8
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/transmit_pause_frame
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/transmit_pause_frame_del
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/shift_pause_valid
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL2
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL3
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL4
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL5
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL6
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL7
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL8
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL9
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL10
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL11
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL12
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL13
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL14
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_DEL15
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/OVERFLOW_DATA
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/transmit_pause_frame_valid
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/store_tx_data_valid
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/load_final_CRC
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/append_end_frame
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_REG
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/TX_DATA_VALID_DELAY
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/CRC_32_64
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/BYTE_COUNTER
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/frame_start_del
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/append_start_pause
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/append_start_pause_del
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/reset_err_pause
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/store_tx_data_valid
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/load_CRC8
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/tx_data_int
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/U_CRC8/CRC_OUT
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/start_CRC8
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/START_CRC8_DEL
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/insert_error
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/store_tx_data
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/store_CRC64
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/store_valid
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/final_byte_count
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/byte_count_reg
add wave -noupdate -format Literal -radix hexadecimal /TransmitTopPause_tb/U_top_module/CRC_OUT
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/append_reg
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/length_register
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/tx_undderrun_int
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/MAX_FRAME_SIZE
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/vlan_enabled_int
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/jumbo_enabled_int
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/tx_enabled_int
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/fcs_enabled_int
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/reset_tx_int
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/read_ifg_int
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/apply_pause_delay
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/store_pause_frame
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TXD_PAUSE_DEL0
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TXD_PAUSE_DEL1
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TXD_PAUSE_DEL2
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TXC_PAUSE_DEL0
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TXC_PAUSE_DEL1
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/TXC_PAUSE_DEL2
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/PAUSEVAL_DEL
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/PAUSEVAL_DEL1
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/PAUSEVAL_DEL2
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/RESET_ERR_PAUSE
add wave -noupdate -format Logic /TransmitTopPause_tb/U_top_module/set_pause_stats
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/store_transmit_pause_value
add wave -noupdate -format Literal /TransmitTopPause_tb/U_top_module/pause_frame_counter
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {713 ns} 0}
WaveRestoreZoom {504 ns} {847 ns}
configure wave -namecolwidth 403
configure wave -valuecolwidth 182
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
/TransmitTop.mpf
0,0 → 1,376
;
; Copyright Model Technology, a Mentor Graphics Corporation company 2003,
; All rights reserved.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
 
UNISIMS_VER = C:\FPGAdv62PS\Modeltech\Xilinx_libs\unisims_ver
SIMPRIMS_VER = C:\FPGAdv62PS\Modeltech\Xilinx_libs\simprims_ver
XILINXCORELIB_VER = C:\FPGAdv62PS\Modeltech\Xilinx_libs\XilinxCoreLib_ver
UNISIM = C:\FPGAdv62PS\Modeltech\Xilinx_libs\unisim
SIMPRIM = C:\FPGAdv62PS\Modeltech\Xilinx_libs\simprim
XILINXCORELIB = C:\FPGAdv62PS\Modeltech\Xilinx_libs\XilinxCoreLib
work = work
[vcom]
; Turn on VHDL-1993 as the default. Default is off (VHDL-1987).
; VHDL93 = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explict enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = false
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 1ns
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = ns
 
; Default run length
RunLength = 100 ns
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus
 
; Stop the simulator after an assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
; from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not define for assertion level, use AssertionFormatBreak
; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
; otherwise use AssertionFormat.
;
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
 
; Assertion File - alternate file for storing assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, or deposit
; or in other terms, fixed, wired, or charged.
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control number of VHDL files open concurrently
; This number should always be less than the
; current ulimit setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the waveform window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of a generate statement label. Do not quote it.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (log only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
[lmc]
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
 
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
[Project]
Project_Version = 5
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 9
Project_File_0 = CRC32_D8.v
Project_File_P_0 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1138046060 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 3 dont_compile 0
Project_File_1 = C:/Documents and Settings/Administrator/Desktop/Transmit Code/TransmitTop/TransmitTop_pause_tb.v
Project_File_P_1 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1141519658 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 7 dont_compile 0
Project_File_2 = C:/Documents and Settings/Administrator/Desktop/Transmit Code/TransmitTop/TransmitTop_min_frame_tb.v
Project_File_P_2 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1140359148 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 6 dont_compile 0
Project_File_3 = TransmitTop.v
Project_File_P_3 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 1 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1143300944 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
Project_File_4 = CRC32_D64.v
Project_File_P_4 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1141580292 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 2 dont_compile 0
Project_File_5 = ack_counter.v
Project_File_P_5 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1137802524 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 0 dont_compile 0
Project_File_6 = TransmitTop_tb.v
Project_File_P_6 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1140351806 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 5 dont_compile 0
Project_File_7 = C:/Documents and Settings/Administrator/Desktop/Transmit Code/TransmitTop/Copy of TransmitTop.v
Project_File_P_7 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1142704298 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 8 dont_compile 0
Project_File_8 = byte_counter.v
Project_File_P_8 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1142697560 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 compile_to work vlog_upper 0 vlog_options {} compile_order 1 dont_compile 0
Project_Sim_Count = 0
Project_Folder_Count = 0
/debug.do
0,0 → 1,130
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_CLK
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/RESET
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_START
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_UNDERRUN
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/TX_ACK
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/FC_TRANS_PAUSEDATA
add wave -noupdate -format Logic -radix unsigned /TransmitTop_min_frame_tb/U_top_module/FC_TRANS_PAUSEVAL
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/FC_TX_PAUSEDATA
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/FC_TX_PAUSEVALID
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/FRAME_START
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/reset_int
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/DELAY_ACK
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/BYTE_COUNTER
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/final_byte_count
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_REG
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL1
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL2
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL3
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL4
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL5
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL6
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL7
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL8
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL9
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL10
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL11
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL12
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL13
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL14
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_DEL15
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_REG
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL1
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL2
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL3
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL4
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL5
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL6
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL7
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL8
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL9
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL10
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL11
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL12
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL13
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL14
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA_VALID_DEL15
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/reset_err_pause
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/apply_pause_delay
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/store_pause_frame
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXD_PAUSE_DEL0
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXD_PAUSE_DEL1
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXD_PAUSE_DEL2
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXC_PAUSE_DEL0
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXC_PAUSE_DEL1
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/TXC_PAUSE_DEL2
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/PAUSEVAL_DEL
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/PAUSEVAL_DEL1
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/PAUSEVAL_DEL2
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/set_pause_stats
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/store_transmit_pause_value
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/pause_frame_counter
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/shift_pause_data
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/shift_pause_valid
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/load_final_CRC
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/append_end_frame
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/START_CRC8_DEL
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/load_CRC8
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/insert_error
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/store_tx_data_valid
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/store_tx_data
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/tx_data_int
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/store_CRC64
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/frame_start_del
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/TX_DATA
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/final_byte_count
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/byte_count_reg
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/append_reg
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/start_CRC8
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/transmit_pause_frame_del
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/transmit_pause_frame
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/append_start_pause
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/append_start_pause_del
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/transmit_pause_frame_valid
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/load_CRC8
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/CRC_OUT
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/vlan_enabled_int
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/jumbo_enabled_int
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/length_register
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/tx_undderrun_int
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/MAX_FRAME_SIZE
add wave -noupdate -divider CRC64
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/DATA_IN
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/CLK
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/RESET
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/START
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/CRC_OUT
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/CRC_REG
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC64/startCRC
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC64/data_del
add wave -noupdate -divider CRC8
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/DATA_IN
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/CLK
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/RESET
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/START
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/LOAD
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/CRC_IN
add wave -noupdate -format Literal -radix hexadecimal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/CRC_OUT
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/U_CRC8/start_int
add wave -noupdate -format Literal /TransmitTop_min_frame_tb/U_top_module/U_CRC8/data_int
add wave -noupdate -format Logic /TransmitTop_min_frame_tb/U_top_module/vlan_enabled_int
add wave -noupdate -format Literal -radix unsigned /TransmitTop_min_frame_tb/U_top_module/length_register
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {240 ns} 0}
WaveRestoreZoom {0 ns} {747 ns}
configure wave -namecolwidth 393
configure wave -valuecolwidth 134
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
/TransmitTop_min_frame_tb.v
0,0 → 1,157
`include "TransmitTop.v"
module TransmitTop_min_frame_tb();
 
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
 
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
 
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
 
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
 
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
 
reg START_TX_BITS;
 
// Initialize all variables
initial begin
 
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET= 1; // Assert the reset
#10 RESET= 0; // De-assert the reset
#15 TX_START = 1;
// TX_DATA = 64'h0000560000000000;
TX_DATA_VALID = 8'hFF;
D_START = 1;
#20 TX_START = 0;
//#1800 TX_DATA_VALID = 8'h07;
#60 TX_DATA_VALID = 8'h07;
// #1960 TX_DATA_VALID = 8'h07;
// TX_DATA = 64'h0000000000000011;
#10 TX_DATA_VALID = 8'h00;
D_START = 0;
//next frame
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
 
#1000 $finish; // Terminate simulation
end
 
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
 
 
 
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
 
end
 
 
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
 
 
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
 
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
 
 
 
 
endmodule
/TransmitTop_pause_tb.v
0,0 → 1,161
`include "TransmitTop.v"
module TransmitTopPause_tb();
 
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
 
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
 
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
 
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
 
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
 
reg START_TX_BITS;
 
// Initialize all variables
initial begin
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET <= 1; // Assert the reset
#10 RESET <= 0; // De-assert the reset
 
#15 //TX_START <= 1;
//TX_DATA_VALID <= 8'hFF;
//D_START <= 1;
#20 TX_START <= 0;
#400 //TX_DATA_VALID <= 8'h00;
//FC_TX_PAUSEVALID <= 1;
//FC_TX_PAUSEDATA <= 30;
FC_TRANS_PAUSEDATA <= 30;
FC_TRANS_PAUSEVAL <= 1;
//TX_DATA_VALID <= 8'h7f;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
//FC_TX_PAUSEVALID <= 0;
//FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
#20 //TX_START <= 1;
//TX_DATA_VALID <= 8'hFF;
//D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
#1300 $finish; // Terminate simulation
end
 
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
 
 
 
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
 
end
 
 
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
 
 
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
 
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
 
 
 
 
endmodule
 
/TransmitTop_tb.v
0,0 → 1,161
`include "TransmitTop.v"
module TransmitTop_tb();
 
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
 
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
 
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
 
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
 
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
 
reg START_TX_BITS;
 
// Initialize all variables
initial begin
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET <= 1; // Assert the reset
#10 RESET <= 0; // De-assert the reset
 
#15 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START <= 1;
#20 TX_START <= 0;
#400 //TX_DATA_VALID <= 8'h00;
//FC_TX_PAUSEVALID <= 1;
//FC_TX_PAUSEDATA <= 30;
// FC_TRANS_PAUSEDATA <= 30;
// FC_TRANS_PAUSEVAL <= 1;
TX_DATA_VALID <= 8'h7f;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
//FC_TX_PAUSEVALID <= 0;
//FC_TX_PAUSEDATA <= 0;
// FC_TRANS_PAUSEDATA <= 0;
// FC_TRANS_PAUSEVAL <= 0;
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
#1300 $finish; // Terminate simulation
end
 
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
 
 
 
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
 
end
 
 
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
 
 
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
 
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
 
 
 
 
endmodule
 
/rxtest.v
0,0 → 1,716
/*-------------------------------------------------------------------------------
-- $Revision: 1.1.1.1 $ $Date: 2006-05-31 05:59:46 $
-- Title : Demo testbench
-- Project : 10 Gigabit Ethernet MAC
-------------------------------------------------------------------------------
-- File : demo_tb.v
-------------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core to
-- demonstrate the functionality.
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Xilinx Inc.
-------------------------------------------------------------------------------
--
-- This testbench performs the following operations on the MAC core:
-- - The clock divide register is set for MIIM operation. */
/* - The clientXGMII port is wired as a loopback, so that transmitted frames
-- are then injected into the receiver.
-- - Four frames are pushed into the receiver. The first is a minimum
-- length frame, the second is slightly longer, the third has an error
-- asserted and the fourth is less than minimum length and is padded
-- up to the minimum.
-- - These frames are then looped back and sent out by the transmitter.
-- */
 
`timescale 1ps / 1ps
 
 
module frame_typ;
// This module abstracts the frame data for simpler manipulation
reg [31:0] data [0:31];
reg [ 3:0] ctrl [0:31];
reg [31:0] crc;
reg underrun;
 
`define FRAME_TYP [32*32+32*4+32+1:1]
 
reg `FRAME_TYP bits;
 
function `FRAME_TYP tobits;
input dummy;
begin
bits = {data[ 0], data[ 1], data[ 2], data[ 3], data[ 4],
data[ 5], data[ 6], data[ 7], data[ 8], data[ 9],
data[10], data[11], data[12], data[13], data[14],
data[15], data[16], data[17], data[18], data[19],
data[20], data[21], data[22], data[23], data[24],
data[25], data[26], data[27], data[28], data[29],
data[30], data[31], ctrl[ 0], ctrl[ 1], ctrl[ 2],
ctrl[ 3], ctrl[ 4], ctrl[ 5], ctrl[ 6], ctrl[ 7],
ctrl[ 8], ctrl[ 9], ctrl[10], ctrl[11], ctrl[12],
ctrl[13], ctrl[14], ctrl[15], ctrl[16], ctrl[17],
ctrl[18], ctrl[19], ctrl[20], ctrl[21], ctrl[22],
ctrl[23], ctrl[24], ctrl[25], ctrl[26], ctrl[27],
ctrl[28], ctrl[29], ctrl[30], ctrl[31], crc, underrun};
tobits = bits;
end
endfunction // tobits
 
task frombits;
input `FRAME_TYP frame;
begin
bits = frame;
{data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], data[ 5],
data[ 6], data[ 7], data[ 8], data[ 9], data[10], data[11],
data[12], data[13], data[14], data[15], data[16], data[17],
data[18], data[19], data[20], data[21], data[22], data[23],
data[24], data[25], data[26], data[27], data[28], data[29],
data[30], data[31], ctrl[ 0], ctrl[ 1], ctrl[ 2], ctrl[ 3],
ctrl[ 4], ctrl[ 5], ctrl[ 6], ctrl[ 7], ctrl[ 8], ctrl[ 9],
ctrl[10], ctrl[11], ctrl[12], ctrl[13], ctrl[14], ctrl[15],
ctrl[16], ctrl[17], ctrl[18], ctrl[19], ctrl[20], ctrl[21],
ctrl[22], ctrl[23], ctrl[24], ctrl[25], ctrl[26], ctrl[27],
ctrl[28], ctrl[29], ctrl[30], ctrl[31], crc, underrun} = bits;
end
endtask // frombits
endmodule // frame_typ
 
 
// Address of management configuration register
`define CONFIG_MANAGEMENT 9'b101000000
// Address of flow control configuration register
`define CONFIG_FLOW_CTRL 9'b011000000
// addresses of statistics registers
`define STATS_TX_OK 9'b000100000
`define STATS_TX_UNDERRUN 9'b000100011
`define STATS_RX_OK 9'b000000000
`define STATS_RX_FCS_ERR 9'b000000001
`define MIN_FRAME_DATA_BYTES 60
 
 
module testbench;
 
// Frame data....
frame_typ frame0();
frame_typ frame1();
frame_typ frame2();
frame_typ frame3();
 
frame_typ tx_stimulus_working_frame();
frame_typ tx_monitor_working_frame();
frame_typ rx_stimulus_working_frame();
frame_typ rx_monitor_working_frame();
 
// Store the frame data etc....
initial
begin
// Frame 0...
frame0.data[0] = 32'h04030201;
frame0.data[1] = 32'h02020605;
frame0.data[2] = 32'h06050403;
frame0.data[3] = 32'h55AA2E00;
frame0.data[4] = 32'hAA55AA55;
frame0.data[5] = 32'h55AA55AA;
frame0.data[6] = 32'hAA55AA55;
frame0.data[7] = 32'h55AA55AA;
frame0.data[8] = 32'hAA55AA55;
frame0.data[9] = 32'h55AA55AA;
frame0.data[10] = 32'hAA55AA55;
frame0.data[11] = 32'h55AA55AA;
frame0.data[12] = 32'hAA55AA55;
frame0.data[13] = 32'h55AA55AA;
frame0.data[14] = 32'hAA55AA55;
frame0.data[15] = 32'h00000000;
frame0.data[16] = 32'h00000000;
frame0.data[17] = 32'h00000000;
frame0.data[18] = 32'h00000000;
frame0.data[19] = 32'h00000000;
frame0.data[20] = 32'h00000000;
frame0.data[21] = 32'h00000000;
frame0.data[22] = 32'h00000000;
frame0.data[23] = 32'h00000000;
frame0.data[24] = 32'h00000000;
frame0.data[25] = 32'h00000000;
frame0.data[26] = 32'h00000000;
frame0.data[27] = 32'h00000000;
frame0.data[28] = 32'h00000000;
frame0.data[29] = 32'h00000000;
frame0.data[30] = 32'h00000000;
frame0.data[31] = 32'h00000000;
frame0.ctrl[0] = 4'b1111;
frame0.ctrl[1] = 4'b1111;
frame0.ctrl[2] = 4'b1111;
frame0.ctrl[3] = 4'b1111;
frame0.ctrl[4] = 4'b1111;
frame0.ctrl[5] = 4'b1111;
frame0.ctrl[6] = 4'b1111;
frame0.ctrl[7] = 4'b1111;
frame0.ctrl[8] = 4'b1111;
frame0.ctrl[9] = 4'b1111;
frame0.ctrl[10] = 4'b1111;
frame0.ctrl[11] = 4'b1111;
frame0.ctrl[12] = 4'b1111;
frame0.ctrl[13] = 4'b1111;
frame0.ctrl[14] = 4'b1111;
frame0.ctrl[15] = 4'b0000;
frame0.ctrl[16] = 4'b0000;
frame0.ctrl[17] = 4'b0000;
frame0.ctrl[18] = 4'b0000;
frame0.ctrl[19] = 4'b0000;
frame0.ctrl[20] = 4'b0000;
frame0.ctrl[21] = 4'b0000;
frame0.ctrl[22] = 4'b0000;
frame0.ctrl[23] = 4'b0000;
frame0.ctrl[24] = 4'b0000;
frame0.ctrl[25] = 4'b0000;
frame0.ctrl[26] = 4'b0000;
frame0.ctrl[27] = 4'b0000;
frame0.ctrl[28] = 4'b0000;
frame0.ctrl[29] = 4'b0000;
frame0.ctrl[30] = 4'b0000;
frame0.ctrl[31] = 4'b0000;
frame0.crc = 32'h0D4820F6;
frame0.underrun = 1'b0;
// Frame 1
frame1.data[0] = 32'h03040506;
frame1.data[1] = 32'h05060102;
frame1.data[2] = 32'h02020304;
frame1.data[3] = 32'hEE110080;
frame1.data[4] = 32'h11EE11EE;
frame1.data[5] = 32'hEE11EE11;
frame1.data[6] = 32'h11EE11EE;
frame1.data[7] = 32'hEE11EE11;
frame1.data[8] = 32'h11EE11EE;
frame1.data[9] = 32'hEE11EE11;
frame1.data[10] = 32'h11EE11EE;
frame1.data[11] = 32'hEE11EE11;
frame1.data[12] = 32'h11EE11EE;
frame1.data[13] = 32'hEE11EE11;
frame1.data[14] = 32'h11EE11EE;
frame1.data[15] = 32'hEE11EE11;
frame1.data[16] = 32'h11EE11EE;
frame1.data[17] = 32'hEE11EE11;
frame1.data[18] = 32'h11EE11EE;
frame1.data[19] = 32'hEE11EE11;
frame1.data[20] = 32'h11EE11EE;
frame1.data[21] = 32'h0000EE11;
frame1.data[22] = 32'h00000000;
frame1.data[23] = 32'h00000000;
frame1.data[24] = 32'h00000000;
frame1.data[25] = 32'h00000000;
frame1.data[26] = 32'h00000000;
frame1.data[27] = 32'h00000000;
frame1.data[28] = 32'h00000000;
frame1.data[29] = 32'h00000000;
frame1.data[30] = 32'h00000000;
frame1.data[31] = 32'h00000000;
 
frame1.ctrl[0] = 4'b1111;
frame1.ctrl[1] = 4'b1111;
frame1.ctrl[2] = 4'b1111;
frame1.ctrl[3] = 4'b1111;
frame1.ctrl[4] = 4'b1111;
frame1.ctrl[5] = 4'b1111;
frame1.ctrl[6] = 4'b1111;
frame1.ctrl[7] = 4'b1111;
frame1.ctrl[8] = 4'b1111;
frame1.ctrl[9] = 4'b1111;
frame1.ctrl[10] = 4'b1111;
frame1.ctrl[11] = 4'b1111;
frame1.ctrl[12] = 4'b1111;
frame1.ctrl[13] = 4'b1111;
frame1.ctrl[14] = 4'b1111;
frame1.ctrl[15] = 4'b1111;
frame1.ctrl[16] = 4'b1111;
frame1.ctrl[17] = 4'b1111;
frame1.ctrl[18] = 4'b1111;
frame1.ctrl[19] = 4'b1111;
frame1.ctrl[20] = 4'b1111;
frame1.ctrl[21] = 4'b0011;
frame1.ctrl[22] = 4'b0000;
frame1.ctrl[23] = 4'b0000;
frame1.ctrl[24] = 4'b0000;
frame1.ctrl[25] = 4'b0000;
frame1.ctrl[26] = 4'b0000;
frame1.ctrl[27] = 4'b0000;
frame1.ctrl[28] = 4'b0000;
frame1.ctrl[29] = 4'b0000;
frame1.ctrl[30] = 4'b0000;
frame1.ctrl[31] = 4'b0000;
frame1.crc = 32'hDE13388C;
frame1.underrun = 1'b0;
// Frame 2
frame2.data[0] = 32'h04030201;
frame2.data[1] = 32'h02020605;
frame2.data[2] = 32'h06050403;
frame2.data[3] = 32'h55AA2E80;
frame2.data[4] = 32'hAA55AA55;
frame2.data[5] = 32'h55AA55AA;
frame2.data[6] = 32'hAA55AA55;
frame2.data[7] = 32'h55AA55AA;
frame2.data[8] = 32'hAA55AA55;
frame2.data[9] = 32'h55AA55AA;
frame2.data[10] = 32'hAA55AA55;
frame2.data[11] = 32'h55AA55AA;
frame2.data[12] = 32'hAA55AA55;
frame2.data[13] = 32'h55AA55AA;
frame2.data[14] = 32'hAA55AA55;
frame2.data[15] = 32'h55AA55AA;
frame2.data[16] = 32'hAA55AA55;
frame2.data[17] = 32'h55AA55AA;
frame2.data[18] = 32'hAA55AA55;
frame2.data[19] = 32'h55AA55AA;
frame2.data[20] = 32'h00000000;
frame2.data[21] = 32'h00000000;
frame2.data[22] = 32'h00000000;
frame2.data[23] = 32'h00000000;
frame2.data[24] = 32'h00000000;
frame2.data[25] = 32'h00000000;
frame2.data[26] = 32'h00000000;
frame2.data[27] = 32'h00000000;
frame2.data[28] = 32'h00000000;
frame2.data[29] = 32'h00000000;
frame2.data[30] = 32'h00000000;
frame2.data[31] = 32'h00000000;
 
frame2.ctrl[0] = 4'b1111;
frame2.ctrl[1] = 4'b1111;
frame2.ctrl[2] = 4'b1111;
frame2.ctrl[3] = 4'b1111;
frame2.ctrl[4] = 4'b1111;
frame2.ctrl[5] = 4'b1111;
frame2.ctrl[6] = 4'b1111;
frame2.ctrl[7] = 4'b1111;
frame2.ctrl[8] = 4'b1111;
frame2.ctrl[9] = 4'b1111;
frame2.ctrl[10] = 4'b1111;
frame2.ctrl[11] = 4'b1111;
frame2.ctrl[12] = 4'b1111;
frame2.ctrl[13] = 4'b1111;
frame2.ctrl[14] = 4'b1111;
frame2.ctrl[15] = 4'b1111;
frame2.ctrl[16] = 4'b1111;
frame2.ctrl[17] = 4'b1111;
frame2.ctrl[18] = 4'b1111;
frame2.ctrl[19] = 4'b1111;
frame2.ctrl[20] = 4'b0000;
frame2.ctrl[21] = 4'b0000;
frame2.ctrl[22] = 4'b0000;
frame2.ctrl[23] = 4'b0000;
frame2.ctrl[24] = 4'b0000;
frame2.ctrl[25] = 4'b0000;
frame2.ctrl[26] = 4'b0000;
frame2.ctrl[27] = 4'b0000;
frame2.ctrl[28] = 4'b0000;
frame2.ctrl[29] = 4'b0000;
frame2.ctrl[30] = 4'b0000;
frame2.ctrl[31] = 4'b0000;
frame2.crc = 32'h20C6B69D;
frame2.underrun = 1'b1;
// Frame 3
frame3.data[0] = 32'h03040506;
frame3.data[1] = 32'h05060102;
frame3.data[2] = 32'h02020304;
frame3.data[3] = 32'hEE111500;
frame3.data[4] = 32'h11EE11EE;
frame3.data[5] = 32'hEE11EE11;
frame3.data[6] = 64'h11EE11EE;
frame3.data[7] = 32'hEE11EE11;
frame3.data[8] = 32'h00EE11EE;
frame3.data[9] = 32'h00000000;
frame3.data[10] = 32'h00000000;
frame3.data[11] = 32'h00000000;
frame3.data[12] = 32'h00000000;
frame3.data[13] = 32'h00000000;
frame3.data[14] = 32'h00000000;
frame3.data[15] = 32'h00000000;
frame3.data[16] = 32'h00000000;
frame3.data[17] = 32'h00000000;
frame3.data[18] = 32'h00000000;
frame3.data[19] = 32'h00000000;
frame3.data[20] = 32'h00000000;
frame3.data[21] = 32'h00000000;
frame3.data[22] = 32'h00000000;
frame3.data[23] = 32'h00000000;
frame3.data[24] = 32'h00000000;
frame3.data[25] = 32'h00000000;
frame3.data[26] = 32'h00000000;
frame3.data[27] = 32'h00000000;
frame3.data[28] = 32'h00000000;
frame3.data[29] = 32'h00000000;
frame3.data[30] = 32'h00000000;
frame3.data[31] = 32'h00000000;
 
frame3.ctrl[0] = 4'b1111;
frame3.ctrl[1] = 4'b1111;
frame3.ctrl[2] = 4'b1111;
frame3.ctrl[3] = 4'b1111;
frame3.ctrl[4] = 4'b1111;
frame3.ctrl[5] = 4'b1111;
frame3.ctrl[6] = 4'b1111;
frame3.ctrl[7] = 4'b1111;
frame3.ctrl[8] = 4'b0111;
frame3.ctrl[9] = 4'b0000;
frame3.ctrl[10] = 4'b0000;
frame3.ctrl[11] = 4'b0000;
frame3.ctrl[12] = 4'b0000;
frame3.ctrl[13] = 4'b0000;
frame3.ctrl[14] = 4'b0000;
frame3.ctrl[15] = 4'b0000;
frame3.ctrl[16] = 4'b0000;
frame3.ctrl[17] = 4'b0000;
frame3.ctrl[18] = 4'b0000;
frame3.ctrl[19] = 4'b0000;
frame3.ctrl[20] = 4'b0000;
frame3.ctrl[21] = 4'b0000;
frame3.ctrl[22] = 4'b0000;
frame3.ctrl[23] = 4'b0000;
frame3.ctrl[24] = 4'b0000;
frame3.ctrl[25] = 4'b0000;
frame3.ctrl[26] = 4'b0000;
frame3.ctrl[27] = 4'b0000;
frame3.ctrl[28] = 4'b0000;
frame3.ctrl[29] = 4'b0000;
frame3.ctrl[30] = 4'b0000;
frame3.ctrl[31] = 4'b0000;
frame3.crc = 32'h6B734A56;
frame3.underrun = 1'b0;
end // initial
 
// DUT signals
reg reset;
 
//Client transmitter signals
//client receiver signals
wire [63:0] rx_data;
wire [7:0] rx_data_valid;
wire rx_good_frame;
wire rx_bad_frame;
wire rx_clk;
wire [28:0] rx_statistics_vector;
wire rx_statistics_valid;
wire [64:0] configuration_vector;
reg xgmii_rx_clk;
reg [31:0] xgmii_rxd;
reg [3:0] xgmii_rxc;
 
reg rx_monitor_finished;
wire simulation_finished;
 
/*---------------------------------------------------------------------------
-- wire up Device Under Test
---------------------------------------------------------------------------*/
rxReceiveEngine uut (
.rxclk_in(xgmii_rx_clk),
.reset_in(reset),
.rxd_in(xgmii_rxd),
.rxc_in(xgmii_rxc),
.rxStatRegPlus(rxStatRegPlus),
.cfgRxRegData_in(configuration_vector),
.rx_data(rx_data),
.rx_data_valid(rx_data_valid),
.rx_good_frame(rx_good_frame),
.rx_bad_frame(rx_bad_frame),
.rxCfgofRS(rxCfgofRS),
.rxTxLinkFault(rxTxLinkFault)
// .fcTxPauseData(),
// .fcTxPauseValid()
);
 
assign configuration_vector = {1'b0, 64'h058f010203040506};
 
/*---------------------------------------------------------------------------
-- Clock drivers
---------------------------------------------------------------------------*/
initial
begin
xgmii_rx_clk <= 0;
#1000;
forever
begin
#3200;
xgmii_rx_clk <= 1;
#3200;
xgmii_rx_clk <= 0;
end
end // initial begin
 
 
 
/* RX Stimulus process - insert frames into the PHY side of the
* receiver
*/
 
task rx_stimulus_send_column;
input [31:0] d;
input [ 3:0] c;
begin
@(posedge xgmii_rx_clk or negedge xgmii_rx_clk);
#1600;
xgmii_rxd <= d;
xgmii_rxc <= c;
end
endtask // rx_stimulus_send_column
 
task rx_stimulus_send_idle;
begin
rx_stimulus_send_column(32'h07070707,4'b1111);
end
endtask // rx_stimulus_send_idle
task rx_stimulus_send_frame;
input `FRAME_TYP frame;
integer column_index, lane_index, byte_count, I, J;
reg [31:0] scratch_column_data, current_column_data;
reg [ 3:0] scratch_column_ctrl, current_column_ctrl;
reg [ 7:0] code_temp;
begin
rx_stimulus_working_frame.frombits(frame);
column_index = 0;
lane_index = 0;
byte_count = 0;
// send preamble
rx_stimulus_send_column(32'h555555FB, 4'b0001);
rx_stimulus_send_column(32'hD5555555, 4'b0000);
// send complete columns
// for(I=0; I<16;I=I+1) begin
// column_index = 0;
while (rx_stimulus_working_frame.ctrl[column_index] === 4'b1111)
begin
rx_stimulus_send_column(rx_stimulus_working_frame.data[column_index],
4'b0000);
column_index = column_index + 1;
byte_count = byte_count + 4;
end
// end
current_column_data = rx_stimulus_working_frame.data[column_index];//data which is not 64 bits
current_column_ctrl = rx_stimulus_working_frame.ctrl[column_index];
while (current_column_ctrl[lane_index]) //send out data which is not 64 bits
begin
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] =
current_column_data[lane_index*8+J];
scratch_column_ctrl[lane_index] = 0;
lane_index = lane_index + 1;
byte_count = byte_count + 1;
end
// send any padding required
while (byte_count < `MIN_FRAME_DATA_BYTES)
begin
if (lane_index == 4)
begin
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
lane_index = 0;
end
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] = 0;
scratch_column_ctrl[lane_index] = 0;
lane_index = lane_index + 1;
byte_count = byte_count + 1;
end // while (byte_count < `MIN_FRAME_DATA_BYTES)
// send the CRC
for (I = 3; I >= 0; I = I - 1)
begin
if (lane_index == 4)
begin
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
lane_index = 0;
end
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] =
rx_stimulus_working_frame.crc[I*8+J];
scratch_column_ctrl = 0;
lane_index = lane_index + 1;
end // for (I = 3; I >= 0; I = I - 1)
// send the terminate/error column
if (lane_index == 4)
begin
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
lane_index = 0;
end
// send an /E/ if underrun, /T/ if not
code_temp = rx_stimulus_working_frame.underrun ? 8'hFE : 8'hFD;
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] = code_temp[J];
scratch_column_ctrl[lane_index] = 1;
 
lane_index = lane_index + 1;
while (lane_index < 4)
begin
code_temp = 8'h07;
for (J = 0; J < 8; J = J + 1)
scratch_column_data[lane_index*8+J] = code_temp[J];
scratch_column_ctrl[lane_index] = 1;
lane_index = lane_index + 1;
end
rx_stimulus_send_column(scratch_column_data,
scratch_column_ctrl);
$display("Receiver: frame inserted into PHY interface");
end
endtask // rx_stimulus_send_frame
 
initial
begin : p_rx_stimulus
integer I;
rx_stimulus_send_idle;
rx_stimulus_send_idle;
for (I = 0; I < 100; I = I + 1)
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame0.tobits(0));
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame1.tobits(0));
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame2.tobits(0));
rx_stimulus_send_idle;
rx_stimulus_send_idle;
rx_stimulus_send_frame(frame3.tobits(0));
while (1)
rx_stimulus_send_idle;
end // block: p_rx_stimulus
 
 
/* rx monitor - checks that the receiver extracts the information
* inserted into the PHY interface
*/
task wait_on_rx_clk;
begin
@(posedge rx_clk);
#6399;
end
endtask // wait_on_rx_clk
task rx_monitor_check_frame;
input `FRAME_TYP frame;
integer column_count, I, J;
reg [31:0] current_column_data;
reg good_frame_flagged;
reg bad_frame_flagged;
begin
rx_monitor_working_frame.frombits(frame);
column_count = 0;
// wait for the first real column of data
while (rx_data_valid === 8'b00000000)
wait_on_rx_clk;
// frame has started, get columns of frame
while (rx_data_valid !== 8'b00000000)
begin
// only check contents of good frames
if (!rx_monitor_working_frame.underrun)
begin
if (rx_data_valid !== { rx_monitor_working_frame.ctrl[column_count+1],
rx_monitor_working_frame.ctrl[column_count] })
$display("ERROR: Receiver fail: RX_DATA_VALID incorrect");
current_column_data = rx_monitor_working_frame.data[column_count];
for (I = 0; I < 4; I = I + 1)
if (rx_data_valid[I])
for (J = 0; J < 8; J = J + 1)
if (rx_data[I*8+J] !== current_column_data[I*8+J])
$display("ERROR: Receiver fail : RX_DATA incorrect");
current_column_data = rx_monitor_working_frame.data[column_count+1];
for (I = 4; I < 8; I = I + 1)
if (rx_data_valid[I])
for (J = 0; J < 8; J = J + 1)
if (rx_data[I*8+J] !== current_column_data[(I-4)*8+J])
$display("ERROR: Receiver fail : RX_DATA incorrect");
end // if (!rx_monitor_working_frame.underrun)
 
good_frame_flagged = rx_good_frame;
bad_frame_flagged = rx_bad_frame;
column_count = column_count + 2;
wait_on_rx_clk;
end // while (RX_DATA_VALID != 8'b00000000)
// check whether the frame has been flagged at the right time
while (!good_frame_flagged && !bad_frame_flagged)
begin
good_frame_flagged = rx_good_frame;
bad_frame_flagged = rx_bad_frame;
if (rx_data_valid !== 8'b00000000)
$display("ERROR: Receiver fail: New frame received before good/bad flag from previous frame");
wait_on_rx_clk;
end
if (rx_monitor_working_frame.underrun)
begin
if (good_frame_flagged)
$display("ERROR: Receive Fail: bad frame flagged as good");
end
else
begin
if (bad_frame_flagged)
$display("ERROR: Receive Fail: good frame flagged as bad");
end
$display("Receiver: Frame extracted from client interface");
end
endtask // rx_monitor_check_frame
 
/*---------------------------------------------------------------------------
-- RX Monitor process. This process checks the data coming out of the
receiver
-- to make sure that it matches that inserted into the transmitter.
---------------------------------------------------------------------------*/
initial
begin : p_rx_monitor
rx_monitor_finished = 0;
// first, get synced up with the RX clock
@(negedge reset)
wait_on_rx_clk;
 
rx_monitor_check_frame(frame0.tobits(0));
rx_monitor_check_frame(frame1.tobits(0));
rx_monitor_check_frame(frame2.tobits(0));
rx_monitor_check_frame(frame3.tobits(0));
rx_monitor_finished = 1;
end // block: p_rx_monitor
 
 
 
 
// reset process
initial
begin
$display("Resetting the core...");
reset <= 1;
#200000;
reset <= 0;
end
 
// Simulation control
assign simulation_finished = rx_monitor_finished;
 
initial
begin
fork: sim_in_progress
@(posedge simulation_finished) disable sim_in_progress;
#10000000 disable sim_in_progress;
join
if (simulation_finished)
$display("** failure: Simulation Stopped");
else
$display("** failure: Testbench timed out");
$stop;
end // initial begin
 
endmodule
 

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