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    /ethmac10g/tags/V10/rtl
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Rev 40 → Rev 72

/verilog/tx_engine/ack_counter.v
0,0 → 1,89
module ack_counter (
clock , // 156 MHz clock
reset , // active high, asynchronous Reset input
ready,
tx_start , // Active high tx_start signal for counter
max_count, //16 bit reg for the maximum count to generate the ack signal
tx_ack // Active high signal
);
 
// Ports declaration
input clock;
input reset;
input ready;
input tx_start;
input [15:0] max_count;
 
output tx_ack;
 
// Wire connections
//Input
wire clock;
wire reset;
wire ready;
wire tx_start;
wire [15:0] max_count;
 
//Output
reg tx_ack;
 
 
 
//Internal wires
reg start_count;
reg start_count_del;
reg [15:0] counter;
 
 
always @ (reset or tx_start or counter or max_count)
begin
 
if (reset) begin
start_count <= 0;
end
 
else if (tx_start) begin
start_count <= 1;
end
 
else if ((counter == max_count) & !ready) begin //& !ready
start_count <= 0;
end
 
end
 
 
always @ (posedge clock or posedge reset)
begin
 
if (reset) begin
counter <= 0;
end
else if (counter == max_count) begin
counter <= 0;
end
 
else if (start_count) begin
counter <= counter + 1;
end
 
end
 
 
always @ (posedge clock or posedge reset)
begin
 
if (reset) begin
start_count_del <= 0;
tx_ack <= 0;
end
else begin
start_count_del <= start_count;
tx_ack <= ~start_count & start_count_del;
end
 
end
 
endmodule // End of Module
 
/verilog/tx_engine/byte_counter.v
0,0 → 1,31
module byte_count_module(CLK, RESET, START, BYTE_COUNTER);
 
// Ports declaration
input CLK;
input RESET;
input START;
 
 
 
output [15:0] BYTE_COUNTER;
 
reg [15:0] BYTE_COUNTER;
reg [15:0] counter;
 
always @(posedge CLK or posedge RESET)
begin
if (RESET == 1) begin
counter = 16'h0000;
end
 
// the ack is delayed which starts the counter
else if (START == 1) begin
counter = counter + 8;
end
 
BYTE_COUNTER = counter;
end
 
 
endmodule // End of Module
 
/verilog/tx_engine/TransmitTop.v
0,0 → 1,1410
/////////////////////////////////////////////////////////////////////////////
//
// Name of module
// 23/1/06 - So far Mentor Precision indicates the current system runs as 101 MHz.
//
/////////////////////////////////////////////////////////////////////////////
module TRANSMIT_TOP(
TX_DATA,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
 
 
/////////////////////////////////////////////////////////////////////////////
//
// Input and output ports definitions
//
/////////////////////////////////////////////////////////////////////////////
 
//Input from user logic
input [63:0] TX_DATA;
input [7:0] TX_DATA_VALID; // To accept the data valid to be available
input TX_CLK;
input RESET;
input TX_START; // This signify the first frame of data
input TX_UNDERRUN; // this will cause an error to be injected into the data
input [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
 
//input to transmit fault signals
input RXTXLINKFAULT;
input LOCALLINKFAULT;
 
input [31:0] TX_CFG_REG_VALUE;
input TX_CFG_REG_VALID;
 
//output to stat register
output TX_STATS_VALID;
output [24:0] TXSTATREGPLUS; // a pulse for each reg for stats
 
//output to user logic
output TX_ACK; //Generated by a counter
 
//output to XGMII
output [63:0] TXD;
output [7:0] TXC;
 
//output [15:0] BYTE_COUNTER_OUT;
 
//Pause inputs
//Transmit pause frames
input [15:0] FC_TRANS_PAUSEDATA; //pause frame data
input FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
 
//apply pause timing
input [15:0] FC_TX_PAUSEDATA;
input FC_TX_PAUSEVALID;
 
 
 
/////////////////////////////////////////////////////////////////////////////
//
// Definitions and parameters
//
/////////////////////////////////////////////////////////////////////////////
 
//possibility to put this in a package.
 
//opcode definitions
parameter PAUSE_OPCODE = 16'b1000100000001000; //8808
parameter VLAN_OPCODE = 16'b1000000100000000; //8100
 
//frame size definitions
parameter VLAN_FRAME_SIZE = 16'b0000010111110010;//1522 bytes
parameter JUMBO_FRAME_SIZE = 16'b0010001100101000;//9000 bytes
parameter NORMAL_FRAME_SIZE = 16'b0000010111101110;//1518 bytes
parameter MIN_FRAME_SIZE = 16'b0000000000111100; //60 bytes
 
 
//Frame definition
parameter IDLE_FRAME = 8'b00000111; //only six preambles as the first preamble is converted into a start flag
parameter IDLE_FRAME_8BYTES = 64'b0000011100000111000001110000011100000111000001110000011100000111;
parameter START_SEQ = 64'b1010101110101010101010101010101010101010101010101010101011111011;
parameter LOCAL_FAULT_SEQ = 64'b0000000100000000000000000000000000000001000000000000000000000000;
parameter REMOTE_FAULT_SEQ = 64'b0000001000000000000000000000000000000010000000000000000000000000;
parameter START_FRAME = 8'b11111011; //only valid in frame 0
parameter TERMINATE_FRAME = 8'b11111101;
parameter SFD_FRAME = 8'b10101011;
parameter PREAMBLE_FRAME = 8'b10101010;
parameter ERROR_FRAME = 8'b11111110;
 
 
parameter SOURCE_ADDR = 48'h010101010101;
parameter DEST_ADDR = 48'h101010101010;
 
parameter PAUSE_FRAME_LENGTH = 8'h02;
 
 
//need a parameter for min frame gap.
 
//Link fault signalling
// send lane 0
 
 
/////////////////////////////////////////////////////////////////////////////
//
// Registers and wires
//
/////////////////////////////////////////////////////////////////////////////
 
 
 
 
wire TX_ACK;
 
reg [24:0] TXSTATREGPLUS;
 
reg TX_STATS_VALID;
 
reg FRAME_START;
 
wire reset_int;
 
reg [15:0] DELAY_ACK;
 
reg [7:0] TX_DATA_VALID_REG;
reg [7:0] TX_DATA_VALID_DEL1;
reg [7:0] TX_DATA_VALID_DEL2;
reg [7:0] TX_DATA_VALID_DEL3;
reg [7:0] TX_DATA_VALID_DEL4;
reg [7:0] TX_DATA_VALID_DEL5;
reg [7:0] TX_DATA_VALID_DEL6;
reg [7:0] TX_DATA_VALID_DEL7;
reg [7:0] TX_DATA_VALID_DEL8;
reg [7:0] TX_DATA_VALID_DEL9;
reg [7:0] TX_DATA_VALID_DEL10;
reg [7:0] TX_DATA_VALID_DEL11;
reg [7:0] TX_DATA_VALID_DEL12;
reg [7:0] TX_DATA_VALID_DEL13;
reg [7:0] TX_DATA_VALID_DEL14;
reg [7:0] TX_DATA_VALID_DEL15;
 
reg [63:0] TX_DATA_DEL1;
reg [63:0] TX_DATA_DEL2;
reg [63:0] TX_DATA_DEL3;
reg [63:0] TX_DATA_DEL4;
reg [63:0] TX_DATA_DEL5;
reg [63:0] TX_DATA_DEL6;
reg [63:0] TX_DATA_DEL7;
reg [63:0] TX_DATA_DEL8;
reg [63:0] TX_DATA_DEL9;
reg [63:0] TX_DATA_DEL10;
reg [63:0] TX_DATA_DEL11;
reg [63:0] TX_DATA_DEL12;
reg [63:0] TX_DATA_DEL13;
reg [63:0] TX_DATA_DEL14;
reg [63:0] TX_DATA_DEL15;
 
reg [7:0] OVERFLOW_VALID;
reg [63:0] OVERFLOW_DATA;
 
reg [63:0] TXD;
reg [7:0] TXC;
 
reg [63:0] TX_DATA_REG, TX_DATA_VALID_DELAY;
 
wire [31:0] CRC_32_64;
 
wire [15:0] BYTE_COUNTER;
 
reg frame_start_del;
 
reg transmit_pause_frame_del, transmit_pause_frame_del2, transmit_pause_frame, append_start_pause, append_start_pause_del , transmit_pause_frame_valid, reset_err_pause, load_CRC8, transmit_pause_frame_del3;
 
reg [7:0] tx_data_int;
reg start_CRC8, START_CRC8_DEL;
reg append_end_frame;
 
 
reg insert_error;
 
reg [7:0] store_tx_data_valid;
reg [63:0] store_tx_data;
reg [31:0] store_CRC64;
reg [7:0] store_valid;
reg load_final_CRC;
 
reg [15:0] final_byte_count, byte_count_reg;
 
wire [31:0] CRC_OUT;
 
reg [9:0] append_reg;
 
 
reg [15:0] length_register;
 
reg tx_undderrun_int;
 
reg [15:0] MAX_FRAME_SIZE;
 
reg vlan_enabled_int;
reg jumbo_enabled_int;
reg tx_enabled_int;
reg fcs_enabled_int;
reg reset_tx_int;
reg read_ifg_int;
 
reg apply_pause_delay;
reg [15:0] store_pause_frame;
 
reg [63:0] TXD_PAUSE_DEL0;
reg [63:0] TXD_PAUSE_DEL1;
reg [63:0] TXD_PAUSE_DEL2;
 
reg [7:0] TXC_PAUSE_DEL0;
reg [7:0] TXC_PAUSE_DEL1;
reg [7:0] TXC_PAUSE_DEL2;
 
reg PAUSEVAL_DEL;
reg PAUSEVAL_DEL1;
reg PAUSEVAL_DEL2;
wire RESET_ERR_PAUSE;
 
reg set_pause_stats;
reg [15:0] store_transmit_pause_value;
reg [3:0] pause_frame_counter;
reg [63:0] shift_pause_data;
 
reg [7:0] shift_pause_valid;
reg [7:0] shift_pause_valid_del;
 
reg [14:0] byte_count_stat;
 
reg [24:0] txstatplus_int;
 
 
/////////////////////////////////////////////////////////////////////////////
//
// Start of code
//
/////////////////////////////////////////////////////////////////////////////
 
 
 
 
//TODO
 
//RX side. need to be able to receive data and calculate the CRC switching between 64 and 8 bit datapath.
//Therefore, the data need to be counted correctly.
//ERROR checking module or process will be needed. This will check if frame is correct length.
//Need to be able to remove redundant frames or columns and also padding. The error module will
//also check the tx_underrun signal as well.
 
//need to be able to cut-off bytes.
 
//Need to add the link fault signalling and config registers.
 
 
//TX side. need to be able to insert the CRC with the data.
//need to define the first column of txd which is START 6 PRE and SFD.
//need to be able invert data_valid for txc.
//need to be able to transmit IDLEs.
 
 
//Format of output
//IDLE 07, START FB TERMINATE FD SFD 10101011 PREAMBLE 10101010 ERROR FE.
 
//IDLE START PREAMBLE SFD DA SA L/T DATA TERMINATE IDLE
 
 
 
 
 
 
 
 
/////////////////////////////////////////////////////////////////////////////
//
// Ack counter
//
/////////////////////////////////////////////////////////////////////////////
 
 
//Ack counter. need to be able to load the frame length, pause frame inter frame delay into the ack counter
// as this will delay the ack signal. The ack signal will initiate the rest of the data transmission from the
// user logic.
 
//need to stop the ack signal from transmitting when a PAUSE frame is transmitting
 
// Connect DUT to test bench
ack_counter U_ACK_CNT(
.clock(TX_CLK),
.reset(reset_int | reset_tx_int),
.ready(FRAME_START | transmit_pause_frame),
.tx_start(TX_START),
.max_count(DELAY_ACK),
.tx_ack(TX_ACK)
);
 
//CRC for 64 bit data
//This seem to be one of the culprit for the timing violation
CRC32_D64 U_CRC64(
.DATA_IN(TX_DATA_REG), //need to swap between pause data
.CLK(TX_CLK),
.RESET(reset_int | TX_ACK | append_start_pause),
.START(frame_start_del | transmit_pause_frame_valid),
.CRC_OUT(CRC_32_64) //need to switch to output some how for a pause frame
);
 
 
//CRC for 8 bit data
CRC32_D8 U_CRC8(
.DATA_IN(tx_data_int), //8bit data
.CLK(TX_CLK),
.RESET(reset_int),
.START(start_CRC8), //this signal will be use to start
.LOAD(load_CRC8), //use this to load first
.CRC_IN(CRC_32_64),
.CRC_OUT(CRC_OUT)
);
 
 
//The start signal need to be high for the count
//This seem to be one of the culprit for the timing violation
byte_count_module U_byte_count_module(
.CLK(TX_CLK),
.RESET(reset_int | TX_ACK),
.START(frame_start_del & FRAME_START),
.BYTE_COUNTER(BYTE_COUNTER)
);
 
 
 
/////////////////////////////////////////////////////////////////////////////
//
// PAUSE FRAME
//
/////////////////////////////////////////////////////////////////////////////
 
always @(posedge TX_CLK)
begin
PAUSEVAL_DEL <= FC_TRANS_PAUSEVAL;
PAUSEVAL_DEL1 <= PAUSEVAL_DEL;
PAUSEVAL_DEL2 <= PAUSEVAL_DEL1;
end
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
transmit_pause_frame <= 0;
end
else if (PAUSEVAL_DEL2) begin
transmit_pause_frame <= 1;
end
else if (pause_frame_counter == 8) begin
transmit_pause_frame <= 0;
end
end
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
set_pause_stats <= 0;
end
else if (PAUSEVAL_DEL2) begin
set_pause_stats <= 1;
end
else if (append_end_frame) begin
set_pause_stats <= 0;
end
end
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
TXD_PAUSE_DEL0 <= 0;
TXD_PAUSE_DEL1 <= 0;
TXD_PAUSE_DEL2 <= 0;
TXC_PAUSE_DEL0 <= 0;
TXC_PAUSE_DEL1 <= 0;
TXC_PAUSE_DEL2 <= 0;
 
store_transmit_pause_value <= 0;
end
else if (FC_TRANS_PAUSEVAL) begin
store_transmit_pause_value <= FC_TRANS_PAUSEDATA;
TXD_PAUSE_DEL1 <= {DEST_ADDR, SOURCE_ADDR[47:32]};
TXD_PAUSE_DEL2 <= {SOURCE_ADDR[31:0], PAUSE_FRAME_LENGTH, PAUSE_OPCODE, FC_TRANS_PAUSEDATA};
 
TXC_PAUSE_DEL1 <= 8'hff;
TXC_PAUSE_DEL2 <= 8'hff;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
pause_frame_counter <= 0;
end
else if (transmit_pause_frame & !FRAME_START) begin
pause_frame_counter <= pause_frame_counter + 1;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
shift_pause_data <= 0;
shift_pause_valid_del <= 0;
shift_pause_valid <= 0;
end
else if (transmit_pause_frame & !FRAME_START) begin
if (pause_frame_counter == 0) begin
shift_pause_data <= TXD_PAUSE_DEL1;
end
else if (pause_frame_counter == 1) begin
shift_pause_data <= TXD_PAUSE_DEL2;
end
else begin
shift_pause_data <= 0;
end
if (pause_frame_counter == 7) begin
shift_pause_valid <= 8'h0f;
end
else if (pause_frame_counter < 7) begin
shift_pause_valid <= 8'hff;
end
else begin
shift_pause_valid <= 0;
end
shift_pause_valid_del <= shift_pause_valid;
end
else begin
shift_pause_data <= 0;
shift_pause_valid <= 0;
shift_pause_valid_del <= shift_pause_valid;
end
end
 
 
 
 
always @(posedge reset_int or posedge TX_CLK)
begin
if (reset_int) begin
FRAME_START <= 0;
end
else if (TX_ACK) begin
FRAME_START <= 1;
end
else if ((TX_DATA_VALID_REG != 8'hff) & (BYTE_COUNTER != 0)) begin
FRAME_START <= 0;
end
end
 
 
 
 
assign reset_int = RESET;
 
 
//TXSTATREGPLUS[24:0]
//24 pause_frame transmitted - count when pause flag is set
//23 to 20 bytes valid
//19 vlan frame - asserted if previous frame was a VLAN - just check if VLAN been set
//18 to 5 last frame length count in bytes stick to 16383 when jumbo frame is greater than value - just load the byte count
//4 if last frame has control type code 88-08 in the length type field - pause frame - check if pause flag is set
//3 underrun frame - check if underrun is set
//2 multicast frame - 01-80-C2-00-00-01 use for pause frame
//1 broadcast frame - al ones
//0 sucessful frame - check if error occurred -use insert error flag
 
 
//TX_STATS_VALID - need to be driving after a frame transmission - use load_overflow signal
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
txstatplus_int <= 0;
end
else if (load_final_CRC) begin
if (insert_error) begin
txstatplus_int[3] <= 1;
end
if (set_pause_stats) begin
txstatplus_int[24] <= 1;
txstatplus_int[4] <= 1;
txstatplus_int[2] <= 1;
txstatplus_int[1] <= 1;
txstatplus_int[18:5] <= 512;
end
if (vlan_enabled_int) begin
txstatplus_int[19] <= 1;
end
else begin
if (final_byte_count[15] == 1) begin
txstatplus_int[18:5] <= 16383;
end
else begin
txstatplus_int[18:5] <= byte_count_stat;
end
end
end
else begin
txstatplus_int <= 0;
end
 
TXSTATREGPLUS <= txstatplus_int;
TX_STATS_VALID <= append_end_frame;
end
 
 
 
 
//input [31:0] TX_CFG_REG_VALUE;
//24:0 reserved
//25 default to 0 - min frame - 1 adjust frame delay by reading inter-frame gap delay reg - DELAY_ACK signal
//26 WAN - not used
//27 VLAN enable default to 0, 1 enabled
//28 default to 1 - transmitter enbaled, 0 - transmitter disabled - possibly used to reset
//29 default to 0 FCS enabled, 1 FCS disabled
//30 default to 0, 1 - Jumbo frame enabled
//31 deafult to 0, 1 - reset transmitter
 
//input TX_CFG_REG_VALID;
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
vlan_enabled_int <= 0;
jumbo_enabled_int <= 0;
tx_enabled_int <= 0;
fcs_enabled_int <= 1;
reset_tx_int <= 0;
read_ifg_int <= 0;
end
else if (TX_CFG_REG_VALID) begin
vlan_enabled_int <= TX_CFG_REG_VALUE[27];
jumbo_enabled_int <= TX_CFG_REG_VALUE[30];
tx_enabled_int <= TX_CFG_REG_VALUE[28]; // Stop ack from generated, hold reset
fcs_enabled_int <= TX_CFG_REG_VALUE[29];
reset_tx_int <= TX_CFG_REG_VALUE[31];
read_ifg_int <= TX_CFG_REG_VALUE[25];
end
end
 
 
//Load the delay value for the acknowledge signal
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
DELAY_ACK <= 16'h0001;
end
else if (apply_pause_delay) begin
DELAY_ACK <= store_pause_frame;
end
else if (read_ifg_int) begin
DELAY_ACK <= TX_IFG_DELAY;
end
end
 
 
//Need to expand to be setup by the config register
//1514 with out FCS added, 1518 when FCS is added
//1518 without FCS added, 1522 when FCS is added
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
MAX_FRAME_SIZE <= 1514;
end
else begin
if (vlan_enabled_int) begin
if (fcs_enabled_int) begin
MAX_FRAME_SIZE <= 1522;
end
else begin
MAX_FRAME_SIZE <= 1518;
end
end
else if (jumbo_enabled_int) begin
if (fcs_enabled_int) begin
MAX_FRAME_SIZE <= 1518;
end
else begin
MAX_FRAME_SIZE <= 1514;
end
end
else begin
if (fcs_enabled_int) begin
MAX_FRAME_SIZE <= 1518;
end
else begin
MAX_FRAME_SIZE <= 1514;
end
end
end
end
 
 
 
 
always @(posedge TX_CLK)
begin
if (reset_int) begin
tx_undderrun_int <= 0;
end
else if (append_end_frame)
tx_undderrun_int <= 0;
end
else if (TX_UNDERRUN == 1) begin
tx_undderrun_int <= 1;
end
end
 
//Indicate an error
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
insert_error <= 0;
end
else if (append_end_frame | reset_err_pause) begin
insert_error <= 0;
end
else if (load_CRC8) begin
if (tx_undderrun_int == 1) begin
insert_error <= 1;
end
else begin
if (length_register == final_byte_count) begin
if (final_byte_count <= MAX_FRAME_SIZE) begin
insert_error <= 0;
end
else begin
insert_error <= 1;
end
end
else if (length_register < MIN_FRAME_SIZE) begin
if (final_byte_count == 64) begin
insert_error <= 0;
end
else begin
insert_error <= 1;
end
end
else begin
insert_error <= 1;
end
end
end
end
 
 
//use for delaying the ack signal when pause is required
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
apply_pause_delay <= 0;
store_pause_frame <= 0;
end
else if (TX_ACK) begin
apply_pause_delay <= 0;
store_pause_frame <= 0;
end
else if (FC_TX_PAUSEVALID) begin
apply_pause_delay <= 1;
store_pause_frame <= FC_TX_PAUSEDATA;
end
end
 
 
 
 
always @(posedge TX_CLK)
begin
if (TX_START) begin
TX_DATA_VALID_DELAY <= IDLE_FRAME_8BYTES;
end
else begin
TX_DATA_VALID_DELAY <= TX_DATA;
end
end
 
 
 
//Shift valid into the system and also ensuring min frame is achieved
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
TX_DATA_VALID_REG <= 0;
end
else if (FRAME_START) begin
if (BYTE_COUNTER < 48) begin
TX_DATA_VALID_REG <= 8'b11111111;
end
else if (BYTE_COUNTER == 48) begin
if (TX_START) begin
TX_DATA_VALID_REG <= 8'b00001111;
end
else begin
TX_DATA_VALID_REG <= 8'b00001111 | TX_DATA_VALID;
end
end
else begin
if (TX_START) begin
TX_DATA_VALID_REG <= 0;
end
else begin
TX_DATA_VALID_REG <= TX_DATA_VALID;
end
end
end
else if (transmit_pause_frame_del) begin
shift_pause_valid_del <= shift_pause_valid;
TX_DATA_VALID_REG <= shift_pause_valid_del;
end
else begin
TX_DATA_VALID_REG <= 0;
end
end
 
 
//Shifting data to the system. Also ensuring min frame is achieved
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
TX_DATA_REG <= IDLE_FRAME_8BYTES;
end
else if (FRAME_START) begin
if (BYTE_COUNTER < 56) begin
case (TX_DATA_VALID_REG)
8'b00000000 : begin
TX_DATA_REG <= TX_DATA_VALID_DELAY;
end
8'b00000001 : begin
TX_DATA_REG <= {56'h00000000000000, TX_DATA_VALID_DELAY[7:0]};
end
8'b00000011 : begin
TX_DATA_REG <= {48'h000000000000, TX_DATA_VALID_DELAY[15:0]};
end
8'b00000111 : begin
TX_DATA_REG <= {40'h0000000000, TX_DATA_VALID_DELAY[23:0]};
end
8'b00001111 : begin
TX_DATA_REG <= {32'h00000000, TX_DATA_VALID_DELAY[31:0]};
end
8'b00011111 : begin
TX_DATA_REG <= {24'h000000, TX_DATA_VALID_DELAY[39:0]};
end
8'b00111111 : begin
TX_DATA_REG <= {16'h0000, TX_DATA_VALID_DELAY[47:0]};
end
8'b01111111 : begin
TX_DATA_REG <= {8'h00, TX_DATA_VALID_DELAY[55:0]};
end
8'b11111111 : begin
TX_DATA_REG <= TX_DATA_VALID_DELAY;
end
endcase
end
else begin
TX_DATA_REG <= TX_DATA_VALID_DELAY;
end
end
else if (transmit_pause_frame_valid) begin
TX_DATA_REG <= shift_pause_data;
end
else begin
if (TX_ACK | append_start_pause) begin
TX_DATA_REG <= START_SEQ;
end
else begin
TX_DATA_REG <= IDLE_FRAME_8BYTES;
end
end
 
end
 
 
 
 
 
 
 
//Use for shifting data to CRC and loading start value for CRC
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
frame_start_del <= 0;
transmit_pause_frame_del <= 0;
transmit_pause_frame_del2 <= 0;
transmit_pause_frame_del3 <= 0;
append_start_pause <= 0;
append_start_pause_del <= 0;
transmit_pause_frame_valid <= 0;
reset_err_pause <= 0;
load_CRC8 <= 0;
end
else begin
frame_start_del <= FRAME_START;
transmit_pause_frame_del <= transmit_pause_frame;
transmit_pause_frame_del2 <= transmit_pause_frame_del;
transmit_pause_frame_del3 <= transmit_pause_frame_del2;
append_start_pause <= (!transmit_pause_frame_del & transmit_pause_frame);
append_start_pause_del <= append_start_pause;
transmit_pause_frame_valid <= (transmit_pause_frame_del & transmit_pause_frame);
reset_err_pause <= (transmit_pause_frame_del & !transmit_pause_frame);
load_CRC8 <= (frame_start_del & !FRAME_START) | (transmit_pause_frame_del3 & !transmit_pause_frame_del2);
end
end
 
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
TX_DATA_VALID_DEL1 <= 0;
TX_DATA_VALID_DEL2 <= 0;
TX_DATA_VALID_DEL3 <= 0;
TX_DATA_VALID_DEL4 <= 0;
TX_DATA_VALID_DEL5 <= 0;
TX_DATA_VALID_DEL6 <= 0;
TX_DATA_VALID_DEL7 <= 0;
TX_DATA_VALID_DEL8 <= 0;
TX_DATA_VALID_DEL9 <= 0;
TX_DATA_VALID_DEL10 <= 0;
TX_DATA_VALID_DEL11 <= 0;
TX_DATA_VALID_DEL12 <= 0;
TX_DATA_VALID_DEL13 <= 0;
TX_DATA_VALID_DEL14 <= 0;
TX_DATA_VALID_DEL15 <= 0;
OVERFLOW_VALID <= 0;
end
else begin
TX_DATA_VALID_DEL1 <= TX_DATA_VALID_REG;
TX_DATA_VALID_DEL2 <= TX_DATA_VALID_DEL1;
TX_DATA_VALID_DEL3 <= TX_DATA_VALID_DEL2;
TX_DATA_VALID_DEL4 <= TX_DATA_VALID_DEL3;
TX_DATA_VALID_DEL5 <= TX_DATA_VALID_DEL4;
TX_DATA_VALID_DEL6 <= TX_DATA_VALID_DEL5;
TX_DATA_VALID_DEL7 <= TX_DATA_VALID_DEL6;
TX_DATA_VALID_DEL8 <= TX_DATA_VALID_DEL7;
TX_DATA_VALID_DEL9 <= TX_DATA_VALID_DEL8;
TX_DATA_VALID_DEL10 <= TX_DATA_VALID_DEL9;
TX_DATA_VALID_DEL11 <= TX_DATA_VALID_DEL10;
TX_DATA_VALID_DEL12 <= TX_DATA_VALID_DEL11;
TX_DATA_VALID_DEL13 <= TX_DATA_VALID_DEL12;
TX_DATA_VALID_DEL14 <= TX_DATA_VALID_DEL13;
 
if (load_final_CRC) begin
case (TX_DATA_VALID_DEL13)
8'b00000000 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b00001111;
end
else begin
TX_DATA_VALID_DEL14 <= 8'b00001111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00000001 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b00011111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00000011 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b00111111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00000111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b01111111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00001111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
end
 
OVERFLOW_VALID <= 8'b00000000;
end
8'b00011111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000001;
end
else begin
OVERFLOW_VALID <= 8'b00000000;
end
end
8'b00111111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000011;
end
else begin
OVERFLOW_VALID <= 8'b00000000;
end
end
8'b01111111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000111;
end
else begin
OVERFLOW_VALID <= 8'b00000000;
end
end
endcase
end
 
else if (append_end_frame) begin
TX_DATA_VALID_DEL14 <= OVERFLOW_VALID;
end
TX_DATA_VALID_DEL15 <= TX_DATA_VALID_DEL14;
TXC <= TX_DATA_VALID_DEL15;
end
end
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
TX_DATA_DEL1 <= 0;
TX_DATA_DEL2 <= 0;
TX_DATA_DEL3 <= 0;
TX_DATA_DEL4 <= 0;
TX_DATA_DEL5 <= 0;
TX_DATA_DEL6 <= 0;
TX_DATA_DEL7 <= 0;
TX_DATA_DEL8 <= 0;
TX_DATA_DEL9 <= 0;
TX_DATA_DEL10 <= 0;
TX_DATA_DEL11 <= 0;
TX_DATA_DEL12 <= 0;
TX_DATA_DEL13 <= 0;
TX_DATA_DEL14 <= 0;
TX_DATA_DEL15 <= 0;
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
else begin
TX_DATA_DEL1 <= TX_DATA_REG;
TX_DATA_DEL2 <= TX_DATA_DEL1;
TX_DATA_DEL3 <= TX_DATA_DEL2;
TX_DATA_DEL4 <= TX_DATA_DEL3;
TX_DATA_DEL5 <= TX_DATA_DEL4;
TX_DATA_DEL6 <= TX_DATA_DEL5;
TX_DATA_DEL7 <= TX_DATA_DEL6;
TX_DATA_DEL8 <= TX_DATA_DEL7;
TX_DATA_DEL9 <= TX_DATA_DEL8;
TX_DATA_DEL10 <= TX_DATA_DEL9;
TX_DATA_DEL11 <= TX_DATA_DEL10;
TX_DATA_DEL12 <= TX_DATA_DEL11;
TX_DATA_DEL13 <= TX_DATA_DEL12;
TX_DATA_DEL14 <= TX_DATA_DEL13;
if (load_final_CRC) begin
case (TX_DATA_VALID_DEL13)
8'b00000000 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[31:0] <= CRC_OUT[31:0];
if (insert_error) begin
TX_DATA_DEL14[39:32] <= ERROR_FRAME;
TX_DATA_DEL14[47:40] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[39:32] <= TERMINATE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
end
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
else begin
if (insert_error) begin
TX_DATA_DEL14[7:0] <= ERROR_FRAME;
TX_DATA_DEL14[15:8] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[7:0] <= TERMINATE_FRAME;
TX_DATA_DEL14[15:8] <= IDLE_FRAME;
end
 
TX_DATA_DEL14[23:16] <= IDLE_FRAME;
TX_DATA_DEL14[31:24] <= IDLE_FRAME;
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
8'b00000001 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0];
TX_DATA_DEL14[39:8] <= CRC_OUT[31:0];
if (insert_error) begin
TX_DATA_DEL14[47:40] <= ERROR_FRAME;
TX_DATA_DEL14[55:48] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[47:40] <= TERMINATE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
end
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
TX_DATA_DEL14 <= TX_DATA_DEL13;
 
end
else begin
TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0];
 
if (insert_error) begin
TX_DATA_DEL14[15:8] <= ERROR_FRAME;
TX_DATA_DEL14[23:16] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[15:8] <= TERMINATE_FRAME;
TX_DATA_DEL14[23:16] <= IDLE_FRAME;
end
TX_DATA_DEL14[31:24] <= IDLE_FRAME;
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
TX_DATA_DEL14 <= TX_DATA_DEL13;
end
 
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
8'b00000011 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0];
TX_DATA_DEL14[47:16] <= CRC_OUT[31:0];
if (insert_error) begin
TX_DATA_DEL14[55:48] <= ERROR_FRAME;
TX_DATA_DEL14[63:56] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[55:48] <= TERMINATE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
else begin
TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0];
if (insert_error) begin
TX_DATA_DEL14[23:16] <= ERROR_FRAME;
TX_DATA_DEL14[31:24] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[23:16] <= TERMINATE_FRAME;
TX_DATA_DEL14[31:24] <= IDLE_FRAME;
end
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
 
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
8'b00000111 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0];
TX_DATA_DEL14[55:24] <= CRC_OUT[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14[63:56] <= ERROR_FRAME;
OVERFLOW_DATA[7:0] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[63:56] <= TERMINATE_FRAME;
end
end
else begin
TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0];
TX_DATA_DEL14[55:24] <= CRC_OUT[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14[31:24] <= ERROR_FRAME;
TX_DATA_DEL14[39:32] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[31:24] <= TERMINATE_FRAME;
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
end
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
8'b00001111 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0];
TX_DATA_DEL14[63:32]<= CRC_OUT[31:0];
 
if (insert_error) begin
OVERFLOW_DATA [7:0] <= ERROR_FRAME;
OVERFLOW_DATA[15:8] <= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [7:0]<= TERMINATE_FRAME;
OVERFLOW_DATA [15:8]<= IDLE_FRAME;
end
OVERFLOW_DATA [23:16]<= IDLE_FRAME;
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14 [39:32] <= ERROR_FRAME;
TX_DATA_DEL14[47:40] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [39:32]<= TERMINATE_FRAME;
TX_DATA_DEL14 [47:40]<= IDLE_FRAME;
end
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
8'b00011111 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0];
TX_DATA_DEL14[63:40] <= CRC_OUT[23:0];
OVERFLOW_DATA [7:0]<= CRC_OUT[31:24];
if (insert_error) begin
OVERFLOW_DATA [15:8]<= ERROR_FRAME;
OVERFLOW_DATA [23:16]<= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [15:8]<= TERMINATE_FRAME;
OVERFLOW_DATA [23:16]<= IDLE_FRAME;
end
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14 [47:40] <= ERROR_FRAME;
TX_DATA_DEL14[55:48] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [47:40]<= TERMINATE_FRAME;
TX_DATA_DEL14 [55:48]<= IDLE_FRAME;
end
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
8'b00111111 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0];
TX_DATA_DEL14[63:48] <= CRC_OUT[15:0];
OVERFLOW_DATA [15:0]<= CRC_OUT[31:16];
if (insert_error) begin
OVERFLOW_DATA [23:16]<= ERROR_FRAME;
OVERFLOW_DATA [31:24]<= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [23:16]<= TERMINATE_FRAME;
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
end
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0];
if (insert_error) begin
TX_DATA_DEL14 [55:48] <= ERROR_FRAME;
TX_DATA_DEL14[63:56] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [55:48]<= TERMINATE_FRAME;
TX_DATA_DEL14 [63:56]<= IDLE_FRAME;
end
end
end
8'b01111111 : begin
if (fcs_enabled_int) begin
TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0];
TX_DATA_DEL14[63:56] <= CRC_OUT[7:0];
OVERFLOW_DATA [23:0]<= CRC_OUT[31:8];
if (insert_error) begin
OVERFLOW_DATA [31:24]<= ERROR_FRAME;
OVERFLOW_DATA [39:32]<= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [31:24]<= TERMINATE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
end
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14 [63:56] <= ERROR_FRAME;
OVERFLOW_DATA[7:0] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [63:56]<= TERMINATE_FRAME;
OVERFLOW_DATA [7:0]<= IDLE_FRAME;
end
end
end
 
endcase
end
else if (append_end_frame) begin
TX_DATA_DEL14 <= OVERFLOW_DATA;
end
 
TX_DATA_DEL15 <= TX_DATA_DEL14;
 
TXD <= TX_DATA_DEL15;
end
end
 
 
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
store_tx_data_valid <= 0;
store_tx_data <= 0;
store_CRC64 <= 0;
tx_data_int <= 0;
end
else if (load_CRC8) begin
store_tx_data_valid <= TX_DATA_VALID_DEL2;
store_tx_data <= TX_DATA_DEL2;
store_CRC64 <= CRC_32_64;
end
else begin
store_tx_data_valid[6:0] <= store_tx_data_valid[7:1];
tx_data_int <= store_tx_data[7:0];
store_tx_data[55:0] <= store_tx_data[63:8];
end
end
 
//Start CRC8 and load CRC8
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
start_CRC8 <= 0;
START_CRC8_DEL <= 0;
end
else begin
start_CRC8 <= store_tx_data_valid[0];
START_CRC8_DEL <= start_CRC8;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
byte_count_reg <= 0;
end
else begin
byte_count_reg <= BYTE_COUNTER;
end
end
 
//Use for determining the number of bytes in the data
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
final_byte_count <= 0;
end
else if (load_CRC8) begin
if (BYTE_COUNTER == 64) begin
final_byte_count <= 60;
end
else begin
final_byte_count <= byte_count_reg;
end
end
else if (start_CRC8) begin
final_byte_count <= final_byte_count + 1;
end
 
if (transmit_pause_frame) begin
byte_count_stat = 512;
end
else begin
byte_count_stat = final_byte_count;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
append_reg <= 0;
load_final_CRC <= 0;
append_end_frame <= 0;
end
else begin
append_reg[0] <= load_CRC8;
append_reg[9:1] <= append_reg[8:0];
load_final_CRC <= append_reg[9];
append_end_frame <= load_final_CRC;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
vlan_enabled_int <= 0;
end
end
 
// VLAN field - 8100 at second 64 bit data at 32:47 and V1 V2 is at 48:63
// length field at third 64 bit data at 0:15
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
length_register <= 0;
end
if (vlan_enabled_int) begin
if (BYTE_COUNTER == 16) begin
length_register <= TX_DATA_REG[15:0];
end
end
else begin
if (BYTE_COUNTER == 8) begin
length_register <= TX_DATA_REG[47:32];
end
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
set_pause_stats <= 0;
end
else if (PAUSEVAL_DEL2) begin
set_pause_stats <= 1;
end
else if (append_end_frame) begin
set_pause_stats <= 0;
end
end
 
 
endmodule
 
/verilog/tx_engine/CRC32_D8.v
0,0 → 1,135
module CRC32_D8(DATA_IN, CLK, RESET, START, LOAD, CRC_IN, CRC_OUT);
 
input [7:0] DATA_IN;
input CLK;
input RESET;
input START;
input LOAD;
input [31:0] CRC_IN;
output [31:0] CRC_OUT;
 
reg [31:0] CRC_OUT;
reg start_int;
reg [7:0] data_int;
always @(posedge CLK)
begin
start_int <= START;
data_int <= DATA_IN;
end
 
always @(posedge CLK or posedge RESET)
begin
if (RESET) begin
CRC_OUT = 0;
end
else if (start_int == 1) begin
CRC_OUT = nextCRC32_D8(data_int, CRC_OUT);
end
else if (LOAD == 1) begin
CRC_OUT = CRC_IN;
end
 
end
 
 
///////////////////////////////////////////////////////////////////////
// File: CRC32_D64.v
// Date: Sun Nov 27 19:32:12 2005
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 64
//
// Info: tools@easics.be
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
 
// polynomial: (0 1 2 3 4 5 7 8 10 11 12 16 22 23 26 32)
// data width: 8
// convention: the first serial data bit is D[7]
function [31:0] nextCRC32_D8;
 
input [7:0] Data;
input [31:0] CRC;
 
reg [7:0] D;
reg [31:0] C;
reg [31:0] NewCRC;
 
begin
 
D = Data;
C = CRC;
 
NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^
C[31];
NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^
C[26] ^ C[30] ^ C[31];
NewCRC[3] = D[7] ^ D[6] ^ D[3] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^
C[26] ^ C[27] ^ C[30] ^ C[31];
NewCRC[4] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^
C[25] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31];
NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[2] ^ D[1] ^ D[0] ^
C[24] ^ C[25] ^ C[26] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^
C[31];
NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^
C[26] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
NewCRC[7] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
C[27] ^ C[28] ^ C[29] ^ C[31];
NewCRC[8] = D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^
C[27] ^ C[28] ^ C[29];
NewCRC[9] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^
C[28] ^ C[29] ^ C[30];
NewCRC[10] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^
C[27] ^ C[29] ^ C[31];
NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^
C[27] ^ C[28];
NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^
C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^
C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^
C[28] ^ C[30] ^ C[31];
NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^
C[29] ^ C[31];
NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
NewCRC[20] = D[4] ^ C[12] ^ C[28];
NewCRC[21] = D[5] ^ C[13] ^ C[29];
NewCRC[22] = D[0] ^ C[14] ^ C[24];
NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^
C[28] ^ C[30];
NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^
C[29] ^ C[31];
NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
NewCRC[31] = D[5] ^ C[23] ^ C[29];
 
nextCRC32_D8 = NewCRC;
 
end
 
endfunction
 
endmodule
 
/verilog/tx_engine/CRC32_D64.v
0,0 → 1,310
module CRC32_D64(DATA_IN, CLK, RESET, START, CRC_OUT);
 
input [63:0] DATA_IN;
input CLK;
input RESET;
input START;
output [31:0] CRC_OUT;
// reg [31:0] CRC_FB;
reg [31:0] CRC_OUT;
reg [31:0] CRC_REG;
 
reg start_int;
reg startCRC;
wire [63:0] data_del;
 
 
assign data_del = {DATA_IN[0],DATA_IN[1],DATA_IN[2],DATA_IN[3],DATA_IN[4],DATA_IN[5],DATA_IN[6],DATA_IN[7],
DATA_IN[8],DATA_IN[9],DATA_IN[10],DATA_IN[11],DATA_IN[12],DATA_IN[13],DATA_IN[14],DATA_IN[15],
DATA_IN[16],DATA_IN[17],DATA_IN[18],DATA_IN[19],DATA_IN[20],DATA_IN[21],DATA_IN[22],DATA_IN[23],
DATA_IN[24],DATA_IN[25],DATA_IN[26],DATA_IN[27],DATA_IN[28],DATA_IN[29],DATA_IN[30],DATA_IN[31],
DATA_IN[32],DATA_IN[33],DATA_IN[34],DATA_IN[35],DATA_IN[36],DATA_IN[37],DATA_IN[38],DATA_IN[39],
DATA_IN[40],DATA_IN[41],DATA_IN[42],DATA_IN[43],DATA_IN[44],DATA_IN[45],DATA_IN[46],DATA_IN[47],
DATA_IN[48],DATA_IN[49],DATA_IN[50],DATA_IN[51],DATA_IN[52],DATA_IN[53],DATA_IN[54],DATA_IN[55],
DATA_IN[56],DATA_IN[57],DATA_IN[58],DATA_IN[59],DATA_IN[60],DATA_IN[61],DATA_IN[62],DATA_IN[63]};
 
//assign data_del = 64'h1000000000000000;
 
always @(START)
begin
startCRC <= START;
end
 
always @(posedge CLK or posedge RESET)
begin
if (RESET) begin
CRC_OUT <= 0;
CRC_REG <= 0;
end
else if (startCRC == 1) begin
CRC_OUT <= nextCRC32_D64(data_del, CRC_OUT);
end
end
///////////////////////////////////////////////////////////////////////
// File: CRC32_D64.v
// Date: Sun Nov 27 19:32:12 2005
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 64
//
// Info: tools@easics.be
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
 
// polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// data width: 64
// convention: the first serial data bit is D[63]
function [31:0] nextCRC32_D64;
 
input [63:0] Data;
input [31:0] CRC;
 
reg [63:0] D;
reg [31:0] C;
reg [31:0] NewCRC;
 
begin
 
D = Data;
C = CRC;
 
NewCRC[0] = D[63] ^ D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[54] ^ D[53] ^
D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[37] ^ D[34] ^
D[32] ^ D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^
D[24] ^ D[16] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[0] ^
C[0] ^ C[2] ^ C[5] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^
C[18] ^ C[21] ^ C[22] ^ C[23] ^ C[26] ^ C[28] ^ C[29] ^
C[31];
NewCRC[1] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^
D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[38] ^
D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[28] ^ D[27] ^ D[24] ^
D[17] ^ D[16] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[7] ^
D[6] ^ D[1] ^ D[0] ^ C[1] ^ C[2] ^ C[3] ^ C[5] ^ C[6] ^
C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^
C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31];
NewCRC[2] = D[59] ^ D[58] ^ D[57] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^
D[44] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^ D[32] ^
D[31] ^ D[30] ^ D[26] ^ D[24] ^ D[18] ^ D[17] ^ D[16] ^
D[14] ^ D[13] ^ D[9] ^ D[8] ^ D[7] ^ D[6] ^ D[2] ^
D[1] ^ D[0] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^
C[12] ^ C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[25] ^ C[26] ^
C[27];
NewCRC[3] = D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[54] ^ D[53] ^ D[52] ^
D[45] ^ D[40] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[33] ^
D[32] ^ D[31] ^ D[27] ^ D[25] ^ D[19] ^ D[18] ^ D[17] ^
D[15] ^ D[14] ^ D[10] ^ D[9] ^ D[8] ^ D[7] ^ D[3] ^
D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^
C[8] ^ C[13] ^ C[20] ^ C[21] ^ C[22] ^ C[24] ^ C[26] ^
C[27] ^ C[28];
NewCRC[4] = D[63] ^ D[59] ^ D[58] ^ D[57] ^ D[50] ^ D[48] ^ D[47] ^
D[46] ^ D[45] ^ D[44] ^ D[41] ^ D[40] ^ D[39] ^ D[38] ^
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[25] ^ D[24] ^ D[20] ^
D[19] ^ D[18] ^ D[15] ^ D[12] ^ D[11] ^ D[8] ^ D[6] ^
D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[1] ^ C[6] ^ C[7] ^ C[8] ^
C[9] ^ C[12] ^ C[13] ^ C[14] ^ C[15] ^ C[16] ^ C[18] ^
C[25] ^ C[26] ^ C[27] ^ C[31];
NewCRC[5] = D[63] ^ D[61] ^ D[59] ^ D[55] ^ D[54] ^ D[53] ^ D[51] ^
D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[42] ^ D[41] ^ D[40] ^
D[39] ^ D[37] ^ D[29] ^ D[28] ^ D[24] ^ D[21] ^ D[20] ^
D[19] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^
D[3] ^ D[1] ^ D[0] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^
C[12] ^ C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ C[22] ^
C[23] ^ C[27] ^ C[29] ^ C[31];
NewCRC[6] = D[62] ^ D[60] ^ D[56] ^ D[55] ^ D[54] ^ D[52] ^ D[51] ^
D[50] ^ D[47] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ D[40] ^
D[38] ^ D[30] ^ D[29] ^ D[25] ^ D[22] ^ D[21] ^ D[20] ^
D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^
D[2] ^ D[1] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^
C[13] ^ C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[23] ^
C[24] ^ C[28] ^ C[30];
NewCRC[7] = D[60] ^ D[58] ^ D[57] ^ D[56] ^ D[54] ^ D[52] ^ D[51] ^
D[50] ^ D[47] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^
D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[29] ^ D[28] ^ D[25] ^
D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[16] ^ D[15] ^ D[10] ^
D[8] ^ D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[0] ^ C[2] ^
C[5] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^
C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[24] ^ C[25] ^
C[26] ^ C[28];
NewCRC[8] = D[63] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[52] ^ D[51] ^
D[50] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[40] ^ D[38] ^
D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[31] ^ D[28] ^
D[23] ^ D[22] ^ D[17] ^ D[12] ^ D[11] ^ D[10] ^ D[8] ^
D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^
C[5] ^ C[6] ^ C[8] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^
C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^
C[31];
NewCRC[9] = D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^
D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ D[39] ^ D[38] ^
D[36] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[29] ^ D[24] ^
D[23] ^ D[18] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[5] ^
D[4] ^ D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
C[6] ^ C[7] ^ C[9] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^
C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[26] ^ C[28] ^ C[29];
NewCRC[10] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^
D[52] ^ D[50] ^ D[42] ^ D[40] ^ D[39] ^ D[36] ^ D[35] ^
D[33] ^ D[32] ^ D[31] ^ D[29] ^ D[28] ^ D[26] ^ D[19] ^
D[16] ^ D[14] ^ D[13] ^ D[9] ^ D[5] ^ D[3] ^ D[2] ^
D[0] ^ C[0] ^ C[1] ^ C[3] ^ C[4] ^ C[7] ^ C[8] ^ C[10] ^
C[18] ^ C[20] ^ C[23] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^
C[30] ^ C[31];
NewCRC[11] = D[59] ^ D[58] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ D[51] ^
D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^
D[40] ^ D[36] ^ D[33] ^ D[31] ^ D[28] ^ D[27] ^ D[26] ^
D[25] ^ D[24] ^ D[20] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
D[12] ^ D[9] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[1] ^ C[4] ^
C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^
C[18] ^ C[19] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ C[26] ^
C[27];
NewCRC[12] = D[63] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ D[53] ^
D[52] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[42] ^
D[41] ^ D[31] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[18] ^
D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[5] ^
D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[9] ^ C[10] ^ C[14] ^
C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^
C[24] ^ C[25] ^ C[27] ^ C[29] ^ C[31];
NewCRC[13] = D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[54] ^ D[53] ^
D[52] ^ D[51] ^ D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[42] ^
D[32] ^ D[31] ^ D[28] ^ D[25] ^ D[22] ^ D[19] ^ D[18] ^
D[16] ^ D[14] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^
D[3] ^ D[2] ^ D[1] ^ C[0] ^ C[10] ^ C[11] ^ C[15] ^
C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^
C[25] ^ C[26] ^ C[28] ^ C[30];
NewCRC[14] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ D[54] ^
D[53] ^ D[52] ^ D[51] ^ D[49] ^ D[48] ^ D[44] ^ D[43] ^
D[33] ^ D[32] ^ D[29] ^ D[26] ^ D[23] ^ D[20] ^ D[19] ^
D[17] ^ D[15] ^ D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^
D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[1] ^ C[11] ^ C[12] ^
C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^
C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31];
NewCRC[15] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^
D[53] ^ D[52] ^ D[50] ^ D[49] ^ D[45] ^ D[44] ^ D[34] ^
D[33] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[20] ^ D[18] ^
D[16] ^ D[15] ^ D[12] ^ D[9] ^ D[8] ^ D[7] ^ D[5] ^
D[4] ^ D[3] ^ C[1] ^ C[2] ^ C[12] ^ C[13] ^ C[17] ^
C[18] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^
C[27] ^ C[28] ^ C[30];
NewCRC[16] = D[57] ^ D[56] ^ D[51] ^ D[48] ^ D[47] ^ D[46] ^ D[44] ^
D[37] ^ D[35] ^ D[32] ^ D[30] ^ D[29] ^ D[26] ^ D[24] ^
D[22] ^ D[21] ^ D[19] ^ D[17] ^ D[13] ^ D[12] ^ D[8] ^
D[5] ^ D[4] ^ D[0] ^ C[0] ^ C[3] ^ C[5] ^ C[12] ^ C[14] ^
C[15] ^ C[16] ^ C[19] ^ C[24] ^ C[25];
NewCRC[17] = D[58] ^ D[57] ^ D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[45] ^
D[38] ^ D[36] ^ D[33] ^ D[31] ^ D[30] ^ D[27] ^ D[25] ^
D[23] ^ D[22] ^ D[20] ^ D[18] ^ D[14] ^ D[13] ^ D[9] ^
D[6] ^ D[5] ^ D[1] ^ C[1] ^ C[4] ^ C[6] ^ C[13] ^ C[15] ^
C[16] ^ C[17] ^ C[20] ^ C[25] ^ C[26];
NewCRC[18] = D[59] ^ D[58] ^ D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[46] ^
D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[31] ^ D[28] ^ D[26] ^
D[24] ^ D[23] ^ D[21] ^ D[19] ^ D[15] ^ D[14] ^ D[10] ^
D[7] ^ D[6] ^ D[2] ^ C[0] ^ C[2] ^ C[5] ^ C[7] ^ C[14] ^
C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[26] ^ C[27];
NewCRC[19] = D[60] ^ D[59] ^ D[54] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^
D[40] ^ D[38] ^ D[35] ^ D[33] ^ D[32] ^ D[29] ^ D[27] ^
D[25] ^ D[24] ^ D[22] ^ D[20] ^ D[16] ^ D[15] ^ D[11] ^
D[8] ^ D[7] ^ D[3] ^ C[0] ^ C[1] ^ C[3] ^ C[6] ^ C[8] ^
C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[27] ^ C[28];
NewCRC[20] = D[61] ^ D[60] ^ D[55] ^ D[52] ^ D[51] ^ D[50] ^ D[48] ^
D[41] ^ D[39] ^ D[36] ^ D[34] ^ D[33] ^ D[30] ^ D[28] ^
D[26] ^ D[25] ^ D[23] ^ D[21] ^ D[17] ^ D[16] ^ D[12] ^
D[9] ^ D[8] ^ D[4] ^ C[1] ^ C[2] ^ C[4] ^ C[7] ^ C[9] ^
C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[28] ^ C[29];
NewCRC[21] = D[62] ^ D[61] ^ D[56] ^ D[53] ^ D[52] ^ D[51] ^ D[49] ^
D[42] ^ D[40] ^ D[37] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^
D[27] ^ D[26] ^ D[24] ^ D[22] ^ D[18] ^ D[17] ^ D[13] ^
D[10] ^ D[9] ^ D[5] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10] ^
C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[29] ^ C[30];
NewCRC[22] = D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^
D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^
D[37] ^ D[36] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^
D[26] ^ D[24] ^ D[23] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^
D[12] ^ D[11] ^ D[9] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^
C[5] ^ C[6] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^
C[16] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^
C[30];
NewCRC[23] = D[62] ^ D[60] ^ D[59] ^ D[56] ^ D[55] ^ D[54] ^ D[50] ^
D[49] ^ D[47] ^ D[46] ^ D[42] ^ D[39] ^ D[38] ^ D[36] ^
D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ D[26] ^ D[20] ^
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[13] ^ D[9] ^ D[6] ^
D[1] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ C[6] ^ C[7] ^ C[10] ^
C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[22] ^ C[23] ^ C[24] ^
C[27] ^ C[28] ^ C[30];
NewCRC[24] = D[63] ^ D[61] ^ D[60] ^ D[57] ^ D[56] ^ D[55] ^ D[51] ^
D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[40] ^ D[39] ^ D[37] ^
D[36] ^ D[35] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[21] ^
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[14] ^ D[10] ^ D[7] ^
D[2] ^ D[1] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[7] ^ C[8] ^
C[11] ^ C[15] ^ C[16] ^ C[18] ^ C[19] ^ C[23] ^ C[24] ^
C[25] ^ C[28] ^ C[29] ^ C[31];
NewCRC[25] = D[62] ^ D[61] ^ D[58] ^ D[57] ^ D[56] ^ D[52] ^ D[51] ^
D[49] ^ D[48] ^ D[44] ^ D[41] ^ D[40] ^ D[38] ^ D[37] ^
D[36] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[22] ^ D[21] ^
D[19] ^ D[18] ^ D[17] ^ D[15] ^ D[11] ^ D[8] ^ D[3] ^
D[2] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[12] ^
C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[24] ^ C[25] ^ C[26] ^
C[29] ^ C[30];
NewCRC[26] = D[62] ^ D[61] ^ D[60] ^ D[59] ^ D[57] ^ D[55] ^ D[54] ^
D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[44] ^ D[42] ^ D[41] ^
D[39] ^ D[38] ^ D[31] ^ D[28] ^ D[26] ^ D[25] ^ D[24] ^
D[23] ^ D[22] ^ D[20] ^ D[19] ^ D[18] ^ D[10] ^ D[6] ^
D[4] ^ D[3] ^ D[0] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[12] ^
C[15] ^ C[16] ^ C[17] ^ C[20] ^ C[22] ^ C[23] ^ C[25] ^
C[27] ^ C[28] ^ C[29] ^ C[30];
NewCRC[27] = D[63] ^ D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[56] ^ D[55] ^
D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[45] ^ D[43] ^ D[42] ^
D[40] ^ D[39] ^ D[32] ^ D[29] ^ D[27] ^ D[26] ^ D[25] ^
D[24] ^ D[23] ^ D[21] ^ D[20] ^ D[19] ^ D[11] ^ D[7] ^
D[5] ^ D[4] ^ D[1] ^ C[0] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^
C[13] ^ C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[23] ^ C[24] ^
C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
NewCRC[28] = D[63] ^ D[62] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^
D[51] ^ D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^
D[40] ^ D[33] ^ D[30] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^
D[24] ^ D[22] ^ D[21] ^ D[20] ^ D[12] ^ D[8] ^ D[6] ^
D[5] ^ D[2] ^ C[1] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^
C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[24] ^ C[25] ^
C[27] ^ C[29] ^ C[30] ^ C[31];
NewCRC[29] = D[63] ^ D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^
D[51] ^ D[50] ^ D[47] ^ D[45] ^ D[44] ^ D[42] ^ D[41] ^
D[34] ^ D[31] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^
D[23] ^ D[22] ^ D[21] ^ D[13] ^ D[9] ^ D[7] ^ D[6] ^
D[3] ^ C[2] ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15] ^
C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^
C[30] ^ C[31];
NewCRC[30] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ D[52] ^
D[51] ^ D[48] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[35] ^
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[24] ^
D[23] ^ D[22] ^ D[14] ^ D[10] ^ D[8] ^ D[7] ^ D[4] ^
C[0] ^ C[3] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ C[16] ^
C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^
C[31];
NewCRC[31] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[53] ^ D[52] ^
D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[36] ^ D[33] ^
D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[25] ^ D[24] ^
D[23] ^ D[15] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ C[1] ^
C[4] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[20] ^
C[21] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ C[30];
 
nextCRC32_D64 = NewCRC;
 
end
 
endfunction
 
endmodule
 
/verilog/rx_engine/rxdatafifo.xco
0,0 → 1,44
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\10G\ethmac10g
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\10G\ethmac10g
SET device = xc2vp20
# SET projectname = F:\10G\ethmac10g
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg676
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET memory_type=Block_Memory
CSET write_acknowledge_flag=false
CSET data_width=64
CSET write_error_flag=false
CSET read_acknowledge_sense=Active_Low
CSET data_count_width=8
CSET fifo_depth=128
CSET component_name=rxdatafifo
CSET data_count=false
CSET read_acknowledge_flag=false
CSET read_error_sense=Active_Low
CSET read_error_flag=false
CSET write_acknowledge_sense=Active_Low
CSET write_error_sense=Active_Low
# END Parameters
GENERATE
 
 
/verilog/rx_engine/dcm0.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
$83x4>7<881:;6?:6/064==6>.bH<5>=;0Z2?77<<:1="9:48/3j3>GUKA]BV<94ASUY[JHKQVIJ_NOKIOE\GIM602KY[WQ@NM[\GIMNFVOSXH\AAM36?DTPRVEE@TQLLJKM[SGK]L;i7L\XZ^MMH\YCKDUX[DZLHHLD[FJL991J^ZTPOONZ[ABUWJ::<6O]W[]LJI_XLMXTO<?>;@PT^ZIIDPUOH_QLLJ35?DTPRVEE@TQKDS]EHLVADFZ:96O]W[]LJI_XNKUNTYK]N@N26>GU_SUDBAWPIOQW[KSJm2KY[WQ@NM[\THEC9>1J^ZTPOONZ[WCDGGLBKR^FNR36?DTPRVEE@TQ]ERGW[II@AJ;37L\XZ^MMH\YQIECOSIH\_LMGAd=F[ZEHSZG[H018ER\XKEAIYK?PBMIMEHC6=2K\VRMCKCWE5ZOX[@MEM@K>5:CT^ZEKCK_M=RAPSHEMEHCa3H]QSNBDBTDW]UC69?1J[WQLLJ@VBQ_WM8UECHJFTb9BS_YADF]_U]K7;@UY[UGU\m1J[WQ\YOVKPJIK<2HDXE:4BTDD0>EKC920OAE?_CWEa>EKC9UIYKIPIOQW<>EKC9UDYY84CMI2<5g<KEA:4=QMUG33?FJL91:TNXHH_HLPPd=DDB;3<RAZT79@HN408<1H@F<W8:AOO7^60930OAE=X^@VBc=DDB8SSO[IG^KMWQ?<KEA9TRAZT49@HN?712IGG4>PBTDe?FJL19UIYKIPIOQW=>EKC0:TCXZ:;BNH@Se<KEAOZRJFVHFF1>EKCOH37NBDFC]JJ0=DDBLS46MCKGZ2<5e<KEAMTRJFVHFFa>EKCORTAXB[IQNZ1>EKC@D:=6MCKHL\@LPNLLUIUR<m;BNHMKYNJ\LL==5LLJKM[LDRNNUBB^Zi;BNHMKYNJ\LLSB[[8:AOOLHXAGi0OAEFN^RFVLICm2IGGD@PSSA\P\VB9;1H@FAZT^RKEVCX[ACMXn5LLJ]EA@BEIJAm7NBD_NWWTPRX\PZN56M@MLKWP@B03JXNMYKK3:F@I==CKDUBB^Zk;EGPO@QXIM@^_Y?=;EDP[CTBY\OEOTQBOEG`?AOTIKFNHRLZF29GHI753MFGSK\JQTGMG\YJGMO>7I]\EO36?ASSQVIROAKPCNPQAFRNGG=0HRXNLTG;?@^SM[DJ@l5IABVLV\YMN<1MMA]J9:DA[VIRZJOh7KKJDCC@OZDRN01MECQZNHVP1>@NPLN37KAZT^QWVd=AG\^TYCG[S`9EKPRX^HF^I<5F5:KAQCA?3@D_I_@NL038NLRSM[UBB][[_U[SA3=KGHNNH;5COBIF@d=KGJANHRAZT29OKR5<EAP<7@QYAMWF3>HB\^EYG95AOOG2?J><GONO^N^Jb:RKEVCX[ACMX45_IOJBWGSTi2ZBBD]HNEGG<>VNF^COXE64PSKNP\VB991[^B^PPHLJWDESA_O>7]]LLJ48TVBHFL>0\^KA8:RPMKECMJ90^^Z9;SQW[LHe3ZCLIUZJROCO2>UNFNFNo6][ASVVTZQFA]<0_YO[UR31?V_T\LGT_T@LHSMMKPU43]E[86Z]UD:8QVCXJ\LL56[\E^@VBBU23_CN[<l4X@U\R@TTAFD:h6VFLHL[)]BE(9$:,^ZZB!2-5%GTK@C87U][6:ZgfZOc991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc;4[183Y0=\83=V86o}w{18`fk?3mif<#vnwc9uawungg*:"=:4vifoa>~d:z9< 8ig755yEFw<<1KLu6k:G8f>4}T<h03n76j:012b06c2:h:ov`77;38j=>=<2.3:76;;|Q7=?>e21o1=>?i51f97gbb3Z<865l58d8274`29?08<><4S5;9<g<?m3;8=k;>6;1335=T>:03n76j:01152ed2:3nj6];9;:a>=c=9:8:;nm53`27?V0421h14h4>3334gf<4k:k0_9758c8;a?74:8=ho7=l4e9P26<?j32n6<==16f1>cd2j2Y?576m:9g95646?m81jo7l;R40>=d=0l0:???8d48ef55<[=314o47e;30641c=3li?n5\628;f?>b2899=:jj:037e<=T<003n76j:01152bb28;?jl5k8c83>4<6sZ>j65l58d8274`28m08n<m4vU:1>5<6280jw^:n:9`9<`<6;8l><i4<b0a8f2c=83:187ot$`8;g>"6n32m7)<?:828 77=0<1/4>46;c6`>5<6;3:1<v*81;6a?!d=;?1/o79n;%g961=#n38?7)??:3:8 47=:=1/=?49c:&27?1f3-;?6?5+1485e>"6?3?<7)?7:308 11==2.8;784$2a96>"4l3=0(>h5569'01<?3->>68;4$5491g=#<m0<h6*:4;08 1c=>?1/9<496:&67?1a3-?=695+59855>"2i3<<7);k:758 0c=82.=>7;l;%4;>2=#>m0:7)9m:458 =6=081/=;4:7:&7<?373-n1?6g<e;29 26=001/;?48f:&2`?073-;n69h4;h1;>5<#?90356*82;5e?>o0?3:1(:>5889'37<0n21b;84?:%53>=?<,?l1;k54i6494?"083227)8i:6d8?l14290/;=479:&5b?1a32c>>7>5$629<<=#>o0<j6*82;5e?>i5<3:1(:>5889'37<0n2.:h7<<;%3b>70<,8h1>85+1b813>"6m3?276a<2;29 26=001/=i4=3:&2e?533-;i6>=4$0a970=<g;21<7*80;::?!152>l0(<j5229'5d<5i2.:n7<6;%3`>7d<3f8h6=4+718;=>=h;?0;6)9?:9;8?j4c290/;=479:&2`?443-;j6>>4$0`96c=#9j08=65`2d83>!1721307b=n:18'35<?121d?o4?:%53>=?<3f=h6=4+718;e>"1m3=m76a94;29 26=001/;?48f:9l31<72-=;6574;|`75?6=:3:1<v*81;43?l3a290/;=479:&46?1a3-;i69=4;n4a>5<#?90356*82;5e?!7d2=:07pl=6;296?6=8r.<=7<<;h7e>5<#?90356*82;5e?>i1j3:1(:>5889'37<0n21vn?o50;094?6|,>;1>>5f5g83>!172130(:<57g98k3d=83.<<766;%51>2`<3ty?<7>52z?7g?5b34>:6;l4$0;907=z{:31<7<t=5a97==::?0=n6*>9;04?xu003:1=v3;c;54?!1>2<l0q~<::18182d2;>01?855g9~w7?=838p19m5299>6d<2n2wx:84?:0y>0f<1<2.<578m;|q77?6=9r7?=7;i;%5:>0`<uz8i6=4>{<0b>3d<,>31:o5rs5094?6|,>31:o5rs3594?6|,>31:o5r}o12>5<6std8>7>51zm76<728qvb>:50;3xyk52290:wp`<6;295~{i;>0;6<urn2:94?7|ug926=4>{|l0e?6=9rwvqpNOCz66><b7nm>=>pNOBz2~DEV|uIJ
/verilog/rx_engine/rxClkgen.v
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rx clk generator ////
//// ////
//// DESCRIPTION: Clk generator for Receive engine of 10 Gigabit ////
//// Ethernet MAC. ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxClkgen(rxclk_in, reset, rxclk, rxclk_180, locked);
input rxclk_in;
input reset;
output rxclk;
output rxclk_180;
output locked;
 
dcm0 rx_dcm(.CLKIN_IN(rxclk_in),
.RST_IN(reset),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(rxclk),
.CLK180_OUT(rxclk_180),
.LOCKED_OUT(locked)
);
 
endmodule
/verilog/rx_engine/rxStateMachine.v
0,0 → 1,198
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxNumCounter ////
//// ////
//// DESCRIPTION: To count bytes have been received. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, length_error, crc_check_valid, crc_check_invalid,
start_da, start_lt, receiving, receiving_d1, good_frame_get, bad_frame_get, get_error_code, wait_crc_check,
get_terminator,check_reset);
input rxclk;
input reset;
input recv_enable;
//PRE & SFD
input get_sfd; // SFD has been received;
//DA field
input local_invalid;// The Frame's DA field is not Local MAC;
//Length/Type field
input length_error;//
//FCS field
input get_terminator;//Indicate end of receiving FCS field;
input crc_check_valid;//Indicate the frame passed CRC Check;
input crc_check_invalid;//Indicate the frame failed in CRC Check;
input get_error_code;
input check_reset;
//DA field
output start_da;// Start to receive Destination Address;
//Length/Type field
output start_lt;// Start to receive Length/Type field;
//Receive process control
output receiving; //Rx Engine is working, not in IDLE state and Check state.
output receiving_d1;
output good_frame_get;// A good frame has been received;
output bad_frame_get; // A bad frame has been received;
output wait_crc_check;//
parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 4;
parameter rxGetError = 8, rxIFGWait = 16;
parameter TP =1;
 
wire start_da;
wire start_lt;
wire receiving;
reg good_frame_get;
reg bad_frame_get;
reg[4:0] rxstate, rxstate_next;
 
always@(rxstate, get_sfd, local_invalid, recv_enable,
get_error_code, length_error, get_terminator, reset)begin
if (reset) begin
rxstate_next <=#TP IDLE;
end
else begin
case (rxstate)
IDLE: begin //5'b00000;
if (get_sfd && recv_enable)
rxstate_next <=#TP rxReceiveDA;
else
rxstate_next <=#TP IDLE;
end
rxReceiveDA: begin //5'b00001
rxstate_next <=#TP rxReceiveLT;
end
rxReceiveLT: begin //5'b00010
rxstate_next <=#TP rxReceiveData;
end
rxReceiveData: begin //5'b00100
if (local_invalid |length_error| get_error_code)
rxstate_next <=#TP rxGetError;
else if (get_terminator)
rxstate_next <=#TP rxIFGWait;
else
rxstate_next <=#TP rxReceiveData;
end
rxGetError: begin //5'b01000
if (get_sfd && recv_enable)
rxstate_next <=#TP rxReceiveDA;
else
rxstate_next <=#TP IDLE;
end
rxIFGWait : begin //5'b10000;
if (get_sfd && recv_enable)
rxstate_next <=#TP rxReceiveDA;
else
rxstate_next <=#TP IDLE;
end
endcase
end
end
 
always@(posedge rxclk or posedge reset) begin
if (reset)
rxstate <=#TP IDLE;
else
rxstate <=#TP rxstate_next;
end
 
assign start_da = rxstate[0];
assign start_lt = rxstate[1];
assign receiving = rxstate[2] | rxstate[1] | rxstate[0]; // in DA,LT,DATA status
reg receiving_d1;
always@(posedge rxclk or posedge reset) begin
if (reset) begin
receiving_d1<=#TP 0;
end
else begin
receiving_d1<=#TP receiving;
end
end
reg wait_crc_check;
always@(posedge rxclk or posedge reset) begin
if (reset)
wait_crc_check <=#TP 0;
else if (rxstate[4])
wait_crc_check <=#TP 1'b1;
else if (crc_check_valid || crc_check_invalid||length_error)
wait_crc_check <=#TP 1'b0;
else
wait_crc_check <=#TP wait_crc_check;
end
 
always@(posedge rxclk or posedge reset)begin
if (reset) begin
bad_frame_get <=#TP 0;
good_frame_get <=#TP 0;
end
else if(rxstate[3] || crc_check_invalid || length_error)begin
bad_frame_get <=#TP 1'b1;
good_frame_get <=#TP 1'b0;
end
else if (crc_check_valid)begin
good_frame_get <=#TP 1'b1;
bad_frame_get <=#TP 1'b0;
end
else if (check_reset)begin
good_frame_get <=#TP 1'b0;
bad_frame_get <=#TP 1'b0;
end
end
endmodule
/verilog/rx_engine/counter.v
0,0 → 1,42
`timescale 100ps / 10ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:53:19 11/22/05
// Design Name:
// Module Name: counter
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counter(clk, reset, load, en, value);
input clk;
input reset;
input load;
input en;
 
parameter WIDTH = 8;
output[WIDTH-1:0] value;
 
reg [WIDTH-1:0] value;
always @(posedge clk or posedge reset)
if (reset)
value <= 0;
else begin
if (load)
value <= 0;
else if (en)
value <= value + 1;
end
endmodule
/verilog/rx_engine/rxCRC.v
0,0 → 1,176
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxCRC ////
//// ////
//// DESCRIPTION: CRC Checker, by using magic word c704dd7b. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxCRC(rxclk, reset, receiving, receiving_d1, CRC_DATA, get_terminator,
get_terminator_d1, wait_crc_check,crc_check_invalid, crc_check_valid, terminator_location,get_error_code);
input rxclk;
input reset;
input get_terminator;
input [63:0] CRC_DATA;
input receiving;
input receiving_d1;
input [2:0] terminator_location;
input wait_crc_check;
 
output crc_check_invalid;
output crc_check_valid;
output get_terminator_d1;
input get_error_code;
 
parameter TP = 1;
 
/////////////////////////////////////////////////////////////////////////////////////////////
// Input registers
/////////////////////////////////////////////////////////////////////////////////////////////
 
reg get_terminator_d1, get_terminator_d2,get_terminator_d3;
always@(posedge rxclk or posedge reset) begin
if(reset)begin
get_terminator_d1 <=#TP 0;
get_terminator_d2 <=#TP 0;
get_terminator_d3 <=#TP 0;
end
else begin
get_terminator_d1 <=#TP get_terminator;
get_terminator_d2 <=#TP get_terminator_d1;
get_terminator_d3 <=#TP get_terminator_d2;
end
end
 
reg[2:0] bytes_cnt;
reg crc_8_en;//enable 8bit CRC
always@(posedge rxclk or posedge reset) begin
if (reset)
bytes_cnt <=#TP 0;
else if (get_terminator)
bytes_cnt <=#TP terminator_location;
else if (crc_8_en)
bytes_cnt <=#TP bytes_cnt-1;
end
 
reg[63:0] terminator_data;
always@(posedge rxclk or posedge reset) begin
if(reset)
terminator_data <=#TP 0;
else if (get_terminator_d2)
terminator_data <=#TP CRC_DATA;
else
terminator_data <=#TP terminator_data<<8;
end
/////////////////////////////////////////////////////////////////////////////////////////////
// 64bits CRC
// start: crc_valid = 8'hff and receiving_frame = 1
// end : crc_valid != 8'hff or receiving_frame = 0
// if bits_more is 0, then CRC check will happen when end happens.
// else 8bits CRC should begin
/////////////////////////////////////////////////////////////////////////////////////////////
 
wire [31:0] crc_from_64;
reg crc_64_en; // 64bit CRC Enable
always@(posedge rxclk or posedge reset) begin
if(reset)
crc_64_en <= #TP 1'b0;
else if(get_error_code) //if error, stop crc checking
crc_64_en <= #TP 1'b0;
else if(receiving_d1 & receiving)
crc_64_en <= #TP 1'b1;
else
crc_64_en <= #TP 1'b0;
end
 
CRC32_D64 crc64(.DATA_IN(CRC_DATA), .CLK(rxclk), .RESET(reset), .START(crc_64_en), .CRC_OUT(crc_from_64), .init(get_terminator_d3|get_error_code));
/////////////////////////////////////////////////////////////////////////////////////////////
// 8bits CRC
/////////////////////////////////////////////////////////////////////////////////////////////
reg[7:0] CRC_DATA_TMP;
always@(posedge rxclk or posedge reset) begin
if(reset)
CRC_DATA_TMP <=#TP 0;
else
CRC_DATA_TMP <=#TP terminator_data[63:56];
end
always@(posedge rxclk or posedge reset) begin
if(reset)
crc_8_en <=#TP 0;
else if (get_terminator_d3)
crc_8_en <=#TP 1'b1;
else if(bytes_cnt==1)
crc_8_en <=#TP 1'b0;
end
reg do_crc_check;
always@(posedge rxclk or posedge reset) begin
if (reset)
do_crc_check <=#TP 0;
else if(terminator_location == 0)
do_crc_check <=#TP get_terminator_d2;
else
do_crc_check <=#TP wait_crc_check & (bytes_cnt==1);
end
wire[31:0] crc_from_8;
CRC32_D8 crc8(.DATA_IN(CRC_DATA_TMP), .CLK(rxclk), .RESET(reset), .START(crc_8_en), .LOAD(~crc_8_en), .CRC_IN(crc_from_64), .CRC_OUT(crc_from_8));
////////////////////////////////////////////////////////////////////////////////////////////
// CRC check
////////////////////////////////////////////////////////////////////////////////////////////
wire crc_check_valid, crc_check_invalid;
 
assign crc_check_valid = wait_crc_check & do_crc_check & (crc_from_8==32'hc704dd7b);
assign crc_check_invalid = wait_crc_check & do_crc_check & (crc_from_8!=32'hc704dd7b);
 
endmodule
/verilog/rx_engine/rxReceiveEngine.v
0,0 → 1,282
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: receive engine ////
//// ////
//// DESCRIPTION: Receive Engine Top Level for the 10 Gigabit ////
//// Ethernet MAC. ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
// No flow control included
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxReceiveEngine(rxclk_in, reset_in, rxd_in, rxc_in, rxStatRegPlus,
cfgRxRegData_in, rx_data, rx_data_valid, rx_good_frame,
rx_bad_frame, rxCfgofRS, rxTxLinkFault);//, fcTxPauseData, fcTxPauseValid);
input rxclk_in; //Input clock of receive engine
input reset_in; //Globle reset of receive engine
input [31:0] rxd_in; //XGMII RXD
input [3:0] rxc_in; //XGMII RXC
output [17:0] rxStatRegPlus; //Signals for statistics
input [64:0] cfgRxRegData_in; //Signals for configuration
output [63:0] rx_data; //Received data sent to upper layer
output [7:0] rx_data_valid; //Receive data valid indicator
output rx_good_frame; //Indicate that a good frame has been received
output rx_bad_frame; //Indicate that a bad frame has been received
output[2:0] rxCfgofRS; //
output [1:0] rxTxLinkFault;
// output [31:0] fcTxPauseData;
// output fcTxPauseValid;
 
parameter TP =1;
 
wire rxclk;
wire rxclk_180;
wire locked;
wire reset_dcm;
wire reset;
 
reg [47:0]MAC_Addr; //MAC Address used in receiving control frame.
reg vlan_enable; //VLAN Enable
reg recv_enable; //Receiver Enable
reg inband_fcs; //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client
reg jumbo_enable;//Jumbo Frame Enable
reg recv_rst; //Receiver reset
 
wire start_da, start_lt;
wire tagged_frame;
wire pause_frame;
wire [47:0] da_addr;
// wire [15:0] lt_data;
wire [`COUNTER_WIDTH-1:0] frame_cnt;
wire [2:0] terminator_location;
wire get_sfd,get_error_code,get_terminator, get_terminator_d1;
wire receiving;
wire receiving_d1,receiving_d2;
 
wire length_error;
wire large_error;
wire small_error;
wire padded_frame;
wire length_65_127;
wire length_128_255;
wire length_256_511;
wire length_512_1023;
wire length_1024_max;
wire jumbo_frame;
 
wire local_invalid;
wire broad_valid;
wire multi_valid;
 
wire good_frame_get, bad_frame_get;
wire wait_crc_check;
 
wire crc_check_valid;
wire crc_check_invalid;
wire check_reset;
 
wire [1:0]link_fault;
 
//////////////////////////////////////////
// Input Registers
//////////////////////////////////////////
wire [63:0] rxd64;
wire [63:0] CRC_DATA;
wire [7:0] rxc8;
 
assign rxTxLinkFault = link_fault;
// assign fcTxPauseValid = pause_frame;
//////////////////////////////////////////
// Read Receiver Configuration Word
//////////////////////////////////////////
reg[52:0] cfgRxRegData;
always@(posedge rxclk or posedge reset)begin
if(reset)
cfgRxRegData <=#TP 0;
else
cfgRxRegData<=#TP cfgRxRegData_in;
end
always@(posedge rxclk or posedge reset)begin
if(reset) begin
MAC_Addr <= 0;
vlan_enable <= 0;
recv_enable <= 0;
inband_fcs <= 0;
jumbo_enable <= 0;
recv_rst <= 0;
end
else begin
MAC_Addr <= cfgRxRegData[47:0];
vlan_enable <= cfgRxRegData[48];
recv_enable <= cfgRxRegData[49];
inband_fcs <= cfgRxRegData[50];
jumbo_enable <= cfgRxRegData[51];
recv_rst <= cfgRxRegData[52];
end
end
//////////////////////////////////////////////////
// Used to count number of received frames(G&B)
//////////////////////////////////////////////////
reg[7:0] cnt;
reg cnt_en;
always@(posedge rxclk or posedge reset) begin
if (reset)
cnt_en <=0;
else if(get_sfd)
cnt_en <=1;
else if(rx_bad_frame|rx_good_frame)
cnt_en <=0;
else
cnt_en <=cnt_en;
end
 
always@(posedge rxclk or posedge reset) begin
if (reset)
cnt <=0;
else if(cnt_en)
cnt<=cnt + 1;
else
cnt <=0;
end
/////////////////////////////////////////
// Reset signals
/////////////////////////////////////////
assign reset_dcm = reset_in | recv_rst;
assign reset = ~locked;
/////////////////////////////////////////
// Write Configuration Words of RS
/////////////////////////////////////////
 
assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault
assign rxCfgofRS[1] = link_fault[0] & link_fault[1]; //get remote fault
assign rxCfgofRS[2] = locked; //Receive DCM locked
////////////////////////////////////////
// Signals for Pause Operation
////////////////////////////////////////
assign fcTxPauseValid = pause_frame;
// assign fcTxPauseData = {16{1'b0},rxd64[15:0]};
 
////////////////////////////////////////
// Receive Clock Generator
////////////////////////////////////////
 
rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
.reset(reset_dcm),
.rxclk(rxclk), // system clock
.rxclk_180(rxclk_180), //reversed clock
.locked(locked)
);
//////////////////////////////////////
// Rx Engine DataPath
//////////////////////////////////////
rxDataPath datapath_main(.rxclk(rxclk), .reset(reset), .rxd64(rxd64), .rxc8(rxc8), .inband_fcs(inband_fcs), .receiving(receiving),
.start_da(start_da), .start_lt(start_lt), .wait_crc_check(wait_crc_check), .get_sfd(get_sfd),
.get_terminator(get_terminator), .get_error_code(get_error_code), .tagged_frame(tagged_frame), .pause_frame(pause_frame),
.da_addr(da_addr), .terminator_location(terminator_location), .CRC_DATA(CRC_DATA), .rx_data_valid(rx_data_valid),
.rx_data(rx_data), .get_terminator_d1(get_terminator_d1),.bad_frame_get(bad_frame_get),.good_frame_get(good_frame_get),
.check_reset(check_reset),.rx_good_frame(rx_good_frame),.rx_bad_frame(rx_bad_frame));//,.fcTxPauseData(fcTxPauseData));
//////////////////////////////////////
// Destination Address Checker
//////////////////////////////////////
 
rxDAchecker dachecker(.rxclk(rxclk), .reset(reset), .local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),
.da_addr(da_addr));
 
/////////////////////////////////////
// Length/Type field checker
/////////////////////////////////////
 
rxLenTypChecker lenchecker(.rxclk(rxclk), .reset(reset), .get_terminator(get_terminator), .terminator_location(terminator_location),
.jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame), .frame_cnt(frame_cnt), .vlan_enable(vlan_enable),
.length_error(length_error), .large_error(large_error),.small_error(small_error), .padded_frame(padded_frame),
.length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),
.length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame)
);
 
/////////////////////////////////////
// Counters used in Receive Engine
/////////////////////////////////////
 
rxNumCounter counters(.rxclk(rxclk), .reset(reset), .receiving(receiving), .frame_cnt(frame_cnt));
/////////////////////////////////////
// State Machine in Receive Process
/////////////////////////////////////
 
rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid),
.length_error(length_error), .crc_check_valid(crc_check_valid), .crc_check_invalid(crc_check_invalid),
.start_da(start_da), .start_lt(start_lt), .receiving(receiving),.good_frame_get(good_frame_get),
.bad_frame_get(bad_frame_get), .get_error_code(get_error_code), .wait_crc_check(wait_crc_check), .get_terminator(get_terminator),
.receiving_d1(receiving_d1),.check_reset(check_reset));
 
/////////////////////////////////////
// CRC Check module
/////////////////////////////////////
rxCRC crcmodule(.rxclk(rxclk), .reset(reset), .CRC_DATA(CRC_DATA), .get_terminator(get_terminator), .terminator_location(terminator_location),
.crc_check_invalid(crc_check_invalid), .crc_check_valid(crc_check_valid),.receiving(receiving),.receiving_d1(receiving_d1),
.get_terminator_d1(get_terminator_d1), .wait_crc_check(wait_crc_check),.get_error_code(get_error_code));
/////////////////////////////////////
// RS Layer
/////////////////////////////////////
rxRSLayer rx_rs(.rxclk(rxclk), .rxclk_180(rxclk_180), .reset(reset), .link_fault(link_fault), .rxd64(rxd64), .rxc8(rxc8), .rxd_in(rxd_in), .rxc_in(rxc_in));
/////////////////////////////////////
// Statistic module
/////////////////////////////////////
rxStatModule rx_stat(.rxclk(rxclk),.reset(reset),.good_frame_get(good_frame_get), .large_error(large_error),.small_error(small_error), .crc_check_invalid(crc_check_invalid),
.receiving(receiving), .padded_frame(padded_frame), .pause_frame(pause_frame), .broad_valid(broad_valid), .multi_valid(multi_valid),
.length_65_127(length_65_127), .length_128_255(length_128_255), .length_256_511(length_256_511), .length_512_1023(length_512_1023),
.length_1024_max(length_1024_max), .jumbo_frame(jumbo_frame),.get_error_code(get_error_code), .rxStatRegPlus(rxStatRegPlus));
endmodule
/verilog/rx_engine/dcm0.v
0,0 → 1,85
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 8.1.03i
// \ \ Application : xaw2verilog
// / / Filename : dcm0.v
// /___/ /\ Timestamp : 05/30/2006 09:16:54
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle F:/10G/rx_engine_v2/dcm0.xaw -st dcm0.v
//Design Name: dcm0
//Device: xc2vp20-6fg676
//
// Module dcm0
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
 
module dcm0(CLKIN_IN,
RST_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK180_OUT,
LOCKED_OUT);
 
input CLKIN_IN;
input RST_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK180_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK180_BUF;
wire GND1;
assign GND1 = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
.O(CLK180_OUT));
DCM DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND1),
.PSCLK(GND1),
.PSEN(GND1),
.PSINCDEC(GND1),
.RST(RST_IN),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(CLK180_BUF),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
defparam DCM_INST.CLK_FEEDBACK = "1X";
defparam DCM_INST.CLKDV_DIVIDE = 2.000000;
defparam DCM_INST.CLKFX_DIVIDE = 1;
defparam DCM_INST.CLKFX_MULTIPLY = 4;
defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_INST.CLKIN_PERIOD = 6.400000;
defparam DCM_INST.CLKOUT_PHASE_SHIFT = "FIXED";
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST.FACTORY_JF = 16'hC080;
defparam DCM_INST.PHASE_SHIFT = 0;
defparam DCM_INST.STARTUP_WAIT = "FALSE";
endmodule
/verilog/rx_engine/rxDAchecker.v
0,0 → 1,84
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: Destination Address Check ////
//// ////
//// DESCRIPTION: Destination Address Checker of 10 Gigabit ////
//// Ethernet MAC. ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxDAchecker(rxclk,reset,local_invalid, broad_valid, multi_valid, MAC_Addr, da_addr);
input rxclk;
input reset;
 
output local_invalid;
output broad_valid;
output multi_valid;
 
input [47:0] MAC_Addr;
input [47:0] da_addr;
parameter TP = 1;
reg multi_valid;
reg broad_valid;
reg local_valid;
always @(posedge rxclk or posedge reset) begin
if (reset) begin
multi_valid <=#TP 0;
broad_valid <=#TP 0;
local_valid <=#TP 0;
end
else begin
multi_valid <=#TP (da_addr==`MULTICAST);
broad_valid <=#TP (da_addr==`BROADCAST);
local_valid <=#TP (da_addr==MAC_Addr);
end
end
 
assign local_invalid = 1'b0;//~local_valid & ~multi_valid & ~broad_valid;
 
endmodule
/verilog/rx_engine/rxcntrlfifo.xco
0,0 → 1,44
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\10G\ethmac10g
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\10G\ethmac10g
SET device = xc2vp20
# SET projectname = F:\10G\ethmac10g
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg676
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET memory_type=Block_Memory
CSET write_acknowledge_flag=false
CSET data_width=8
CSET write_error_flag=false
CSET read_acknowledge_sense=Active_Low
CSET data_count_width=1
CSET fifo_depth=128
CSET component_name=rxcntrlfifo
CSET data_count=false
CSET read_acknowledge_flag=false
CSET read_error_sense=Active_Low
CSET read_error_flag=false
CSET write_acknowledge_sense=Active_Low
CSET write_error_sense=Active_Low
# END Parameters
GENERATE
 
 
/verilog/rx_engine/rxRSIO.v
0,0 → 1,133
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxRSIO ////
//// ////
//// DESCRIPTION: Datapath of Reconciliation Sublayer. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxRSIO(rxclk, rxclk_180, reset, rxd_in, rxc_in, rxd64, rxc8, local_fault, remote_fault);
input rxclk;
input rxclk_180;
input reset;
input [31:0] rxd_in;
input [3:0] rxc_in;
output [63:0] rxd64;
output [7:0] rxc8;
output local_fault;
output remote_fault;
 
parameter TP =1;
 
reg local_fault, remote_fault;
// wire get_align, get_seq;
always@(posedge rxclk or posedge reset) begin
if(reset) begin
local_fault <=#TP 0;
remote_fault <=#TP 0;
end
else begin
local_fault <=#TP (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & ~rxd_in[30] & rxd_in[31];
remote_fault<=#TP (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & rxd_in[30] & rxd_in[31];
end
end
// assign get_align = ((rxd_in[7:0]==`START) & rxc_in[0]) & ((rxd_in[15:8]==`PREAMBLE) & ~rxc_in[1]);
// assign get_seq = (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & rxd_in[31];
// assign local_fault = get_seq & ~rxd_in[30];
// assign remote_fault = get_seq & rxd_in[30];
reg[7:0] rxc8_in_tmp;
reg[63:0]rxd64_in_tmp;
// reg get_align_reg;
// always@(posedge rxclk_180 or posedge reset) begin
// if (reset)
// get_align_reg <=#TP 0;
// else if(get_align)
// get_align_reg <=#TP 1'b1;
// else
// get_align_reg <=#TP get_align_reg;
// end
always@(posedge rxclk_180) begin
if (reset)begin
rxd64_in_tmp[63:32] <=#TP 0;
rxc8_in_tmp[7:4] <=#TP 0;
end
else begin
rxd64_in_tmp[63:32] <=#TP rxd_in;
rxc8_in_tmp[7:4] <=#TP rxc_in;
end
end
always@(posedge rxclk) begin
if (reset)begin
rxd64_in_tmp[31:0] <=#TP 0;
rxc8_in_tmp[3:0] <=#TP 0;
end
else begin
rxd64_in_tmp[31:0] <=#TP rxd_in;
rxc8_in_tmp[3:0] <=#TP rxc_in;
end
end
 
reg[63:0] rxd64;
reg[7:0] rxc8;
always@(posedge rxclk) begin
// if(reset) begin
// rxc8<=#TP 0;
// rxd64 <=#TP 0;
// end
// else begin
rxc8<=#TP rxc8_in_tmp;
rxd64 <=#TP rxd64_in_tmp;
// end
end
 
 
endmodule
/verilog/rx_engine/rxdatafifo.v
0,0 → 1,107
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2004 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rxdatafifo.v when simulating
// the core, rxdatafifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module rxdatafifo(
clk,
sinit,
din,
wr_en,
rd_en,
dout,
full,
empty);
 
 
input clk;
input sinit;
input [63 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
 
// synopsys translate_off
 
SYNC_FIFO_V5_0 #(
8, // c_dcount_width
0, // c_enable_rlocs
0, // c_has_dcount
0, // c_has_rd_ack
0, // c_has_rd_err
0, // c_has_wr_ack
0, // c_has_wr_err
1, // c_memory_type
0, // c_ports_differ
1, // c_rd_ack_low
1, // c_rd_err_low
64, // c_read_data_width
128, // c_read_depth
64, // c_write_data_width
128, // c_write_depth
1, // c_wr_ack_low
1) // c_wr_err_low
inst (
.CLK(clk),
.SINIT(sinit),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_ACK(),
.WR_ACK(),
.RD_ERR(),
.WR_ERR(),
.DATA_COUNT());
 
 
// synopsys translate_on
 
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of rxdatafifo is "true"
 
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rxdatafifo is "black_box"
 
endmodule
 
/verilog/rx_engine/CRC32_D64.v
0,0 → 1,293
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////
// File: CRC32_D64.v
// Date: Sun Nov 27 19:32:12 2005
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 64
//
// Info: tools@easics.be
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
 
 
module CRC32_D64(DATA_IN, CLK, RESET, START, init, CRC_OUT);
 
input [63:0] DATA_IN;
input CLK;
input RESET;
input START;
input init;
output [31:0] CRC_OUT;
 
reg [31:0] CRC_OUT;
 
always @(posedge CLK)
begin
if (RESET) begin
// CRC_OUT = 0;
CRC_OUT = 32'hffffffff;
end
else if (init) begin
CRC_OUT = 32'hffffffff;
// CRC_OUT = 0;
end
else if (START) begin
CRC_OUT = nextCRC32_D64(DATA_IN, CRC_OUT);
end
end
 
 
// polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// data width: 64
// convention: the first serial data bit is D[63]
function [31:0] nextCRC32_D64;
 
input [63:0] Data;
input [31:0] CRC;
 
reg [63:0] D;
reg [31:0] C;
reg [31:0] NewCRC;
 
begin
 
D = Data;
C = CRC;
 
NewCRC[0] = D[63] ^ D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[54] ^ D[53] ^
D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[37] ^ D[34] ^
D[32] ^ D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^
D[24] ^ D[16] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[0] ^
C[0] ^ C[2] ^ C[5] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^
C[18] ^ C[21] ^ C[22] ^ C[23] ^ C[26] ^ C[28] ^ C[29] ^
C[31];
NewCRC[1] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^
D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[38] ^
D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[28] ^ D[27] ^ D[24] ^
D[17] ^ D[16] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[7] ^
D[6] ^ D[1] ^ D[0] ^ C[1] ^ C[2] ^ C[3] ^ C[5] ^ C[6] ^
C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^
C[24] ^ C[26] ^ C[27] ^ C[28] ^ C[30] ^ C[31];
NewCRC[2] = D[59] ^ D[58] ^ D[57] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^
D[44] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^ D[32] ^
D[31] ^ D[30] ^ D[26] ^ D[24] ^ D[18] ^ D[17] ^ D[16] ^
D[14] ^ D[13] ^ D[9] ^ D[8] ^ D[7] ^ D[6] ^ D[2] ^
D[1] ^ D[0] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^
C[12] ^ C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[25] ^ C[26] ^
C[27];
NewCRC[3] = D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[54] ^ D[53] ^ D[52] ^
D[45] ^ D[40] ^ D[39] ^ D[38] ^ D[37] ^ D[36] ^ D[33] ^
D[32] ^ D[31] ^ D[27] ^ D[25] ^ D[19] ^ D[18] ^ D[17] ^
D[15] ^ D[14] ^ D[10] ^ D[9] ^ D[8] ^ D[7] ^ D[3] ^
D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[7] ^
C[8] ^ C[13] ^ C[20] ^ C[21] ^ C[22] ^ C[24] ^ C[26] ^
C[27] ^ C[28];
NewCRC[4] = D[63] ^ D[59] ^ D[58] ^ D[57] ^ D[50] ^ D[48] ^ D[47] ^
D[46] ^ D[45] ^ D[44] ^ D[41] ^ D[40] ^ D[39] ^ D[38] ^
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[25] ^ D[24] ^ D[20] ^
D[19] ^ D[18] ^ D[15] ^ D[12] ^ D[11] ^ D[8] ^ D[6] ^
D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[1] ^ C[6] ^ C[7] ^ C[8] ^
C[9] ^ C[12] ^ C[13] ^ C[14] ^ C[15] ^ C[16] ^ C[18] ^
C[25] ^ C[26] ^ C[27] ^ C[31];
NewCRC[5] = D[63] ^ D[61] ^ D[59] ^ D[55] ^ D[54] ^ D[53] ^ D[51] ^
D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[42] ^ D[41] ^ D[40] ^
D[39] ^ D[37] ^ D[29] ^ D[28] ^ D[24] ^ D[21] ^ D[20] ^
D[19] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^
D[3] ^ D[1] ^ D[0] ^ C[5] ^ C[7] ^ C[8] ^ C[9] ^ C[10] ^
C[12] ^ C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[21] ^ C[22] ^
C[23] ^ C[27] ^ C[29] ^ C[31];
NewCRC[6] = D[62] ^ D[60] ^ D[56] ^ D[55] ^ D[54] ^ D[52] ^ D[51] ^
D[50] ^ D[47] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^ D[40] ^
D[38] ^ D[30] ^ D[29] ^ D[25] ^ D[22] ^ D[21] ^ D[20] ^
D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^ D[5] ^ D[4] ^
D[2] ^ D[1] ^ C[6] ^ C[8] ^ C[9] ^ C[10] ^ C[11] ^
C[13] ^ C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[23] ^
C[24] ^ C[28] ^ C[30];
NewCRC[7] = D[60] ^ D[58] ^ D[57] ^ D[56] ^ D[54] ^ D[52] ^ D[51] ^
D[50] ^ D[47] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[41] ^
D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[29] ^ D[28] ^ D[25] ^
D[24] ^ D[23] ^ D[22] ^ D[21] ^ D[16] ^ D[15] ^ D[10] ^
D[8] ^ D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[0] ^ C[2] ^
C[5] ^ C[7] ^ C[9] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^
C[15] ^ C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[24] ^ C[25] ^
C[26] ^ C[28];
NewCRC[8] = D[63] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[52] ^ D[51] ^
D[50] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[40] ^ D[38] ^
D[37] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[31] ^ D[28] ^
D[23] ^ D[22] ^ D[17] ^ D[12] ^ D[11] ^ D[10] ^ D[8] ^
D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^
C[5] ^ C[6] ^ C[8] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^
C[18] ^ C[19] ^ C[20] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^
C[31];
NewCRC[9] = D[61] ^ D[60] ^ D[58] ^ D[55] ^ D[53] ^ D[52] ^ D[51] ^
D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^ D[39] ^ D[38] ^
D[36] ^ D[35] ^ D[34] ^ D[33] ^ D[32] ^ D[29] ^ D[24] ^
D[23] ^ D[18] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[5] ^
D[4] ^ D[2] ^ D[1] ^ C[0] ^ C[1] ^ C[2] ^ C[3] ^ C[4] ^
C[6] ^ C[7] ^ C[9] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^
C[19] ^ C[20] ^ C[21] ^ C[23] ^ C[26] ^ C[28] ^ C[29];
NewCRC[10] = D[63] ^ D[62] ^ D[60] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^
D[52] ^ D[50] ^ D[42] ^ D[40] ^ D[39] ^ D[36] ^ D[35] ^
D[33] ^ D[32] ^ D[31] ^ D[29] ^ D[28] ^ D[26] ^ D[19] ^
D[16] ^ D[14] ^ D[13] ^ D[9] ^ D[5] ^ D[3] ^ D[2] ^
D[0] ^ C[0] ^ C[1] ^ C[3] ^ C[4] ^ C[7] ^ C[8] ^ C[10] ^
C[18] ^ C[20] ^ C[23] ^ C[24] ^ C[26] ^ C[27] ^ C[28] ^
C[30] ^ C[31];
NewCRC[11] = D[59] ^ D[58] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^ D[51] ^
D[50] ^ D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^
D[40] ^ D[36] ^ D[33] ^ D[31] ^ D[28] ^ D[27] ^ D[26] ^
D[25] ^ D[24] ^ D[20] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
D[12] ^ D[9] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[1] ^ C[4] ^
C[8] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^ C[16] ^
C[18] ^ C[19] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^ C[26] ^
C[27];
NewCRC[12] = D[63] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^ D[53] ^
D[52] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^ D[46] ^ D[42] ^
D[41] ^ D[31] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[18] ^
D[17] ^ D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[6] ^ D[5] ^
D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[9] ^ C[10] ^ C[14] ^
C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^
C[24] ^ C[25] ^ C[27] ^ C[29] ^ C[31];
NewCRC[13] = D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[54] ^ D[53] ^
D[52] ^ D[51] ^ D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[42] ^
D[32] ^ D[31] ^ D[28] ^ D[25] ^ D[22] ^ D[19] ^ D[18] ^
D[16] ^ D[14] ^ D[13] ^ D[10] ^ D[7] ^ D[6] ^ D[5] ^
D[3] ^ D[2] ^ D[1] ^ C[0] ^ C[10] ^ C[11] ^ C[15] ^
C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^
C[25] ^ C[26] ^ C[28] ^ C[30];
NewCRC[14] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[55] ^ D[54] ^
D[53] ^ D[52] ^ D[51] ^ D[49] ^ D[48] ^ D[44] ^ D[43] ^
D[33] ^ D[32] ^ D[29] ^ D[26] ^ D[23] ^ D[20] ^ D[19] ^
D[17] ^ D[15] ^ D[14] ^ D[11] ^ D[8] ^ D[7] ^ D[6] ^
D[4] ^ D[3] ^ D[2] ^ C[0] ^ C[1] ^ C[11] ^ C[12] ^
C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^
C[24] ^ C[26] ^ C[27] ^ C[29] ^ C[31];
NewCRC[15] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[56] ^ D[55] ^ D[54] ^
D[53] ^ D[52] ^ D[50] ^ D[49] ^ D[45] ^ D[44] ^ D[34] ^
D[33] ^ D[30] ^ D[27] ^ D[24] ^ D[21] ^ D[20] ^ D[18] ^
D[16] ^ D[15] ^ D[12] ^ D[9] ^ D[8] ^ D[7] ^ D[5] ^
D[4] ^ D[3] ^ C[1] ^ C[2] ^ C[12] ^ C[13] ^ C[17] ^
C[18] ^ C[20] ^ C[21] ^ C[22] ^ C[23] ^ C[24] ^ C[25] ^
C[27] ^ C[28] ^ C[30];
NewCRC[16] = D[57] ^ D[56] ^ D[51] ^ D[48] ^ D[47] ^ D[46] ^ D[44] ^
D[37] ^ D[35] ^ D[32] ^ D[30] ^ D[29] ^ D[26] ^ D[24] ^
D[22] ^ D[21] ^ D[19] ^ D[17] ^ D[13] ^ D[12] ^ D[8] ^
D[5] ^ D[4] ^ D[0] ^ C[0] ^ C[3] ^ C[5] ^ C[12] ^ C[14] ^
C[15] ^ C[16] ^ C[19] ^ C[24] ^ C[25];
NewCRC[17] = D[58] ^ D[57] ^ D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[45] ^
D[38] ^ D[36] ^ D[33] ^ D[31] ^ D[30] ^ D[27] ^ D[25] ^
D[23] ^ D[22] ^ D[20] ^ D[18] ^ D[14] ^ D[13] ^ D[9] ^
D[6] ^ D[5] ^ D[1] ^ C[1] ^ C[4] ^ C[6] ^ C[13] ^ C[15] ^
C[16] ^ C[17] ^ C[20] ^ C[25] ^ C[26];
NewCRC[18] = D[59] ^ D[58] ^ D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[46] ^
D[39] ^ D[37] ^ D[34] ^ D[32] ^ D[31] ^ D[28] ^ D[26] ^
D[24] ^ D[23] ^ D[21] ^ D[19] ^ D[15] ^ D[14] ^ D[10] ^
D[7] ^ D[6] ^ D[2] ^ C[0] ^ C[2] ^ C[5] ^ C[7] ^ C[14] ^
C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[26] ^ C[27];
NewCRC[19] = D[60] ^ D[59] ^ D[54] ^ D[51] ^ D[50] ^ D[49] ^ D[47] ^
D[40] ^ D[38] ^ D[35] ^ D[33] ^ D[32] ^ D[29] ^ D[27] ^
D[25] ^ D[24] ^ D[22] ^ D[20] ^ D[16] ^ D[15] ^ D[11] ^
D[8] ^ D[7] ^ D[3] ^ C[0] ^ C[1] ^ C[3] ^ C[6] ^ C[8] ^
C[15] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[27] ^ C[28];
NewCRC[20] = D[61] ^ D[60] ^ D[55] ^ D[52] ^ D[51] ^ D[50] ^ D[48] ^
D[41] ^ D[39] ^ D[36] ^ D[34] ^ D[33] ^ D[30] ^ D[28] ^
D[26] ^ D[25] ^ D[23] ^ D[21] ^ D[17] ^ D[16] ^ D[12] ^
D[9] ^ D[8] ^ D[4] ^ C[1] ^ C[2] ^ C[4] ^ C[7] ^ C[9] ^
C[16] ^ C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[28] ^ C[29];
NewCRC[21] = D[62] ^ D[61] ^ D[56] ^ D[53] ^ D[52] ^ D[51] ^ D[49] ^
D[42] ^ D[40] ^ D[37] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^
D[27] ^ D[26] ^ D[24] ^ D[22] ^ D[18] ^ D[17] ^ D[13] ^
D[10] ^ D[9] ^ D[5] ^ C[2] ^ C[3] ^ C[5] ^ C[8] ^ C[10] ^
C[17] ^ C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[29] ^ C[30];
NewCRC[22] = D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^
D[48] ^ D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^
D[37] ^ D[36] ^ D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^
D[26] ^ D[24] ^ D[23] ^ D[19] ^ D[18] ^ D[16] ^ D[14] ^
D[12] ^ D[11] ^ D[9] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^
C[5] ^ C[6] ^ C[9] ^ C[11] ^ C[12] ^ C[13] ^ C[15] ^
C[16] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^ C[29] ^
C[30];
NewCRC[23] = D[62] ^ D[60] ^ D[59] ^ D[56] ^ D[55] ^ D[54] ^ D[50] ^
D[49] ^ D[47] ^ D[46] ^ D[42] ^ D[39] ^ D[38] ^ D[36] ^
D[35] ^ D[34] ^ D[31] ^ D[29] ^ D[27] ^ D[26] ^ D[20] ^
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[13] ^ D[9] ^ D[6] ^
D[1] ^ D[0] ^ C[2] ^ C[3] ^ C[4] ^ C[6] ^ C[7] ^ C[10] ^
C[14] ^ C[15] ^ C[17] ^ C[18] ^ C[22] ^ C[23] ^ C[24] ^
C[27] ^ C[28] ^ C[30];
NewCRC[24] = D[63] ^ D[61] ^ D[60] ^ D[57] ^ D[56] ^ D[55] ^ D[51] ^
D[50] ^ D[48] ^ D[47] ^ D[43] ^ D[40] ^ D[39] ^ D[37] ^
D[36] ^ D[35] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[21] ^
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[14] ^ D[10] ^ D[7] ^
D[2] ^ D[1] ^ C[0] ^ C[3] ^ C[4] ^ C[5] ^ C[7] ^ C[8] ^
C[11] ^ C[15] ^ C[16] ^ C[18] ^ C[19] ^ C[23] ^ C[24] ^
C[25] ^ C[28] ^ C[29] ^ C[31];
NewCRC[25] = D[62] ^ D[61] ^ D[58] ^ D[57] ^ D[56] ^ D[52] ^ D[51] ^
D[49] ^ D[48] ^ D[44] ^ D[41] ^ D[40] ^ D[38] ^ D[37] ^
D[36] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[22] ^ D[21] ^
D[19] ^ D[18] ^ D[17] ^ D[15] ^ D[11] ^ D[8] ^ D[3] ^
D[2] ^ C[1] ^ C[4] ^ C[5] ^ C[6] ^ C[8] ^ C[9] ^ C[12] ^
C[16] ^ C[17] ^ C[19] ^ C[20] ^ C[24] ^ C[25] ^ C[26] ^
C[29] ^ C[30];
NewCRC[26] = D[62] ^ D[61] ^ D[60] ^ D[59] ^ D[57] ^ D[55] ^ D[54] ^
D[52] ^ D[49] ^ D[48] ^ D[47] ^ D[44] ^ D[42] ^ D[41] ^
D[39] ^ D[38] ^ D[31] ^ D[28] ^ D[26] ^ D[25] ^ D[24] ^
D[23] ^ D[22] ^ D[20] ^ D[19] ^ D[18] ^ D[10] ^ D[6] ^
D[4] ^ D[3] ^ D[0] ^ C[6] ^ C[7] ^ C[9] ^ C[10] ^ C[12] ^
C[15] ^ C[16] ^ C[17] ^ C[20] ^ C[22] ^ C[23] ^ C[25] ^
C[27] ^ C[28] ^ C[29] ^ C[30];
NewCRC[27] = D[63] ^ D[62] ^ D[61] ^ D[60] ^ D[58] ^ D[56] ^ D[55] ^
D[53] ^ D[50] ^ D[49] ^ D[48] ^ D[45] ^ D[43] ^ D[42] ^
D[40] ^ D[39] ^ D[32] ^ D[29] ^ D[27] ^ D[26] ^ D[25] ^
D[24] ^ D[23] ^ D[21] ^ D[20] ^ D[19] ^ D[11] ^ D[7] ^
D[5] ^ D[4] ^ D[1] ^ C[0] ^ C[7] ^ C[8] ^ C[10] ^ C[11] ^
C[13] ^ C[16] ^ C[17] ^ C[18] ^ C[21] ^ C[23] ^ C[24] ^
C[26] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
NewCRC[28] = D[63] ^ D[62] ^ D[61] ^ D[59] ^ D[57] ^ D[56] ^ D[54] ^
D[51] ^ D[50] ^ D[49] ^ D[46] ^ D[44] ^ D[43] ^ D[41] ^
D[40] ^ D[33] ^ D[30] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^
D[24] ^ D[22] ^ D[21] ^ D[20] ^ D[12] ^ D[8] ^ D[6] ^
D[5] ^ D[2] ^ C[1] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^
C[14] ^ C[17] ^ C[18] ^ C[19] ^ C[22] ^ C[24] ^ C[25] ^
C[27] ^ C[29] ^ C[30] ^ C[31];
NewCRC[29] = D[63] ^ D[62] ^ D[60] ^ D[58] ^ D[57] ^ D[55] ^ D[52] ^
D[51] ^ D[50] ^ D[47] ^ D[45] ^ D[44] ^ D[42] ^ D[41] ^
D[34] ^ D[31] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[25] ^
D[23] ^ D[22] ^ D[21] ^ D[13] ^ D[9] ^ D[7] ^ D[6] ^
D[3] ^ C[2] ^ C[9] ^ C[10] ^ C[12] ^ C[13] ^ C[15] ^
C[18] ^ C[19] ^ C[20] ^ C[23] ^ C[25] ^ C[26] ^ C[28] ^
C[30] ^ C[31];
NewCRC[30] = D[63] ^ D[61] ^ D[59] ^ D[58] ^ D[56] ^ D[53] ^ D[52] ^
D[51] ^ D[48] ^ D[46] ^ D[45] ^ D[43] ^ D[42] ^ D[35] ^
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[26] ^ D[24] ^
D[23] ^ D[22] ^ D[14] ^ D[10] ^ D[8] ^ D[7] ^ D[4] ^
C[0] ^ C[3] ^ C[10] ^ C[11] ^ C[13] ^ C[14] ^ C[16] ^
C[19] ^ C[20] ^ C[21] ^ C[24] ^ C[26] ^ C[27] ^ C[29] ^
C[31];
NewCRC[31] = D[62] ^ D[60] ^ D[59] ^ D[57] ^ D[54] ^ D[53] ^ D[52] ^
D[49] ^ D[47] ^ D[46] ^ D[44] ^ D[43] ^ D[36] ^ D[33] ^
D[31] ^ D[30] ^ D[29] ^ D[28] ^ D[27] ^ D[25] ^ D[24] ^
D[23] ^ D[15] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ C[1] ^
C[4] ^ C[11] ^ C[12] ^ C[14] ^ C[15] ^ C[17] ^ C[20] ^
C[21] ^ C[22] ^ C[25] ^ C[27] ^ C[28] ^ C[30];
 
nextCRC32_D64 = NewCRC;
 
end
 
endfunction
endmodule
/verilog/rx_engine/rxReceiveEngine.ucf
0,0 → 1,24
#AREA_GROUP "AG_counters" RANGE = SLICE_X34Y37:SLICE_X41Y32
#INST "counters" AREA_GROUP = "AG_counters"
#AREA_GROUP "AG_crcmodule" RANGE = SLICE_X32Y21:SLICE_X49Y4
#INST "crcmodule" AREA_GROUP = "AG_crcmodule"
#AREA_GROUP "AG_datapath_main" RANGE = SLICE_X14Y35:SLICE_X29Y20
#INST "datapath_main" AREA_GROUP = "AG_datapath_main"
#AREA_GROUP "AG_lenchecker" RANGE = SLICE_X44Y37:SLICE_X51Y30
#INST "lenchecker" AREA_GROUP = "AG_lenchecker"
#AREA_GROUP "AG_rx_rs" RANGE = SLICE_X0Y31:SLICE_X9Y20
#INST "rx_rs" AREA_GROUP = "AG_rx_rs"
#AREA_GROUP "AG_rx_stat" RANGE = SLICE_X46Y27:SLICE_X49Y24
#INST "rx_stat" AREA_GROUP = "AG_rx_stat"
#AREA_GROUP "AG_statemachine" RANGE = SLICE_X34Y27:SLICE_X41Y24
#INST "statemachine" AREA_GROUP = "AG_statemachine"
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
#PACE: Start of PACE Area Constraints
AREA_GROUP "AG_rxReceiveEngine" RANGE = SLICE_X2Y37:SLICE_X33Y2 ;
INST "/" AREA_GROUP = "AG_rxReceiveEngine" ;
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
NET "rxclk_in" TNM_NET = "rxclk_in";
TIMESPEC "TS_rxclk_in" = PERIOD "rxclk_in" 6.5 ns HIGH 50 %;
#OFFSET = IN 2 ns BEFORE "rxclk_in" HIGH ;
/verilog/rx_engine/rxStatModule.v
0,0 → 1,182
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxStatModule ////
//// ////
//// DESCRIPTION: Generate signals for statistics. These signals ////
//// will be used in Management Module. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxStatModule(rxclk, reset, good_frame_get,crc_check_invalid, large_error, small_error,
receiving, padded_frame, pause_frame, broad_valid, multi_valid,
length_65_127, length_128_255, length_256_511, length_512_1023, length_1024_max,
jumbo_frame, get_error_code, rxStatRegPlus);
 
input rxclk;
input reset;
input good_frame_get;
input large_error;
input small_error;
input crc_check_invalid;
input receiving;
input padded_frame;
input pause_frame;
input broad_valid;
input multi_valid;
input length_65_127;
input length_128_255;
input length_256_511;
input length_512_1023;
input length_1024_max;
input jumbo_frame;
input get_error_code;
output [17:0] rxStatRegPlus;
 
parameter TP =1;
 
wire[17:0] rxStatRegPlus_tmp;
 
////////////////////////////////////////////
// Count for Frames Received OK
////////////////////////////////////////////
assign rxStatRegPlus_tmp[0] = good_frame_get;
 
////////////////////////////////////////////
// Count for FCS check error
////////////////////////////////////////////
assign rxStatRegPlus_tmp[1] = crc_check_invalid;
 
////////////////////////////////////////////
// Count for BroadCast Frame Received OK
////////////////////////////////////////////
assign rxStatRegPlus_tmp[2] = broad_valid & good_frame_get;
 
/////////////////////////////////////////////
// Count for Multicast Frame Received OK
/////////////////////////////////////////////
assign rxStatRegPlus_tmp[3] = multi_valid & good_frame_get;
 
////////////////////////////////////////////
// Count for 64 byte Frame Received OK
////////////////////////////////////////////
assign rxStatRegPlus_tmp[4] = padded_frame & good_frame_get;
 
////////////////////////////////////////////
// Count for 65-127 byte Frames Received OK
////////////////////////////////////////////
assign rxStatRegPlus_tmp[5] = length_65_127 & good_frame_get;
 
////////////////////////////////////////////
// Count for 128-255 byte Frames Received OK
////////////////////////////////////////////
assign rxStatRegPlus_tmp[6] = length_128_255 & good_frame_get;
 
////////////////////////////////////////////
// Count for 256-511 byte Frames Received OK
////////////////////////////////////////////
assign rxStatRegPlus_tmp[7] = length_256_511 & good_frame_get;
 
//////////////////////////////////////////////
// Count for 512-1023 byte Frames Received OK
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[8] = length_512_1023 & good_frame_get;
 
//////////////////////////////////////////////
// Count for 1024-1518 byte Frames Received OK
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[9] = length_1024_max & good_frame_get;
 
//////////////////////////////////////////////
// Count for Control Frames Received OK
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[10] = pause_frame & good_frame_get;
 
//////////////////////////////////////////////
// Count for Length/Type Out of Range
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[11] = large_error;
 
//////////////////////////////////////////////
// Count for Pause Frames Received OK
//////////////////////////////////////////////
assign rxStatRegPlus_tmp[12] = pause_frame & good_frame_get;
 
/////////////////////////////////////////////////////////////
// Count for Control Frames Received with Unsupported Opcode.
/////////////////////////////////////////////////////////////
// assign rxStatRegPlus_tmp[13] = pause_frame & good_frame_get;
 
///////////////////////////////////////////////
// Count for Oversize Frames Received OK
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[14] = jumbo_frame & good_frame_get;
 
///////////////////////////////////////////////
// Count for Undersized Frames Received
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[15] = small_error;
 
///////////////////////////////////////////////
// Count for Fragment Frames Received
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[16] = receiving & get_error_code;
 
///////////////////////////////////////////////
// Count for Number of Bytes Received
///////////////////////////////////////////////
assign rxStatRegPlus_tmp[17] = receiving;
 
reg[17:0] rxStatRegPlus;
always@(posedge rxclk or posedge reset) begin
if(reset)
rxStatRegPlus <=#TP 0;
else
rxStatRegPlus <=#TP rxStatRegPlus_tmp;
end
 
endmodule
/verilog/rx_engine/rxRSLayer.v
0,0 → 1,85
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxRSLayer ////
//// ////
//// DESCRIPTION: Reconciliation SubLayer of 10 Gigabit Ethernet. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxRSLayer(rxclk, rxclk_180, reset, link_fault, rxd64, rxc8, rxd_in, rxc_in);
input rxclk;
input rxclk_180;
input reset;
input [31:0] rxd_in;
input [3:0] rxc_in;
output [1:0] link_fault;
output [63:0] rxd64;
output [7:0] rxc8;
 
wire local_fault;
wire remote_fault;
wire[1:0] link_fault;
 
rxRSIO datapath(.rxclk(rxclk),
.rxclk_180(rxclk_180),
.reset(reset),
.rxd_in(rxd_in),
.rxc_in(rxc_in),
.rxd64(rxd64),
.rxc8(rxc8),
.local_fault(local_fault),
.remote_fault(remote_fault)
);
rxLinkFaultState statemachine(.rxclk(rxclk_180),
.reset(reset),
.local_fault(local_fault),
.remote_fault(remote_fault),
.link_fault(link_fault)
);
 
endmodule
/verilog/rx_engine/rxDataPath.v
0,0 → 1,450
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: Data Path of Receive Module ////
//// ////
//// DESCRIPTION: Data path of Receive Engine of 10 Gigabit ////
//// Ethernet MAC. Used to recognize every field of a ////
//// frame, including SOF, EOF, Length, Destination Addr ////
//// , Source Addr and Data field. ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxDataPath(rxclk, reset, rxd64, rxc8, inband_fcs, receiving, start_da, start_lt, wait_crc_check, get_sfd,
get_terminator, get_error_code, tagged_frame, pause_frame, da_addr, terminator_location, CRC_DATA,
rx_data_valid, rx_data,get_terminator_d1, bad_frame_get, good_frame_get,check_reset,rx_good_frame,rx_bad_frame);
// fcTxPauseData);
input rxclk;
input reset;
input [63:0] rxd64;
input [7:0] rxc8;
input inband_fcs;
input receiving;
input start_da;
input start_lt;
input wait_crc_check;
input get_terminator_d1;
input bad_frame_get;
input good_frame_get;
output get_sfd;
output get_terminator; //get T indicator
output get_error_code; //get Error indicator
output tagged_frame;
output pause_frame;
output[47:0] da_addr;
output[2:0] terminator_location;
output[63:0] CRC_DATA;
output[7:0] rx_data_valid;
output[63:0] rx_data;
output check_reset;
output rx_good_frame;
output rx_bad_frame;
// output [31:0]fcTxPauseData;
parameter TP = 1;
parameter IDLE = 0, READ = 1, WAIT_TMP = 2, WAIT = 3;
//////////////////////////////////////////////
// Pipe Line Stage
//////////////////////////////////////////////
reg [63:0] rxd64_d1,rxd64_d2,rxd64_d3,CRC_DATA;
reg [7:0] rxc8_d1, rxc8_d2, rxc8_d3;
reg receiving_d1, receiving_d2;
reg wait_crc_check_d1;
// assign fcTxPauseData = rxd64_d1[31:0];
// Data pipeline
always@(posedge rxclk or posedge reset) begin
if (reset) begin
rxd64_d1<=#TP 0;
rxd64_d2<=#TP 0;
rxd64_d3<=#TP 0;
CRC_DATA<=0;
end
else begin
rxd64_d1<=#TP rxd64;
rxd64_d2<=#TP rxd64_d1;
rxd64_d3<=#TP rxd64_d2;
CRC_DATA <={rxd64_d2[0],rxd64_d2[1],rxd64_d2[2],rxd64_d2[3],rxd64_d2[4],rxd64_d2[5],rxd64_d2[6],rxd64_d2[7],
rxd64_d2[8],rxd64_d2[9],rxd64_d2[10],rxd64_d2[11],rxd64_d2[12],rxd64_d2[13],rxd64_d2[14],rxd64_d2[15],
rxd64_d2[16],rxd64_d2[17],rxd64_d2[18],rxd64_d2[19],rxd64_d2[20],rxd64_d2[21],rxd64_d2[22],rxd64_d2[23],
rxd64_d2[24],rxd64_d2[25],rxd64_d2[26],rxd64_d2[27],rxd64_d2[28],rxd64_d2[29],rxd64_d2[30],rxd64_d2[31],
rxd64_d2[32],rxd64_d2[33],rxd64_d2[34],rxd64_d2[35],rxd64_d2[36],rxd64_d2[37],rxd64_d2[38],rxd64_d2[39],
rxd64_d2[40],rxd64_d2[41],rxd64_d2[42],rxd64_d2[43],rxd64_d2[44],rxd64_d2[45],rxd64_d2[46],rxd64_d2[47],
rxd64_d2[48],rxd64_d2[49],rxd64_d2[50],rxd64_d2[51],rxd64_d2[52],rxd64_d2[53],rxd64_d2[54],rxd64_d2[55],
rxd64_d2[56],rxd64_d2[57],rxd64_d2[58],rxd64_d2[59],rxd64_d2[60],rxd64_d2[61],rxd64_d2[62],rxd64_d2[63]};
end
end
//control pipeline
always@(posedge rxclk or posedge reset)begin
if (reset) begin
rxc8_d1<=#TP 0;
rxc8_d2<=#TP 0;
rxc8_d3<=#TP 0;
end
else begin
rxc8_d1<=#TP rxc8;
rxc8_d2<=#TP rxc8_d1;
rxc8_d3<=#TP rxc8_d2;
end
end
always @(posedge rxclk or posedge reset)begin
if (reset) begin
receiving_d1 <=#TP 0;
receiving_d2 <=#TP 0;
wait_crc_check_d1 <=#TP 0;
end
else begin
receiving_d1 <=#TP receiving;
receiving_d2 <=#TP receiving_d1;
wait_crc_check_d1 <=#TP wait_crc_check;
end
end
////////////////////////////////////////////
// Frame analysis
////////////////////////////////////////////
reg get_sfd; //get sfd indicator
reg get_terminator; //get T indicator
reg get_error_code; //get Error indicator
reg[7:0] get_e_chk;
reg[7:0] rxc_end_data; //seperate DATA with FCS
reg [2:0]terminator_location; //for n*8bits(n<8), get n
reg[47:0] da_addr; //get Desetination Address
reg tagged_frame; //Tagged frame indicator(type interpret)
reg pause_frame; //Pause frame indicator(type interpret)
//1. SFD
always@(posedge rxclk or posedge reset) begin
if (reset)
get_sfd <=#TP 0;
else
get_sfd <=#TP (rxd64[7:0] ==`START) & (rxd64[63:56]== `SFD) & (rxc8 == 8'h01);
end
 
//2. EFD
reg this_cycle;
// -----------------------------------------------
//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
// -----------------------------------------------
//|<-------- EFD -------->|<-------- EFD -------->|
//|<-- this_cycle = '1' ->|<-- this_cycle = '0' ->|
always@(posedge rxclk or posedge reset) begin
if (reset) begin
get_terminator <=#TP 0;
terminator_location <=#TP 0;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 0;
end
else begin
if (rxc8[0] & (rxd64[7:0] ==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 0;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b00001111;
end
else if (rxc8[1] & (rxd64[15:8] ==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 1;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b00011111;
end
else if (rxc8[2] & (rxd64[23:16]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 2;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b00111111;
end
else if (rxc8[3] & (rxd64[31:24]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 3;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b01111111;
end
else if (rxc8[4] & (rxd64[39:32]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 4;
this_cycle <=#TP 1'b1;
rxc_end_data <=#TP 8'b11111111;
end
else if (rxc8[5] & (rxd64[47:40]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 5;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 8'b00000001;
end
else if (rxc8[6] & (rxd64[55:48]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 6;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 8'b00000011;
end
else if (rxc8[7] & (rxd64[63:56]==`TERMINATE)) begin
get_terminator <=#TP 1'b1;
terminator_location <=#TP 7;
this_cycle <=#TP 1'b0;
rxc_end_data <=#TP 8'b00000111;
end
else begin
get_terminator <=#TP 1'b0;
terminator_location <=#TP terminator_location;
this_cycle <=#TP this_cycle;
rxc_end_data <=#TP rxc_end_data;
end
end
end
//3. Error Character
always@(posedge rxclk or posedge reset) begin
if (reset)
get_e_chk <=#TP 0;
else begin
get_e_chk[0] <=#TP rxc8[0] & (rxd64[7:0] ==`ERROR);
get_e_chk[1] <=#TP rxc8[1] & (rxd64[15:8] ==`ERROR);
get_e_chk[2] <=#TP rxc8[2] & (rxd64[23:16]==`ERROR);
get_e_chk[3] <=#TP rxc8[3] & (rxd64[31:24]==`ERROR);
get_e_chk[4] <=#TP rxc8[4] & (rxd64[39:32]==`ERROR);
get_e_chk[5] <=#TP rxc8[5] & (rxd64[47:40]==`ERROR);
get_e_chk[6] <=#TP rxc8[6] & (rxd64[55:48]==`ERROR);
get_e_chk[7] <=#TP rxc8[7] & (rxd64[63:56]==`ERROR);
end
end
always@(posedge rxclk or posedge reset) begin
if (reset)
get_error_code <=#TP 0;
else
get_error_code <=#TP receiving & (| get_e_chk);
end
//////////////////////////////////////
// Get Destination Address
//////////////////////////////////////
always@(posedge rxclk or posedge reset)begin
if (reset)
da_addr <=#TP 0;
else if (start_da)
da_addr <=#TP rxd64_d1[47:0];
else
da_addr <=#TP da_addr;
end
 
//////////////////////////////////////
// Get Length/Type Field
//////////////////////////////////////
 
// reg[15:0] lt_data;
// always@(posedge rxclk or posedge reset)begin
// if (reset)
// lt_data <=#TP 0;
// else if (start_lt)
// lt_data <=#TP rxd64_d1[47:32];
// else
// lt_data <=#TP lt_data;
// end
 
//tagged frame indicator
always@(posedge rxclk or posedge reset) begin
if (reset)
tagged_frame <=#TP 1'b0;
else if (start_lt)
tagged_frame <=#TP (rxd64[63:32] == `TAG_SIGN);
else
tagged_frame <=#TP tagged_frame;
end
//pause frame indicator
always@(posedge rxclk or posedge reset) begin
if (reset)
pause_frame <=#TP 1'b0;
else if (start_lt)
pause_frame <=#TP (rxd64[47:32] == `PAUSE_SIGN);
else
pause_frame <=#TP 1'b0;
end
 
/////////////////////////////////////////////
// Generate proper rxc to FIFO
/////////////////////////////////////////////
 
reg [7:0]rxc_final;
wire [7:0]rxc_fifo; //rxc send to fifo
always@(posedge rxclk or posedge reset) begin
if (reset)
rxc_final <=#TP 0;
else if (get_terminator & this_cycle)
rxc_final <=#TP rxc_end_data;
else if (get_terminator_d1 & ~this_cycle)
rxc_final <=#TP rxc_end_data;
else if (receiving)
rxc_final <=`ALLONES8;
else
rxc_final <=0;
end
 
assign rxc_fifo = inband_fcs? ~rxc8_d3:rxc_final;
////////////////////////////////////////////////////////////////
// FIFO management, to generate rx_good_frame/rx_bad_frame
// after a frame has been totally received.
////////////////////////////////////////////////////////////////
wire rxfifo_full;
wire rxfifo_empty;
wire fifo_wr_en;
wire [63:0] rx_data_tmp;
wire [7:0] rx_data_valid_tmp;
reg one_frame_end;
always@(posedge rxclk or posedge reset) begin
if(reset)
one_frame_end <= 1'b0;
else if(rx_data_valid_tmp!=8'hff)
one_frame_end <= 1'b1;
else
one_frame_end <= 1'b0;
end
reg fifo_rd_en;
reg[1:0] fifo_state;
reg rx_good_frame;
reg rx_bad_frame;
reg check_reset;
always@(posedge rxclk or posedge reset) begin
if(reset) begin
fifo_rd_en <= 1'b0;
fifo_state <= IDLE;
rx_good_frame <= 1'b0;
rx_bad_frame <= 1'b0;
check_reset <= 1'b0;
end
else
case (fifo_state)
IDLE: begin
rx_good_frame <= 1'b0;
rx_bad_frame <= 1'b0;
check_reset <= 1'b0;
fifo_state <= IDLE;
fifo_rd_en <= 1'b0;
if(~rxfifo_empty) begin
fifo_rd_en <= 1'b1;
fifo_state <= READ;
end
end
READ: begin
check_reset <= 1'b0;
fifo_rd_en <= 1'b1;
rx_good_frame <= 1'b0;
rx_bad_frame <= 1'b0;
fifo_state <= READ;
if(rx_data_valid_tmp!=8'hff)
fifo_state <= WAIT_TMP;
end
WAIT_TMP: begin
if(rx_data_valid_tmp!=8'hff)
fifo_state <= WAIT;
end
WAIT: begin
rx_good_frame <= 1'b0;
rx_bad_frame <= 1'b0;
fifo_state <= WAIT;
check_reset <= 1'b0;
fifo_rd_en <= 1'b0;
if(bad_frame_get | good_frame_get)begin
rx_good_frame <= good_frame_get;
rx_bad_frame <= bad_frame_get;
fifo_state <= IDLE;
check_reset <= 1'b1;
end
end
endcase
end
 
assign fifo_wr_en = receiving_d2;
rxdatafifo rxdatain(.clk(rxclk),
.sinit(reset),
.din(rxd64_d3),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dout(rx_data_tmp),
.full(rxfifo_full),
.empty(rxfifo_empty));
 
rxcntrlfifo rxcntrlin(.clk(rxclk),
.sinit(reset),
.din(rxc_fifo),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dout(rx_data_valid_tmp),
.full(),
.empty());
reg fifo_rd_en_d1;
always@(posedge rxclk) begin
fifo_rd_en_d1 <=#TP fifo_rd_en;
end
reg [63:0] rx_data;
always@(posedge rxclk or posedge reset) begin
if (reset)
rx_data <= 0;
else
rx_data <=#TP rx_data_tmp;
end
reg [7:0] rx_data_valid;
always@(posedge rxclk or posedge reset) begin
if (reset)
rx_data_valid <=#TP 0;
else
rx_data_valid <=#TP rx_data_valid_tmp;
end
endmodule
/verilog/rx_engine/rxcntrlfifo.v
0,0 → 1,107
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2004 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rxcntrlfifo.v when simulating
// the core, rxcntrlfifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module rxcntrlfifo(
clk,
sinit,
din,
wr_en,
rd_en,
dout,
full,
empty);
 
 
input clk;
input sinit;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
 
// synopsys translate_off
 
SYNC_FIFO_V5_0 #(
1, // c_dcount_width
0, // c_enable_rlocs
0, // c_has_dcount
0, // c_has_rd_ack
0, // c_has_rd_err
0, // c_has_wr_ack
0, // c_has_wr_err
1, // c_memory_type
0, // c_ports_differ
1, // c_rd_ack_low
1, // c_rd_err_low
8, // c_read_data_width
128, // c_read_depth
8, // c_write_data_width
128, // c_write_depth
1, // c_wr_ack_low
1) // c_wr_err_low
inst (
.CLK(clk),
.SINIT(sinit),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_ACK(),
.WR_ACK(),
.RD_ERR(),
.WR_ERR(),
.DATA_COUNT());
 
 
// synopsys translate_on
 
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of rxcntrlfifo is "true"
 
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rxcntrlfifo is "black_box"
 
endmodule
 
/verilog/rx_engine/rxLinkFaultState.v
0,0 → 1,160
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxLinkFaultState ////
//// ////
//// DESCRIPTION: State machine for Link Fault Signalling. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxLinkFaultState(rxclk, reset, local_fault, remote_fault, link_fault);
input rxclk;
input reset;
input local_fault;
input remote_fault;
output[1:0] link_fault;
parameter TP =1;
parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;
 
//------------------------------------------------
// Link Fault Signalling Statemachine
//------------------------------------------------
wire fault_type;
wire get_one_fault;
wire no_new_type;
 
reg[2:0] linkstate, linkstate_next;
reg[5:0] col_cnt;
reg seq_cnt;
reg[1:0] seq_type;
reg[1:0] last_seq_type;
reg[1:0] link_fault;
reg reset_col_cnt;
wire seq_cnt_3;
wire col_cnt_64;
 
assign fault_type = {local_fault, remote_fault};
assign get_one_fault = local_fault | remote_fault;
assign no_new_type = (seq_type == last_seq_type);
assign col_cnt_64 = & col_cnt;
always@(posedge rxclk or posedge reset)begin
if (reset) begin
seq_type <=#TP 0;
seq_cnt <=#TP 0;
last_seq_type <=#TP 0;
reset_col_cnt<= #TP 1;
link_fault <=#TP 2'b00;
linkstate<= #TP IDLE;
end
else begin
seq_type <= #TP fault_type;
last_seq_type <=#TP seq_type;
case (linkstate)
IDLE: begin
linkstate <=#TP IDLE;
reset_col_cnt <= #TP 1;
seq_cnt <= #TP 0;
link_fault <= #TP 2'b00;
if (get_one_fault)
linkstate<=#TP LinkFaultDetect;
end
 
LinkFaultDetect: begin
linkstate <=#TP LinkFaultDetect;
reset_col_cnt <=#TP 1;
if (get_one_fault & no_new_type) begin
if (seq_cnt) begin
linkstate <=#TP IDLE;
link_fault <=#TP seq_type; //final fault indeed(equals to GetFault status)
end
else
seq_cnt <=#TP seq_cnt + 1;
end
else if(~get_one_fault) begin
reset_col_cnt <=#TP 0;
if (col_cnt_64)
linkstate <=#TP IDLE;
end
else if(get_one_fault & ~no_new_type)
linkstate <=#TP NewFaultType;
end
 
NewFaultType: begin
seq_cnt <=#TP 0;
linkstate <=#TP LinkFaultDetect;
reset_col_cnt<=#TP 1;
end
 
// GetFault: begin
// linkstate <=#TP IDLE;
// reset_col_cnt <=#TP 1;
// link_fault <=#TP seq_type;
// if (get_one_fault & no_new_type)
// link_fault <=#TP seq_type;
// else if (~get_one_fault) begin
// reset_col_cnt<=#TP 0;
// if(col_cnt_128)
// linkstate <=#TP IDLE;
// end
// else if (get_one_fault & ~no_new_type)
// linkstate <=#TP NewFaultType;
// end
endcase
end
end
 
always@(posedge rxclk or posedge reset) begin
if (reset)
col_cnt <=#TP 0;
else if (reset_col_cnt)
col_cnt <=#TP 0;
else
col_cnt <=#TP col_cnt + 1;
end
 
endmodule
/verilog/rx_engine/timescale.v
0,0 → 1,48
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: timescale.v ////
//// ////
//// DESCRIPTION: ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
`timescale 100ps / 10ps
/verilog/rx_engine/CRC32_D8.v
0,0 → 1,136
`timescale 1ns / 1ps
module CRC32_D8(DATA_IN, CLK, RESET, START, LOAD, CRC_IN, CRC_OUT);
 
input [7:0] DATA_IN;
input CLK;
input RESET;
input START;
input LOAD;
input [31:0] CRC_IN;
output [31:0] CRC_OUT;
 
reg [31:0] CRC_OUT;
// reg start_int;
// reg [7:0] data_int;
//always @(posedge CLK)
//begin
// start_int <= START;
// data_int <= DATA_IN;
//end
 
always @(posedge CLK or posedge RESET)
begin
if (RESET) begin
CRC_OUT <= 0;
end
else if (START) begin
CRC_OUT <= nextCRC32_D8(DATA_IN, CRC_OUT);
end
else if (LOAD) begin
CRC_OUT <= CRC_IN;
end
 
end
 
 
///////////////////////////////////////////////////////////////////////
// File: CRC32_D64.v
// Date: Sun Nov 27 19:32:12 2005
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 64
//
// Info: tools@easics.be
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
 
// polynomial: (0 1 2 3 4 5 7 8 10 11 12 16 22 23 26 32)
// data width: 8
// convention: the first serial data bit is D[7]
function [31:0] nextCRC32_D8;
 
input [7:0] Data;
input [31:0] CRC;
 
reg [7:0] D;
reg [31:0] C;
reg [31:0] NewCRC;
 
begin
 
D = Data;
C = CRC;
 
NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^
C[31];
NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^
C[26] ^ C[30] ^ C[31];
NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^
C[31];
NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
C[27] ^ C[28] ^ C[30];
NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^
C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^
C[28] ^ C[29] ^ C[30] ^ C[31];
NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^
C[27] ^ C[29] ^ C[31];
NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^
C[27] ^ C[28];
NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^
C[28] ^ C[29];
NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^
C[27] ^ C[29];
NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^
C[27] ^ C[28];
NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^
C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^
C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^
C[28] ^ C[30] ^ C[31];
NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^
C[29] ^ C[31];
NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
NewCRC[20] = D[4] ^ C[12] ^ C[28];
NewCRC[21] = D[5] ^ C[13] ^ C[29];
NewCRC[22] = D[0] ^ C[14] ^ C[24];
NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^
C[28] ^ C[30];
NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^
C[29] ^ C[31];
NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
NewCRC[31] = D[5] ^ C[23] ^ C[29];
 
nextCRC32_D8 = NewCRC;
 
end
 
endfunction
 
endmodule
 
/verilog/rx_engine/rxNumCounter.v
0,0 → 1,71
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: rxNumCounter ////
//// ////
//// DESCRIPTION: To count bytes have been received. ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxNumCounter(rxclk, reset, receiving, frame_cnt);
input rxclk; //receive clk
input reset; //globe reset
 
input receiving; //start to count data field
 
output[`COUNTER_WIDTH-1:0] frame_cnt;
 
parameter TP =1;
 
// Data counter
// used in rxReceiveData field,
// this counter is used for frames whose length is larger than 64
// Of course it also count actual bytes of frames whose length is shorter than 64.
counter data_counter(.clk(rxclk), .reset(reset), .load(~receiving), .en(receiving), .value(frame_cnt));
defparam data_counter.WIDTH = `COUNTER_WIDTH;
 
endmodule
/verilog/rx_engine/xgiga_define.v
0,0 → 1,80
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: definition of parameters ////
//// ////
//// DESCRIPTION: ////
//// ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`define ALLONES 64'hffffffffffffffff
`define ALLONES8 8'hff
`define ALLZEROS 8'h00
 
///////////////////////////////////////////////
// Length parameters
///////////////////////////////////////////////
`define MAX_VALID_LENGTH 12'h0be
`define MAX_VALID_BITS_MORE 3'h6
`define MAX_TAG_LENGTH 12'h0bf
`define MAX_TAG_BITS_MORE 3'h2
`define MAX_JUMBO_LENGTH 12'h466
`define MIN_VALID_LENGTH 8'h08
///////////////////////////////////////////////
// Frame field parameters
///////////////////////////////////////////////
`define PREAMBLE 8'h55
`define START 8'hfb
`define TERMINATE 8'hfd
`define SFD 8'hd5
`define SEQUENCE 8'h9a
`define ERROR 8'hfe
`define TAG_SIGN 16'h0081//8100
`define PAUSE_SIGN 32'h01000888//8808
 
`define MULTICAST 48'h0180C2000001
`define BROADCAST 48'hffffffffffff
////////////////////////////////////////////////
// Frame bytes counter parameter
////////////////////////////////////////////////
`define COUNTER_WIDTH 12
/verilog/rx_engine/rxLenTypChecker.v
0,0 → 1,220
//////////////////////////////////////////////////////////////////////
//// ////
//// MODULE NAME: Frame Length Checker ////
//// ////
//// DESCRIPTION: Frame Length Checker of 10 Gigabit ////
//// Ethernet MAC. Many statistics are implemented ////
//// here. ////
//// ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac10g/ ////
//// ////
//// AUTHOR(S): ////
//// Zheng Cao ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
//
//
//
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "xgiga_define.v"
 
module rxLenTypChecker(rxclk, reset, get_terminator, terminator_location, jumbo_enable, tagged_frame,
frame_cnt, vlan_enable,length_error,large_error, small_error, padded_frame, length_65_127,
length_128_255, length_256_511, length_512_1023, length_1024_max,jumbo_frame);
input rxclk;
input reset;
input jumbo_enable; //Enable jumbo frame recieving
input vlan_enable; //VLAN mode enable bit
input tagged_frame; //number of 64bits DATA field of tagged frame contains
input get_terminator;
input[`COUNTER_WIDTH-1:0] frame_cnt;
input[2:0] terminator_location;
 
output length_error;
output large_error;
output small_error;
output padded_frame;
output length_65_127;
output length_128_255;
output length_256_511;
output length_512_1023;
output length_1024_max;
output jumbo_frame;
parameter TP =1 ;
 
reg [2:0]location_reg;
always@(posedge rxclk or posedge reset)begin
if (reset)
location_reg <=#TP 0;
else if(get_terminator)
location_reg <=#TP terminator_location;
else
location_reg <=#TP location_reg;
end
 
reg large_error;
always@(posedge rxclk or posedge reset)begin
if(reset)
large_error <=#TP 1'b0;
else if(tagged_frame & vlan_enable) begin
if ((frame_cnt == `MAX_TAG_LENGTH) & (location_reg > `MAX_TAG_BITS_MORE))
large_error <=#TP 1'b1;
else if ((frame_cnt > `MAX_TAG_LENGTH) & ~jumbo_enable)
large_error <=#TP 1'b1;
else if(frame_cnt > `MAX_JUMBO_LENGTH)
large_error <=#TP 1'b1;
else
large_error <=#TP 1'b0;
end
else begin
if ((frame_cnt == `MAX_VALID_LENGTH) & (location_reg > `MAX_VALID_BITS_MORE))
large_error <=#TP 1'b1;
else if((frame_cnt > `MAX_VALID_LENGTH) & ~jumbo_enable)
large_error <=#TP 1'b1;
else if(frame_cnt > `MAX_JUMBO_LENGTH)
large_error <=#TP 1'b1;
else
large_error <=#TP 1'b0;
end
end
 
reg small_error;
always@(posedge rxclk or posedge reset) begin
if(reset)
small_error <=#TP 0;
else
small_error <=#TP get_terminator & (frame_cnt< `MIN_VALID_LENGTH);
end
 
wire length_error;
assign length_error = small_error | large_error;
/////////////////////////////////////////////////
// Statistic signals
/////////////////////////////////////////////////
///////////////////////////////////
// 64byte frame received OK
///////////////////////////////////
 
reg padded_frame;
always@(posedge rxclk or posedge reset) begin
if(reset)
padded_frame <=#TP 0;
else
padded_frame <=#TP get_terminator & (frame_cnt==`MIN_VALID_LENGTH);
end
 
///////////////////////////////////
// 65-127 byte Frame Received OK
///////////////////////////////////
 
reg length_65_127;
always@(posedge rxclk or posedge reset) begin
if(reset)
length_65_127 <=#TP 0;
else
length_65_127 <=#TP get_terminator & (frame_cnt>`MIN_VALID_LENGTH) & (frame_cnt <=127);
end
 
///////////////////////////////////
// 128-255 byte Frame Received OK
///////////////////////////////////
 
reg length_128_255;
always@(posedge rxclk or posedge reset) begin
if(reset)
length_128_255 <=#TP 0;
else
length_128_255 <=#TP get_terminator & (frame_cnt>128) & (frame_cnt <=255);
end
 
///////////////////////////////////
// 256-511 byte Frame Received OK
///////////////////////////////////
 
reg length_256_511;
always@(posedge rxclk or posedge reset) begin
if(reset)
length_256_511 <=#TP 0;
else
length_256_511 <=#TP get_terminator & (frame_cnt>256) & (frame_cnt <=511);
end
 
///////////////////////////////////
// 512-1023 byte Frame Received OK
///////////////////////////////////
 
reg length_512_1023;
always@(posedge rxclk or posedge reset) begin
if(reset)
length_512_1023 <=#TP 0;
else
length_512_1023 <=#TP get_terminator & (frame_cnt>512) & (frame_cnt <=1023);
end
 
///////////////////////////////////
// 1024-max byte Frame Received OK
///////////////////////////////////
 
reg length_1024_max;
always@(posedge rxclk or posedge reset) begin
if(reset)
length_1024_max <=#TP 0;
else
length_1024_max <=#TP get_terminator & (frame_cnt>1024) & (frame_cnt <=`MAX_VALID_LENGTH);
end
 
//////////////////////////////////////////////
// Count for Control Frames Received OK
//////////////////////////////////////////////
//how to indicate a control frame(not clearly specificated in 802.3
 
///////////////////////////////////////////////
// Count for Oversize Frames Received OK
///////////////////////////////////////////////
reg jumbo_frame;
always@(posedge rxclk or posedge reset) begin
if(reset)
jumbo_frame <=#TP 0;
else
jumbo_frame <=#TP get_terminator & jumbo_enable & (frame_cnt > `MAX_VALID_LENGTH) & (frame_cnt < `MAX_JUMBO_LENGTH);
end
 
endmodule

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