URL
https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk
Subversion Repositories fade_ether_protocol
Compare Revisions
- This comparison shows the changes necessary to convert path
/fade_ether_protocol/trunk/old_stable_version/FPGA_no_MAC/src/ack_fifo
- from Rev 3 to Rev 34
- ↔ Reverse comparison
Rev 3 → Rev 34
/rec_to_pkg.py
0,0 → 1,124
#!/usr/bin/python |
# The script below is written by Wojciech M. Zabolotny |
# wzab<at>ise.pw.edu.pl 19.03.2012 |
# it is published as PUBLIC DOMAIN |
import sys |
class field: |
last_bit = 0; |
def __init__(self,field_desc): |
fd = field_desc.split(",") |
self.fname = fd[0] |
if not fd[1] in ["signed","unsigned","std_logic_vector"]: |
raise Exception("Wrong field type") |
self.ftype = fd[1] |
if len(fd)==3: |
self.b1=int(fd[2])-1 |
self.b2=0 |
elif len(fd)==4: |
self.b1=int(fd[2]) |
self.b2=int(fd[3]) |
else: |
raise Exception("Syntax error in line: "+field_desc) |
#Assign vector bits |
self.v1=field.last_bit |
self.v2=field.last_bit+abs(self.b2-self.b1) |
field.last_bit = self.v2+1 |
|
if len(sys.argv) != 2: |
print """ |
The rec_to_pkg scripts creates VHDL package for conversion |
between the VHDL records containing "signed" and "unsigned" |
fields and std_logic_vectors. |
It should be called as: rec_to_pkg.py description_file |
where the description file should have the following syntax: |
|
#Optional comment line |
record record_name |
#optional comment lines |
#[...] |
field_name,signed_or_unsigned,width |
#or |
field_name,signed_or_unsigned,left_bit_nr,right_bit_nr |
end |
|
The generated package is written to the record_name_pkg.vhd file |
""" |
exit(0) |
fin=open(sys.argv[1]) |
#Read the full description of the type |
type_desc=[l.strip() for l in fin.readlines() if len(l) > 0 and l[0] != "#" ] |
#The first line should contain the record name |
l=type_desc[0].split(" ") |
if l[0] != "record": |
raise Exception("Syntax error! The first line should have form \"record name_of_type\"") |
type_name=l[1] |
pkg_name=type_name+"_pkg" |
#Prepare for analysis of fields |
msb=0 |
fields=[] |
end_found = False |
#Find the field definitions |
for l in type_desc[1:]: |
if l=="end": |
end_found=True |
break |
fields.append(field(l)) |
if not end_found: |
raise Exception("Syntax error: no \"end\" found") |
#If we got here, probably the syntax was correct |
#Lets generate the package |
p="""\ |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
""" |
p+="package "+pkg_name+" is\n\n" |
p+="type "+type_name+" is record\n" |
for f in fields: |
s=" "+f.fname+" : "+f.ftype+"(" |
if f.b1 > f.b2: |
s=s+str(f.b1)+" downto "+str(f.b2)+");\n" |
else: |
s=s+str(f.b1)+" to "+str(f.b2)+");\n" |
p+=s |
p+="end record;\n\n" |
#Write width of our type |
p+="constant "+type_name+"_width : integer := "+str(field.last_bit)+";\n\n" |
#Write headers of conversion functions |
p+="function "+type_name+"_to_stlv(\n" |
p+=" constant din : "+type_name+")\n" |
p+=" return std_logic_vector;\n\n" |
p+="function stlv_to_"+type_name+"(\n" |
p+=" constant din : std_logic_vector)\n" |
p+=" return "+type_name+";\n\n" |
p+="end "+pkg_name+";\n\n" |
#Now the body of the package - the conversion functions |
p+="package body "+pkg_name+" is\n\n" |
# |
p+="function "+type_name+"_to_stlv(\n" |
p+=" constant din : "+type_name+")\n" |
p+=" return std_logic_vector is\n" |
p+=" variable res : std_logic_vector("+str(field.last_bit-1)+" downto 0);\n" |
p+="begin\n" |
for f in fields: |
p+=" res("+str(f.v2)+" downto "+str(f.v1)+ ") := std_logic_vector(din."+f.fname+");\n" |
p+=" return res;\n" |
p+="end "+type_name+"_to_stlv;\n\n" |
# |
p+="function stlv_to_"+type_name+"(\n" |
p+=" constant din : std_logic_vector)\n" |
p+=" return "+type_name+" is\n" |
p+=" variable res : "+type_name+";\n" |
p+="begin\n" |
for f in fields: |
p+=" res."+f.fname+":="+f.ftype+"(din("+str(f.v2)+" downto "+str(f.v1)+"));\n" |
p+=" return res;\n" |
p+="end stlv_to_"+type_name+";\n\n" |
p+="end "+pkg_name+";\n" |
|
#The output file name |
fout_name=type_name+"_pkg.vhd" |
fout=open(fout_name,"w") |
fout.write(p) |
fout.close() |
|
rec_to_pkg.py
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ack.rec
===================================================================
--- ack.rec (nonexistent)
+++ ack.rec (revision 34)
@@ -0,0 +1,12 @@
+# This is a test record - packet acknowledgment
+record pkt_ack
+# Below are fields definitions
+# First two pointers fo linked list
+# pkt - number of the packet
+pkt,unsigned,8
+# set - number of the set
+set,unsigned,16
+# cmd - command - 1 for ACK
+cmd,unsigned,8
+end
+
Index: pkt_ack_pkg.vhd
===================================================================
--- pkt_ack_pkg.vhd (nonexistent)
+++ pkt_ack_pkg.vhd (revision 34)
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+package pkt_ack_pkg is
+
+type pkt_ack is record
+ pkt : unsigned(7 downto 0);
+ set : unsigned(15 downto 0);
+ cmd : unsigned(7 downto 0);
+end record;
+
+constant pkt_ack_width : integer := 32;
+
+function pkt_ack_to_stlv(
+ constant din : pkt_ack)
+ return std_logic_vector;
+
+function stlv_to_pkt_ack(
+ constant din : std_logic_vector)
+ return pkt_ack;
+
+end pkt_ack_pkg;
+
+package body pkt_ack_pkg is
+
+function pkt_ack_to_stlv(
+ constant din : pkt_ack)
+ return std_logic_vector is
+ variable res : std_logic_vector(31 downto 0);
+begin
+ res(7 downto 0) := std_logic_vector(din.pkt);
+ res(23 downto 8) := std_logic_vector(din.set);
+ res(31 downto 24) := std_logic_vector(din.cmd);
+ return res;
+end pkt_ack_to_stlv;
+
+function stlv_to_pkt_ack(
+ constant din : std_logic_vector)
+ return pkt_ack is
+ variable res : pkt_ack;
+begin
+ res.pkt:=unsigned(din(7 downto 0));
+ res.set:=unsigned(din(23 downto 8));
+ res.cmd:=unsigned(din(31 downto 24));
+ return res;
+end stlv_to_pkt_ack;
+
+end pkt_ack_pkg;