Subversion Repositories fade_ether_protocol

/experimental_jumbo_frames_version/fpga/rec_to_pkg.py File deleted

experimental_jumbo_frames_version/fpga/rec_to_pkg.py Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: experimental_jumbo_frames_version/fpga/dpram_inf.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/dpram_inf.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/dpram_inf.vhd (nonexistent) @@ -1,61 +0,0 @@ --- A parameterized, inferable, true dual-port, common-clock block RAM in VHDL. --- Original file was taken from: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ --- No license information were provided by the original author. --- Minimal modifications were introduced by me to make it suitable for my FPGA --- interface. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity dp_ram_scl is - generic ( - DATA_WIDTH : integer := 72; - ADDR_WIDTH : integer := 10 - ); - port ( - -- Port A - clk_a : in std_logic; - we_a : in std_logic; - addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); - data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); - q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); - - -- Port B - clk_b : in std_logic; - we_b : in std_logic; - addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); - data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); - q_b : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); -end dp_ram_scl; - -architecture rtl of dp_ram_scl is - -- Shared memory - type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); - shared variable mem : mem_type; -begin - --- Port A - process(clk_a) - begin - if(clk_a'event and clk_a = '1') then - if(we_a = '1') then - mem(conv_integer(addr_a)) := data_a; - end if; - q_a <= mem(conv_integer(addr_a)); - end if; - end process; - --- Port B - process(clk_b) - begin - if(clk_b'event and clk_b = '1') then - if(we_b = '1') then - mem(conv_integer(addr_b)) := data_b; - end if; - q_b <= mem(conv_integer(addr_b)); - end if; - end process; - -end rtl; Index: experimental_jumbo_frames_version/fpga/pkt_ack_pkg.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/pkt_ack_pkg.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/pkt_ack_pkg.vhd (nonexistent) @@ -1,48 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -package pkt_ack_pkg is - -type pkt_ack is record - pkt : unsigned(31 downto 0); - seq : unsigned(15 downto 0); - cmd : unsigned(15 downto 0); -end record; - -constant pkt_ack_width : integer := 64; - -function pkt_ack_to_stlv( - constant din : pkt_ack) - return std_logic_vector; - -function stlv_to_pkt_ack( - constant din : std_logic_vector) - return pkt_ack; - -end pkt_ack_pkg; - -package body pkt_ack_pkg is - -function pkt_ack_to_stlv( - constant din : pkt_ack) - return std_logic_vector is - variable res : std_logic_vector(63 downto 0); -begin - res(31 downto 0) := std_logic_vector(din.pkt); - res(47 downto 32) := std_logic_vector(din.seq); - res(63 downto 48) := std_logic_vector(din.cmd); - return res; -end pkt_ack_to_stlv; - -function stlv_to_pkt_ack( - constant din : std_logic_vector) - return pkt_ack is - variable res : pkt_ack; -begin - res.pkt:=unsigned(din(31 downto 0)); - res.seq:=unsigned(din(47 downto 32)); - res.cmd:=unsigned(din(63 downto 48)); - return res; -end stlv_to_pkt_ack; - -end pkt_ack_pkg; Index: experimental_jumbo_frames_version/fpga/desc_mgr_pkg.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/desc_mgr_pkg.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/desc_mgr_pkg.vhd (nonexistent) @@ -1,25 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; -use ieee.std_logic_textio.all; -library work; -use work.pkt_ack_pkg.all; - -package desc_mgr_pkg is - - constant LOG2_N_OF_PKTS : integer := 4; - constant N_OF_PKTS : integer := 2**LOG2_N_OF_PKTS; - constant LOG2_NWRDS_IN_PKT : integer := 10; - constant NWRDS_IN_PKT : integer := 1024; - constant N_OF_SETS : integer := 65536; - - -- Commands - constant FCMD_START : integer := 1; - constant FCMD_STOP : integer := 2; - constant FCMD_ACK : integer := 3; - constant FCMD_NACK : integer := 4; - constant FCMD_RESET : integer := 5; - -end desc_mgr_pkg; - Index: experimental_jumbo_frames_version/fpga/crc_gen2.py =================================================================== --- experimental_jumbo_frames_version/fpga/crc_gen2.py (revision 21) +++ experimental_jumbo_frames_version/fpga/crc_gen2.py (nonexistent) @@ -1,136 +0,0 @@ -#!/usr/bin/python -# This is the public domain code written by Wojciech M. Zabolotny -# ( wzab(at)ise.pw.edu.pl ) -# The functionality has been inspired by the CRC Tool available -# at http://www.easics.com/webtools/crctool , however the code -# has been written independently. -# In fact I have decided to write this code, when I was not able to -# generate CRC with the crctool for a particular non-typical length -# of data word. -# The program crc_gen.py generates the VHDL code for CRC update for given -# length of the data vector. -# The length of the CRC results from the coefficient of the CRC polynomial. -# The arguments are as follows: -# 1st: Function name. The package name is created by prefixing it with -# pkg_ -# 2nd: L - for data fed LSB first, M for data fed MSB first -# 3rd: the width of the data bus, -# 4th and next: the coefficients of the polynomial (the exponents in fact). -# For example, to generate the expression for CRC7 for 12bit data transmitted LSB first -# you should call: -# crc_gen.py crc7_d12 L 12 7 3 0 -# To generate CRC-12 for 16 bit data transmitted MSB first, you should call: -# crc_gen.py crc12_d16 M 16 12 11 3 2 1 0 -# The generated code implements a package with the function calculating -# the new value of the CRC from the previous value of the CRC and -# the data word. -import sys -fun_name=sys.argv[1] -pkg_name = "pkg_"+fun_name -data_order=sys.argv[2] -if data_order != 'L' and data_order != 'M': - print "The second argument must be 'L' or 'M', not the '"+data_order+"'" - sys.exit(1) -data_len=int(sys.argv[3]) -poly=[] -for i in range(4,len(sys.argv)): - poly.append(int(sys.argv[i])) -crc_len=max(poly) - -#The class "xor_result" implements result of xor-ing of multiple -# CRC and DATA bits -# dirty trick: the class relies on global variables crc_len and data_len -class xor_result: - def __init__(self,c=-1,d=-1): - self.c=crc_len*[0] - self.d=data_len*[0] - if(c>-1): - self.c[c]=1 - if(d>-1): - self.d[d]=1 - def copy(self): - res=xor_result() - for i in range(0,crc_len): - res.c[i]=self.c[i] - for i in range(0,data_len): - res.d[i]=self.d[i] - return res - # The new XOR operator - def __xor__(self,x): - res=xor_result() - for i in range(0,crc_len): - res.c[i]=self.c[i]^x.c[i] - for i in range(0,data_len): - res.d[i]=self.d[i]^x.d[i] - return res - def tostr(self): - res="" - for i in range(0,crc_len): - if self.c[i]==1: - if res=="": - res+="c("+str(i)+")" - else: - res+=" xor c("+str(i)+")" - for i in range(0,data_len): - if self.d[i]==1: - if res=="": - res+="d("+str(i)+")" - else: - res+=" xor d("+str(i)+")" - return res - - -#Now we create the CRC vector, which initially contains only the bits -#of the initial value of the CRC -CRC=[ xor_result(c=i) for i in range(0,crc_len) ] -#And the data vector -DATA=[ xor_result(d=i) for i in range(0,data_len) ] -#Now we pass the data through the CRC polynomial -if data_order == 'L': - d_range = range(0,data_len) - ord_name = "LSB" -elif data_order == 'M': - d_range = range(data_len-1,-1,-1) - ord_name = "MSB" -else: - print "Internal error" - sys.exit(1) -for i in d_range: - #We create the vector for the new CRC - NCRC = [ xor_result() for k in range(0,crc_len) ] - #First - the basic shift operation - for j in range(1,crc_len): - NCRC[j]=CRC[j-1].copy() - #Now we add the feedback - FB=DATA[i] ^ CRC[crc_len-1] - for j in poly: - if j == crc_len: - # This does not require any action - pass - else: - NCRC[j]=NCRC[j] ^ FB - CRC=NCRC -pkg_text = '''library ieee; -use ieee.std_logic_1164.all; -package ''' + pkg_name +" is\n" -pkg_text += " -- CRC update for "+str(crc_len)+"-bit CRC and "+\ - str(data_len)+"-bit data ("+ord_name+" first)\n" -pkg_text += " -- The CRC polynomial exponents: "+str(poly)+"\n" -fun_decl = ' function ' + fun_name +"(\n" +\ -' din : std_logic_vector('+str(data_len-1)+' downto 0);\n'+\ -' crc : std_logic_vector('+str(crc_len-1)+' downto 0))\n'+\ -' return std_logic_vector' -pkg_text += fun_decl+';\n' -pkg_text += 'end '+pkg_name+';\n\n' -pkg_text += "package body " + pkg_name +" is\n" -pkg_text += fun_decl + ' is \n' -pkg_text += ' variable c,n : std_logic_vector(' + str(crc_len-1)+' downto 0);\n' -pkg_text += ' variable d : std_logic_vector(' + str(data_len-1)+' downto 0);\n' -pkg_text += ' begin\n' -pkg_text += ' c := crc;\n d := din; \n' -for i in range(0,len(CRC)): - pkg_text += " n("+str(i)+") := "+CRC[i].tostr()+";\n" -pkg_text += ' return n;\n' -pkg_text += ' end '+fun_name+";\n" -pkg_text += 'end '+pkg_name+";\n" -print pkg_text

experimental_jumbo_frames_version/fpga/crc_gen2.py Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: experimental_jumbo_frames_version/fpga/atlys/atlys_eth.ucf =================================================================== --- experimental_jumbo_frames_version/fpga/atlys/atlys_eth.ucf (revision 21) +++ experimental_jumbo_frames_version/fpga/atlys/atlys_eth.ucf (nonexistent) @@ -1,118 +0,0 @@ -#@ NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10 -#@ NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10 -#@ NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10 -NET "GPIO_LED<0>" LOC = "U18"; ## 2 on DS11 LED -NET "GPIO_LED<1>" LOC = "M14"; ## 2 on DS12 LED -NET "GPIO_LED<2>" LOC = "N14"; ## 2 on DS13 LED -NET "GPIO_LED<3>" LOC = "L14"; ## 2 on DS14 LED -NET "GPIO_LED<4>" LOC = "M13"; ## 2 on DS11 LED -NET "GPIO_LED<5>" LOC = "D4"; ## 2 on DS12 LED -NET "GPIO_LED<6>" LOC = "P16"; ## 2 on DS13 LED -NET "GPIO_LED<7>" LOC = "N12"; ## 2 on DS14 LED -NET "SWITCHES<0>" LOC = "A10"; -NET "SWITCHES<1>" LOC = "D14"; -NET "SWITCHES<2>" LOC = "C14"; -NET "SWITCHES<3>" LOC = "P15"; -NET "SWITCHES<4>" LOC = "P12"; -NET "SWITCHES<5>" LOC = "R5"; -NET "SWITCHES<6>" LOC = "T5"; -NET "SWITCHES<7>" LOC = "E4"; - -## -NET "CPU_RESET" LOC = "T15"; ## 2 on SW9 pushbutton -## -NET "PHY_COL" LOC = "C17"; ## 114 on U3 -NET "PHY_CRS" LOC = "C18"; ## 115 on U3 -NET "PHY_INT" LOC = "L16"; ## 32 on U3 -NET "PHY_MDC" LOC = "F16"; ## 35 on U3 -NET "PHY_MDIO" LOC = "N17"; ## 33 on U3 -NET "PHY_RESET" LOC = "G13"; ## 36 on U3 -NET "PHY_RXCLK" LOC = "K15"; ## 7 on U3 -NET "PHY_RXCTL_RXDV" LOC = "F17"; ## 4 on U3 -NET "PHY_RXD<0>" LOC = "G16"; ## 3 on U3 -NET "PHY_RXD<1>" LOC = "H14"; ## 128 on U3 -NET "PHY_RXD<2>" LOC = "E16"; ## 126 on U3 -NET "PHY_RXD<3>" LOC = "F15"; ## 125 on U3 -NET "PHY_RXD<4>" LOC = "F14"; ## 124 on U3 -NET "PHY_RXD<5>" LOC = "E18"; ## 123 on U3 -NET "PHY_RXD<6>" LOC = "D18"; ## 121 on U3 -NET "PHY_RXD<7>" LOC = "D17"; ## 120 on U3 -NET "PHY_RXER" LOC = "F18"; ## 8 on U3 -NET "PHY_TXCLK" LOC = "K16"; ## 10 on U3 -NET "PHY_TXCTL_TXEN" LOC = "H15"; ## 16 on U3 -NET "PHY_TXC_GTXCLK" LOC = "L12"; ## 14 on U3 -NET "PHY_TXD<0>" LOC = "H16"; ## 18 on U3 -NET "PHY_TXD<1>" LOC = "H13"; ## 19 on U3 -NET "PHY_TXD<2>" LOC = "K14"; ## 20 on U3 -NET "PHY_TXD<3>" LOC = "K13"; ## 24 on U3 -NET "PHY_TXD<4>" LOC = "J13"; ## 25 on U3 -NET "PHY_TXD<5>" LOC = "G14"; ## 26 on U3 -NET "PHY_TXD<6>" LOC = "H12"; ## 28 on U3 -NET "PHY_TXD<7>" LOC = "K12"; ## 29 on U3 -NET "PHY_TXER" LOC = "G18"; ## 13 on U3 -## -NET "SYSCLK" LOC = "L15"; -## -#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1 -#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1 -#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1 -#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1 -#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1 -#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1 -#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1 -#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1 -# -#@ NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm) -#@ NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm) -#@ NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm) -#@ NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm) -#@ NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm) -#@ NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm) -#@ NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm) -#@ NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm) -# -#@ NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16 -#@ NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16 -# -#@ PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; - -#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04 -NET "sysclk" TNM_NET = sysclk; -TIMESPEC TS_sysclk = PERIOD "sysclk" 10 ns HIGH 50%; -#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30 -NET "phy_rxclk" TNM_NET = phy_rxclk; -TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%; -NET "phy_txclk" TNM_NET = phy_txclk; -TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 8 ns HIGH 50%; -NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk; -TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%; - -INST "phy_col" TNM = phy_inputs; -INST "phy_crs" TNM = phy_inputs; -INST "phy_int" TNM = phy_inputs; -INST "phy_mdio" TNM = phy_inputs; -INST "phy_rxctl_rxdv" TNM = phy_inputs; -INST "phy_rxd<0>" TNM = phy_inputs; -INST "phy_rxd<1>" TNM = phy_inputs; -INST "phy_rxd<2>" TNM = phy_inputs; -INST "phy_rxd<3>" TNM = phy_inputs; -INST "phy_rxd<4>" TNM = phy_inputs; -INST "phy_rxd<5>" TNM = phy_inputs; -INST "phy_rxd<6>" TNM = phy_inputs; -INST "phy_rxd<7>" TNM = phy_inputs; -INST "phy_rxer" TNM = phy_inputs; -TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_rxclk"; -TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_txclk"; -INST "phy_txctl_txen" TNM = phy_outputs; -INST "phy_txd<0>" TNM = phy_outputs; -INST "phy_txd<1>" TNM = phy_outputs; -INST "phy_txd<2>" TNM = phy_outputs; -INST "phy_txd<3>" TNM = phy_outputs; -INST "phy_txd<4>" TNM = phy_outputs; -INST "phy_txd<5>" TNM = phy_outputs; -INST "phy_txd<6>" TNM = phy_outputs; -INST "phy_txd<7>" TNM = phy_outputs; -INST "phy_txer" TNM = phy_outputs; -TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_rxclk"; -TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_txclk"; Index: experimental_jumbo_frames_version/fpga/atlys/eth_sender8.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/atlys/eth_sender8.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/atlys/eth_sender8.vhd (nonexistent) @@ -1,396 +0,0 @@ -------------------------------------------------------------------------------- --- Title : FPGA Ethernet interface - block sending packets via GMII Phy --- Project : -------------------------------------------------------------------------------- --- File : eth_sender8.vhd --- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) --- License : BSD License --- Company : --- Created : 2012-03-30 --- Last update: 2014-10-19 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: This file implements the state machine, which manages the --- table of packet descriptors, used to resend only not confirmed packets -------------------------------------------------------------------------------- --- Copyright (c) 2012 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2012-03-30 1.0 WZab Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.pkg_newcrc32_d8.all; -use work.desc_mgr_pkg.all; - -entity eth_sender is - - port ( - -- Configuration - peer_mac : in std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - pkt_number : in unsigned(31 downto 0); - seq_number : in unsigned(15 downto 0); - transm_delay : in unsigned(31 downto 0); - -- System interface - clk : in std_logic; - rst_n : in std_logic; - -- Control interface - ready : out std_logic; - flushed : in std_logic; - start : in std_logic; - cmd_start : in std_logic; - -- Data memory interface - tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); - tx_mem_data : in std_logic_vector(63 downto 0); - -- User command response interface - cmd_response : in std_logic_vector(12*8-1 downto 0); - -- TX Phy interface - Tx_Clk : in std_logic; - Tx_En : out std_logic; - TxD : out std_logic_vector(7 downto 0) - ); - -end eth_sender; - - -architecture beh1 of eth_sender is - - type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_PREAMB, WST_SEND_SOF, - WST_SEND_HEADER, WST_SEND_CMD_HEADER, WST_SEND_CMD_TRAILER, - WST_SEND_DATA, WST_SEND_CRC, - WST_SEND_COMPLETED); - - type T_ETH_SENDER_REGS is record - state : T_ETH_SENDER_STATE; - ready : std_logic; - count : integer; - byte : integer; - mem_addr : unsigned (LOG2_NWRDS_IN_PKT-1 downto 0); - crc32 : std_logic_vector(31 downto 0); - end record; - - constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := ( - state => WST_IDLE, - ready => '1', - count => 0, - byte => 0, - mem_addr => (others => '0'), - crc32 => (others => '0') - ) ; - - signal r, r_n : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI; - - type T_ETH_SENDER_COMB is record - TxD : std_logic_vector(7 downto 0); - Tx_En : std_logic; - mem_addr : unsigned(LOG2_NWRDS_IN_PKT-1 downto 0); - end record; - - constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := ( - TxD => (others => '0'), - Tx_En => '0', - mem_addr => (others => '0') - ); - - signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT; - - signal s_header : std_logic_vector(8*40-1 downto 0) := (others => '0'); - constant HEADER_LEN : integer := 40; -- 40 bytes - signal s_cmd_header : std_logic_vector(8*32-1 downto 0) := (others => '0'); - constant CMD_HEADER_LEN : integer := 32; -- 32 bytes - - signal cmd_only : std_logic := '0'; - - function select_byte ( - constant vec : std_logic_vector; - constant byte_num : integer) - return std_logic_vector is - variable v_byte : std_logic_vector(7 downto 0); - begin - -- first select byte - v_byte := vec(vec'left-byte_num*8 downto vec'left-byte_num*8-7); - return v_byte; - end select_byte; - - function rev(a : in std_logic_vector) - return std_logic_vector is - variable result : std_logic_vector(a'range); - alias aa : std_logic_vector(a'reverse_range) is a; - begin - for i in aa'range loop - result(i) := aa(i); - end loop; - return result; - end; -- function reverse_any_bus - - signal tx_rst_n, tx_rst_n_0, tx_rst_n_1 : std_logic := '0'; - signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; - - signal start_0, tx_start, tx_start_1, tx_start_0 : std_logic := '0'; - signal tx_ready, ready_0, ready_1 : std_logic := '0'; - - type T_STATE1 is (ST1_IDLE, ST1_WAIT_NOT_READY, ST1_WAIT_NOT_START, - ST1_WAIT_READY); - signal state1 : T_STATE1; - - type T_STATE2 is (ST2_IDLE, ST2_WAIT_NOT_READY, ST2_WAIT_READY); - signal state2 : T_STATE2; - signal dta_packet_type : std_logic_vector(15 downto 0) := (others => '0'); - -begin -- beh1 - dta_packet_type <= x"a5a5" when flushed = '0' else x"a5a6"; - -- Packet header - s_header <= peer_mac & my_mac & my_ether_type & x"0100" & - dta_packet_type & std_logic_vector(seq_number(15 downto 0)) & - std_logic_vector(pkt_number) & std_logic_vector(transm_delay) & cmd_response; - -- Command response packet header - we have unused 16 bits in the response packet... - s_cmd_header <= peer_mac & my_mac & my_ether_type & x"0100" & - x"a55a" & x"0000" & cmd_response; - - -- Connection of the signals - - -- The memory address is built from the packet number (6 bits) and word - -- number (8 bits) - tx_mem_addr <= std_logic_vector(pkt_number(LOG2_N_OF_PKTS-1 downto 0)) & std_logic_vector(c.mem_addr); - - -- Main state machine used to send the packet - -- W calej maszynie trzeba jeszcze dodac obsluge kolizji!!! - -- Oprocz tego trzeba przeanalizowac poprawnosc przejsc miedzy domenami zegara - - - snd1 : process (Tx_Clk, tx_rst_n) - begin - if tx_rst_n = '0' then -- asynchronous reset (active low) - r <= ETH_SENDER_REGS_INI; - TxD <= (others => '0'); - Tx_En <= '0'; - elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge - r <= r_n; - -- To minimize glitches and propagation delay, let's add pipeline register - Tx_En <= c.Tx_En; - TxD <= c.TxD; - end if; - end process snd1; -- snd1 - - snd2 : process (r, s_header, tx_mem_data, tx_start) - variable v_TxD : std_logic_vector(7 downto 0); - begin -- process snd1 - -- default values - c <= ETH_SENDER_COMB_DEFAULT; - r_n <= r; - case r.state is - when WST_IDLE => - r_n.ready <= '1'; - if tx_start = '1' then - r_n.ready <= '0'; - r_n.state <= WST_SEND_PREAMB; - r_n.count <= 7; - end if; - when WST_SEND_PREAMB => - -- Trzeba dodac wykrywanie kolizji! - c.TxD <= x"55"; - c.Tx_En <= '1'; - r_n.count <= r.count - 1; - if r.count = 1 then - r_n.state <= WST_SEND_SOF; - end if; - when WST_SEND_SOF => - c.TxD <= x"D5"; - c.Tx_En <= '1'; - -- Prepare for sending of header - r_n.crc32 <= (others => '1'); - if cmd_only = '1' then - r_n.state <= WST_SEND_CMD_HEADER; - else - r_n.state <= WST_SEND_HEADER; - end if; - r_n.count <= 0; - when WST_SEND_CMD_HEADER => - v_TxD := select_byte(s_cmd_header, r.count); - c.TxD <= v_TxD; - c.Tx_En <= '1'; - r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); - if r.count < CMD_HEADER_LEN-1 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.byte <= 0; - r_n.mem_addr <= (others => '0'); - c.mem_addr <= (others => '0'); - r_n.state <= WST_SEND_CMD_TRAILER; - end if; - when WST_SEND_CMD_TRAILER => - v_TxD := (others => '0'); - c.TxD <= v_TxD; - c.Tx_En <= '1'; - r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); - if r.count < 64-CMD_HEADER_LEN-1 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.byte <= 0; - r_n.mem_addr <= (others => '0'); - c.mem_addr <= (others => '0'); - r_n.state <= WST_SEND_CRC; - end if; - when WST_SEND_HEADER => - v_TxD := select_byte(s_header, r.count); - c.TxD <= v_TxD; - c.Tx_En <= '1'; - r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); - if r.count < HEADER_LEN-1 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.byte <= 0; - r_n.mem_addr <= (others => '0'); - c.mem_addr <= (others => '0'); - r_n.state <= WST_SEND_DATA; - end if; - when WST_SEND_DATA => - -- send the data byte by byte - v_TxD := select_byte(tx_mem_data, r.byte); - c.TxD <= v_TxD; - c.Tx_En <= '1'; - r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); - if r.byte < 7 then - r_n.byte <= r.byte + 1; - c.mem_addr <= r.mem_addr; - else - r_n.byte <= 0; - -- Check, if we have sent all the data - -- We send 8192 bytes, which takes 1024 64-bit words - if r.mem_addr < 1023 then - r_n.mem_addr <= r.mem_addr + 1; - c.mem_addr <= r.mem_addr + 1; - else - -- We send the CRC - r_n.state <= WST_SEND_CRC; - end if; - end if; - when WST_SEND_CRC => - v_TxD := r.crc32(31-r.byte*8 downto 24-r.byte*4); - c.TxD <= not rev(v_TxD); - c.Tx_En <= '1'; - if r.byte < 3 then - r_n.byte <= r.byte + 1; - else - r_n.count <= 12; -- generate the IFG - 12 bytes = 96 - -- bits - r_n.state <= WST_SEND_COMPLETED; - end if; - when WST_SEND_COMPLETED => - if r.count > 0 then - r_n.count <= r.count - 1; - else - r_n.ready <= '1'; - r_n.state <= WST_IDLE; - end if; - end case; - end process snd2; - - - -- Synchronization of the reset signal for the Tx_Clk domain - process (Tx_Clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - tx_rst_n_0 <= '0'; - tx_rst_n_1 <= '0'; - tx_rst_n <= '0'; - elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge - tx_rst_n_0 <= rst_n; - tx_rst_n_1 <= tx_rst_n_0; - tx_rst_n <= tx_rst_n_1; - end if; - end process; - - -- Synchronization of signals passing clock domains - -- Signal start is sent from the Clk domain. - -- When it is asserted, we must immediately deassert signal ready, - -- then generate the synchronized start and after internal ready - -- is asserted, we can output it again... - - -- Ustawienie na 1 takt zegara "clk" sygnalu start powinno zainicjowac wysylanie - -- w tym bloku musimy zadbac o stosowne wydluzenie sygnalu start i jego synchronizacje - -- miedzy domenami zegara... - process (clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - ready <= '0'; - ready_1 <= '0'; - ready_0 <= '0'; - state2 <= ST2_IDLE; - elsif clk'event and clk = '1' then -- rising clock edge - ready_1 <= tx_ready; - ready_0 <= ready_1; - case state2 is - when ST2_IDLE => - if start = '1' and ready_0 = '1' then - cmd_only <= '0'; - start_0 <= '1'; - ready <= '0'; - state2 <= ST2_WAIT_NOT_READY; - elsif cmd_start = '1' and ready_0 = '1' then - cmd_only <= '1'; - start_0 <= '1'; - ready <= '0'; - state2 <= ST2_WAIT_NOT_READY; - else - ready <= ready_0; -- Needed to provide correct start! - end if; - when ST2_WAIT_NOT_READY => - if ready_0 = '0' then - start_0 <= '0'; - state2 <= ST2_WAIT_READY; - end if; - when ST2_WAIT_READY => - if ready_0 = '1' then - ready <= '1'; - state2 <= ST2_IDLE; - end if; - when others => null; - end case; - end if; - end process; - - process (Tx_Clk, tx_rst_n) - begin -- process - if tx_rst_n = '0' then -- asynchronous reset (active low) - tx_start <= '0'; - tx_start_0 <= '0'; - state1 <= ST1_IDLE; - tx_ready <= '1'; - elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge - tx_start_0 <= start_0; - tx_start <= tx_start_0; - case state1 is - when ST1_IDLE => - if tx_start = '1' then - tx_ready <= '0'; -- this should cause tx_start to go low - state1 <= ST1_WAIT_NOT_READY; - end if; - when ST1_WAIT_NOT_READY => - if r.ready = '0' then - state1 <= ST1_WAIT_NOT_START; - end if; - when ST1_WAIT_NOT_START => - if tx_start = '0' then - state1 <= ST1_WAIT_READY; - end if; - when ST1_WAIT_READY => - if r.ready = '1' then - tx_ready <= '1'; - state1 <= ST1_IDLE; - end if; - when others => null; - end case; - end if; - end process; - -end beh1; Index: experimental_jumbo_frames_version/fpga/atlys/ack_fifo.xco =================================================================== --- experimental_jumbo_frames_version/fpga/atlys/ack_fifo.xco (revision 21) +++ experimental_jumbo_frames_version/fpga/atlys/ack_fifo.xco (nonexistent) @@ -1,213 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Sun Oct 5 18:40:09 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:fifo_generator:9.3 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 -# END Select -# BEGIN Parameters -CSET add_ngc_constraint_axi=false -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET aruser_width=1 -CSET awuser_width=1 -CSET axi_address_width=32 -CSET axi_data_width=64 -CSET axi_type=AXI4_Stream -CSET axis_type=FIFO -CSET buser_width=1 -CSET clock_enable_type=Slave_Interface_Clock_Enable -CSET clock_type_axi=Common_Clock -CSET component_name=ack_fifo -CSET data_count=false -CSET data_count_width=9 -CSET disable_timing_violations=false -CSET disable_timing_violations_axi=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_assert_value_axis=1022 -CSET empty_threshold_assert_value_rach=1022 -CSET empty_threshold_assert_value_rdch=1022 -CSET empty_threshold_assert_value_wach=1022 -CSET empty_threshold_assert_value_wdch=1022 -CSET empty_threshold_assert_value_wrch=1022 -CSET empty_threshold_negate_value=5 -CSET enable_aruser=false -CSET enable_awuser=false -CSET enable_buser=false -CSET enable_common_overflow=false -CSET enable_common_underflow=false -CSET enable_data_counts_axis=false -CSET enable_data_counts_rach=false -CSET enable_data_counts_rdch=false -CSET enable_data_counts_wach=false -CSET enable_data_counts_wdch=false -CSET enable_data_counts_wrch=false -CSET enable_ecc=false -CSET enable_ecc_axis=false -CSET enable_ecc_rach=false -CSET enable_ecc_rdch=false -CSET enable_ecc_wach=false -CSET enable_ecc_wdch=false -CSET enable_ecc_wrch=false -CSET enable_read_channel=false -CSET enable_read_pointer_increment_by2=false -CSET enable_reset_synchronization=true -CSET enable_ruser=false -CSET enable_tdata=false -CSET enable_tdest=false -CSET enable_tid=false -CSET enable_tkeep=false -CSET enable_tlast=false -CSET enable_tready=true -CSET enable_tstrobe=false -CSET enable_tuser=false -CSET enable_write_channel=false -CSET enable_wuser=false -CSET fifo_application_type_axis=Data_FIFO -CSET fifo_application_type_rach=Data_FIFO -CSET fifo_application_type_rdch=Data_FIFO -CSET fifo_application_type_wach=Data_FIFO -CSET fifo_application_type_wdch=Data_FIFO -CSET fifo_application_type_wrch=Data_FIFO -CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET fifo_implementation_axis=Common_Clock_Block_RAM -CSET fifo_implementation_rach=Common_Clock_Block_RAM -CSET fifo_implementation_rdch=Common_Clock_Block_RAM -CSET fifo_implementation_wach=Common_Clock_Block_RAM -CSET fifo_implementation_wdch=Common_Clock_Block_RAM -CSET fifo_implementation_wrch=Common_Clock_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=511 -CSET full_threshold_assert_value_axis=1023 -CSET full_threshold_assert_value_rach=1023 -CSET full_threshold_assert_value_rdch=1023 -CSET full_threshold_assert_value_wach=1023 -CSET full_threshold_assert_value_wdch=1023 -CSET full_threshold_assert_value_wrch=1023 -CSET full_threshold_negate_value=510 -CSET id_width=4 -CSET inject_dbit_error=false -CSET inject_dbit_error_axis=false -CSET inject_dbit_error_rach=false -CSET inject_dbit_error_rdch=false -CSET inject_dbit_error_wach=false -CSET inject_dbit_error_wdch=false -CSET inject_dbit_error_wrch=false -CSET inject_sbit_error=false -CSET inject_sbit_error_axis=false -CSET inject_sbit_error_rach=false -CSET inject_sbit_error_rdch=false -CSET inject_sbit_error_wach=false -CSET inject_sbit_error_wdch=false -CSET inject_sbit_error_wrch=false -CSET input_data_width=64 -CSET input_depth=512 -CSET input_depth_axis=1024 -CSET input_depth_rach=16 -CSET input_depth_rdch=1024 -CSET input_depth_wach=16 -CSET input_depth_wdch=1024 -CSET input_depth_wrch=16 -CSET interface_type=Native -CSET output_data_width=64 -CSET output_depth=512 -CSET overflow_flag=false -CSET overflow_flag_axi=false -CSET overflow_sense=Active_High -CSET overflow_sense_axi=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET programmable_full_type_axis=No_Programmable_Full_Threshold -CSET programmable_full_type_rach=No_Programmable_Full_Threshold -CSET programmable_full_type_rdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wach=No_Programmable_Full_Threshold -CSET programmable_full_type_wdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wrch=No_Programmable_Full_Threshold -CSET rach_type=FIFO -CSET rdch_type=FIFO -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=9 -CSET register_slice_mode_axis=Fully_Registered -CSET register_slice_mode_rach=Fully_Registered -CSET register_slice_mode_rdch=Fully_Registered -CSET register_slice_mode_wach=Fully_Registered -CSET register_slice_mode_wdch=Fully_Registered -CSET register_slice_mode_wrch=Fully_Registered -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET ruser_width=1 -CSET synchronization_stages=2 -CSET synchronization_stages_axi=2 -CSET tdata_width=64 -CSET tdest_width=4 -CSET tid_width=8 -CSET tkeep_width=4 -CSET tstrb_width=4 -CSET tuser_width=4 -CSET underflow_flag=false -CSET underflow_flag_axi=false -CSET underflow_sense=Active_High -CSET underflow_sense_axi=Active_High -CSET use_clock_enable=false -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET wach_type=FIFO -CSET wdch_type=FIFO -CSET wrch_type=FIFO -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=9 -CSET wuser_width=1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T12:39:56Z -# END Extra information -GENERATE -# CRC: d1e681fd Index: experimental_jumbo_frames_version/fpga/atlys/dcm1.xco =================================================================== --- experimental_jumbo_frames_version/fpga/atlys/dcm1.xco (revision 21) +++ experimental_jumbo_frames_version/fpga/atlys/dcm1.xco (nonexistent) @@ -1,269 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Sun Sep 28 17:26:58 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:clk_wiz:3.6 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 -# END Select -# BEGIN Parameters -CSET calc_done=DONE -CSET clk_in_sel_port=CLK_IN_SEL -CSET clk_out1_port=CLK_OUT1 -CSET clk_out1_use_fine_ps_gui=false -CSET clk_out2_port=CLK_OUT2 -CSET clk_out2_use_fine_ps_gui=false -CSET clk_out3_port=CLK_OUT3 -CSET clk_out3_use_fine_ps_gui=false -CSET clk_out4_port=CLK_OUT4 -CSET clk_out4_use_fine_ps_gui=false -CSET clk_out5_port=CLK_OUT5 -CSET clk_out5_use_fine_ps_gui=false -CSET clk_out6_port=CLK_OUT6 -CSET clk_out6_use_fine_ps_gui=false -CSET clk_out7_port=CLK_OUT7 -CSET clk_out7_use_fine_ps_gui=false -CSET clk_valid_port=CLK_VALID -CSET clkfb_in_n_port=CLKFB_IN_N -CSET clkfb_in_p_port=CLKFB_IN_P -CSET clkfb_in_port=CLKFB_IN -CSET clkfb_in_signaling=SINGLE -CSET clkfb_out_n_port=CLKFB_OUT_N -CSET clkfb_out_p_port=CLKFB_OUT_P -CSET clkfb_out_port=CLKFB_OUT -CSET clkfb_stopped_port=CLKFB_STOPPED -CSET clkin1_jitter_ps=100.0 -CSET clkin1_ui_jitter=0.010 -CSET clkin2_jitter_ps=100.0 -CSET clkin2_ui_jitter=0.010 -CSET clkout1_drives=BUFG -CSET clkout1_requested_duty_cycle=50.000 -CSET clkout1_requested_out_freq=125.000 -CSET clkout1_requested_phase=0.000 -CSET clkout2_drives=BUFG -CSET clkout2_requested_duty_cycle=50.000 -CSET clkout2_requested_out_freq=64.000 -CSET clkout2_requested_phase=0.000 -CSET clkout2_used=true -CSET clkout3_drives=BUFG -CSET clkout3_requested_duty_cycle=50.000 -CSET clkout3_requested_out_freq=64.000 -CSET clkout3_requested_phase=0.000 -CSET clkout3_used=true -CSET clkout4_drives=BUFG -CSET clkout4_requested_duty_cycle=50.000 -CSET clkout4_requested_out_freq=100.000 -CSET clkout4_requested_phase=0.000 -CSET clkout4_used=false -CSET clkout5_drives=BUFG -CSET clkout5_requested_duty_cycle=50.000 -CSET clkout5_requested_out_freq=100.000 -CSET clkout5_requested_phase=0.000 -CSET clkout5_used=false -CSET clkout6_drives=BUFG -CSET clkout6_requested_duty_cycle=50.000 -CSET clkout6_requested_out_freq=100.000 -CSET clkout6_requested_phase=0.000 -CSET clkout6_used=false -CSET clkout7_drives=BUFG -CSET clkout7_requested_duty_cycle=50.000 -CSET clkout7_requested_out_freq=100.000 -CSET clkout7_requested_phase=0.000 -CSET clkout7_used=false -CSET clock_mgr_type=AUTO -CSET component_name=dcm1 -CSET daddr_port=DADDR -CSET dclk_port=DCLK -CSET dcm_clk_feedback=1X -CSET dcm_clk_out1_port=CLKFX -CSET dcm_clk_out2_port=CLK0 -CSET dcm_clk_out3_port=CLK0 -CSET dcm_clk_out4_port=CLK0 -CSET dcm_clk_out5_port=CLK0 -CSET dcm_clk_out6_port=CLK0 -CSET dcm_clkdv_divide=2.0 -CSET dcm_clkfx_divide=4 -CSET dcm_clkfx_multiply=5 -CSET dcm_clkgen_clk_out1_port=CLKFX -CSET dcm_clkgen_clk_out2_port=CLKFX -CSET dcm_clkgen_clk_out3_port=CLKFX -CSET dcm_clkgen_clkfx_divide=1 -CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=4 -CSET dcm_clkgen_clkfxdv_divide=2 -CSET dcm_clkgen_clkin_period=10.000 -CSET dcm_clkgen_notes=None -CSET dcm_clkgen_spread_spectrum=NONE -CSET dcm_clkgen_startup_wait=false -CSET dcm_clkin_divide_by_2=false -CSET dcm_clkin_period=10.000 -CSET dcm_clkout_phase_shift=NONE -CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS -CSET dcm_notes=None -CSET dcm_phase_shift=0 -CSET dcm_pll_cascade=NONE -CSET dcm_startup_wait=false -CSET den_port=DEN -CSET din_port=DIN -CSET dout_port=DOUT -CSET drdy_port=DRDY -CSET dwe_port=DWE -CSET feedback_source=FDBK_AUTO -CSET in_freq_units=Units_MHz -CSET in_jitter_units=Units_UI -CSET input_clk_stopped_port=INPUT_CLK_STOPPED -CSET jitter_options=UI -CSET jitter_sel=No_Jitter -CSET locked_port=LOCKED -CSET mmcm_bandwidth=OPTIMIZED -CSET mmcm_clkfbout_mult_f=4.000 -CSET mmcm_clkfbout_phase=0.000 -CSET mmcm_clkfbout_use_fine_ps=false -CSET mmcm_clkin1_period=10.000 -CSET mmcm_clkin2_period=10.000 -CSET mmcm_clkout0_divide_f=4.000 -CSET mmcm_clkout0_duty_cycle=0.500 -CSET mmcm_clkout0_phase=0.000 -CSET mmcm_clkout0_use_fine_ps=false -CSET mmcm_clkout1_divide=1 -CSET mmcm_clkout1_duty_cycle=0.500 -CSET mmcm_clkout1_phase=0.000 -CSET mmcm_clkout1_use_fine_ps=false -CSET mmcm_clkout2_divide=1 -CSET mmcm_clkout2_duty_cycle=0.500 -CSET mmcm_clkout2_phase=0.000 -CSET mmcm_clkout2_use_fine_ps=false -CSET mmcm_clkout3_divide=1 -CSET mmcm_clkout3_duty_cycle=0.500 -CSET mmcm_clkout3_phase=0.000 -CSET mmcm_clkout3_use_fine_ps=false -CSET mmcm_clkout4_cascade=false -CSET mmcm_clkout4_divide=1 -CSET mmcm_clkout4_duty_cycle=0.500 -CSET mmcm_clkout4_phase=0.000 -CSET mmcm_clkout4_use_fine_ps=false -CSET mmcm_clkout5_divide=1 -CSET mmcm_clkout5_duty_cycle=0.500 -CSET mmcm_clkout5_phase=0.000 -CSET mmcm_clkout5_use_fine_ps=false -CSET mmcm_clkout6_divide=1 -CSET mmcm_clkout6_duty_cycle=0.500 -CSET mmcm_clkout6_phase=0.000 -CSET mmcm_clkout6_use_fine_ps=false -CSET mmcm_clock_hold=false -CSET mmcm_compensation=ZHOLD -CSET mmcm_divclk_divide=1 -CSET mmcm_notes=None -CSET mmcm_ref_jitter1=0.010 -CSET mmcm_ref_jitter2=0.010 -CSET mmcm_startup_wait=false -CSET num_out_clks=3 -CSET override_dcm=false -CSET override_dcm_clkgen=false -CSET override_mmcm=false -CSET override_pll=false -CSET platform=lin64 -CSET pll_bandwidth=OPTIMIZED -CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=5 -CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=10.000 -CSET pll_clkout0_divide=4 -CSET pll_clkout0_duty_cycle=0.500 -CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=8 -CSET pll_clkout1_duty_cycle=0.500 -CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=8 -CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=0.000 -CSET pll_clkout3_divide=1 -CSET pll_clkout3_duty_cycle=0.500 -CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=1 -CSET pll_clkout4_duty_cycle=0.500 -CSET pll_clkout4_phase=0.000 -CSET pll_clkout5_divide=1 -CSET pll_clkout5_duty_cycle=0.500 -CSET pll_clkout5_phase=0.000 -CSET pll_compensation=SYSTEM_SYNCHRONOUS -CSET pll_divclk_divide=1 -CSET pll_notes=None -CSET pll_ref_jitter=0.010 -CSET power_down_port=POWER_DOWN -CSET prim_in_freq=100.000 -CSET prim_in_jitter=0.010 -CSET prim_source=Single_ended_clock_capable_pin -CSET primary_port=CLK_IN1 -CSET primitive=MMCM -CSET primtype_sel=PLL_BASE -CSET psclk_port=PSCLK -CSET psdone_port=PSDONE -CSET psen_port=PSEN -CSET psincdec_port=PSINCDEC -CSET relative_inclk=REL_PRIMARY -CSET reset_port=RESET -CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.010 -CSET secondary_port=CLK_IN2 -CSET secondary_source=Single_ended_clock_capable_pin -CSET ss_mod_freq=250 -CSET ss_mode=CENTER_HIGH -CSET status_port=STATUS -CSET summary_strings=empty -CSET use_clk_valid=false -CSET use_clkfb_stopped=false -CSET use_dyn_phase_shift=false -CSET use_dyn_reconfig=false -CSET use_freeze=false -CSET use_freq_synth=true -CSET use_inclk_stopped=false -CSET use_inclk_switchover=false -CSET use_locked=true -CSET use_max_i_jitter=false -CSET use_min_o_jitter=false -CSET use_min_power=false -CSET use_phase_alignment=true -CSET use_power_down=false -CSET use_reset=true -CSET use_spread_spectrum=false -CSET use_spread_spectrum_1=false -CSET use_status=false -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-05-10T12:44:55Z -# END Extra information -GENERATE -# CRC: fdec5cf3 Index: experimental_jumbo_frames_version/fpga/atlys/eth_receiver8.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/atlys/eth_receiver8.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/atlys/eth_receiver8.vhd (nonexistent) @@ -1,350 +0,0 @@ -------------------------------------------------------------------------------- --- Title : FPGA Ethernet interface - block receiving packets from MII PHY --- Project : -------------------------------------------------------------------------------- --- File : eth_receiver4.vhd --- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) --- License : BSD License --- Company : --- Created : 2012-03-30 --- Last update: 2014-10-19 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: This file implements the state machine, which manages the --- table of packet descriptors, used to resend only not confirmed packets -------------------------------------------------------------------------------- --- Copyright (c) 2012 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2012-03-30 1.0 WZab Created -------------------------------------------------------------------------------- - --- Uwaga! Tu mamy rzeczywiste problemy z obsluga odebranych pakietow! --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.desc_mgr_pkg.all; -use work.pkt_ack_pkg.all; -use work.pkg_newcrc32_d8.all; - -entity eth_receiver is - - port ( - -- Configuration - peer_mac : out std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - transmit_data : out std_logic; - restart : out std_logic; - -- ACK FIFO interface - ack_fifo_full : in std_logic; - ack_fifo_wr_en : out std_logic; - ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); - -- System interface - clk : in std_logic; - rst_n : in std_logic; - dbg : out std_logic_vector(3 downto 0); - -- MAC inerface - Rx_Clk : in std_logic; - Rx_Er : in std_logic; - Rx_Dv : in std_logic; - RxD : in std_logic_vector(7 downto 0) - ); - -end eth_receiver; - - -architecture beh1 of eth_receiver is - - type T_STATE is (ST_RCV_IDLE, ST_RCV_PREAMB, ST_RCV_DEST, ST_RCV_SOURCE, ST_RCV_CMD, - ST_RCV_PROTO, ST_RCV_WAIT_IDLE, ST_RCV_ARGS, ST_RCV_PROCESS, ST_RCV_UPDATE, - ST_RCV_TRAILER); - - - - function rev(a : in std_logic_vector) - return std_logic_vector is - variable result : std_logic_vector(a'range); - alias aa : std_logic_vector(a'reverse_range) is a; - begin - for i in aa'range loop - result(i) := aa(i); - end loop; - return result; - end; -- function reverse_any_bus - - - type T_RCV_REGS is record - state : T_STATE; - transmit_data : std_logic; - restart : std_logic; - update_flag : std_logic; - count : integer range 0 to 256; - dbg : std_logic_vector(3 downto 0); - crc32 : std_logic_vector(31 downto 0); - cmd : std_logic_vector(63 downto 0); - mac_addr : std_logic_vector(47 downto 0); - peer_mac : std_logic_vector(47 downto 0); - end record; - - constant RCV_REGS_INI : T_RCV_REGS := ( - state => ST_RCV_IDLE, - transmit_data => '0', - restart => '0', - update_flag => '0', - count => 0, - dbg => (others => '0'), - crc32 => (others => '0'), - cmd => (others => '0'), - mac_addr => (others => '0'), - peer_mac => (others => '0') - ); - - - signal r, r_n : T_RCV_REGS := RCV_REGS_INI; - - type T_RCV_COMB is record - ack_fifo_wr_en : std_logic; - ack_fifo_din : std_logic_vector(pkt_ack_width-1 downto 0); - Rx_mac_rd : std_logic; - restart : std_logic; - end record; - - constant RCV_COMB_DEFAULT : T_RCV_COMB := ( - ack_fifo_wr_en => '0', - ack_fifo_din => (others => '0'), - Rx_mac_rd => '0', - restart => '0' - ); - - signal c : T_RCV_COMB := RCV_COMB_DEFAULT; - - signal rx_rst_n, rx_rst_n_0, rx_rst_n_1 : std_logic := '0'; - signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; - - constant proto_id : std_logic_vector(31 downto 0) := x"fade0100"; - -begin -- beh1 - - ack_fifo_din <= c.ack_fifo_din; - ack_fifo_wr_en <= c.ack_fifo_wr_en; - - dbg <= r.dbg; - - -- Reading of ethernet data - rdp1 : process (Rx_Clk, rx_rst_n) - begin -- process rdp1 - if rx_rst_n = '0' then -- asynchronous reset (active low) - r <= RCV_REGS_INI; - elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge - r <= r_n; - end if; - end process rdp1; - - rdp2 : process (RxD, Rx_Dv, ack_fifo_full, my_ether_type, my_mac, r, - update_flag) - - variable ack_pkt_in : pkt_ack; - variable v_mac_addr : std_logic_vector(47 downto 0); - variable v_cmd : std_logic_vector(63 downto 0); - - begin -- process - c <= RCV_COMB_DEFAULT; - r_n <= r; - --dbg <= "1111"; - case r.state is - when ST_RCV_IDLE => - --dbg <= "0000"; - if Rx_Dv = '1' then - if RxD = x"55" then - r_n.count <= 1; - r_n.state <= ST_RCV_PREAMB; - end if; - end if; - when ST_RCV_PREAMB => - --dbg <= "0001"; - if Rx_Dv = '0' then - -- interrupted preamble reception - r_n.state <= ST_RCV_IDLE; - elsif RxD = x"55" then - if r.count < 7 then - r_n.count <= r.count + 1; - end if; - elsif (RxD = x"d5") and (r.count = 7) then --D - -- We start reception of the packet - r_n.crc32 <= (others => '1'); - r_n.count <= 0; - -- First we receive the sender address - r_n.state <= ST_RCV_DEST; - else - -- something wrong happened during preamble detection - r_n.state <= ST_RCV_WAIT_IDLE; - end if; - when ST_RCV_DEST => - --dbg <= "0010"; - if Rx_Dv = '1' then - r_n.crc32 <= newcrc32_d8(RxD, r.crc32); - if my_mac(47-r.count*8 downto 40-r.count*8) /= RxD then - -- Not our address, return to IDLE! - r_n.state <= ST_RCV_WAIT_IDLE; - elsif r.count < 5 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.state <= ST_RCV_SOURCE; - -- Our address! Receive the sender - end if; - else - -- packet broken? - r_n.state <= ST_RCV_IDLE; - end if; - when ST_RCV_SOURCE => - --dbg <= "0011"; - if Rx_Dv = '1' then - r_n.crc32 <= newcrc32_d8(RxD, r.crc32); - v_mac_addr := r.mac_addr; - v_mac_addr(47-r.count*8 downto 40-r.count*8) := RxD; - r_n.mac_addr <= v_mac_addr; - if r.count < 5 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.state <= ST_RCV_PROTO; - end if; - else - -- packet broken? - r_n.state <= ST_RCV_IDLE; - end if; - when ST_RCV_PROTO => - if Rx_Dv = '1' then - r_n.crc32 <= newcrc32_d8(RxD, r.crc32); - if proto_id(31-r.count*8 downto 24-r.count*8) /= RxD then - -- Incorrect type of frame or protocol ID - r_n.state <= ST_RCV_IDLE; - elsif r.count < 3 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.state <= ST_RCV_CMD; - end if; - end if; - when ST_RCV_CMD => - --dbg <= "0100"; - if Rx_Dv = '1' then - r_n.crc32 <= newcrc32_d8(RxD, r.crc32); - v_cmd := r.cmd; - v_cmd(63-r.count*8 downto 56-r.count*8) := RxD; - r_n.cmd <= v_cmd; - if r.count < 7 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.state <= ST_RCV_TRAILER; - end if; - end if; - when ST_RCV_TRAILER => - -- No detection of too long frames! - --dbg <= "0110"; - if Rx_Dv = '0' then - -- End of packet, check the checksum - if r.crc32 /= x"c704dd7b" then - -- Wrong checksum, ignore packet - r_n.state <= ST_RCV_IDLE; - else - -- Checksum OK, process the packet - r_n.state <= ST_RCV_PROCESS; - end if; - else - r_n.crc32 <= newcrc32_d8(RxD, r.crc32); - end if; - when ST_RCV_PROCESS => - --For ACK - --dbg <= "0111"; - -- We can copy the sender - r_n.peer_mac <= r.mac_addr; - case to_integer(unsigned(r.cmd(63 downto 48))) is - -- Handle commands, which require immediate action - when FCMD_START => - r_n.dbg(0) <= not r.dbg(0); - -- Start transmission command - r_n.transmit_data <= '1'; - when FCMD_STOP => - r_n.dbg(1) <= not r.dbg(1); - -- Stop transmission command - r_n.transmit_data <= '0'; - when FCMD_RESET => - r_n.dbg(3) <= not r.dbg(3); - -- Stop transmission and retransmission - r_n.restart <= '1'; - when others => - null; - end case; - -- All commands are written to the acknowledge and commands - -- FIFO, so they will be handled by the descriptor manager - -- Handle the user commands - if ack_fifo_full = '0' then - ack_pkt_in.cmd := unsigned(r.cmd(63 downto 48)); - ack_pkt_in.seq := unsigned(r.cmd(47 downto 32)); - ack_pkt_in.pkt := unsigned(r.cmd(31 downto 0)); - c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); - c.ack_fifo_wr_en <= '1'; - end if; - r_n.state <= ST_RCV_UPDATE; - when ST_RCV_UPDATE => - --dbg <= "1000"; - r_n.update_flag <= not r.update_flag; - r_n.state <= ST_RCV_IDLE; - when ST_RCV_WAIT_IDLE => - --dbg <= "1001"; - if Rx_Dv = '0' then - r_n.state <= ST_RCV_IDLE; - end if; - when others => null; - end case; - end process rdp2; - - -- Synchronization of the reset signal for the Rx_Clk domain - process (Rx_Clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - rx_rst_n_0 <= '0'; - rx_rst_n_1 <= '0'; - rx_rst_n <= '0'; - elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge - rx_rst_n_0 <= rst_n; - rx_rst_n_1 <= rx_rst_n_0; - rx_rst_n <= rx_rst_n_1; - end if; - end process; - - - -- Synchronization of output signals between the clock domains - process (clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - peer_mac <= (others => '0'); - transmit_data <= '0'; - restart <= '0'; - update_flag_0 <= '0'; - update_flag_1 <= '0'; - update_flag <= '0'; - elsif clk'event and clk = '1' then -- rising clock edge - -- Synchronization of the update_flag - update_flag_0 <= r.update_flag; - update_flag_1 <= update_flag_0; - update_flag <= update_flag_1; - -- When update flag has changed, rewrite synchronized fields - if update_flag /= update_flag_1 then - peer_mac <= r.peer_mac; - transmit_data <= r.transmit_data; - restart <= r.restart; - end if; - end if; - end process; - -end beh1; Index: experimental_jumbo_frames_version/fpga/atlys/atlys_eth_top.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/atlys/atlys_eth_top.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/atlys/atlys_eth_top.vhd (nonexistent) @@ -1,583 +0,0 @@ -------------------------------------------------------------------------------- --- Title : L3 FADE protocol demo for Digilent Atlys board --- Project : -------------------------------------------------------------------------------- --- File : atlys_eth_top.vhd --- Author : Wojciech M. Zabolotny --- License : BSD License --- Company : --- Created : 2010-08-03 --- Last update: 2014-10-20 --- Platform : --- Standard : VHDL -------------------------------------------------------------------------------- --- Description: --- This file implements the top entity, integrating all component -------------------------------------------------------------------------------- --- Copyright (c) 2012 --- This is public domain code!!! -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2010-08-03 1.0 wzab Created -------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.pkt_ack_pkg.all; -use work.desc_mgr_pkg.all; - -entity atlys_eth is - - port ( - cpu_reset : in std_logic; --- -- DDR2 interface --- ddr2_a : out std_logic_vector(12 downto 0); --- ddr2_ba : out std_logic_vector(2 downto 0); --- ddr2_cas_b : out std_logic; --- ddr2_cke : out std_logic; --- ddr2_clk_n : out std_logic; --- ddr2_clk_p : out std_logic; --- ddr2_dq : inout std_logic_vector(15 downto 0); --- ddr2_ldm : out std_logic; --- ddr2_ldqs_n : out std_logic; --- ddr2_ldqs_p : out std_logic; --- ddr2_odt : out std_logic; --- ddr2_ras_b : out std_logic; --- ddr2_udm : out std_logic; --- ddr2_udqs_n : out std_logic; --- ddr2_udqs_p : out std_logic; --- ddr2_we_b : out std_logic; --- -- FLASH interface --- flash_a : out std_logic_vector(24 downto 0); --- flash_ce_b : out std_logic; --- flash_d : inout std_logic_vector(7 downto 0); --- flash_oe_b : out std_logic; --- flash_we_b : out std_logic; --- -- FMC interface --- fmc_la28_n : out std_logic; --- fmc_la28_p : out std_logic; --- fmc_la29_n : out std_logic; --- fmc_la29_p : out std_logic; --- fmc_la30_n : out std_logic; --- fmc_la30_p : out std_logic; --- fmc_la31_n : out std_logic; --- fmc_la31_p : out std_logic; --- iic_scl_main : out std_logic; --- iic_sda_main : out std_logic; - - --gpio_hdr : in std_logic_vector(7 downto 0); - --- fmc_clk0_m2c_n : out std_logic; --- fmc_clk0_m2c_p : out std_logic; --- fmc_clk1_m2c_n : out std_logic; --- fmc_clk1_m2c_p : out std_logic; --- fmc_la00_cc_n : out std_logic; --- fmc_la00_cc_p : out std_logic; --- fmc_la01_cc_n : out std_logic; --- fmc_la01_cc_p : out std_logic; --- fmc_la02_n : out std_logic; --- fmc_la02_p : out std_logic; --- fmc_la03_n : out std_logic; --- fmc_la03_p : out std_logic; --- fmc_la04_n : out std_logic; --- fmc_la04_p : out std_logic; --- led : out std_logic_vector(3 downto 0); - switches : in std_logic_vector(7 downto 0); --- flash_oen : out std_logic; --- flash_wen : out std_logic; --- flash_cen : out std_logic; - gpio_led : out std_logic_vector(7 downto 0); - -- PHY interface - phy_col : in std_logic; - phy_crs : in std_logic; - phy_int : in std_logic; - phy_mdc : out std_logic; - phy_mdio : inout std_logic; - phy_reset : out std_logic; - phy_rxclk : in std_logic; - phy_rxctl_rxdv : in std_logic; - phy_rxd : in std_logic_vector(7 downto 0); - phy_rxer : in std_logic; - phy_txclk : in std_logic; - phy_txctl_txen : out std_logic; - phy_txc_gtxclk : out std_logic; - phy_txd : out std_logic_vector(7 downto 0); - phy_txer : out std_logic; - sysclk : in std_logic - ); - -end atlys_eth; - -architecture beh of atlys_eth is - - component dp_ram_scl - generic ( - DATA_WIDTH : integer; - ADDR_WIDTH : integer); - port ( - clk_a : in std_logic; - we_a : in std_logic; - addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); - data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); - q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); - clk_b : in std_logic; - we_b : in std_logic; - addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); - data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); - q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); - end component; - - component ack_fifo - port ( - rst : in std_logic; - wr_clk : in std_logic; - rd_clk : in std_logic; - din : in std_logic_vector(pkt_ack_width-1 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(pkt_ack_width-1 downto 0); - full : out std_logic; - empty : out std_logic); - end component; - - component dcm1 - port ( - CLK_IN1 : in std_logic; - CLK_OUT1 : out std_logic; - CLK_OUT2 : out std_logic; - CLK_OUT3 : out std_logic; - RESET : in std_logic; - LOCKED : out std_logic); - end component; - - component desc_manager is - generic ( - LOG2_N_OF_PKTS : integer; - N_OF_PKTS : integer); - port ( - dta : in std_logic_vector(63 downto 0); - dta_we : in std_logic; - dta_eod : in std_logic; - dta_ready : out std_logic; - pkt_number : out unsigned(31 downto 0); - seq_number : out unsigned(15 downto 0); - cmd_response_out : out std_logic_vector(12*8-1 downto 0); - snd_cmd_start : out std_logic; - snd_start : out std_logic; - flushed : out std_logic; - snd_ready : in std_logic; - dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); - dmem_dta : out std_logic_vector(63 downto 0); - dmem_we : out std_logic; - ack_fifo_empty : in std_logic; - ack_fifo_rd_en : out std_logic; - ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); - cmd_code : out std_logic_vector(15 downto 0); - cmd_seq : out std_logic_vector(15 downto 0); - cmd_arg : out std_logic_vector(31 downto 0); - cmd_run : out std_logic; - cmd_retr_s : out std_logic; - cmd_ack : in std_logic; - cmd_response_in : in std_logic_vector(8*12-1 downto 0); - transmit_data : in std_logic; - transm_delay : out unsigned(31 downto 0); - dbg : out std_logic_vector(3 downto 0); - clk : in std_logic; - rst_n : in std_logic); - end component desc_manager; - - component cmd_proc is - port ( - cmd_code : in std_logic_vector(15 downto 0); - cmd_seq : in std_logic_vector(15 downto 0); - cmd_arg : in std_logic_vector(31 downto 0); - cmd_run : in std_logic; - cmd_ack : out std_logic; - cmd_response : out std_logic_vector(8*12-1 downto 0); - clk : in std_logic; - rst_p : in std_logic); - end component cmd_proc; - - component eth_sender is - port ( - peer_mac : in std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - pkt_number : in unsigned(31 downto 0); - seq_number : in unsigned(15 downto 0); - transm_delay : in unsigned(31 downto 0); - clk : in std_logic; - rst_n : in std_logic; - ready : out std_logic; - flushed : in std_logic; - start : in std_logic; - cmd_start : in std_logic; - tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); - tx_mem_data : in std_logic_vector(63 downto 0); - cmd_response : in std_logic_vector(12*8-1 downto 0); - Tx_Clk : in std_logic; - Tx_En : out std_logic; - TxD : out std_logic_vector(7 downto 0)); - end component eth_sender; - - component eth_receiver - port ( - peer_mac : out std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - transmit_data : out std_logic; - restart : out std_logic; - ack_fifo_full : in std_logic; - ack_fifo_wr_en : out std_logic; - ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); - clk : in std_logic; - rst_n : in std_logic; - dbg : out std_logic_vector(3 downto 0); - Rx_Clk : in std_logic; - Rx_Er : in std_logic; - Rx_Dv : in std_logic; - RxD : in std_logic_vector(7 downto 0)); - end component; - - component jtag_bus_ctl - generic ( - d_width : integer; - a_width : integer); - port ( - din : in std_logic_vector((d_width-1) downto 0); - dout : out std_logic_vector((d_width-1) downto 0); - addr : out std_logic_vector((a_width-1) downto 0); - nwr : out std_logic; - nrd : out std_logic); - end component; - - - signal my_mac : std_logic_vector(47 downto 0); - constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; - signal transm_delay : unsigned(31 downto 0); - signal restart : std_logic; - signal dta : std_logic_vector(63 downto 0); - signal dta_we : std_logic := '0'; - signal dta_ready : std_logic; - signal snd_start : std_logic; - signal snd_ready : std_logic; - signal flushed : std_logic := '0'; - signal dta_eod : std_logic := '0'; - signal dmem_addr : std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); - signal dmem_dta : std_logic_vector(63 downto 0); - signal dmem_we : std_logic; - signal addr_a, addr_b : integer; - signal test_dta : unsigned(63 downto 0); - signal tx_mem_addr : std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); - signal tx_mem_data : std_logic_vector(63 downto 0); - - signal arg1, arg2, res1 : unsigned(7 downto 0); - signal res2 : unsigned(15 downto 0); - signal sender : std_logic_vector(47 downto 0); - signal peer_mac : std_logic_vector(47 downto 0); - signal inputs, din, dout : std_logic_vector(7 downto 0); - signal addr, leds : std_logic_vector(3 downto 0); - signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic; - signal not_cpu_reset, rst_del : std_logic; - - signal set_number : unsigned(15 downto 0); - signal pkt_number : unsigned(31 downto 0); - signal seq_number : unsigned(15 downto 0) := (others => '0'); - signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); - - - signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); - signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; - signal transmit_data, td_del0, td_del1 : std_logic := '0'; - - signal read_addr : std_logic_vector(15 downto 0); - signal read_data : std_logic_vector(15 downto 0); - signal read_done, read_in_progress : std_logic; - - signal dbg : std_logic_vector(3 downto 0); - - signal led_counter : integer := 0; - signal tx_counter : integer := 10000; - signal Reset : std_logic; - signal Clk_125M : std_logic; - signal Clk_user : std_logic; - signal Clk_reg : std_logic; - signal Speed : std_logic_vector(2 downto 0); - signal Rx_mac_ra : std_logic; - signal Rx_mac_rd : std_logic; - signal Rx_mac_data : std_logic_vector(31 downto 0); - signal Rx_mac_BE : std_logic_vector(1 downto 0); - signal Rx_mac_pa : std_logic; - signal Rx_mac_sop : std_logic; - signal Rx_mac_eop : std_logic; - signal Tx_mac_wa : std_logic; - signal Tx_mac_wr : std_logic; - signal Tx_mac_data : std_logic_vector(31 downto 0); - signal Tx_mac_BE : std_logic_vector(1 downto 0); - signal Tx_mac_sop : std_logic; - signal Tx_mac_eop : std_logic; - signal Pkg_lgth_fifo_rd : std_logic; - signal Pkg_lgth_fifo_ra : std_logic; - signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0); - signal Gtx_clk : std_logic; - signal Rx_clk : std_logic; - signal Tx_clk : std_logic; - signal Tx_er : std_logic; - signal Tx_en : std_logic; - signal Txd : std_logic_vector(7 downto 0); - signal Rx_er : std_logic; - signal Rx_dv : std_logic; - signal Rxd : std_logic_vector(7 downto 0); - signal Crs : std_logic; - signal Col : std_logic; - signal CSB : std_logic := '1'; - signal WRB : std_logic := '1'; - signal CD_in : std_logic_vector(15 downto 0) := (others => '0'); - signal CD_out : std_logic_vector(15 downto 0) := (others => '0'); - signal CA : std_logic_vector(7 downto 0) := (others => '0'); - signal s_Mdo : std_logic; - signal s_MdoEn : std_logic; - signal s_Mdi : std_logic; - - signal s_dta_we : std_logic; - - -- signals related to user commands handling - signal cmd_response_in, cmd_response_out : std_logic_vector(12*8-1 downto 0) := (others => '0'); - signal cmd_start : std_logic := '0'; - signal cmd_run : std_logic := '0'; - signal cmd_retr_s : std_logic := '0'; - signal cmd_ack : std_logic := '0'; - signal cmd_code : std_logic_vector(15 downto 0) := (others => '0'); - signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0'); - signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0'); - - -begin -- beh - - -- Allow selection of MAC with the DIP switch to allow testing - -- with multiple boards! - with switches(1 downto 0) select - my_mac <= - x"de_ad_ba_be_be_ef" when "00", - x"de_ad_ba_be_be_e1" when "01", - x"de_ad_ba_be_be_e2" when "10", - x"de_ad_ba_be_be_e3" when "11"; - - --- iic_sda_main <= 'Z'; --- iic_scl_main <= 'Z'; - - not_cpu_reset <= not cpu_reset; - rst_p <= not rst_n; - --- flash_oe_b <= '1'; --- flash_we_b <= '1'; --- flash_ce_b <= '1'; - - tx_clk <= Clk_125M; - rx_clk <= phy_rxclk; - - Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra; - - addr_a <= to_integer(unsigned(dmem_addr)); - addr_b <= to_integer(unsigned(tx_mem_addr)); - - dp_ram_scl_1 : dp_ram_scl - generic map ( - DATA_WIDTH => 64, - ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT) - port map ( - clk_a => clk_user, - we_a => dmem_we, - addr_a => dmem_addr, - data_a => dmem_dta, - q_a => open, - clk_b => Tx_clk, - we_b => '0', - addr_b => tx_mem_addr, - data_b => (others => '0'), - q_b => tx_mem_data); - - desc_manager_1 : desc_manager - generic map ( - LOG2_N_OF_PKTS => LOG2_N_OF_PKTS, - N_OF_PKTS => N_OF_PKTS) - port map ( - dta => dta, - dta_we => dta_we, - dta_ready => dta_ready, - pkt_number => pkt_number, - seq_number => seq_number, - cmd_response_out => cmd_response_out, - snd_start => snd_start, - flushed => flushed, - snd_cmd_start => cmd_start, - snd_ready => snd_ready, - dta_eod => dta_eod, - dmem_addr => dmem_addr, - dmem_dta => dmem_dta, - dmem_we => dmem_we, - ack_fifo_empty => ack_fifo_empty, - ack_fifo_rd_en => ack_fifo_rd_en, - ack_fifo_dout => ack_fifo_dout, - cmd_code => cmd_code, - cmd_seq => cmd_seq, - cmd_arg => cmd_arg, - cmd_run => cmd_run, - cmd_retr_s => cmd_retr_s, - cmd_ack => cmd_ack, - cmd_response_in => cmd_response_in, - transmit_data => transmit_data, - transm_delay => transm_delay, - dbg => dbg, - clk => clk_user, - rst_n => rst_n); - - cmd_proc_1 : cmd_proc - port map ( - cmd_code => cmd_code, - cmd_seq => cmd_seq, - cmd_arg => cmd_arg, - cmd_run => cmd_run, - cmd_ack => cmd_ack, - cmd_response => cmd_response_in, - clk => clk_user, - rst_p => rst_p); - - eth_sender_1 : eth_sender - port map ( - peer_mac => peer_mac, - my_mac => my_mac, - my_ether_type => my_ether_type, - pkt_number => pkt_number, - seq_number => seq_number, - transm_delay => transm_delay, - clk => clk_user, - rst_n => rst_n, - ready => snd_ready, - flushed => flushed, - start => snd_start, - cmd_start => cmd_start, - tx_mem_addr => tx_mem_addr, - tx_mem_data => tx_mem_data, - cmd_response => cmd_response_out, - Tx_Clk => tx_clk, - Tx_En => phy_txctl_txen, - TxD => PHY_Txd); - - eth_receiver_2 : eth_receiver - port map ( - peer_mac => peer_mac, - my_mac => my_mac, - my_ether_type => my_ether_type, - transmit_data => transmit_data, - restart => restart, - ack_fifo_full => ack_fifo_full, - ack_fifo_wr_en => ack_fifo_wr_en, - ack_fifo_din => ack_fifo_din, - clk => clk_user, - rst_n => rst_n, - dbg => open, --dbg, - Rx_Clk => rx_clk, - Rx_Er => PHY_Rxer, - Rx_Dv => phy_rxctl_rxdv, - RxD => PHY_Rxd); - - dcm1_1 : dcm1 - port map ( - CLK_IN1 => sysclk, - CLK_OUT1 => Clk_125M, - CLK_OUT2 => Clk_user, - CLK_OUT3 => Clk_reg, - RESET => not_cpu_reset, - LOCKED => dcm_locked); - - process (Clk_user, not_cpu_reset) - begin -- process - if not_cpu_reset = '1' then -- asynchronous reset (active low) - rst_n <= '0'; - rst_del <= '0'; - elsif Clk_user'event and Clk_user = '1' then -- rising clock edge - if restart = '1' then - rst_n <= '0'; - rst_del <= '0'; - else - if dcm_locked = '1' then - rst_del <= '1'; - rst_n <= rst_del; - end if; - end if; - end if; - end process; - - -- reset - - phy_reset <= rst_n; - - -- Connection of MDI - --s_Mdi <= PHY_MDIO; - --PHY_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo; - - phy_txer <= '0'; - phy_mdio <= 'Z'; - phy_mdc <= '0'; - - phy_txc_gtxclk <= tx_clk; - - ack_fifo_1 : ack_fifo - port map ( - rst => rst_p, - wr_clk => rx_clk, - rd_clk => Clk_user, - din => ack_fifo_din, - wr_en => ack_fifo_wr_en, - rd_en => ack_fifo_rd_en, - dout => ack_fifo_dout, - full => ack_fifo_full, - empty => ack_fifo_empty); - - --E_TXD <= s_Txd(3 downto 0); - --s_Rxd <= "0000" & E_RXD; - - -- signal generator - - dta <= std_logic_vector(test_dta); - s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; - dta_we <= s_dta_we; - - process (Clk_user, rst_n) - begin -- process - - if rst_n = '0' then -- asynchronous reset (active low) - td_del0 <= '0'; - td_del1 <= '0'; - test_dta <= (others => '0'); - elsif Clk_user'event and Clk_user = '1' then -- rising clock edge - if s_dta_we = '1' then - test_dta <= test_dta + x"1234567809abcdef"; - end if; - -- Generate the dta_eod pulse after transmit_data - -- goes low - td_del0 <= transmit_data; - td_del1 <= td_del0; - if (td_del1 = '1') and (td_del0 = '0') then - dta_eod <= '1'; - else - dta_eod <= '0'; - end if; - end if; - end process; - - -- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2)); - gpio_led(0) <= snd_ready; - gpio_led(1) <= transmit_data; - gpio_led(2) <= flushed; - gpio_led(3) <= Tx_mac_wa; - gpio_led(7 downto 4) <= dbg; ---gpio_led(6) <= ack_fifo_full; ---gpio_led(7) <= not ack_fifo_empty; -end beh; Index: experimental_jumbo_frames_version/fpga/pkg_newcrc32_d16.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/pkg_newcrc32_d16.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/pkg_newcrc32_d16.vhd (nonexistent) @@ -1,57 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -package pkg_newcrc32_d16 is - -- CRC update for 32-bit CRC and 16-bit data (LSB first) - -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] - function newcrc32_d16( - din : std_logic_vector(15 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector; -end pkg_newcrc32_d16; - -package body pkg_newcrc32_d16 is - function newcrc32_d16( - din : std_logic_vector(15 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector is - variable c, n : std_logic_vector(31 downto 0); - variable d : std_logic_vector(15 downto 0); - begin - c := crc; - d := din; - n(0) := c(16) xor c(22) xor c(25) xor c(26) xor c(28) xor d(3) xor d(5) xor d(6) xor d(9) xor d(15); - n(1) := c(16) xor c(17) xor c(22) xor c(23) xor c(25) xor c(27) xor c(28) xor c(29) xor d(2) xor d(3) xor d(4) xor d(6) xor d(8) xor d(9) xor d(14) xor d(15); - n(2) := c(16) xor c(17) xor c(18) xor c(22) xor c(23) xor c(24) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(7) xor d(8) xor d(9) xor d(13) xor d(14) xor d(15); - n(3) := c(17) xor c(18) xor c(19) xor c(23) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(6) xor d(7) xor d(8) xor d(12) xor d(13) xor d(14); - n(4) := c(16) xor c(18) xor c(19) xor c(20) xor c(22) xor c(24) xor c(27) xor c(28) xor c(31) xor d(0) xor d(3) xor d(4) xor d(7) xor d(9) xor d(11) xor d(12) xor d(13) xor d(15); - n(5) := c(16) xor c(17) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(26) xor c(29) xor d(2) xor d(5) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(14) xor d(15); - n(6) := c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(27) xor c(30) xor d(1) xor d(4) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14); - n(7) := c(16) xor c(18) xor c(19) xor c(21) xor c(23) xor c(24) xor c(26) xor c(31) xor d(0) xor d(5) xor d(7) xor d(8) xor d(10) xor d(12) xor d(13) xor d(15); - n(8) := c(16) xor c(17) xor c(19) xor c(20) xor c(24) xor c(26) xor c(27) xor c(28) xor d(3) xor d(4) xor d(5) xor d(7) xor d(11) xor d(12) xor d(14) xor d(15); - n(9) := c(17) xor c(18) xor c(20) xor c(21) xor c(25) xor c(27) xor c(28) xor c(29) xor d(2) xor d(3) xor d(4) xor d(6) xor d(10) xor d(11) xor d(13) xor d(14); - n(10) := c(16) xor c(18) xor c(19) xor c(21) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(10) xor d(12) xor d(13) xor d(15); - n(11) := c(16) xor c(17) xor c(19) xor c(20) xor c(25) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(6) xor d(11) xor d(12) xor d(14) xor d(15); - n(12) := c(16) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(25) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(6) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14) xor d(15); - n(13) := c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(23) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5) xor d(8) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14); - n(14) := c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13); - n(15) := c(19) xor c(20) xor c(21) xor c(23) xor c(24) xor c(25) xor c(28) xor c(31) xor d(0) xor d(3) xor d(6) xor d(7) xor d(8) xor d(10) xor d(11) xor d(12); - n(16) := c(0) xor c(16) xor c(20) xor c(21) xor c(24) xor c(28) xor c(29) xor d(2) xor d(3) xor d(7) xor d(10) xor d(11) xor d(15); - n(17) := c(1) xor c(17) xor c(21) xor c(22) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(9) xor d(10) xor d(14); - n(18) := c(2) xor c(18) xor c(22) xor c(23) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(8) xor d(9) xor d(13); - n(19) := c(3) xor c(19) xor c(23) xor c(24) xor c(27) xor c(31) xor d(0) xor d(4) xor d(7) xor d(8) xor d(12); - n(20) := c(4) xor c(20) xor c(24) xor c(25) xor c(28) xor d(3) xor d(6) xor d(7) xor d(11); - n(21) := c(5) xor c(21) xor c(25) xor c(26) xor c(29) xor d(2) xor d(5) xor d(6) xor d(10); - n(22) := c(6) xor c(16) xor c(25) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(6) xor d(15); - n(23) := c(7) xor c(16) xor c(17) xor c(22) xor c(25) xor c(29) xor c(31) xor d(0) xor d(2) xor d(6) xor d(9) xor d(14) xor d(15); - n(24) := c(8) xor c(17) xor c(18) xor c(23) xor c(26) xor c(30) xor d(1) xor d(5) xor d(8) xor d(13) xor d(14); - n(25) := c(9) xor c(18) xor c(19) xor c(24) xor c(27) xor c(31) xor d(0) xor d(4) xor d(7) xor d(12) xor d(13); - n(26) := c(10) xor c(16) xor c(19) xor c(20) xor c(22) xor c(26) xor d(5) xor d(9) xor d(11) xor d(12) xor d(15); - n(27) := c(11) xor c(17) xor c(20) xor c(21) xor c(23) xor c(27) xor d(4) xor d(8) xor d(10) xor d(11) xor d(14); - n(28) := c(12) xor c(18) xor c(21) xor c(22) xor c(24) xor c(28) xor d(3) xor d(7) xor d(9) xor d(10) xor d(13); - n(29) := c(13) xor c(19) xor c(22) xor c(23) xor c(25) xor c(29) xor d(2) xor d(6) xor d(8) xor d(9) xor d(12); - n(30) := c(14) xor c(20) xor c(23) xor c(24) xor c(26) xor c(30) xor d(1) xor d(5) xor d(7) xor d(8) xor d(11); - n(31) := c(15) xor c(21) xor c(24) xor c(25) xor c(27) xor c(31) xor d(0) xor d(4) xor d(6) xor d(7) xor d(10); - return n; - end newcrc32_d16; -end pkg_newcrc32_d16; - Index: experimental_jumbo_frames_version/fpga/ack.rec =================================================================== --- experimental_jumbo_frames_version/fpga/ack.rec (revision 21) +++ experimental_jumbo_frames_version/fpga/ack.rec (nonexistent) @@ -1,12 +0,0 @@ -# This is a test record - packet acknowledgment -record pkt_ack -# Below are fields definitions -# First two pointers fo linked list -# pkt - number of the packet -pkt,unsigned,32 -# seq - sequential number of the packet -seq,unsigned,16 -# cmd - command - 1 for ACK -cmd,unsigned,16 -end - Index: experimental_jumbo_frames_version/fpga/pkg_newcrc32_d32.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/pkg_newcrc32_d32.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/pkg_newcrc32_d32.vhd (nonexistent) @@ -1,57 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -package pkg_newcrc32_d32 is - -- CRC update for 32-bit CRC and 32-bit data (LSB first) - -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] - function newcrc32_d32( - din : std_logic_vector(31 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector; -end pkg_newcrc32_d32; - -package body pkg_newcrc32_d32 is - function newcrc32_d32( - din : std_logic_vector(31 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector is - variable c, n : std_logic_vector(31 downto 0); - variable d : std_logic_vector(31 downto 0); - begin - c := crc; - d := din; - n(0) := c(0) xor c(6) xor c(9) xor c(10) xor c(12) xor c(16) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7) xor d(15) xor d(19) xor d(21) xor d(22) xor d(25) xor d(31); - n(1) := c(0) xor c(1) xor c(6) xor c(7) xor c(9) xor c(11) xor c(12) xor c(13) xor c(16) xor c(17) xor c(24) xor c(27) xor c(28) xor d(3) xor d(4) xor d(7) xor d(14) xor d(15) xor d(18) xor d(19) xor d(20) xor d(22) xor d(24) xor d(25) xor d(30) xor d(31); - n(2) := c(0) xor c(1) xor c(2) xor c(6) xor c(7) xor c(8) xor c(9) xor c(13) xor c(14) xor c(16) xor c(17) xor c(18) xor c(24) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(7) xor d(13) xor d(14) xor d(15) xor d(17) xor d(18) xor d(22) xor d(23) xor d(24) xor d(25) xor d(29) xor d(30) xor d(31); - n(3) := c(1) xor c(2) xor c(3) xor c(7) xor c(8) xor c(9) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(25) xor c(27) xor c(31) xor d(0) xor d(4) xor d(6) xor d(12) xor d(13) xor d(14) xor d(16) xor d(17) xor d(21) xor d(22) xor d(23) xor d(24) xor d(28) xor d(29) xor d(30); - n(4) := c(0) xor c(2) xor c(3) xor c(4) xor c(6) xor c(8) xor c(11) xor c(12) xor c(15) xor c(18) xor c(19) xor c(20) xor c(24) xor c(25) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(6) xor d(7) xor d(11) xor d(12) xor d(13) xor d(16) xor d(19) xor d(20) xor d(23) xor d(25) xor d(27) xor d(28) xor d(29) xor d(31); - n(5) := c(0) xor c(1) xor c(3) xor c(4) xor c(5) xor c(6) xor c(7) xor c(10) xor c(13) xor c(19) xor c(20) xor c(21) xor c(24) xor c(28) xor c(29) xor d(2) xor d(3) xor d(7) xor d(10) xor d(11) xor d(12) xor d(18) xor d(21) xor d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(30) xor d(31); - n(6) := c(1) xor c(2) xor c(4) xor c(5) xor c(6) xor c(7) xor c(8) xor c(11) xor c(14) xor c(20) xor c(21) xor c(22) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(9) xor d(10) xor d(11) xor d(17) xor d(20) xor d(23) xor d(24) xor d(25) xor d(26) xor d(27) xor d(29) xor d(30); - n(7) := c(0) xor c(2) xor c(3) xor c(5) xor c(7) xor c(8) xor c(10) xor c(15) xor c(16) xor c(21) xor c(22) xor c(23) xor c(24) xor c(25) xor c(28) xor c(29) xor d(2) xor d(3) xor d(6) xor d(7) xor d(8) xor d(9) xor d(10) xor d(15) xor d(16) xor d(21) xor d(23) xor d(24) xor d(26) xor d(28) xor d(29) xor d(31); - n(8) := c(0) xor c(1) xor c(3) xor c(4) xor c(8) xor c(10) xor c(11) xor c(12) xor c(17) xor c(22) xor c(23) xor c(28) xor c(31) xor d(0) xor d(3) xor d(8) xor d(9) xor d(14) xor d(19) xor d(20) xor d(21) xor d(23) xor d(27) xor d(28) xor d(30) xor d(31); - n(9) := c(1) xor c(2) xor c(4) xor c(5) xor c(9) xor c(11) xor c(12) xor c(13) xor c(18) xor c(23) xor c(24) xor c(29) xor d(2) xor d(7) xor d(8) xor d(13) xor d(18) xor d(19) xor d(20) xor d(22) xor d(26) xor d(27) xor d(29) xor d(30); - n(10) := c(0) xor c(2) xor c(3) xor c(5) xor c(9) xor c(13) xor c(14) xor c(16) xor c(19) xor c(26) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(5) xor d(12) xor d(15) xor d(17) xor d(18) xor d(22) xor d(26) xor d(28) xor d(29) xor d(31); - n(11) := c(0) xor c(1) xor c(3) xor c(4) xor c(9) xor c(12) xor c(14) xor c(15) xor c(16) xor c(17) xor c(20) xor c(24) xor c(25) xor c(26) xor c(27) xor c(28) xor c(31) xor d(0) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor d(11) xor d(14) xor d(15) xor d(16) xor d(17) xor d(19) xor d(22) xor d(27) xor d(28) xor d(30) xor d(31); - n(12) := c(0) xor c(1) xor c(2) xor c(4) xor c(5) xor c(6) xor c(9) xor c(12) xor c(13) xor c(15) xor c(17) xor c(18) xor c(21) xor c(24) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4) xor d(7) xor d(10) xor d(13) xor d(14) xor d(16) xor d(18) xor d(19) xor d(22) xor d(25) xor d(26) xor d(27) xor d(29) xor d(30) xor d(31); - n(13) := c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(7) xor c(10) xor c(13) xor c(14) xor c(16) xor c(18) xor c(19) xor c(22) xor c(25) xor c(28) xor c(31) xor d(0) xor d(3) xor d(6) xor d(9) xor d(12) xor d(13) xor d(15) xor d(17) xor d(18) xor d(21) xor d(24) xor d(25) xor d(26) xor d(28) xor d(29) xor d(30); - n(14) := c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(8) xor c(11) xor c(14) xor c(15) xor c(17) xor c(19) xor c(20) xor c(23) xor c(26) xor c(29) xor d(2) xor d(5) xor d(8) xor d(11) xor d(12) xor d(14) xor d(16) xor d(17) xor d(20) xor d(23) xor d(24) xor d(25) xor d(27) xor d(28) xor d(29); - n(15) := c(3) xor c(4) xor c(5) xor c(7) xor c(8) xor c(9) xor c(12) xor c(15) xor c(16) xor c(18) xor c(20) xor c(21) xor c(24) xor c(27) xor c(30) xor d(1) xor d(4) xor d(7) xor d(10) xor d(11) xor d(13) xor d(15) xor d(16) xor d(19) xor d(22) xor d(23) xor d(24) xor d(26) xor d(27) xor d(28); - n(16) := c(0) xor c(4) xor c(5) xor c(8) xor c(12) xor c(13) xor c(17) xor c(19) xor c(21) xor c(22) xor c(24) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5) xor d(7) xor d(9) xor d(10) xor d(12) xor d(14) xor d(18) xor d(19) xor d(23) xor d(26) xor d(27) xor d(31); - n(17) := c(1) xor c(5) xor c(6) xor c(9) xor c(13) xor c(14) xor c(18) xor c(20) xor c(22) xor c(23) xor c(25) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4) xor d(6) xor d(8) xor d(9) xor d(11) xor d(13) xor d(17) xor d(18) xor d(22) xor d(25) xor d(26) xor d(30); - n(18) := c(2) xor c(6) xor c(7) xor c(10) xor c(14) xor c(15) xor c(19) xor c(21) xor c(23) xor c(24) xor c(26) xor c(28) xor c(31) xor d(0) xor d(3) xor d(5) xor d(7) xor d(8) xor d(10) xor d(12) xor d(16) xor d(17) xor d(21) xor d(24) xor d(25) xor d(29); - n(19) := c(3) xor c(7) xor c(8) xor c(11) xor c(15) xor c(16) xor c(20) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor d(2) xor d(4) xor d(6) xor d(7) xor d(9) xor d(11) xor d(15) xor d(16) xor d(20) xor d(23) xor d(24) xor d(28); - n(20) := c(4) xor c(8) xor c(9) xor c(12) xor c(16) xor c(17) xor c(21) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor d(1) xor d(3) xor d(5) xor d(6) xor d(8) xor d(10) xor d(14) xor d(15) xor d(19) xor d(22) xor d(23) xor d(27); - n(21) := c(5) xor c(9) xor c(10) xor c(13) xor c(17) xor c(18) xor c(22) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(9) xor d(13) xor d(14) xor d(18) xor d(21) xor d(22) xor d(26); - n(22) := c(0) xor c(9) xor c(11) xor c(12) xor c(14) xor c(16) xor c(18) xor c(19) xor c(23) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(8) xor d(12) xor d(13) xor d(15) xor d(17) xor d(19) xor d(20) xor d(22) xor d(31); - n(23) := c(0) xor c(1) xor c(6) xor c(9) xor c(13) xor c(15) xor c(16) xor c(17) xor c(19) xor c(20) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(11) xor d(12) xor d(14) xor d(15) xor d(16) xor d(18) xor d(22) xor d(25) xor d(30) xor d(31); - n(24) := c(1) xor c(2) xor c(7) xor c(10) xor c(14) xor c(16) xor c(17) xor c(18) xor c(20) xor c(21) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(10) xor d(11) xor d(13) xor d(14) xor d(15) xor d(17) xor d(21) xor d(24) xor d(29) xor d(30); - n(25) := c(2) xor c(3) xor c(8) xor c(11) xor c(15) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14) xor d(16) xor d(20) xor d(23) xor d(28) xor d(29); - n(26) := c(0) xor c(3) xor c(4) xor c(6) xor c(10) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(25) xor c(26) xor c(28) xor c(31) xor d(0) xor d(3) xor d(5) xor d(6) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13) xor d(21) xor d(25) xor d(27) xor d(28) xor d(31); - n(27) := c(1) xor c(4) xor c(5) xor c(7) xor c(11) xor c(19) xor c(20) xor c(21) xor c(23) xor c(24) xor c(25) xor c(26) xor c(27) xor c(29) xor d(2) xor d(4) xor d(5) xor d(6) xor d(7) xor d(8) xor d(10) xor d(11) xor d(12) xor d(20) xor d(24) xor d(26) xor d(27) xor d(30); - n(28) := c(2) xor c(5) xor c(6) xor c(8) xor c(12) xor c(20) xor c(21) xor c(22) xor c(24) xor c(25) xor c(26) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor d(9) xor d(10) xor d(11) xor d(19) xor d(23) xor d(25) xor d(26) xor d(29); - n(29) := c(3) xor c(6) xor c(7) xor c(9) xor c(13) xor c(21) xor c(22) xor c(23) xor c(25) xor c(26) xor c(27) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(8) xor d(9) xor d(10) xor d(18) xor d(22) xor d(24) xor d(25) xor d(28); - n(30) := c(4) xor c(7) xor c(8) xor c(10) xor c(14) xor c(22) xor c(23) xor c(24) xor c(26) xor c(27) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(7) xor d(8) xor d(9) xor d(17) xor d(21) xor d(23) xor d(24) xor d(27); - n(31) := c(5) xor c(8) xor c(9) xor c(11) xor c(15) xor c(23) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(7) xor d(8) xor d(16) xor d(20) xor d(22) xor d(23) xor d(26); - return n; - end newcrc32_d32; -end pkg_newcrc32_d32; - Index: experimental_jumbo_frames_version/fpga/pkg_newcrc32_d64.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/pkg_newcrc32_d64.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/pkg_newcrc32_d64.vhd (nonexistent) @@ -1,57 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -package pkg_newcrc32_d64 is - -- CRC update for 32-bit CRC and 64-bit data (LSB first) - -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] - function newcrc32_d64( - din : std_logic_vector(63 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector; -end pkg_newcrc32_d64; - -package body pkg_newcrc32_d64 is - function newcrc32_d64( - din : std_logic_vector(63 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector is - variable c, n : std_logic_vector(31 downto 0); - variable d : std_logic_vector(63 downto 0); - begin - c := crc; - d := din; - n(0) := c(0) xor c(2) xor c(5) xor c(12) xor c(13) xor c(15) xor c(16) xor c(18) xor c(21) xor c(22) xor c(23) xor c(26) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(5) xor d(8) xor d(9) xor d(10) xor d(13) xor d(15) xor d(16) xor d(18) xor d(19) xor d(26) xor d(29) xor d(31) xor d(32) xor d(33) xor d(34) xor d(35) xor d(37) xor d(38) xor d(39) xor d(47) xor d(51) xor d(53) xor d(54) xor d(57) xor d(63); - n(1) := c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(12) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(21) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(4) xor d(5) xor d(7) xor d(10) xor d(12) xor d(13) xor d(14) xor d(16) xor d(17) xor d(19) xor d(25) xor d(26) xor d(28) xor d(29) xor d(30) xor d(35) xor d(36) xor d(39) xor d(46) xor d(47) xor d(50) xor d(51) xor d(52) xor d(54) xor d(56) xor d(57) xor d(62) xor d(63); - n(2) := c(0) xor c(3) xor c(4) xor c(5) xor c(6) xor c(7) xor c(12) xor c(19) xor c(20) xor c(21) xor c(23) xor c(25) xor c(26) xor c(27) xor d(4) xor d(5) xor d(6) xor d(8) xor d(10) xor d(11) xor d(12) xor d(19) xor d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(31) xor d(32) xor d(33) xor d(37) xor d(39) xor d(45) xor d(46) xor d(47) xor d(49) xor d(50) xor d(54) xor d(55) xor d(56) xor d(57) xor d(61) xor d(62) xor d(63); - n(3) := c(0) xor c(1) xor c(4) xor c(5) xor c(6) xor c(7) xor c(8) xor c(13) xor c(20) xor c(21) xor c(22) xor c(24) xor c(26) xor c(27) xor c(28) xor d(3) xor d(4) xor d(5) xor d(7) xor d(9) xor d(10) xor d(11) xor d(18) xor d(23) xor d(24) xor d(25) xor d(26) xor d(27) xor d(30) xor d(31) xor d(32) xor d(36) xor d(38) xor d(44) xor d(45) xor d(46) xor d(48) xor d(49) xor d(53) xor d(54) xor d(55) xor d(56) xor d(60) xor d(61) xor d(62); - n(4) := c(1) xor c(6) xor c(7) xor c(8) xor c(9) xor c(12) xor c(13) xor c(14) xor c(15) xor c(16) xor c(18) xor c(25) xor c(26) xor c(27) xor c(31) xor d(0) xor d(4) xor d(5) xor d(6) xor d(13) xor d(15) xor d(16) xor d(17) xor d(18) xor d(19) xor d(22) xor d(23) xor d(24) xor d(25) xor d(30) xor d(32) xor d(33) xor d(34) xor d(38) xor d(39) xor d(43) xor d(44) xor d(45) xor d(48) xor d(51) xor d(52) xor d(55) xor d(57) xor d(59) xor d(60) xor d(61) xor d(63); - n(5) := c(5) xor c(7) xor c(8) xor c(9) xor c(10) xor c(12) xor c(14) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(23) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(8) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14) xor d(17) xor d(19) xor d(21) xor d(22) xor d(23) xor d(24) xor d(26) xor d(34) xor d(35) xor d(39) xor d(42) xor d(43) xor d(44) xor d(50) xor d(53) xor d(56) xor d(57) xor d(58) xor d(59) xor d(60) xor d(62) xor d(63); - n(6) := c(6) xor c(8) xor c(9) xor c(10) xor c(11) xor c(13) xor c(15) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(28) xor c(30) xor d(1) xor d(3) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13) xor d(16) xor d(18) xor d(20) xor d(21) xor d(22) xor d(23) xor d(25) xor d(33) xor d(34) xor d(38) xor d(41) xor d(42) xor d(43) xor d(49) xor d(52) xor d(55) xor d(56) xor d(57) xor d(58) xor d(59) xor d(61) xor d(62); - n(7) := c(0) xor c(2) xor c(5) xor c(7) xor c(9) xor c(10) xor c(11) xor c(13) xor c(14) xor c(15) xor c(18) xor c(19) xor c(20) xor c(22) xor c(24) xor c(25) xor c(26) xor c(28) xor d(3) xor d(5) xor d(6) xor d(7) xor d(9) xor d(11) xor d(12) xor d(13) xor d(16) xor d(17) xor d(18) xor d(20) xor d(21) xor d(22) xor d(24) xor d(26) xor d(29) xor d(31) xor d(34) xor d(35) xor d(38) xor d(39) xor d(40) xor d(41) xor d(42) xor d(47) xor d(48) xor d(53) xor d(55) xor d(56) xor d(58) xor d(60) xor d(61) xor d(63); - n(8) := c(0) xor c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(8) xor c(10) xor c(11) xor c(13) xor c(14) xor c(18) xor c(19) xor c(20) xor c(22) xor c(25) xor c(27) xor c(28) xor c(31) xor d(0) xor d(3) xor d(4) xor d(6) xor d(9) xor d(11) xor d(12) xor d(13) xor d(17) xor d(18) xor d(20) xor d(21) xor d(23) xor d(25) xor d(26) xor d(28) xor d(29) xor d(30) xor d(31) xor d(32) xor d(35) xor d(40) xor d(41) xor d(46) xor d(51) xor d(52) xor d(53) xor d(55) xor d(59) xor d(60) xor d(62) xor d(63); - n(9) := c(0) xor c(1) xor c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(9) xor c(11) xor c(12) xor c(14) xor c(15) xor c(19) xor c(20) xor c(21) xor c(23) xor c(26) xor c(28) xor c(29) xor d(2) xor d(3) xor d(5) xor d(8) xor d(10) xor d(11) xor d(12) xor d(16) xor d(17) xor d(19) xor d(20) xor d(22) xor d(24) xor d(25) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31) xor d(34) xor d(39) xor d(40) xor d(45) xor d(50) xor d(51) xor d(52) xor d(54) xor d(58) xor d(59) xor d(61) xor d(62); - n(10) := c(0) xor c(1) xor c(3) xor c(4) xor c(7) xor c(8) xor c(10) xor c(18) xor c(20) xor c(23) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(4) xor d(5) xor d(7) xor d(8) xor d(11) xor d(13) xor d(21) xor d(23) xor d(24) xor d(27) xor d(28) xor d(30) xor d(31) xor d(32) xor d(34) xor d(35) xor d(37) xor d(44) xor d(47) xor d(49) xor d(50) xor d(54) xor d(58) xor d(60) xor d(61) xor d(63); - n(11) := c(1) xor c(4) xor c(8) xor c(9) xor c(11) xor c(12) xor c(13) xor c(15) xor c(16) xor c(18) xor c(19) xor c(22) xor c(23) xor c(24) xor c(25) xor c(26) xor c(27) xor d(4) xor d(5) xor d(6) xor d(7) xor d(8) xor d(9) xor d(12) xor d(13) xor d(15) xor d(16) xor d(18) xor d(19) xor d(20) xor d(22) xor d(23) xor d(27) xor d(30) xor d(32) xor d(35) xor d(36) xor d(37) xor d(38) xor d(39) xor d(43) xor d(46) xor d(47) xor d(48) xor d(49) xor d(51) xor d(54) xor d(59) xor d(60) xor d(62) xor d(63); - n(12) := c(9) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(20) xor c(21) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(6) xor d(7) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(16) xor d(17) xor d(21) xor d(22) xor d(32) xor d(33) xor d(36) xor d(39) xor d(42) xor d(45) xor d(46) xor d(48) xor d(50) xor d(51) xor d(54) xor d(57) xor d(58) xor d(59) xor d(61) xor d(62) xor d(63); - n(13) := c(0) xor c(10) xor c(11) xor c(15) xor c(16) xor c(18) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor d(1) xor d(3) xor d(5) xor d(6) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(15) xor d(16) xor d(20) xor d(21) xor d(31) xor d(32) xor d(35) xor d(38) xor d(41) xor d(44) xor d(45) xor d(47) xor d(49) xor d(50) xor d(53) xor d(56) xor d(57) xor d(58) xor d(60) xor d(61) xor d(62); - n(14) := c(0) xor c(1) xor c(11) xor c(12) xor c(16) xor c(17) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(14) xor d(15) xor d(19) xor d(20) xor d(30) xor d(31) xor d(34) xor d(37) xor d(40) xor d(43) xor d(44) xor d(46) xor d(48) xor d(49) xor d(52) xor d(55) xor d(56) xor d(57) xor d(59) xor d(60) xor d(61); - n(15) := c(1) xor c(2) xor c(12) xor c(13) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(25) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(6) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14) xor d(18) xor d(19) xor d(29) xor d(30) xor d(33) xor d(36) xor d(39) xor d(42) xor d(43) xor d(45) xor d(47) xor d(48) xor d(51) xor d(54) xor d(55) xor d(56) xor d(58) xor d(59) xor d(60); - n(16) := c(0) xor c(3) xor c(5) xor c(12) xor c(14) xor c(15) xor c(16) xor c(19) xor c(24) xor c(25) xor d(6) xor d(7) xor d(12) xor d(15) xor d(16) xor d(17) xor d(19) xor d(26) xor d(28) xor d(31) xor d(33) xor d(34) xor d(37) xor d(39) xor d(41) xor d(42) xor d(44) xor d(46) xor d(50) xor d(51) xor d(55) xor d(58) xor d(59) xor d(63); - n(17) := c(1) xor c(4) xor c(6) xor c(13) xor c(15) xor c(16) xor c(17) xor c(20) xor c(25) xor c(26) xor d(5) xor d(6) xor d(11) xor d(14) xor d(15) xor d(16) xor d(18) xor d(25) xor d(27) xor d(30) xor d(32) xor d(33) xor d(36) xor d(38) xor d(40) xor d(41) xor d(43) xor d(45) xor d(49) xor d(50) xor d(54) xor d(57) xor d(58) xor d(62); - n(18) := c(0) xor c(2) xor c(5) xor c(7) xor c(14) xor c(16) xor c(17) xor c(18) xor c(21) xor c(26) xor c(27) xor d(4) xor d(5) xor d(10) xor d(13) xor d(14) xor d(15) xor d(17) xor d(24) xor d(26) xor d(29) xor d(31) xor d(32) xor d(35) xor d(37) xor d(39) xor d(40) xor d(42) xor d(44) xor d(48) xor d(49) xor d(53) xor d(56) xor d(57) xor d(61); - n(19) := c(0) xor c(1) xor c(3) xor c(6) xor c(8) xor c(15) xor c(17) xor c(18) xor c(19) xor c(22) xor c(27) xor c(28) xor d(3) xor d(4) xor d(9) xor d(12) xor d(13) xor d(14) xor d(16) xor d(23) xor d(25) xor d(28) xor d(30) xor d(31) xor d(34) xor d(36) xor d(38) xor d(39) xor d(41) xor d(43) xor d(47) xor d(48) xor d(52) xor d(55) xor d(56) xor d(60); - n(20) := c(1) xor c(2) xor c(4) xor c(7) xor c(9) xor c(16) xor c(18) xor c(19) xor c(20) xor c(23) xor c(28) xor c(29) xor d(2) xor d(3) xor d(8) xor d(11) xor d(12) xor d(13) xor d(15) xor d(22) xor d(24) xor d(27) xor d(29) xor d(30) xor d(33) xor d(35) xor d(37) xor d(38) xor d(40) xor d(42) xor d(46) xor d(47) xor d(51) xor d(54) xor d(55) xor d(59); - n(21) := c(2) xor c(3) xor c(5) xor c(8) xor c(10) xor c(17) xor c(19) xor c(20) xor c(21) xor c(24) xor c(29) xor c(30) xor d(1) xor d(2) xor d(7) xor d(10) xor d(11) xor d(12) xor d(14) xor d(21) xor d(23) xor d(26) xor d(28) xor d(29) xor d(32) xor d(34) xor d(36) xor d(37) xor d(39) xor d(41) xor d(45) xor d(46) xor d(50) xor d(53) xor d(54) xor d(58); - n(22) := c(2) xor c(3) xor c(4) xor c(5) xor c(6) xor c(9) xor c(11) xor c(12) xor c(13) xor c(15) xor c(16) xor c(20) xor c(23) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(8) xor d(11) xor d(15) xor d(16) xor d(18) xor d(19) xor d(20) xor d(22) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(32) xor d(34) xor d(36) xor d(37) xor d(39) xor d(40) xor d(44) xor d(45) xor d(47) xor d(49) xor d(51) xor d(52) xor d(54) xor d(63); - n(23) := c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(22) xor c(23) xor c(24) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(7) xor d(8) xor d(9) xor d(13) xor d(14) xor d(16) xor d(17) xor d(21) xor d(24) xor d(25) xor d(27) xor d(28) xor d(29) xor d(32) xor d(34) xor d(36) xor d(37) xor d(43) xor d(44) xor d(46) xor d(47) xor d(48) xor d(50) xor d(54) xor d(57) xor d(62) xor d(63); - n(24) := c(0) xor c(3) xor c(4) xor c(5) xor c(7) xor c(8) xor c(11) xor c(15) xor c(16) xor c(18) xor c(19) xor c(23) xor c(24) xor c(25) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(6) xor d(7) xor d(8) xor d(12) xor d(13) xor d(15) xor d(16) xor d(20) xor d(23) xor d(24) xor d(26) xor d(27) xor d(28) xor d(31) xor d(33) xor d(35) xor d(36) xor d(42) xor d(43) xor d(45) xor d(46) xor d(47) xor d(49) xor d(53) xor d(56) xor d(61) xor d(62); - n(25) := c(1) xor c(4) xor c(5) xor c(6) xor c(8) xor c(9) xor c(12) xor c(16) xor c(17) xor c(19) xor c(20) xor c(24) xor c(25) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5) xor d(6) xor d(7) xor d(11) xor d(12) xor d(14) xor d(15) xor d(19) xor d(22) xor d(23) xor d(25) xor d(26) xor d(27) xor d(30) xor d(32) xor d(34) xor d(35) xor d(41) xor d(42) xor d(44) xor d(45) xor d(46) xor d(48) xor d(52) xor d(55) xor d(60) xor d(61); - n(26) := c(6) xor c(7) xor c(9) xor c(10) xor c(12) xor c(15) xor c(16) xor c(17) xor c(20) xor c(22) xor c(23) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(8) xor d(9) xor d(11) xor d(14) xor d(15) xor d(16) xor d(19) xor d(21) xor d(22) xor d(24) xor d(25) xor d(32) xor d(35) xor d(37) xor d(38) xor d(39) xor d(40) xor d(41) xor d(43) xor d(44) xor d(45) xor d(53) xor d(57) xor d(59) xor d(60) xor d(63); - n(27) := c(0) xor c(7) xor c(8) xor c(10) xor c(11) xor c(13) xor c(16) xor c(17) xor c(18) xor c(21) xor c(23) xor c(24) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(7) xor d(8) xor d(10) xor d(13) xor d(14) xor d(15) xor d(18) xor d(20) xor d(21) xor d(23) xor d(24) xor d(31) xor d(34) xor d(36) xor d(37) xor d(38) xor d(39) xor d(40) xor d(42) xor d(43) xor d(44) xor d(52) xor d(56) xor d(58) xor d(59) xor d(62); - n(28) := c(1) xor c(8) xor c(9) xor c(11) xor c(12) xor c(14) xor c(17) xor c(18) xor c(19) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(4) xor d(6) xor d(7) xor d(9) xor d(12) xor d(13) xor d(14) xor d(17) xor d(19) xor d(20) xor d(22) xor d(23) xor d(30) xor d(33) xor d(35) xor d(36) xor d(37) xor d(38) xor d(39) xor d(41) xor d(42) xor d(43) xor d(51) xor d(55) xor d(57) xor d(58) xor d(61); - n(29) := c(2) xor c(9) xor c(10) xor c(12) xor c(13) xor c(15) xor c(18) xor c(19) xor c(20) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(5) xor d(6) xor d(8) xor d(11) xor d(12) xor d(13) xor d(16) xor d(18) xor d(19) xor d(21) xor d(22) xor d(29) xor d(32) xor d(34) xor d(35) xor d(36) xor d(37) xor d(38) xor d(40) xor d(41) xor d(42) xor d(50) xor d(54) xor d(56) xor d(57) xor d(60); - n(30) := c(0) xor c(3) xor c(10) xor c(11) xor c(13) xor c(14) xor c(16) xor c(19) xor c(20) xor c(21) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(10) xor d(11) xor d(12) xor d(15) xor d(17) xor d(18) xor d(20) xor d(21) xor d(28) xor d(31) xor d(33) xor d(34) xor d(35) xor d(36) xor d(37) xor d(39) xor d(40) xor d(41) xor d(49) xor d(53) xor d(55) xor d(56) xor d(59); - n(31) := c(1) xor c(4) xor c(11) xor c(12) xor c(14) xor c(15) xor c(17) xor c(20) xor c(21) xor c(22) xor c(25) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(6) xor d(9) xor d(10) xor d(11) xor d(14) xor d(16) xor d(17) xor d(19) xor d(20) xor d(27) xor d(30) xor d(32) xor d(33) xor d(34) xor d(35) xor d(36) xor d(38) xor d(39) xor d(40) xor d(48) xor d(52) xor d(54) xor d(55) xor d(58); - return n; - end newcrc32_d64; -end pkg_newcrc32_d64; - Index: experimental_jumbo_frames_version/fpga/pkg_newcrc32_d8.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/pkg_newcrc32_d8.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/pkg_newcrc32_d8.vhd (nonexistent) @@ -1,57 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -package pkg_newcrc32_d8 is - -- CRC update for 32-bit CRC and 8-bit data (LSB first) - -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] - function newcrc32_d8( - din : std_logic_vector(7 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector; -end pkg_newcrc32_d8; - -package body pkg_newcrc32_d8 is - function newcrc32_d8( - din : std_logic_vector(7 downto 0); - crc : std_logic_vector(31 downto 0)) - return std_logic_vector is - variable c, n : std_logic_vector(31 downto 0); - variable d : std_logic_vector(7 downto 0); - begin - c := crc; - d := din; - n(0) := c(24) xor c(30) xor d(1) xor d(7); - n(1) := c(24) xor c(25) xor c(30) xor c(31) xor d(0) xor d(1) xor d(6) xor d(7); - n(2) := c(24) xor c(25) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(6) xor d(7); - n(3) := c(25) xor c(26) xor c(27) xor c(31) xor d(0) xor d(4) xor d(5) xor d(6); - n(4) := c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(5) xor d(7); - n(5) := c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(7); - n(6) := c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6); - n(7) := c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7); - n(8) := c(0) xor c(24) xor c(25) xor c(27) xor c(28) xor d(3) xor d(4) xor d(6) xor d(7); - n(9) := c(1) xor c(25) xor c(26) xor c(28) xor c(29) xor d(2) xor d(3) xor d(5) xor d(6); - n(10) := c(2) xor c(24) xor c(26) xor c(27) xor c(29) xor d(2) xor d(4) xor d(5) xor d(7); - n(11) := c(3) xor c(24) xor c(25) xor c(27) xor c(28) xor d(3) xor d(4) xor d(6) xor d(7); - n(12) := c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7); - n(13) := c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(4) xor d(5) xor d(6); - n(14) := c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(4) xor d(5); - n(15) := c(7) xor c(27) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(4); - n(16) := c(8) xor c(24) xor c(28) xor c(29) xor d(2) xor d(3) xor d(7); - n(17) := c(9) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6); - n(18) := c(10) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5); - n(19) := c(11) xor c(27) xor c(31) xor d(0) xor d(4); - n(20) := c(12) xor c(28) xor d(3); - n(21) := c(13) xor c(29) xor d(2); - n(22) := c(14) xor c(24) xor d(7); - n(23) := c(15) xor c(24) xor c(25) xor c(30) xor d(1) xor d(6) xor d(7); - n(24) := c(16) xor c(25) xor c(26) xor c(31) xor d(0) xor d(5) xor d(6); - n(25) := c(17) xor c(26) xor c(27) xor d(4) xor d(5); - n(26) := c(18) xor c(24) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(7); - n(27) := c(19) xor c(25) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(6); - n(28) := c(20) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5); - n(29) := c(21) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4); - n(30) := c(22) xor c(28) xor c(31) xor d(0) xor d(3); - n(31) := c(23) xor c(29) xor d(2); - return n; - end newcrc32_d8; -end pkg_newcrc32_d8; - Index: experimental_jumbo_frames_version/fpga/desc_manager_simple.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/desc_manager_simple.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/desc_manager_simple.vhd (nonexistent) @@ -1,676 +0,0 @@ -------------------------------------------------------------------------------- --- Title : FPGA Ethernet interface - descriptor manager --- Project : -------------------------------------------------------------------------------- --- File : desc_manager.vhd --- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) --- License : BSD License --- Company : --- Created : 2012-03-30 --- Last update: 2014-10-20 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: This file implements the state machine, which manages the --- table of packet descriptors, used to resend only not confirmed packets -------------------------------------------------------------------------------- --- Copyright (c) 2012 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2012-03-30 1.0 WZab Created -------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; -library work; -use work.pkt_ack_pkg.all; -use work.desc_mgr_pkg.all; -use work.pkt_desc_pkg.all; - -entity desc_memory is - - port ( - clk : in std_logic; - desc_we : in std_logic; - desc_addr : in integer range 0 to N_OF_PKTS-1; - desc_out : in pkt_desc; - desc_in : out pkt_desc); - -end desc_memory; - -architecture beh1 of desc_memory is - - type T_PKT_DESC_MEM is array (0 to N_OF_PKTS-1) of std_logic_vector(pkt_desc_width-1 downto 0); - signal desc_mem : T_PKT_DESC_MEM := (others => (others => '0')); - signal din : std_logic_vector(pkt_desc_width-1 downto 0) := (others => '0'); - signal dout : std_logic_vector(pkt_desc_width-1 downto 0) := (others => '0'); - signal rdaddr : integer range 0 to N_OF_PKTS-1; - - -begin -- beh1 - - din <= pkt_desc_to_stlv(desc_out); - desc_in <= stlv_to_pkt_desc(dout); - - process (clk) - begin -- process - if (clk'event and clk = '1') then -- rising clock edge - if (desc_we = '1') then - desc_mem(desc_addr) <= din; - end if; - rdaddr <= desc_addr; - end if; - end process; - dout <= desc_mem(rdaddr); - -end beh1; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; -library work; -use work.pkt_ack_pkg.all; -use work.desc_mgr_pkg.all; -use work.pkt_desc_pkg.all; - -entity desc_manager is - - generic ( - LOG2_N_OF_PKTS : integer := LOG2_N_OF_PKTS; - N_OF_PKTS : integer := N_OF_PKTS - ); -- Number of packet_logi buffers - - port ( - -- Data input interface - dta : in std_logic_vector(63 downto 0); - dta_we : in std_logic; - dta_eod : in std_logic; - dta_ready : out std_logic; - -- ETH Sender interface - pkt_number : out unsigned(31 downto 0); - seq_number : out unsigned(15 downto 0); - cmd_response_out : out std_logic_vector(12*8-1 downto 0); - snd_cmd_start : out std_logic; - snd_start : out std_logic; - flushed : out std_logic; - snd_ready : in std_logic; - - -- Data memory interface - dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); - dmem_dta : out std_logic_vector(63 downto 0); - dmem_we : out std_logic; - -- Interface to the ACK FIFO - ack_fifo_empty : in std_logic; - ack_fifo_rd_en : out std_logic; - ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); - -- User command interface - cmd_code : out std_logic_vector(15 downto 0); - cmd_seq : out std_logic_vector(15 downto 0); - cmd_arg : out std_logic_vector(31 downto 0); - cmd_run : out std_logic; - cmd_retr_s : out std_logic; - cmd_ack : in std_logic; - cmd_response_in : in std_logic_vector(8*12-1 downto 0); - -- - transmit_data : in std_logic; - transm_delay : out unsigned(31 downto 0); - -- - dbg : out std_logic_vector(3 downto 0); - -- - clk : in std_logic; - rst_n : in std_logic); - -end desc_manager; - -architecture dmgr_a1 of desc_manager is - - constant PKT_CNT_MAX : integer := 3000; - - - function is_bigger ( - constant v1, v2 : unsigned(15 downto 0)) - return boolean is - variable res : boolean; - variable tmp : unsigned(15 downto 0); - begin -- function is_bigger - -- subtract v2-v1 modulo 2**16 - tmp := v2-v1; - -- if the result is "negative" - bit 15 is '1' - -- and we consider v1 to be "bigger" (in modulo sense) than v2 - if tmp(15) = '1' then - return true; - else - return false; - end if; - - end function is_bigger; - - -- To simplify description of state machines, all registers are grouped - -- in a record : - - type T_DESC_MGR_REGS is record - cmd_ack : std_logic; - cmd_ack_0 : std_logic; - cmd_run : std_logic; - cmd_retr : std_logic; - cmd_code : unsigned(15 downto 0); - cmd_seq : unsigned(15 downto 0); - cmd_arg : unsigned(31 downto 0); - pkt : unsigned(31 downto 0); - cur_pkt : unsigned(31 downto 0); - seq : unsigned(15 downto 0); - ack_seq : unsigned(15 downto 0); - retr_flag : std_logic; - flushed : std_logic; - all_pkt_count : integer range 0 to PKT_CNT_MAX; - retr_pkt_count : integer range 0 to PKT_CNT_MAX; - retr_delay : unsigned(31 downto 0); - transm_delay : unsigned(31 downto 0); - nxt : unsigned(LOG2_N_OF_PKTS-1 downto 0); - tail_ptr : unsigned(LOG2_N_OF_PKTS-1 downto 0); - head_ptr : unsigned(LOG2_N_OF_PKTS-1 downto 0); - retr_ptr : unsigned(LOG2_N_OF_PKTS-1 downto 0); -- Number of the packet buffer, which is retransmitted - -- when equal to head_ptr - - -- retransmission is finished - retr_nxt : unsigned(LOG2_N_OF_PKTS-1 downto 0); -- buffer, which will be - -- retransmitted next - -- when equal to head_ptr -- no retransmission - -- is performed - end record; - - constant DESC_MGR_REGS_INI : T_DESC_MGR_REGS := ( - retr_delay => (others => '0'), - transm_delay => to_unsigned(10000, 32), - all_pkt_count => 0, - retr_pkt_count => 0, - cmd_ack_0 => '0', - cmd_ack => '0', - cmd_run => '0', - cmd_retr => '0', - cmd_code => (others => '0'), - cmd_seq => (others => '0'), - cmd_arg => (others => '0'), - pkt => (others => '0'), - seq => (others => '0'), - ack_seq => (others => '0'), - retr_flag => '0', - flushed => '0', - cur_pkt => (others => '0'), - nxt => (others => '0'), - tail_ptr => (others => '0'), - head_ptr => (others => '0'), - retr_ptr => (others => '0'), - retr_nxt => (others => '0') - ); - - -- To simplify setting of outputs of my Mealy state machine, all combinatorial - -- outputs are grouped in a record - type T_DESC_MGR_COMB is record - dta_buf_free : std_logic; - desc_addr : unsigned(LOG2_N_OF_PKTS-1 downto 0); - desc_we : std_logic; - ack_rd : std_logic; - snd_start : std_logic; - snd_cmd_start : std_logic; - desc_out : pkt_desc; - end record; - - constant DESC_MGR_COMB_DEFAULT : T_DESC_MGR_COMB := - ( - dta_buf_free => '0', - desc_addr => (others => '0'), - desc_we => '0', - ack_rd => '0', - snd_start => '0', - snd_cmd_start => '0', - desc_out => ( - confirmed => '0', - valid => '0', - sent => '0', - flushed => '0', - pkt => (others => '0'), - seq => (others => '0') - ) - ); - - type T_DESC_MGR_STATE is (ST_DMGR_IDLE, ST_DMGR_CMD, ST_DMGR_START, ST_DMGR_RST, ST_DMGR_RST1, - ST_DMGR_ACK1, ST_DMGR_INS1, ST_DMGR_INS2, ST_DMGR_ACK_TAIL, - ST_DMGR_ACK_TAIL_1, - ST_DMGR_RETR, ST_DMGR_RETR_2); - - signal desc_in : pkt_desc; - - signal r, r_i : T_DESC_MGR_REGS := DESC_MGR_REGS_INI; - signal c : T_DESC_MGR_COMB; - signal dmgr_state, dmgr_state_next : T_DESC_MGR_STATE := ST_DMGR_RST; - attribute keep : string; - attribute keep of dmgr_state : signal is "true"; - - signal dta_buf_full : std_logic := '0'; - signal dta_buf_flush : std_logic := '0'; - signal stored_dta_eod : std_logic := '0'; - - signal ack_pkt_in : pkt_ack; - - signal wrd_addr : integer range 0 to NWRDS_IN_PKT-1; -- We use 64-bit words, so the - -- data word address is between - -- 0 and 1023 - - component desc_memory - port ( - clk : in std_logic; - desc_we : in std_logic; - desc_addr : in integer range 0 to N_OF_PKTS-1; - desc_out : in pkt_desc; - desc_in : out pkt_desc); - end component; - - -begin -- dmgr_a1 - - transm_delay <= r.transm_delay; - pkt_number <= r.pkt; - seq_number <= r.seq; - flushed <= r.flushed; - dta_ready <= not dta_buf_full; - snd_start <= c.snd_start; - ack_fifo_rd_en <= c.ack_rd; - - cmd_code <= std_logic_vector(r.cmd_code); - cmd_seq <= std_logic_vector(r.cmd_seq); - cmd_arg <= std_logic_vector(r.cmd_arg); - cmd_run <= r.cmd_run; - cmd_retr_s <= r.cmd_retr; - snd_cmd_start <= c.snd_cmd_start; - - ack_pkt_in <= stlv_to_pkt_ack(ack_fifo_dout); - - -- Transmit command response only when the command is completed - -- (to avoid transmiting unstable values, which could e.g. affect - -- packet CRC calculations) - cmd_response_out <= cmd_response_in when r.cmd_ack = r.cmd_run else (others => '0'); - - -- Packet descriptors are stored in the desc_memory - - desc_memory_1 : desc_memory - port map ( - clk => clk, - desc_we => c.desc_we, - desc_addr => to_integer(c.desc_addr), - desc_out => c.desc_out, - desc_in => desc_in); - - -- Process used to fill the buffer memory with the data to be transmitted - -- We simply write words to the memory buffer pointed by r.head_ptr - -- When we write the last (0xff-th) word, we signal that the buffer - -- is full. - -- Additionally, when the buffer is partially filled, but the transmission - -- is stopped, we should also signal, that the buffer must be transmitted. - -- However in this case we should also inform the recipient about it. - -- How we can do it? - dta_rcv : process (clk, rst_n) - begin -- process dta_rcv - if rst_n = '0' then -- asynchronous reset (active low) - wrd_addr <= 0; - dta_buf_flush <= '0'; - dta_buf_full <= '0'; - dmem_we <= '0'; - stored_dta_eod <= '0'; - elsif clk'event and clk = '1' then -- rising clock edge - dmem_we <= '0'; - -- if we signalled "data full", we are only waiting for - -- dta_buf_free; - -- However even in this state we must receive the "dta_eod" signal - if dta_buf_full = '1' then - if dta_eod = '1' then - stored_dta_eod <= '1'; - end if; - if c.dta_buf_free = '1' then - dta_buf_full <= '0'; - dta_buf_flush <= '0'; - wrd_addr <= 0; - end if; - else - -- end of data is signalled, mark the last buffer as full - if (dta_eod = '1') or (stored_dta_eod = '1') then - -- Clear the stored eod - stored_dta_eod <= '0'; - -- In the last word of the packet, write the number of written words - dmem_addr <= std_logic_vector(r.head_ptr) & - std_logic_vector(to_unsigned(NWRDS_IN_PKT-1, LOG2_NWRDS_IN_PKT)); - dmem_dta <= std_logic_vector(to_unsigned(wrd_addr, 64)); - dmem_we <= '1'; - dta_buf_flush <= '1'; - dta_buf_full <= '1'; - -- if data write requested - write it - elsif dta_we = '1' then - dmem_addr <= std_logic_vector(r.head_ptr) & - std_logic_vector(to_unsigned(wrd_addr, LOG2_NWRDS_IN_PKT)); - dmem_we <= '1'; - dmem_dta <= dta; - if wrd_addr < NWRDS_IN_PKT-1 then - wrd_addr <= wrd_addr + 1; - else - dta_buf_flush <= '0'; - dta_buf_full <= '1'; - end if; - end if; - end if; - end if; - end process dta_rcv; - - - c1 : process (ack_fifo_empty, ack_pkt_in, cmd_ack, desc_in, - dmgr_state, dta_buf_full, dta_buf_flush, r, snd_ready) - begin -- process c1 - c <= DESC_MGR_COMB_DEFAULT; -- set defaults - r_i <= r; -- avoid latches - -- Synchronize command acknowledge lines - r_i.cmd_ack_0 <= cmd_ack; - r_i.cmd_ack <= r.cmd_ack_0; - if r.retr_delay /= to_unsigned(0, r.retr_delay'length) then - r_i.retr_delay <= r.retr_delay-1; - end if; - dmgr_state_next <= dmgr_state; - -- State machine - case dmgr_state is - when ST_DMGR_RST => - dbg <= x"1"; - dmgr_state_next <= ST_DMGR_RST1; - when ST_DMGR_RST1 => - -- We should initialize the 0th position of list descriptors - dbg <= x"2"; - c.desc_addr <= r.head_ptr; - c.desc_out <= desc_in; - c.desc_out.confirmed <= '0'; - c.desc_out.valid <= '0'; - c.desc_out.sent <= '0'; - c.desc_out.pkt <= to_unsigned(0, 32); - c.desc_we <= '1'; - dmgr_state_next <= ST_DMGR_IDLE; - when ST_DMGR_IDLE => - dbg <= x"3"; - -- First we check, if there are any packets to acknowledge - -- or commands to execute - if ack_fifo_empty = '0' then - if (to_integer(ack_pkt_in.cmd) = FCMD_ACK) or - (to_integer(ack_pkt_in.cmd) = FCMD_NACK) then - -- Prepare for reading of the command. - c.desc_addr <= ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0); - dmgr_state_next <= ST_DMGR_ACK1; - else - -- This is a command which requires sending of response. - -- This will be handled by the cmd_proc block (in case - -- of START and STOP it is not the most efficient way, - -- but still sufficient). - -- Always request transmission of result - r_i.cmd_retr <= '1'; - -- Check if this is a new command (just checking the sequence number, - -- to avoid more complex logic) - if ack_pkt_in.seq /= r.cmd_seq then - -- If no, store the command and it's argument, and order it to be executed - r_i.cmd_code <= ack_pkt_in.cmd; - r_i.cmd_seq <= ack_pkt_in.seq; - r_i.cmd_arg <= ack_pkt_in.pkt; - end if; - c.ack_rd <= '1'; -- Confirm, that the command was read - dmgr_state_next <= ST_DMGR_CMD; - end if; - elsif dta_buf_full = '1' then - -- We should handle reception of data. - -- If the previously filled buffer is full, pass it for transmission, - -- and allocate the next one. - -- - -- Calculate the number of the packet, which shoud be the next "head" - -- packet. We utilize the fact, that calculations are performed modulo - -- N_OF_PKTS (because pointers have length of LOG2_N_OF_PKTS) - r_i.nxt <= r.head_ptr + 1; - -- Prepare for reading of the current "head" descriptor - c.desc_addr <= r.head_ptr; - dmgr_state_next <= ST_DMGR_INS1; - elsif (r.tail_ptr /= r.head_ptr) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then - -- We need to (re)transmit some buffers - -- prepare reading of the descriptor, which should be transmitted - c.desc_addr <= r.retr_nxt; - dmgr_state_next <= ST_DMGR_RETR; - elsif r.cmd_retr = '1' and (r.cmd_ack = r.cmd_run) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then - -- No data waiting for transmission, and the command response should - -- be transmitted - if snd_ready = '1' then - r_i.retr_delay <= r.transm_delay; - r_i.cmd_retr <= '0'; - c.snd_cmd_start <= '1'; - end if; - end if; - when ST_DMGR_CMD => - r_i.cmd_run <= not r.cmd_run; - dmgr_state_next <= ST_DMGR_IDLE; - when ST_DMGR_INS1 => - dbg <= x"4"; - -- First we check, if there is free space, r.nxt is the number of the - -- future head packet. - if (r.nxt = r.tail_ptr) then - -- No free place! The packet, which we would like to fill is still - -- occupied. - -- Return to idle, waiting until something is freed. - -- In this case we should also force retransmission - if r.retr_delay = 0 then - c.desc_addr <= r.retr_nxt; - dmgr_state_next <= ST_DMGR_RETR; - else - dmgr_state_next <= ST_DMGR_IDLE; - end if; - else - -- We can fill the next buffer - -- First we mark the previous head packet - -- as valid and not confirmed - -- We also set the "flushed" status appropriately - c.desc_addr <= r.head_ptr; - c.desc_out <= desc_in; - c.desc_out.confirmed <= '0'; - c.desc_out.valid <= '1'; - if dta_buf_flush = '1' then - c.desc_out.flushed <= '1'; - else - c.desc_out.flushed <= '0'; - end if; - c.desc_we <= '1'; - -- Now we move the "head" pointer - r_i.head_ptr <= r.nxt; - -- Increase the packet number! - -- We utilize the fact, that packet number automatically - -- wraps to 0 after sending of 2**32 packets! - r_i.cur_pkt <= r.cur_pkt + 1; - dmgr_state_next <= ST_DMGR_INS2; - end if; - when ST_DMGR_INS2 => - dbg <= x"5"; - -- We fill the new head descriptor - c.desc_addr <= r.head_ptr; - c.desc_out.pkt <= r.cur_pkt; - c.desc_out.confirmed <= '0'; - c.desc_out.valid <= '0'; - c.desc_out.sent <= '0'; - c.desc_out.flushed <= '0'; - c.desc_we <= '1'; - -- Signal, that the buffer is freed - c.dta_buf_free <= '1'; - dmgr_state_next <= ST_DMGR_IDLE; - when ST_DMGR_ACK1 => - dbg <= x"6"; - -- In this state the desc memory should respond with the data of the - -- buffered packet, so we can state, if this packet is really correctly - -- acknowledged (here we also ignore the NACK packets! - case to_integer(ack_pkt_in.cmd) is - when FCMD_ACK => - if (ack_pkt_in.pkt = desc_in.pkt) and - (desc_in.valid = '1') then - -- This is really correct, unconfirmed packet - -- Increase the counter of not-repeated ACK packets - -- Write the confirmation - c.desc_addr <= ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0); - c.desc_out <= desc_in; - c.desc_out.valid <= '0'; - c.desc_out.confirmed <= '1'; - c.desc_we <= '1'; - -- Here we also handle the case, if the acknowledged packet was - -- the one which is now scheduled for retransmission... - if ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0) = r.retr_nxt then - r_i.retr_nxt <= r.retr_nxt + 1; - end if; - -- Check, if we need to update the "tail" pointer - if r.tail_ptr = ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0) then - c.ack_rd <= '1'; - dmgr_state_next <= ST_DMGR_ACK_TAIL; - else - -- If this is not the tail pointer, it means, that some packets - -- or acknowledgements have been lost - -- We trigger retransmission of those packets - r_i.ack_seq <= ack_pkt_in.seq; - r_i.retr_nxt <= r.tail_ptr; - -- Set the flag stating that only "earlier" packets should be retransmitted - r_i.retr_flag <= '1'; - c.ack_rd <= '1'; - dmgr_state_next <= ST_DMGR_IDLE; - end if; - else - -- This packet was already confirmed - -- just flush the ack_fifo - c.ack_rd <= '1'; - dmgr_state_next <= ST_DMGR_IDLE; - end if; - when FCMD_NACK=> - -- This was a NACK command, currently we simply ignore it - -- (later on we will use it to trigger retransmission). - c.ack_rd <= '1'; - dmgr_state_next <= ST_DMGR_IDLE; - when others => null; - end case; - when ST_DMGR_ACK_TAIL => - dbg <= x"7"; - c.desc_addr <= r.tail_ptr; - dmgr_state_next <= ST_DMGR_ACK_TAIL_1; - when ST_DMGR_ACK_TAIL_1 => - dbg <= x"8"; - -- In this state we update the "tail" pointer if necessary - if r.tail_ptr /= r.head_ptr then - if desc_in.confirmed = '1' then - r_i.tail_ptr <= r.tail_ptr + 1; -- it will wrap to 0 automatically! - c.desc_addr <= r.tail_ptr + 1; - -- We remain in that state, to check the next packet descriptor - else - -- We return to idle - dmgr_state_next <= ST_DMGR_IDLE; - end if; - else - -- Buffer is empty - return to idle - dmgr_state_next <= ST_DMGR_IDLE; - end if; - when ST_DMGR_RETR => - dbg <= x"9"; - -- Here we handle the transmission of a new packet, - -- retransmission of not confirmed packet - -- We must be sure, that the transmitter is ready - if snd_ready = '0' then - -- transmitter not ready, return to idle - dmgr_state_next <= ST_DMGR_IDLE; - else - -- We will be able to send the next packet, but let's check if - -- this is not the currently filled packet - if r.retr_nxt = r.head_ptr then - -- All packets (re)transmitted, go to the begining of the list - r_i.retr_nxt <= r.tail_ptr; - -- Clear the flag stating that only packets older than the last - -- acknowledged should be transmitted - r_i.retr_flag <= '0'; - -- and return to idle. - dmgr_state_next <= ST_DMGR_IDLE; - else - -- before jumping to ST_DMGR_RETR, the address bus - -- was set to the address of r.retr_nxt, so now - -- we can read the descriptor, and check if the packet - -- needs to be retransmitted at all... - r_i.pkt <= desc_in.pkt; - r_i.flushed <= desc_in.flushed; - r_i.retr_ptr <= r.retr_nxt; - r_i.retr_nxt <= r.retr_nxt + 1; - if desc_in.valid = '1' and desc_in.confirmed = '0' and - ((r.retr_flag = '0') or is_bigger(r.ack_seq, desc_in.seq)) then - if desc_in.sent = '1' then - -- Increase count of retransmitted packets for - -- adaptive adjustment of delay - if r.retr_pkt_count < PKT_CNT_MAX then - r_i.retr_pkt_count <= r.retr_pkt_count + 1; - end if; - end if; - -- Increase count of all packets for adaptive adjustment - -- of delay - if r.all_pkt_count < PKT_CNT_MAX then - r_i.all_pkt_count <= r.all_pkt_count + 1; - end if; - -- Mark the packet as sent - c.desc_addr <= r.retr_nxt; - c.desc_out <= desc_in; - c.desc_out.sent <= '1'; - -- increase the sequential number - r_i.seq <= r.seq + 1; - -- store the packet sequential number - c.desc_out.seq <= r.seq + 1; - c.desc_we <= '1'; - dmgr_state_next <= ST_DMGR_RETR_2; - else - dmgr_state_next <= ST_DMGR_IDLE; - end if; - end if; - end if; - when ST_DMGR_RETR_2 => - dbg <= x"a"; - -- In this state, we simply trigger the sender! - c.snd_start <= '1'; - if r.cmd_ack = r.cmd_run then - -- command response will be transmitted, so clear the related flag - r_i.cmd_retr <= '0'; - end if; - r_i.retr_delay <= r.transm_delay; - -- And we update the delay using the packet statistics - -- You may change the constants used in expressions - -- below to change speed of adjustment - if r.all_pkt_count >= PKT_CNT_MAX then - if r.retr_pkt_count < PKT_CNT_MAX/32 then - if r.transm_delay > 16 then - r_i.transm_delay <= r.transm_delay-r.transm_delay/16; - end if; - elsif r.retr_pkt_count > PKT_CNT_MAX/8 then - if r.transm_delay < 1000000 then - r_i.transm_delay <= r.transm_delay+r.transm_delay/4; - end if; - end if; - r_i.all_pkt_count <= 0; - r_i.retr_pkt_count <= 0; - end if; - dmgr_state_next <= ST_DMGR_IDLE; - when others => null; - end case; - end process c1; - --- Synchronous process - process (clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - r <= DESC_MGR_REGS_INI; - dmgr_state <= ST_DMGR_RST; - elsif clk'event and clk = '1' then -- rising clock edge - r <= r_i; - dmgr_state <= dmgr_state_next; - end if; - end process; - -end dmgr_a1; - - - Index: experimental_jumbo_frames_version/fpga/kc705/wzconstr.xdc =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/wzconstr.xdc (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/wzconstr.xdc (nonexistent) @@ -1,35 +0,0 @@ -set_property PACKAGE_PIN H2 [get_ports gtx10g_txp] -set_property PACKAGE_PIN J8 [get_ports gtx_refclk_p] -set_property IOSTANDARD LVCMOS18 [get_ports clk_2] -set_property IOSTANDARD LVCMOS18 [get_ports resetdone] -set_property IOSTANDARD LVCMOS18 [get_ports start] -set_property IOSTANDARD LVCMOS18 [get_ports txusrclk2_out] -set_property IOSTANDARD LVCMOS18 [get_ports txusrclk_out] - - -set_property PACKAGE_PIN AG5 [get_ports start] -set_property PACKAGE_PIN AE20 [get_ports clk_2] -set_property PACKAGE_PIN AB8 [get_ports txusrclk2_out] -set_property PACKAGE_PIN AA8 [get_ports txusrclk_out] -set_property PACKAGE_PIN AC9 [get_ports resetdone] -set_property PACKAGE_PIN AB12 [get_ports rst_p] - - -set_property PACKAGE_PIN AB9 [get_ports core_ready] -set_property IOSTANDARD LVCMOS18 [get_ports core_ready] - - -set_property IOSTANDARD LVCMOS18 [get_ports rst_p] - -create_clock -period 6.400 -name clk156 -waveform {0.000 3.200} [get_nets *156*] - -create_clock -period 6.400 -name gtx_refclk -waveform {0.000 3.200} [get_ports {gtx_refclk_n gtx_refclk_p}] - -set_property PACKAGE_PIN AE26 [get_ports trig_ack] - -set_property IOSTANDARD LVCMOS18 [get_ports trig_ack] -set_property LOC BSCAN_X0Y0 [get_cells dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst] - -set_property PACKAGE_PIN G19 [get_ports led5] -set_property IOSTANDARD LVCMOS18 [get_ports led5] -set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] Index: experimental_jumbo_frames_version/fpga/kc705/ila_1.xci =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/ila_1.xci (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/ila_1.xci (nonexistent) @@ -1,2124 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ila_1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 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NUM_OF_PROBES=12,DATA_DEPTH=1024,PROBE0_WIDTH=64,PROBE0_MU_CNT=1,PROBE1_WIDTH=8,PROBE1_MU_CNT=1,PROBE2_WIDTH=3,PROBE2_MU_CNT=1,PROBE3_WIDTH=8,PROBE3_MU_CNT=1,PROBE4_WIDTH=4,PROBE4_MU_CNT=1,PROBE5_WIDTH=32,PROBE5_MU_CNT=1,PROBE6_WIDTH=32,PROBE6_MU_CNT=1,PROBE7_WIDTH=16,PROBE7_MU_CNT=1,PROBE8_WIDTH=32,PROBE8_MU_CNT=1,PROBE9_WIDTH=32,PROBE9_MU_CNT=1,PROBE10_WIDTH=64,PROBE10_MU_CNT=1,PROBE11_WIDTH=8,PROBE11_MU_CNT=1,PROBE12_WIDTH=1,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1,PROBE64_WIDTH=1,PROBE64_MU_CNT=1,PROBE65_WIDTH=1,PROBE65_MU_CNT=1,PROBE66_WIDTH=1,PROBE66_MU_CNT=1,PROBE67_WIDTH=1,PROBE67_MU_CNT=1,PROBE68_WIDTH=1,PROBE68_MU_CNT=1,PROBE69_WIDTH=1,PROBE69_MU_CNT=1,PROBE70_WIDTH=1,PROBE70_MU_CNT=1,PROBE71_WIDTH=1,PROBE71_MU_CNT=1,PROBE72_WIDTH=1,PROBE72_MU_CNT=1,PROBE73_WIDTH=1,PROBE73_MU_CNT=1,PROBE74_WIDTH=1,PROBE74_MU_CNT=1,PROBE75_WIDTH=1,PROBE75_MU_CNT=1,PROBE76_WIDTH=1,PROBE76_MU_CNT=1,PROBE77_WIDTH=1,PROBE77_MU_CNT=1,PROBE78_WIDTH=1,PROBE78_MU_CNT=1,PROBE79_WIDTH=1,PROBE79_MU_CNT=1,PROBE80_WIDTH=1,PROBE80_MU_CNT=1,PROBE81_WIDTH=1,PROBE81_MU_CNT=1,PROBE82_WIDTH=1,PROBE82_MU_CNT=1,PROBE83_WIDTH=1,PROBE83_MU_CNT=1,PROBE84_WIDTH=1,PROBE84_MU_CNT=1,PROBE85_WIDTH=1,PROBE85_MU_CNT=1,PROBE86_WIDTH=1,PROBE86_MU_CNT=1,PROBE87_WIDTH=1,PROBE87_MU_CNT=1,PROBE88_WIDTH=1,PROBE88_MU_CNT=1,PROBE89_WIDTH=1,PROBE89_MU_CNT=1,PROBE90_WIDTH=1,PROBE90_MU_CNT=1,PROBE91_WIDTH=1,PROBE91_MU_CNT=1,PROBE92_WIDTH=1,PROBE92_MU_CNT=1,PROBE93_WIDTH=1,PROBE93_MU_CNT=1,PROBE94_WIDTH=1,PROBE94_MU_CNT=1,PROBE95_WIDTH=1,PROBE95_MU_CNT=1,PROBE96_WIDTH=1,PROBE96_MU_CNT=1,PROBE97_WIDTH=1,PROBE97_MU_CNT=1,PROBE98_WIDTH=1,PROBE98_MU_CNT=1,PROBE99_WIDTH=1,PROBE99_MU_CNT=1,PROBE100_WIDTH=1,PROBE100_MU_CNT=1,PROBE101_WIDTH=1,PROBE101_MU_CNT=1,PROBE102_WIDTH=1,PROBE102_MU_CNT=1,PROBE103_WIDTH=1,PROBE103_MU_CNT=1,PROBE104_WIDTH=1,PROBE104_MU_CNT=1,PROBE105_WIDTH=1,PROBE105_MU_CNT=1,PROBE106_WIDTH=1,PROBE106_MU_CNT=1,PROBE107_WIDTH=1,PROBE107_MU_CNT=1,PROBE108_WIDTH=1,PROBE108_MU_CNT=1,PROBE109_WIDTH=1,PROBE109_MU_CNT=1,PROBE110_WIDTH=1,PROBE110_MU_CNT=1,PROBE111_WIDTH=1,PROBE111_MU_CNT=1,PROBE112_WIDTH=1,PROBE112_MU_CNT=1,PROBE113_WIDTH=1,PROBE113_MU_CNT=1,PROBE114_WIDTH=1,PROBE114_MU_CNT=1,PROBE115_WIDTH=1,PROBE115_MU_CNT=1,PROBE116_WIDTH=1,PROBE116_MU_CNT=1,PROBE117_WIDTH=1,PROBE117_MU_CNT=1,PROBE118_WIDTH=1,PROBE118_MU_CNT=1,PROBE119_WIDTH=1,PROBE119_MU_CNT=1,PROBE120_WIDTH=1,PROBE120_MU_CNT=1,PROBE121_WIDTH=1,PROBE121_MU_CNT=1,PROBE122_WIDTH=1,PROBE122_MU_CNT=1,PROBE123_WIDTH=1,PROBE123_MU_CNT=1,PROBE124_WIDTH=1,PROBE124_MU_CNT=1,PROBE125_WIDTH=1,PROBE125_MU_CNT=1,PROBE126_WIDTH=1,PROBE126_MU_CNT=1,PROBE127_WIDTH=1,PROBE127_MU_CNT=1,PROBE128_WIDTH=1,PROBE128_MU_CNT=1,PROBE129_WIDTH=1,PROBE129_MU_CNT=1,PROBE130_WIDTH=1,PROBE130_MU_CNT=1,PROBE131_WIDTH=1,PROBE131_MU_CNT=1,PROBE132_WIDTH=1,PROBE132_MU_CNT=1,PROBE133_WIDTH=1,PROBE133_MU_CNT=1,PROBE134_WIDTH=1,PROBE134_MU_CNT=1,PROBE135_WIDTH=1,PROBE135_MU_CNT=1,PROBE136_WIDTH=1,PROBE136_MU_CNT=1,PROBE137_WIDTH=1,PROBE137_MU_CNT=1,PROBE138_WIDTH=1,PROBE138_MU_CNT=1,PROBE139_WIDTH=1,PROBE139_MU_CNT=1,PROBE140_WIDTH=1,PROBE140_MU_CNT=1,PROBE141_WIDTH=1,PROBE141_MU_CNT=1,PROBE142_WIDTH=1,PROBE142_MU_CNT=1,PROBE143_WIDTH=1,PROBE143_MU_CNT=1,PROBE144_WIDTH=1,PROBE144_MU_CNT=1,PROBE145_WIDTH=1,PROBE145_MU_CNT=1,PROBE146_WIDTH=1,PROBE146_MU_CNT=1,PROBE147_WIDTH=1,PROBE147_MU_CNT=1,PROBE148_WIDTH=1,PROBE148_MU_CNT=1,PROBE149_WIDTH=1,PROBE149_MU_CNT=1,PROBE150_WIDTH=1,PROBE150_MU_CNT=1,PROBE151_WIDTH=1,PROBE151_MU_CNT=1,PROBE152_WIDTH=1,PROBE152_MU_CNT=1,PROBE153_WIDTH=1,PROBE153_MU_CNT=1,PROBE154_WIDTH=1,PROBE154_MU_CNT=1,PROBE155_WIDTH=1,PROBE155_MU_CNT=1,PROBE156_WIDTH=1,PROBE156_MU_CNT=1,PROBE157_WIDTH=1,PROBE157_MU_CNT=1,PROBE158_WIDTH=1,PROBE158_MU_CNT=1,PROBE159_WIDTH=1,PROBE159_MU_CNT=1,PROBE160_WIDTH=1,PROBE160_MU_CNT=1,PROBE161_WIDTH=1,PROBE161_MU_CNT=1,PROBE162_WIDTH=1,PROBE162_MU_CNT=1,PROBE163_WIDTH=1,PROBE163_MU_CNT=1,PROBE164_WIDTH=1,PROBE164_MU_CNT=1,PROBE165_WIDTH=1,PROBE165_MU_CNT=1,PROBE166_WIDTH=1,PROBE166_MU_CNT=1,PROBE167_WIDTH=1,PROBE167_MU_CNT=1,PROBE168_WIDTH=1,PROBE168_MU_CNT=1,PROBE169_WIDTH=1,PROBE169_MU_CNT=1,PROBE170_WIDTH=1,PROBE170_MU_CNT=1,PROBE171_WIDTH=1,PROBE171_MU_CNT=1,PROBE172_WIDTH=1,PROBE172_MU_CNT=1,PROBE173_WIDTH=1,PROBE173_MU_CNT=1,PROBE174_WIDTH=1,PROBE174_MU_CNT=1,PROBE175_WIDTH=1,PROBE175_MU_CNT=1,PROBE176_WIDTH=1,PROBE176_MU_CNT=1,PROBE177_WIDTH=1,PROBE177_MU_CNT=1,PROBE178_WIDTH=1,PROBE178_MU_CNT=1,PROBE179_WIDTH=1,PROBE179_MU_CNT=1,PROBE180_WIDTH=1,PROBE180_MU_CNT=1,PROBE181_WIDTH=1,PROBE181_MU_CNT=1,PROBE182_WIDTH=1,PROBE182_MU_CNT=1,PROBE183_WIDTH=1,PROBE183_MU_CNT=1,PROBE184_WIDTH=1,PROBE184_MU_CNT=1,PROBE185_WIDTH=1,PROBE185_MU_CNT=1,PROBE186_WIDTH=1,PROBE186_MU_CNT=1,PROBE187_WIDTH=1,PROBE187_MU_CNT=1,PROBE188_WIDTH=1,PROBE188_MU_CNT=1,PROBE189_WIDTH=1,PROBE189_MU_CNT=1,PROBE190_WIDTH=1,PROBE190_MU_CNT=1,PROBE191_WIDTH=1,PROBE191_MU_CNT=1,PROBE192_WIDTH=1,PROBE192_MU_CNT=1,PROBE193_WIDTH=1,PROBE193_MU_CNT=1,PROBE194_WIDTH=1,PROBE194_MU_CNT=1,PROBE195_WIDTH=1,PROBE195_MU_CNT=1,PROBE196_WIDTH=1,PROBE196_MU_CNT=1,PROBE197_WIDTH=1,PROBE197_MU_CNT=1,PROBE198_WIDTH=1,PROBE198_MU_CNT=1,PROBE199_WIDTH=1,PROBE199_MU_CNT=1,PROBE200_WIDTH=1,PROBE200_MU_CNT=1,PROBE201_WIDTH=1,PROBE201_MU_CNT=1,PROBE202_WIDTH=1,PROBE202_MU_CNT=1,PROBE203_WIDTH=1,PROBE203_MU_CNT=1,PROBE204_WIDTH=1,PROBE204_MU_CNT=1,PROBE205_WIDTH=1,PROBE205_MU_CNT=1,PROBE206_WIDTH=1,PROBE206_MU_CNT=1,PROBE207_WIDTH=1,PROBE207_MU_CNT=1,PROBE208_WIDTH=1,PROBE208_MU_CNT=1,PROBE209_WIDTH=1,PROBE209_MU_CNT=1,PROBE210_WIDTH=1,PROBE210_MU_CNT=1,PROBE211_WIDTH=1,PROBE211_MU_CNT=1,PROBE212_WIDTH=1,PROBE212_MU_CNT=1,PROBE213_WIDTH=1,PROBE213_MU_CNT=1,PROBE214_WIDTH=1,PROBE214_MU_CNT=1,PROBE215_WIDTH=1,PROBE215_MU_CNT=1,PROBE216_WIDTH=1,PROBE216_MU_CNT=1,PROBE217_WIDTH=1,PROBE217_MU_CNT=1,PROBE218_WIDTH=1,PROBE218_MU_CNT=1,PROBE219_WIDTH=1,PROBE219_MU_CNT=1,PROBE220_WIDTH=1,PROBE220_MU_CNT=1,PROBE221_WIDTH=1,PROBE221_MU_CNT=1,PROBE222_WIDTH=1,PROBE222_MU_CNT=1,PROBE223_WIDTH=1,PROBE223_MU_CNT=1,PROBE224_WIDTH=1,PROBE224_MU_CNT=1,PROBE225_WIDTH=1,PROBE225_MU_CNT=1,PROBE226_WIDTH=1,PROBE226_MU_CNT=1,PROBE227_WIDTH=1,PROBE227_MU_CNT=1,PROBE228_WIDTH=1,PROBE228_MU_CNT=1,PROBE229_WIDTH=1,PROBE229_MU_CNT=1,PROBE230_WIDTH=1,PROBE230_MU_CNT=1,PROBE231_WIDTH=1,PROBE231_MU_CNT=1,PROBE232_WIDTH=1,PROBE232_MU_CNT=1,PROBE233_WIDTH=1,PROBE233_MU_CNT=1,PROBE234_WIDTH=1,PROBE234_MU_CNT=1,PROBE235_WIDTH=1,PROBE235_MU_CNT=1,PROBE236_WIDTH=1,PROBE236_MU_CNT=1,PROBE237_WIDTH=1,PROBE237_MU_CNT=1,PROBE238_WIDTH=1,PROBE238_MU_CNT=1,PROBE239_WIDTH=1,PROBE239_MU_CNT=1,PROBE240_WIDTH=1,PROBE240_MU_CNT=1,PROBE241_WIDTH=1,PROBE241_MU_CNT=1,PROBE242_WIDTH=1,PROBE242_MU_CNT=1,PROBE243_WIDTH=1,PROBE243_MU_CNT=1,PROBE244_WIDTH=1,PROBE244_MU_CNT=1,PROBE245_WIDTH=1,PROBE245_MU_CNT=1,PROBE246_WIDTH=1,PROBE246_MU_CNT=1,PROBE247_WIDTH=1,PROBE247_MU_CNT=1,PROBE248_WIDTH=1,PROBE248_MU_CNT=1,PROBE249_WIDTH=1,PROBE249_MU_CNT=1,PROBE250_WIDTH=1,PROBE250_MU_CNT=1,PROBE251_WIDTH=1,PROBE251_MU_CNT=1,PROBE252_WIDTH=1,PROBE252_MU_CNT=1,PROBE253_WIDTH=1,PROBE253_MU_CNT=1,PROBE254_WIDTH=1,PROBE254_MU_CNT=1,PROBE255_WIDTH=1,PROBE255_MU_CNT=1,PROBE256_WIDTH=1,PROBE256_MU_CNT=1,PROBE257_WIDTH=1,PROBE257_MU_CNT=1,PROBE258_WIDTH=1,PROBE258_MU_CNT=1,PROBE259_WIDTH=1,PROBE259_MU_CNT=1,PROBE260_WIDTH=1,PROBE260_MU_CNT=1,PROBE261_WIDTH=1,PROBE261_MU_CNT=1,PROBE262_WIDTH=1,PROBE262_MU_CNT=1,PROBE263_WIDTH=1,PROBE263_MU_CNT=1,PROBE264_WIDTH=1,PROBE264_MU_CNT=1,PROBE265_WIDTH=1,PROBE265_MU_CNT=1,PROBE266_WIDTH=1,PROBE266_MU_CNT=1,PROBE267_WIDTH=1,PROBE267_MU_CNT=1,PROBE268_WIDTH=1,PROBE268_MU_CNT=1,PROBE269_WIDTH=1,PROBE269_MU_CNT=1,PROBE270_WIDTH=1,PROBE270_MU_CNT=1,PROBE271_WIDTH=1,PROBE271_MU_CNT=1,PROBE272_WIDTH=1,PROBE272_MU_CNT=1,PROBE273_WIDTH=1,PROBE273_MU_CNT=1,PROBE274_WIDTH=1,PROBE274_MU_CNT=1,PROBE275_WIDTH=1,PROBE275_MU_CNT=1,PROBE276_WIDTH=1,PROBE276_MU_CNT=1,PROBE277_WIDTH=1,PROBE277_MU_CNT=1,PROBE278_WIDTH=1,PROBE278_MU_CNT=1,PROBE279_WIDTH=1,PROBE279_MU_CNT=1,PROBE280_WIDTH=1,PROBE280_MU_CNT=1,PROBE281_WIDTH=1,PROBE281_MU_CNT=1,PROBE282_WIDTH=1,PROBE282_MU_CNT=1,PROBE283_WIDTH=1,PROBE283_MU_CNT=1,PROBE284_WIDTH=1,PROBE284_MU_CNT=1,PROBE285_WIDTH=1,PROBE285_MU_CNT=1,PROBE286_WIDTH=1,PROBE286_MU_CNT=1,PROBE287_WIDTH=1,PROBE287_MU_CNT=1,PROBE288_WIDTH=1,PROBE288_MU_CNT=1,PROBE289_WIDTH=1,PROBE289_MU_CNT=1,PROBE290_WIDTH=1,PROBE290_MU_CNT=1,PROBE291_WIDTH=1,PROBE291_MU_CNT=1,PROBE292_WIDTH=1,PROBE292_MU_CNT=1,PROBE293_WIDTH=1,PROBE293_MU_CNT=1,PROBE294_WIDTH=1,PROBE294_MU_CNT=1,PROBE295_WIDTH=1,PROBE295_MU_CNT=1,PROBE296_WIDTH=1,PROBE296_MU_CNT=1,PROBE297_WIDTH=1,PROBE297_MU_CNT=1,PROBE298_WIDTH=1,PROBE298_MU_CNT=1,PROBE299_WIDTH=1,PROBE299_MU_CNT=1,PROBE300_WIDTH=1,PROBE300_MU_CNT=1,PROBE301_WIDTH=1,PROBE301_MU_CNT=1,PROBE302_WIDTH=1,PROBE302_MU_CNT=1,PROBE303_WIDTH=1,PROBE303_MU_CNT=1,PROBE304_WIDTH=1,PROBE304_MU_CNT=1,PROBE305_WIDTH=1,PROBE305_MU_CNT=1,PROBE306_WIDTH=1,PROBE306_MU_CNT=1,PROBE307_WIDTH=1,PROBE307_MU_CNT=1,PROBE308_WIDTH=1,PROBE308_MU_CNT=1,PROBE309_WIDTH=1,PROBE309_MU_CNT=1,PROBE310_WIDTH=1,PROBE310_MU_CNT=1,PROBE311_WIDTH=1,PROBE311_MU_CNT=1,PROBE312_WIDTH=1,PROBE312_MU_CNT=1,PROBE313_WIDTH=1,PROBE313_MU_CNT=1,PROBE314_WIDTH=1,PROBE314_MU_CNT=1,PROBE315_WIDTH=1,PROBE315_MU_CNT=1,PROBE316_WIDTH=1,PROBE316_MU_CNT=1,PROBE317_WIDTH=1,PROBE317_MU_CNT=1,PROBE318_WIDTH=1,PROBE318_MU_CNT=1,PROBE319_WIDTH=1,PROBE319_MU_CNT=1,PROBE320_WIDTH=1,PROBE320_MU_CNT=1,PROBE321_WIDTH=1,PROBE321_MU_CNT=1,PROBE322_WIDTH=1,PROBE322_MU_CNT=1,PROBE323_WIDTH=1,PROBE323_MU_CNT=1,PROBE324_WIDTH=1,PROBE324_MU_CNT=1,PROBE325_WIDTH=1,PROBE325_MU_CNT=1,PROBE326_WIDTH=1,PROBE326_MU_CNT=1,PROBE327_WIDTH=1,PROBE327_MU_CNT=1,PROBE328_WIDTH=1,PROBE328_MU_CNT=1,PROBE329_WIDTH=1,PROBE329_MU_CNT=1,PROBE330_WIDTH=1,PROBE330_MU_CNT=1,PROBE331_WIDTH=1,PROBE331_MU_CNT=1,PROBE332_WIDTH=1,PROBE332_MU_CNT=1,PROBE333_WIDTH=1,PROBE333_MU_CNT=1,PROBE334_WIDTH=1,PROBE334_MU_CNT=1,PROBE335_WIDTH=1,PROBE335_MU_CNT=1,PROBE336_WIDTH=1,PROBE336_MU_CNT=1,PROBE337_WIDTH=1,PROBE337_MU_CNT=1,PROBE338_WIDTH=1,PROBE338_MU_CNT=1,PROBE339_WIDTH=1,PROBE339_MU_CNT=1,PROBE340_WIDTH=1,PROBE340_MU_CNT=1,PROBE341_WIDTH=1,PROBE341_MU_CNT=1,PROBE342_WIDTH=1,PROBE342_MU_CNT=1,PROBE343_WIDTH=1,PROBE343_MU_CNT=1,PROBE344_WIDTH=1,PROBE344_MU_CNT=1,PROBE345_WIDTH=1,PROBE345_MU_CNT=1,PROBE346_WIDTH=1,PROBE346_MU_CNT=1,PROBE347_WIDTH=1,PROBE347_MU_CNT=1,PROBE348_WIDTH=1,PROBE348_MU_CNT=1,PROBE349_WIDTH=1,PROBE349_MU_CNT=1,PROBE350_WIDTH=1,PROBE350_MU_CNT=1,PROBE351_WIDTH=1,PROBE351_MU_CNT=1,PROBE352_WIDTH=1,PROBE352_MU_CNT=1,PROBE353_WIDTH=1,PROBE353_MU_CNT=1,PROBE354_WIDTH=1,PROBE354_MU_CNT=1,PROBE355_WIDTH=1,PROBE355_MU_CNT=1,PROBE356_WIDTH=1,PROBE356_MU_CNT=1,PROBE357_WIDTH=1,PROBE357_MU_CNT=1,PROBE358_WIDTH=1,PROBE358_MU_CNT=1,PROBE359_WIDTH=1,PROBE359_MU_CNT=1,PROBE360_WIDTH=1,PROBE360_MU_CNT=1,PROBE361_WIDTH=1,PROBE361_MU_CNT=1,PROBE362_WIDTH=1,PROBE362_MU_CNT=1,PROBE363_WIDTH=1,PROBE363_MU_CNT=1,PROBE364_WIDTH=1,PROBE364_MU_CNT=1,PROBE365_WIDTH=1,PROBE365_MU_CNT=1,PROBE366_WIDTH=1,PROBE366_MU_CNT=1,PROBE367_WIDTH=1,PROBE367_MU_CNT=1,PROBE368_WIDTH=1,PROBE368_MU_CNT=1,PROBE369_WIDTH=1,PROBE369_MU_CNT=1,PROBE370_WIDTH=1,PROBE370_MU_CNT=1,PROBE371_WIDTH=1,PROBE371_MU_CNT=1,PROBE372_WIDTH=1,PROBE372_MU_CNT=1,PROBE373_WIDTH=1,PROBE373_MU_CNT=1,PROBE374_WIDTH=1,PROBE374_MU_CNT=1,PROBE375_WIDTH=1,PROBE375_MU_CNT=1,PROBE376_WIDTH=1,PROBE376_MU_CNT=1,PROBE377_WIDTH=1,PROBE377_MU_CNT=1,PROBE378_WIDTH=1,PROBE378_MU_CNT=1,PROBE379_WIDTH=1,PROBE379_MU_CNT=1,PROBE380_WIDTH=1,PROBE380_MU_CNT=1,PROBE381_WIDTH=1,PROBE381_MU_CNT=1,PROBE382_WIDTH=1,PROBE382_MU_CNT=1,PROBE383_WIDTH=1,PROBE383_MU_CNT=1,PROBE384_WIDTH=1,PROBE384_MU_CNT=1,PROBE385_WIDTH=1,PROBE385_MU_CNT=1,PROBE386_WIDTH=1,PROBE386_MU_CNT=1,PROBE387_WIDTH=1,PROBE387_MU_CNT=1,PROBE388_WIDTH=1,PROBE388_MU_CNT=1,PROBE389_WIDTH=1,PROBE389_MU_CNT=1,PROBE390_WIDTH=1,PROBE390_MU_CNT=1,PROBE391_WIDTH=1,PROBE391_MU_CNT=1,PROBE392_WIDTH=1,PROBE392_MU_CNT=1,PROBE393_WIDTH=1,PROBE393_MU_CNT=1,PROBE394_WIDTH=1,PROBE394_MU_CNT=1,PROBE395_WIDTH=1,PROBE395_MU_CNT=1,PROBE396_WIDTH=1,PROBE396_MU_CNT=1,PROBE397_WIDTH=1,PROBE397_MU_CNT=1,PROBE398_WIDTH=1,PROBE398_MU_CNT=1,PROBE399_WIDTH=1,PROBE399_MU_CNT=1,PROBE400_WIDTH=1,PROBE400_MU_CNT=1,PROBE401_WIDTH=1,PROBE401_MU_CNT=1,PROBE402_WIDTH=1,PROBE402_MU_CNT=1,PROBE403_WIDTH=1,PROBE403_MU_CNT=1,PROBE404_WIDTH=1,PROBE404_MU_CNT=1,PROBE405_WIDTH=1,PROBE405_MU_CNT=1,PROBE406_WIDTH=1,PROBE406_MU_CNT=1,PROBE407_WIDTH=1,PROBE407_MU_CNT=1,PROBE408_WIDTH=1,PROBE408_MU_CNT=1,PROBE409_WIDTH=1,PROBE409_MU_CNT=1,PROBE410_WIDTH=1,PROBE410_MU_CNT=1,PROBE411_WIDTH=1,PROBE411_MU_CNT=1,PROBE412_WIDTH=1,PROBE412_MU_CNT=1,PROBE413_WIDTH=1,PROBE413_MU_CNT=1,PROBE414_WIDTH=1,PROBE414_MU_CNT=1,PROBE415_WIDTH=1,PROBE415_MU_CNT=1,PROBE416_WIDTH=1,PROBE416_MU_CNT=1,PROBE417_WIDTH=1,PROBE417_MU_CNT=1,PROBE418_WIDTH=1,PROBE418_MU_CNT=1,PROBE419_WIDTH=1,PROBE419_MU_CNT=1,PROBE420_WIDTH=1,PROBE420_MU_CNT=1,PROBE421_WIDTH=1,PROBE421_MU_CNT=1,PROBE422_WIDTH=1,PROBE422_MU_CNT=1,PROBE423_WIDTH=1,PROBE423_MU_CNT=1,PROBE424_WIDTH=1,PROBE424_MU_CNT=1,PROBE425_WIDTH=1,PROBE425_MU_CNT=1,PROBE426_WIDTH=1,PROBE426_MU_CNT=1,PROBE427_WIDTH=1,PROBE427_MU_CNT=1,PROBE428_WIDTH=1,PROBE428_MU_CNT=1,PROBE429_WIDTH=1,PROBE429_MU_CNT=1,PROBE430_WIDTH=1,PROBE430_MU_CNT=1,PROBE431_WIDTH=1,PROBE431_MU_CNT=1,PROBE432_WIDTH=1,PROBE432_MU_CNT=1,PROBE433_WIDTH=1,PROBE433_MU_CNT=1,PROBE434_WIDTH=1,PROBE434_MU_CNT=1,PROBE435_WIDTH=1,PROBE435_MU_CNT=1,PROBE436_WIDTH=1,PROBE436_MU_CNT=1,PROBE437_WIDTH=1,PROBE437_MU_CNT=1,PROBE438_WIDTH=1,PROBE438_MU_CNT=1,PROBE439_WIDTH=1,PROBE439_MU_CNT=1,PROBE440_WIDTH=1,PROBE440_MU_CNT=1,PROBE441_WIDTH=1,PROBE441_MU_CNT=1,PROBE442_WIDTH=1,PROBE442_MU_CNT=1,PROBE443_WIDTH=1,PROBE443_MU_CNT=1,PROBE444_WIDTH=1,PROBE444_MU_CNT=1,PROBE445_WIDTH=1,PROBE445_MU_CNT=1,PROBE446_WIDTH=1,PROBE446_MU_CNT=1,PROBE447_WIDTH=1,PROBE447_MU_CNT=1,PROBE448_WIDTH=1,PROBE448_MU_CNT=1,PROBE449_WIDTH=1,PROBE449_MU_CNT=1,PROBE450_WIDTH=1,PROBE450_MU_CNT=1,PROBE451_WIDTH=1,PROBE451_MU_CNT=1,PROBE452_WIDTH=1,PROBE452_MU_CNT=1,PROBE453_WIDTH=1,PROBE453_MU_CNT=1,PROBE454_WIDTH=1,PROBE454_MU_CNT=1,PROBE455_WIDTH=1,PROBE455_MU_CNT=1,PROBE456_WIDTH=1,PROBE456_MU_CNT=1,PROBE457_WIDTH=1,PROBE457_MU_CNT=1,PROBE458_WIDTH=1,PROBE458_MU_CNT=1,PROBE459_WIDTH=1,PROBE459_MU_CNT=1,PROBE460_WIDTH=1,PROBE460_MU_CNT=1,PROBE461_WIDTH=1,PROBE461_MU_CNT=1,PROBE462_WIDTH=1,PROBE462_MU_CNT=1,PROBE463_WIDTH=1,PROBE463_MU_CNT=1,PROBE464_WIDTH=1,PROBE464_MU_CNT=1,PROBE465_WIDTH=1,PROBE465_MU_CNT=1,PROBE466_WIDTH=1,PROBE466_MU_CNT=1,PROBE467_WIDTH=1,PROBE467_MU_CNT=1,PROBE468_WIDTH=1,PROBE468_MU_CNT=1,PROBE469_WIDTH=1,PROBE469_MU_CNT=1,PROBE470_WIDTH=1,PROBE470_MU_CNT=1,PROBE471_WIDTH=1,PROBE471_MU_CNT=1,PROBE472_WIDTH=1,PROBE472_MU_CNT=1,PROBE473_WIDTH=1,PROBE473_MU_CNT=1,PROBE474_WIDTH=1,PROBE474_MU_CNT=1,PROBE475_WIDTH=1,PROBE475_MU_CNT=1,PROBE476_WIDTH=1,PROBE476_MU_CNT=1,PROBE477_WIDTH=1,PROBE477_MU_CNT=1,PROBE478_WIDTH=1,PROBE478_MU_CNT=1,PROBE479_WIDTH=1,PROBE479_MU_CNT=1,PROBE480_WIDTH=1,PROBE480_MU_CNT=1,PROBE481_WIDTH=1,PROBE481_MU_CNT=1,PROBE482_WIDTH=1,PROBE482_MU_CNT=1,PROBE483_WIDTH=1,PROBE483_MU_CNT=1,PROBE484_WIDTH=1,PROBE484_MU_CNT=1,PROBE485_WIDTH=1,PROBE485_MU_CNT=1,PROBE486_WIDTH=1,PROBE486_MU_CNT=1,PROBE487_WIDTH=1,PROBE487_MU_CNT=1,PROBE488_WIDTH=1,PROBE488_MU_CNT=1,PROBE489_WIDTH=1,PROBE489_MU_CNT=1,PROBE490_WIDTH=1,PROBE490_MU_CNT=1,PROBE491_WIDTH=1,PROBE491_MU_CNT=1,PROBE492_WIDTH=1,PROBE492_MU_CNT=1,PROBE493_WIDTH=1,PROBE493_MU_CNT=1,PROBE494_WIDTH=1,PROBE494_MU_CNT=1,PROBE495_WIDTH=1,PROBE495_MU_CNT=1,PROBE496_WIDTH=1,PROBE496_MU_CNT=1,PROBE497_WIDTH=1,PROBE497_MU_CNT=1,PROBE498_WIDTH=1,PROBE498_MU_CNT=1,PROBE499_WIDTH=1,PROBE499_MU_CNT=1,PROBE500_WIDTH=1,PROBE500_MU_CNT=1,PROBE501_WIDTH=1,PROBE501_MU_CNT=1,PROBE502_WIDTH=1,PROBE502_MU_CNT=1,PROBE503_WIDTH=1,PROBE503_MU_CNT=1,PROBE504_WIDTH=1,PROBE504_MU_CNT=1,PROBE505_WIDTH=1,PROBE505_MU_CNT=1,PROBE506_WIDTH=1,PROBE506_MU_CNT=1,PROBE507_WIDTH=1,PROBE507_MU_CNT=1,PROBE508_WIDTH=1,PROBE508_MU_CNT=1,PROBE509_WIDTH=1,PROBE509_MU_CNT=1,PROBE510_WIDTH=1,PROBE510_MU_CNT=1,PROBE511_WIDTH=1,PROBE511_MU_CNT=1,PROBE512_WIDTH=1,PROBE512_MU_CNT=1,PROBE513_WIDTH=1,PROBE513_MU_CNT=1,PROBE514_WIDTH=1,PROBE514_MU_CNT=1,PROBE515_WIDTH=1,PROBE515_MU_CNT=1,PROBE516_WIDTH=1,PROBE516_MU_CNT=1,PROBE517_WIDTH=1,PROBE517_MU_CNT=1,PROBE518_WIDTH=1,PROBE518_MU_CNT=1,PROBE519_WIDTH=1,PROBE519_MU_CNT=1,PROBE520_WIDTH=1,PROBE520_MU_CNT=1,PROBE521_WIDTH=1,PROBE521_MU_CNT=1,PROBE522_WIDTH=1,PROBE522_MU_CNT=1,PROBE523_WIDTH=1,PROBE523_MU_CNT=1,PROBE524_WIDTH=1,PROBE524_MU_CNT=1,PROBE525_WIDTH=1,PROBE525_MU_CNT=1,PROBE526_WIDTH=1,PROBE526_MU_CNT=1,PROBE527_WIDTH=1,PROBE527_MU_CNT=1,PROBE528_WIDTH=1,PROBE528_MU_CNT=1,PROBE529_WIDTH=1,PROBE529_MU_CNT=1,PROBE530_WIDTH=1,PROBE530_MU_CNT=1,PROBE531_WIDTH=1,PROBE531_MU_CNT=1,PROBE532_WIDTH=1,PROBE532_MU_CNT=1,PROBE533_WIDTH=1,PROBE533_MU_CNT=1,PROBE534_WIDTH=1,PROBE534_MU_CNT=1,PROBE535_WIDTH=1,PROBE535_MU_CNT=1,PROBE536_WIDTH=1,PROBE536_MU_CNT=1,PROBE537_WIDTH=1,PROBE537_MU_CNT=1,PROBE538_WIDTH=1,PROBE538_MU_CNT=1,PROBE539_WIDTH=1,PROBE539_MU_CNT=1,PROBE540_WIDTH=1,PROBE540_MU_CNT=1,PROBE541_WIDTH=1,PROBE541_MU_CNT=1,PROBE542_WIDTH=1,PROBE542_MU_CNT=1,PROBE543_WIDTH=1,PROBE543_MU_CNT=1,PROBE544_WIDTH=1,PROBE544_MU_CNT=1,PROBE545_WIDTH=1,PROBE545_MU_CNT=1,PROBE546_WIDTH=1,PROBE546_MU_CNT=1,PROBE547_WIDTH=1,PROBE547_MU_CNT=1,PROBE548_WIDTH=1,PROBE548_MU_CNT=1,PROBE549_WIDTH=1,PROBE549_MU_CNT=1,PROBE550_WIDTH=1,PROBE550_MU_CNT=1,PROBE551_WIDTH=1,PROBE551_MU_CNT=1,PROBE552_WIDTH=1,PROBE552_MU_CNT=1,PROBE553_WIDTH=1,PROBE553_MU_CNT=1,PROBE554_WIDTH=1,PROBE554_MU_CNT=1,PROBE555_WIDTH=1,PROBE555_MU_CNT=1,PROBE556_WIDTH=1,PROBE556_MU_CNT=1,PROBE557_WIDTH=1,PROBE557_MU_CNT=1,PROBE558_WIDTH=1,PROBE558_MU_CNT=1,PROBE559_WIDTH=1,PROBE559_MU_CNT=1,PROBE560_WIDTH=1,PROBE560_MU_CNT=1,PROBE561_WIDTH=1,PROBE561_MU_CNT=1,PROBE562_WIDTH=1,PROBE562_MU_CNT=1,PROBE563_WIDTH=1,PROBE563_MU_CNT=1,PROBE564_WIDTH=1,PROBE564_MU_CNT=1,PROBE565_WIDTH=1,PROBE565_MU_CNT=1,PROBE566_WIDTH=1,PROBE566_MU_CNT=1,PROBE567_WIDTH=1,PROBE567_MU_CNT=1,PROBE568_WIDTH=1,PROBE568_MU_CNT=1,PROBE569_WIDTH=1,PROBE569_MU_CNT=1,PROBE570_WIDTH=1,PROBE570_MU_CNT=1,PROBE571_WIDTH=1,PROBE571_MU_CNT=1,PROBE572_WIDTH=1,PROBE572_MU_CNT=1,PROBE573_WIDTH=1,PROBE573_MU_CNT=1,PROBE574_WIDTH=1,PROBE574_MU_CNT=1,PROBE575_WIDTH=1,PROBE575_MU_CNT=1,PROBE576_WIDTH=1,PROBE576_MU_CNT=1,PROBE577_WIDTH=1,PROBE577_MU_CNT=1,PROBE578_WIDTH=1,PROBE578_MU_CNT=1,PROBE579_WIDTH=1,PROBE579_MU_CNT=1,PROBE580_WIDTH=1,PROBE580_MU_CNT=1,PROBE581_WIDTH=1,PROBE581_MU_CNT=1,PROBE582_WIDTH=1,PROBE582_MU_CNT=1,PROBE583_WIDTH=1,PROBE583_MU_CNT=1,PROBE584_WIDTH=1,PROBE584_MU_CNT=1,PROBE585_WIDTH=1,PROBE585_MU_CNT=1,PROBE586_WIDTH=1,PROBE586_MU_CNT=1,PROBE587_WIDTH=1,PROBE587_MU_CNT=1,PROBE588_WIDTH=1,PROBE588_MU_CNT=1,PROBE589_WIDTH=1,PROBE589_MU_CNT=1,PROBE590_WIDTH=1,PROBE590_MU_CNT=1,PROBE591_WIDTH=1,PROBE591_MU_CNT=1,PROBE592_WIDTH=1,PROBE592_MU_CNT=1,PROBE593_WIDTH=1,PROBE593_MU_CNT=1,PROBE594_WIDTH=1,PROBE594_MU_CNT=1,PROBE595_WIDTH=1,PROBE595_MU_CNT=1,PROBE596_WIDTH=1,PROBE596_MU_CNT=1,PROBE597_WIDTH=1,PROBE597_MU_CNT=1,PROBE598_WIDTH=1,PROBE598_MU_CNT=1,PROBE599_WIDTH=1,PROBE599_MU_CNT=1,PROBE600_WIDTH=1,PROBE600_MU_CNT=1,PROBE601_WIDTH=1,PROBE601_MU_CNT=1,PROBE602_WIDTH=1,PROBE602_MU_CNT=1,PROBE603_WIDTH=1,PROBE603_MU_CNT=1,PROBE604_WIDTH=1,PROBE604_MU_CNT=1,PROBE605_WIDTH=1,PROBE605_MU_CNT=1,PROBE606_WIDTH=1,PROBE606_MU_CNT=1,PROBE607_WIDTH=1,PROBE607_MU_CNT=1,PROBE608_WIDTH=1,PROBE608_MU_CNT=1,PROBE609_WIDTH=1,PROBE609_MU_CNT=1,PROBE610_WIDTH=1,PROBE610_MU_CNT=1,PROBE611_WIDTH=1,PROBE611_MU_CNT=1,PROBE612_WIDTH=1,PROBE612_MU_CNT=1,PROBE613_WIDTH=1,PROBE613_MU_CNT=1,PROBE614_WIDTH=1,PROBE614_MU_CNT=1,PROBE615_WIDTH=1,PROBE615_MU_CNT=1,PROBE616_WIDTH=1,PROBE616_MU_CNT=1,PROBE617_WIDTH=1,PROBE617_MU_CNT=1,PROBE618_WIDTH=1,PROBE618_MU_CNT=1,PROBE619_WIDTH=1,PROBE619_MU_CNT=1,PROBE620_WIDTH=1,PROBE620_MU_CNT=1,PROBE621_WIDTH=1,PROBE621_MU_CNT=1,PROBE622_WIDTH=1,PROBE622_MU_CNT=1,PROBE623_WIDTH=1,PROBE623_MU_CNT=1,PROBE624_WIDTH=1,PROBE624_MU_CNT=1,PROBE625_WIDTH=1,PROBE625_MU_CNT=1,PROBE626_WIDTH=1,PROBE626_MU_CNT=1,PROBE627_WIDTH=1,PROBE627_MU_CNT=1,PROBE628_WIDTH=1,PROBE628_MU_CNT=1,PROBE629_WIDTH=1,PROBE629_MU_CNT=1,PROBE630_WIDTH=1,PROBE630_MU_CNT=1,PROBE631_WIDTH=1,PROBE631_MU_CNT=1,PROBE632_WIDTH=1,PROBE632_MU_CNT=1,PROBE633_WIDTH=1,PROBE633_MU_CNT=1,PROBE634_WIDTH=1,PROBE634_MU_CNT=1,PROBE635_WIDTH=1,PROBE635_MU_CNT=1,PROBE636_WIDTH=1,PROBE636_MU_CNT=1,PROBE637_WIDTH=1,PROBE637_MU_CNT=1,PROBE638_WIDTH=1,PROBE638_MU_CNT=1,PROBE639_WIDTH=1,PROBE639_MU_CNT=1,PROBE640_WIDTH=1,PROBE640_MU_CNT=1,PROBE641_WIDTH=1,PROBE641_MU_CNT=1,PROBE642_WIDTH=1,PROBE642_MU_CNT=1,PROBE643_WIDTH=1,PROBE643_MU_CNT=1,PROBE644_WIDTH=1,PROBE644_MU_CNT=1,PROBE645_WIDTH=1,PROBE645_MU_CNT=1,PROBE646_WIDTH=1,PROBE646_MU_CNT=1,PROBE647_WIDTH=1,PROBE647_MU_CNT=1,PROBE648_WIDTH=1,PROBE648_MU_CNT=1,PROBE649_WIDTH=1,PROBE649_MU_CNT=1,PROBE650_WIDTH=1,PROBE650_MU_CNT=1,PROBE651_WIDTH=1,PROBE651_MU_CNT=1,PROBE652_WIDTH=1,PROBE652_MU_CNT=1,PROBE653_WIDTH=1,PROBE653_MU_CNT=1,PROBE654_WIDTH=1,PROBE654_MU_CNT=1,PROBE655_WIDTH=1,PROBE655_MU_CNT=1,PROBE656_WIDTH=1,PROBE656_MU_CNT=1,PROBE657_WIDTH=1,PROBE657_MU_CNT=1,PROBE658_WIDTH=1,PROBE658_MU_CNT=1,PROBE659_WIDTH=1,PROBE659_MU_CNT=1,PROBE660_WIDTH=1,PROBE660_MU_CNT=1,PROBE661_WIDTH=1,PROBE661_MU_CNT=1,PROBE662_WIDTH=1,PROBE662_MU_CNT=1,PROBE663_WIDTH=1,PROBE663_MU_CNT=1,PROBE664_WIDTH=1,PROBE664_MU_CNT=1,PROBE665_WIDTH=1,PROBE665_MU_CNT=1,PROBE666_WIDTH=1,PROBE666_MU_CNT=1,PROBE667_WIDTH=1,PROBE667_MU_CNT=1,PROBE668_WIDTH=1,PROBE668_MU_CNT=1,PROBE669_WIDTH=1,PROBE669_MU_CNT=1,PROBE670_WIDTH=1,PROBE670_MU_CNT=1,PROBE671_WIDTH=1,PROBE671_MU_CNT=1,PROBE672_WIDTH=1,PROBE672_MU_CNT=1,PROBE673_WIDTH=1,PROBE673_MU_CNT=1,PROBE674_WIDTH=1,PROBE674_MU_CNT=1,PROBE675_WIDTH=1,PROBE675_MU_CNT=1,PROBE676_WIDTH=1,PROBE676_MU_CNT=1,PROBE677_WIDTH=1,PROBE677_MU_CNT=1,PROBE678_WIDTH=1,PROBE678_MU_CNT=1,PROBE679_WIDTH=1,PROBE679_MU_CNT=1,PROBE680_WIDTH=1,PROBE680_MU_CNT=1,PROBE681_WIDTH=1,PROBE681_MU_CNT=1,PROBE682_WIDTH=1,PROBE682_MU_CNT=1,PROBE683_WIDTH=1,PROBE683_MU_CNT=1,PROBE684_WIDTH=1,PROBE684_MU_CNT=1,PROBE685_WIDTH=1,PROBE685_MU_CNT=1,PROBE686_WIDTH=1,PROBE686_MU_CNT=1,PROBE687_WIDTH=1,PROBE687_MU_CNT=1,PROBE688_WIDTH=1,PROBE688_MU_CNT=1,PROBE689_WIDTH=1,PROBE689_MU_CNT=1,PROBE690_WIDTH=1,PROBE690_MU_CNT=1,PROBE691_WIDTH=1,PROBE691_MU_CNT=1,PROBE692_WIDTH=1,PROBE692_MU_CNT=1,PROBE693_WIDTH=1,PROBE693_MU_CNT=1,PROBE694_WIDTH=1,PROBE694_MU_CNT=1,PROBE695_WIDTH=1,PROBE695_MU_CNT=1,PROBE696_WIDTH=1,PROBE696_MU_CNT=1,PROBE697_WIDTH=1,PROBE697_MU_CNT=1,PROBE698_WIDTH=1,PROBE698_MU_CNT=1,PROBE699_WIDTH=1,PROBE699_MU_CNT=1,PROBE700_WIDTH=1,PROBE700_MU_CNT=1,PROBE701_WIDTH=1,PROBE701_MU_CNT=1,PROBE702_WIDTH=1,PROBE702_MU_CNT=1,PROBE703_WIDTH=1,PROBE703_MU_CNT=1,PROBE704_WIDTH=1,PROBE704_MU_CNT=1,PROBE705_WIDTH=1,PROBE705_MU_CNT=1,PROBE706_WIDTH=1,PROBE706_MU_CNT=1,PROBE707_WIDTH=1,PROBE707_MU_CNT=1,PROBE708_WIDTH=1,PROBE708_MU_CNT=1,PROBE709_WIDTH=1,PROBE709_MU_CNT=1,PROBE710_WIDTH=1,PROBE710_MU_CNT=1,PROBE711_WIDTH=1,PROBE711_MU_CNT=1,PROBE712_WIDTH=1,PROBE712_MU_CNT=1,PROBE713_WIDTH=1,PROBE713_MU_CNT=1,PROBE714_WIDTH=1,PROBE714_MU_CNT=1,PROBE715_WIDTH=1,PROBE715_MU_CNT=1,PROBE716_WIDTH=1,PROBE716_MU_CNT=1,PROBE717_WIDTH=1,PROBE717_MU_CNT=1,PROBE718_WIDTH=1,PROBE718_MU_CNT=1,PROBE719_WIDTH=1,PROBE719_MU_CNT=1,PROBE720_WIDTH=1,PROBE720_MU_CNT=1,PROBE721_WIDTH=1,PROBE721_MU_CNT=1,PROBE722_WIDTH=1,PROBE722_MU_CNT=1,PROBE723_WIDTH=1,PROBE723_MU_CNT=1,PROBE724_WIDTH=1,PROBE724_MU_CNT=1,PROBE725_WIDTH=1,PROBE725_MU_CNT=1,PROBE726_WIDTH=1,PROBE726_MU_CNT=1,PROBE727_WIDTH=1,PROBE727_MU_CNT=1,PROBE728_WIDTH=1,PROBE728_MU_CNT=1,PROBE729_WIDTH=1,PROBE729_MU_CNT=1,PROBE730_WIDTH=1,PROBE730_MU_CNT=1,PROBE731_WIDTH=1,PROBE731_MU_CNT=1,PROBE732_WIDTH=1,PROBE732_MU_CNT=1,PROBE733_WIDTH=1,PROBE733_MU_CNT=1,PROBE734_WIDTH=1,PROBE734_MU_CNT=1,PROBE735_WIDTH=1,PROBE735_MU_CNT=1,PROBE736_WIDTH=1,PROBE736_MU_CNT=1,PROBE737_WIDTH=1,PROBE737_MU_CNT=1,PROBE738_WIDTH=1,PROBE738_MU_CNT=1,PROBE739_WIDTH=1,PROBE739_MU_CNT=1,PROBE740_WIDTH=1,PROBE740_MU_CNT=1,PROBE741_WIDTH=1,PROBE741_MU_CNT=1,PROBE742_WIDTH=1,PROBE742_MU_CNT=1,PROBE743_WIDTH=1,PROBE743_MU_CNT=1,PROBE744_WIDTH=1,PROBE744_MU_CNT=1,PROBE745_WIDTH=1,PROBE745_MU_CNT=1,PROBE746_WIDTH=1,PROBE746_MU_CNT=1,PROBE747_WIDTH=1,PROBE747_MU_CNT=1,PROBE748_WIDTH=1,PROBE748_MU_CNT=1,PROBE749_WIDTH=1,PROBE749_MU_CNT=1,PROBE750_WIDTH=1,PROBE750_MU_CNT=1,PROBE751_WIDTH=1,PROBE751_MU_CNT=1,PROBE752_WIDTH=1,PROBE752_MU_CNT=1,PROBE753_WIDTH=1,PROBE753_MU_CNT=1,PROBE754_WIDTH=1,PROBE754_MU_CNT=1,PROBE755_WIDTH=1,PROBE755_MU_CNT=1,PROBE756_WIDTH=1,PROBE756_MU_CNT=1,PROBE757_WIDTH=1,PROBE757_MU_CNT=1,PROBE758_WIDTH=1,PROBE758_MU_CNT=1,PROBE759_WIDTH=1,PROBE759_MU_CNT=1,PROBE760_WIDTH=1,PROBE760_MU_CNT=1,PROBE761_WIDTH=1,PROBE761_MU_CNT=1,PROBE762_WIDTH=1,PROBE762_MU_CNT=1,PROBE763_WIDTH=1,PROBE763_MU_CNT=1,PROBE764_WIDTH=1,PROBE764_MU_CNT=1,PROBE765_WIDTH=1,PROBE765_MU_CNT=1,PROBE766_WIDTH=1,PROBE766_MU_CNT=1,PROBE767_WIDTH=1,PROBE767_MU_CNT=1,PROBE768_WIDTH=1,PROBE768_MU_CNT=1,PROBE769_WIDTH=1,PROBE769_MU_CNT=1,PROBE770_WIDTH=1,PROBE770_MU_CNT=1,PROBE771_WIDTH=1,PROBE771_MU_CNT=1,PROBE772_WIDTH=1,PROBE772_MU_CNT=1,PROBE773_WIDTH=1,PROBE773_MU_CNT=1,PROBE774_WIDTH=1,PROBE774_MU_CNT=1,PROBE775_WIDTH=1,PROBE775_MU_CNT=1,PROBE776_WIDTH=1,PROBE776_MU_CNT=1,PROBE777_WIDTH=1,PROBE777_MU_CNT=1,PROBE778_WIDTH=1,PROBE778_MU_CNT=1,PROBE779_WIDTH=1,PROBE779_MU_CNT=1,PROBE780_WIDTH=1,PROBE780_MU_CNT=1,PROBE781_WIDTH=1,PROBE781_MU_CNT=1,PROBE782_WIDTH=1,PROBE782_MU_CNT=1,PROBE783_WIDTH=1,PROBE783_MU_CNT=1,PROBE784_WIDTH=1,PROBE784_MU_CNT=1,PROBE785_WIDTH=1,PROBE785_MU_CNT=1,PROBE786_WIDTH=1,PROBE786_MU_CNT=1,PROBE787_WIDTH=1,PROBE787_MU_CNT=1,PROBE788_WIDTH=1,PROBE788_MU_CNT=1,PROBE789_WIDTH=1,PROBE789_MU_CNT=1,PROBE790_WIDTH=1,PROBE790_MU_CNT=1,PROBE791_WIDTH=1,PROBE791_MU_CNT=1,PROBE792_WIDTH=1,PROBE792_MU_CNT=1,PROBE793_WIDTH=1,PROBE793_MU_CNT=1,PROBE794_WIDTH=1,PROBE794_MU_CNT=1,PROBE795_WIDTH=1,PROBE795_MU_CNT=1,PROBE796_WIDTH=1,PROBE796_MU_CNT=1,PROBE797_WIDTH=1,PROBE797_MU_CNT=1,PROBE798_WIDTH=1,PROBE798_MU_CNT=1,PROBE799_WIDTH=1,PROBE799_MU_CNT=1,PROBE800_WIDTH=1,PROBE800_MU_CNT=1,PROBE801_WIDTH=1,PROBE801_MU_CNT=1,PROBE802_WIDTH=1,PROBE802_MU_CNT=1,PROBE803_WIDTH=1,PROBE803_MU_CNT=1,PROBE804_WIDTH=1,PROBE804_MU_CNT=1,PROBE805_WIDTH=1,PROBE805_MU_CNT=1,PROBE806_WIDTH=1,PROBE806_MU_CNT=1,PROBE807_WIDTH=1,PROBE807_MU_CNT=1,PROBE808_WIDTH=1,PROBE808_MU_CNT=1,PROBE809_WIDTH=1,PROBE809_MU_CNT=1,PROBE810_WIDTH=1,PROBE810_MU_CNT=1,PROBE811_WIDTH=1,PROBE811_MU_CNT=1,PROBE812_WIDTH=1,PROBE812_MU_CNT=1,PROBE813_WIDTH=1,PROBE813_MU_CNT=1,PROBE814_WIDTH=1,PROBE814_MU_CNT=1,PROBE815_WIDTH=1,PROBE815_MU_CNT=1,PROBE816_WIDTH=1,PROBE816_MU_CNT=1,PROBE817_WIDTH=1,PROBE817_MU_CNT=1,PROBE818_WIDTH=1,PROBE818_MU_CNT=1,PROBE819_WIDTH=1,PROBE819_MU_CNT=1,PROBE820_WIDTH=1,PROBE820_MU_CNT=1,PROBE821_WIDTH=1,PROBE821_MU_CNT=1,PROBE822_WIDTH=1,PROBE822_MU_CNT=1,PROBE823_WIDTH=1,PROBE823_MU_CNT=1,PROBE824_WIDTH=1,PROBE824_MU_CNT=1,PROBE825_WIDTH=1,PROBE825_MU_CNT=1,PROBE826_WIDTH=1,PROBE826_MU_CNT=1,PROBE827_WIDTH=1,PROBE827_MU_CNT=1,PROBE828_WIDTH=1,PROBE828_MU_CNT=1,PROBE829_WIDTH=1,PROBE829_MU_CNT=1,PROBE830_WIDTH=1,PROBE830_MU_CNT=1,PROBE831_WIDTH=1,PROBE831_MU_CNT=1,PROBE832_WIDTH=1,PROBE832_MU_CNT=1,PROBE833_WIDTH=1,PROBE833_MU_CNT=1,PROBE834_WIDTH=1,PROBE834_MU_CNT=1,PROBE835_WIDTH=1,PROBE835_MU_CNT=1,PROBE836_WIDTH=1,PROBE836_MU_CNT=1,PROBE837_WIDTH=1,PROBE837_MU_CNT=1,PROBE838_WIDTH=1,PROBE838_MU_CNT=1,PROBE839_WIDTH=1,PROBE839_MU_CNT=1,PROBE840_WIDTH=1,PROBE840_MU_CNT=1,PROBE841_WIDTH=1,PROBE841_MU_CNT=1,PROBE842_WIDTH=1,PROBE842_MU_CNT=1,PROBE843_WIDTH=1,PROBE843_MU_CNT=1,PROBE844_WIDTH=1,PROBE844_MU_CNT=1,PROBE845_WIDTH=1,PROBE845_MU_CNT=1,PROBE846_WIDTH=1,PROBE846_MU_CNT=1,PROBE847_WIDTH=1,PROBE847_MU_CNT=1,PROBE848_WIDTH=1,PROBE848_MU_CNT=1,PROBE849_WIDTH=1,PROBE849_MU_CNT=1,PROBE850_WIDTH=1,PROBE850_MU_CNT=1,PROBE851_WIDTH=1,PROBE851_MU_CNT=1,PROBE852_WIDTH=1,PROBE852_MU_CNT=1,PROBE853_WIDTH=1,PROBE853_MU_CNT=1,PROBE854_WIDTH=1,PROBE854_MU_CNT=1,PROBE855_WIDTH=1,PROBE855_MU_CNT=1,PROBE856_WIDTH=1,PROBE856_MU_CNT=1,PROBE857_WIDTH=1,PROBE857_MU_CNT=1,PROBE858_WIDTH=1,PROBE858_MU_CNT=1,PROBE859_WIDTH=1,PROBE859_MU_CNT=1,PROBE860_WIDTH=1,PROBE860_MU_CNT=1,PROBE861_WIDTH=1,PROBE861_MU_CNT=1,PROBE862_WIDTH=1,PROBE862_MU_CNT=1,PROBE863_WIDTH=1,PROBE863_MU_CNT=1,PROBE864_WIDTH=1,PROBE864_MU_CNT=1,PROBE865_WIDTH=1,PROBE865_MU_CNT=1,PROBE866_WIDTH=1,PROBE866_MU_CNT=1,PROBE867_WIDTH=1,PROBE867_MU_CNT=1,PROBE868_WIDTH=1,PROBE868_MU_CNT=1,PROBE869_WIDTH=1,PROBE869_MU_CNT=1,PROBE870_WIDTH=1,PROBE870_MU_CNT=1,PROBE871_WIDTH=1,PROBE871_MU_CNT=1,PROBE872_WIDTH=1,PROBE872_MU_CNT=1,PROBE873_WIDTH=1,PROBE873_MU_CNT=1,PROBE874_WIDTH=1,PROBE874_MU_CNT=1,PROBE875_WIDTH=1,PROBE875_MU_CNT=1,PROBE876_WIDTH=1,PROBE876_MU_CNT=1,PROBE877_WIDTH=1,PROBE877_MU_CNT=1,PROBE878_WIDTH=1,PROBE878_MU_CNT=1,PROBE879_WIDTH=1,PROBE879_MU_CNT=1,PROBE880_WIDTH=1,PROBE880_MU_CNT=1,PROBE881_WIDTH=1,PROBE881_MU_CNT=1,PROBE882_WIDTH=1,PROBE882_MU_CNT=1,PROBE883_WIDTH=1,PROBE883_MU_CNT=1,PROBE884_WIDTH=1,PROBE884_MU_CNT=1,PROBE885_WIDTH=1,PROBE885_MU_CNT=1,PROBE886_WIDTH=1,PROBE886_MU_CNT=1,PROBE887_WIDTH=1,PROBE887_MU_CNT=1,PROBE888_WIDTH=1,PROBE888_MU_CNT=1,PROBE889_WIDTH=1,PROBE889_MU_CNT=1,PROBE890_WIDTH=1,PROBE890_MU_CNT=1,PROBE891_WIDTH=1,PROBE891_MU_CNT=1,PROBE892_WIDTH=1,PROBE892_MU_CNT=1,PROBE893_WIDTH=1,PROBE893_MU_CNT=1,PROBE894_WIDTH=1,PROBE894_MU_CNT=1,PROBE895_WIDTH=1,PROBE895_MU_CNT=1,PROBE896_WIDTH=1,PROBE896_MU_CNT=1,PROBE897_WIDTH=1,PROBE897_MU_CNT=1,PROBE898_WIDTH=1,PROBE898_MU_CNT=1,PROBE899_WIDTH=1,PROBE899_MU_CNT=1,PROBE900_WIDTH=1,PROBE900_MU_CNT=1,PROBE901_WIDTH=1,PROBE901_MU_CNT=1,PROBE902_WIDTH=1,PROBE902_MU_CNT=1,PROBE903_WIDTH=1,PROBE903_MU_CNT=1,PROBE904_WIDTH=1,PROBE904_MU_CNT=1,PROBE905_WIDTH=1,PROBE905_MU_CNT=1,PROBE906_WIDTH=1,PROBE906_MU_CNT=1,PROBE907_WIDTH=1,PROBE907_MU_CNT=1,PROBE908_WIDTH=1,PROBE908_MU_CNT=1,PROBE909_WIDTH=1,PROBE909_MU_CNT=1,PROBE910_WIDTH=1,PROBE910_MU_CNT=1,PROBE911_WIDTH=1,PROBE911_MU_CNT=1,PROBE912_WIDTH=1,PROBE912_MU_CNT=1,PROBE913_WIDTH=1,PROBE913_MU_CNT=1,PROBE914_WIDTH=1,PROBE914_MU_CNT=1,PROBE915_WIDTH=1,PROBE915_MU_CNT=1,PROBE916_WIDTH=1,PROBE916_MU_CNT=1,PROBE917_WIDTH=1,PROBE917_MU_CNT=1,PROBE918_WIDTH=1,PROBE918_MU_CNT=1,PROBE919_WIDTH=1,PROBE919_MU_CNT=1,PROBE920_WIDTH=1,PROBE920_MU_CNT=1,PROBE921_WIDTH=1,PROBE921_MU_CNT=1,PROBE922_WIDTH=1,PROBE922_MU_CNT=1,PROBE923_WIDTH=1,PROBE923_MU_CNT=1,PROBE924_WIDTH=1,PROBE924_MU_CNT=1,PROBE925_WIDTH=1,PROBE925_MU_CNT=1,PROBE926_WIDTH=1,PROBE926_MU_CNT=1,PROBE927_WIDTH=1,PROBE927_MU_CNT=1,PROBE928_WIDTH=1,PROBE928_MU_CNT=1,PROBE929_WIDTH=1,PROBE929_MU_CNT=1,PROBE930_WIDTH=1,PROBE930_MU_CNT=1,PROBE931_WIDTH=1,PROBE931_MU_CNT=1,PROBE932_WIDTH=1,PROBE932_MU_CNT=1,PROBE933_WIDTH=1,PROBE933_MU_CNT=1,PROBE934_WIDTH=1,PROBE934_MU_CNT=1,PROBE935_WIDTH=1,PROBE935_MU_CNT=1,PROBE936_WIDTH=1,PROBE936_MU_CNT=1,PROBE937_WIDTH=1,PROBE937_MU_CNT=1,PROBE938_WIDTH=1,PROBE938_MU_CNT=1,PROBE939_WIDTH=1,PROBE939_MU_CNT=1,PROBE940_WIDTH=1,PROBE940_MU_CNT=1,PROBE941_WIDTH=1,PROBE941_MU_CNT=1,PROBE942_WIDTH=1,PROBE942_MU_CNT=1,PROBE943_WIDTH=1,PROBE943_MU_CNT=1,PROBE944_WIDTH=1,PROBE944_MU_CNT=1,PROBE945_WIDTH=1,PROBE945_MU_CNT=1,PROBE946_WIDTH=1,PROBE946_MU_CNT=1,PROBE947_WIDTH=1,PROBE947_MU_CNT=1,PROBE948_WIDTH=1,PROBE948_MU_CNT=1,PROBE949_WIDTH=1,PROBE949_MU_CNT=1,PROBE950_WIDTH=1,PROBE950_MU_CNT=1,PROBE951_WIDTH=1,PROBE951_MU_CNT=1,PROBE952_WIDTH=1,PROBE952_MU_CNT=1,PROBE953_WIDTH=1,PROBE953_MU_CNT=1,PROBE954_WIDTH=1,PROBE954_MU_CNT=1,PROBE955_WIDTH=1,PROBE955_MU_CNT=1,PROBE956_WIDTH=1,PROBE956_MU_CNT=1,PROBE957_WIDTH=1,PROBE957_MU_CNT=1,PROBE958_WIDTH=1,PROBE958_MU_CNT=1,PROBE959_WIDTH=1,PROBE959_MU_CNT=1,PROBE960_WIDTH=1,PROBE960_MU_CNT=1,PROBE961_WIDTH=1,PROBE961_MU_CNT=1,PROBE962_WIDTH=1,PROBE962_MU_CNT=1,PROBE963_WIDTH=1,PROBE963_MU_CNT=1,PROBE964_WIDTH=1,PROBE964_MU_CNT=1,PROBE965_WIDTH=1,PROBE965_MU_CNT=1,PROBE966_WIDTH=1,PROBE966_MU_CNT=1,PROBE967_WIDTH=1,PROBE967_MU_CNT=1,PROBE968_WIDTH=1,PROBE968_MU_CNT=1,PROBE969_WIDTH=1,PROBE969_MU_CNT=1,PROBE970_WIDTH=1,PROBE970_MU_CNT=1,PROBE971_WIDTH=1,PROBE971_MU_CNT=1,PROBE972_WIDTH=1,PROBE972_MU_CNT=1,PROBE973_WIDTH=1,PROBE973_MU_CNT=1,PROBE974_WIDTH=1,PROBE974_MU_CNT=1,PROBE975_WIDTH=1,PROBE975_MU_CNT=1,PROBE976_WIDTH=1,PROBE976_MU_CNT=1,PROBE977_WIDTH=1,PROBE977_MU_CNT=1,PROBE978_WIDTH=1,PROBE978_MU_CNT=1,PROBE979_WIDTH=1,PROBE979_MU_CNT=1,PROBE980_WIDTH=1,PROBE980_MU_CNT=1,PROBE981_WIDTH=1,PROBE981_MU_CNT=1,PROBE982_WIDTH=1,PROBE982_MU_CNT=1,PROBE983_WIDTH=1,PROBE983_MU_CNT=1,PROBE984_WIDTH=1,PROBE984_MU_CNT=1,PROBE985_WIDTH=1,PROBE985_MU_CNT=1,PROBE986_WIDTH=1,PROBE986_MU_CNT=1,PROBE987_WIDTH=1,PROBE987_MU_CNT=1,PROBE988_WIDTH=1,PROBE988_MU_CNT=1,PROBE989_WIDTH=1,PROBE989_MU_CNT=1,PROBE990_WIDTH=1,PROBE990_MU_CNT=1,PROBE991_WIDTH=1,PROBE991_MU_CNT=1,PROBE992_WIDTH=1,PROBE992_MU_CNT=1,PROBE993_WIDTH=1,PROBE993_MU_CNT=1,PROBE994_WIDTH=1,PROBE994_MU_CNT=1,PROBE995_WIDTH=1,PROBE995_MU_CNT=1,PROBE996_WIDTH=1,PROBE996_MU_CNT=1,PROBE997_WIDTH=1,PROBE997_MU_CNT=1,PROBE998_WIDTH=1,PROBE998_MU_CNT=1,PROBE999_WIDTH=1,PROBE999_MU_CNT=1,PROBE1000_WIDTH=1,PROBE1000_MU_CNT=1,PROBE1001_WIDTH=1,PROBE1001_MU_CNT=1,PROBE1002_WIDTH=1,PROBE1002_MU_CNT=1,PROBE1003_WIDTH=1,PROBE1003_MU_CNT=1,PROBE1004_WIDTH=1,PROBE1004_MU_CNT=1,PROBE1005_WIDTH=1,PROBE1005_MU_CNT=1,PROBE1006_WIDTH=1,PROBE1006_MU_CNT=1,PROBE1007_WIDTH=1,PROBE1007_MU_CNT=1,PROBE1008_WIDTH=1,PROBE1008_MU_CNT=1,PROBE1009_WIDTH=1,PROBE1009_MU_CNT=1,PROBE1010_WIDTH=1,PROBE1010_MU_CNT=1,PROBE1011_WIDTH=1,PROBE1011_MU_CNT=1,PROBE1012_WIDTH=1,PROBE1012_MU_CNT=1,PROBE1013_WIDTH=1,PROBE1013_MU_CNT=1,PROBE1014_WIDTH=1,PROBE1014_MU_CNT=1,PROBE1015_WIDTH=1,PROBE1015_MU_CNT=1,PROBE1016_WIDTH=1,PROBE1016_MU_CNT=1,PROBE1017_WIDTH=1,PROBE1017_MU_CNT=1,PROBE1018_WIDTH=1,PROBE1018_MU_CNT=1,PROBE1019_WIDTH=1,PROBE1019_MU_CNT=1,PROBE1020_WIDTH=1,PROBE1020_MU_CNT=1,PROBE1021_WIDTH=1,PROBE1021_MU_CNT=1,PROBE1022_WIDTH=1,PROBE1022_MU_CNT=1,PROBE1023_WIDTH=1,PROBE1023_MU_CNT=1 - kintex7 - AXI4 - 1 - 0 - 12 - 1024 - 2013 - 3 - 4 - 0 - 1 - 0 - 0 - 0 - kintex7 - xc7k325t - ffg900 - -2 - C - - VHDL - MIXED - TRUE - TRUE - xilinx.com:kc705:part0:0.9 - TRUE - 2014.3 - 0 - OUT_OF_CONTEXT - - . - . - - - - Index: experimental_jumbo_frames_version/fpga/kc705/kc705_fade_top.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/kc705_fade_top.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/kc705_fade_top.vhd (nonexistent) @@ -1,665 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.pkt_ack_pkg.all; -use work.desc_mgr_pkg.all; - -entity kc705_10g_2 is - - port ( - gtx10g_txn : out std_logic; - gtx10g_txp : out std_logic; - gtx10g_rxn : in std_logic; - gtx10g_rxp : in std_logic; - gtx_refclk_n : in std_logic; - gtx_refclk_p : in std_logic; - --xgmii_txd : in std_logic_vector(63 downto 0); - --xgmii_txc : in std_logic_vector(7 downto 0); - --xgmii_rxd : out std_logic_vector(63 downto 0); - --xgmii_rxc : out std_logic_vector(7 downto 0); - txusrclk_out : out std_logic; - txusrclk2_out : out std_logic; - resetdone : out std_logic; - core_ready : out std_logic; - trig_ack : out std_logic; - led5 : out std_logic; - clk_2 : in std_logic; - start : in std_logic; - rst_p : in std_logic); - -end kc705_10g_2; - -architecture beh1 of kc705_10g_2 is - - signal heart_bit : integer := 0; - - signal refclk_p : std_logic := '0'; - signal refclk_n : std_logic := '0'; - signal reset : std_logic := '0'; - signal s_resetdone : std_logic := '0'; - signal core_clk156_out : std_logic := '0'; - signal txp : std_logic := '0'; - signal txn : std_logic := '0'; - signal rxp : std_logic := '0'; - signal rxn : std_logic := '0'; - signal dclk_out : std_logic := '0'; - signal s_txusrclk_out : std_logic := '0'; - signal s_txusrclk2_out : std_logic := '0'; - signal areset_clk156_out : std_logic := '0'; - signal gttxreset_out : std_logic := '0'; - signal gtrxreset_out : std_logic := '0'; - signal txuserrdy_out : std_logic := '0'; - signal reset_counter_done_out : std_logic := '0'; - signal qplllock_out : std_logic := '0'; - signal qplloutclk_out : std_logic := '0'; - signal qplloutrefclk_out : std_logic := '0'; - signal xgmii_txd : std_logic_vector(63 downto 0) := (others => '0'); - signal xgmii_txc : std_logic_vector(7 downto 0) := (others => '0'); - signal xgmii_rxd : std_logic_vector(63 downto 0) := (others => '0'); - signal xgmii_rxc : std_logic_vector(7 downto 0) := (others => '0'); - signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0'); - signal status_vector : std_logic_vector(447 downto 0) := (others => '0'); - signal core_status : std_logic_vector(7 downto 0) := (others => '0'); - signal signal_detect : std_logic := '0'; - signal tx_fault : std_logic := '0'; - signal drp_req : std_logic := '0'; - signal drp_gnt : std_logic := '0'; - signal drp_den_o : std_logic := '0'; - signal drp_dwe_o : std_logic := '0'; - signal drp_daddr_o : std_logic_vector(15 downto 0) := (others => '0'); - signal drp_di_o : std_logic_vector(15 downto 0) := (others => '0'); - signal drp_drdy_o : std_logic := '0'; - signal drp_drpdo_o : std_logic_vector(15 downto 0) := (others => '0'); - signal drp_den_i : std_logic := '0'; - signal drp_dwe_i : std_logic := '0'; - signal drp_daddr_i : std_logic_vector(15 downto 0) := (others => '0'); - signal drp_di_i : std_logic_vector(15 downto 0) := (others => '0'); - signal drp_drdy_i : std_logic := '0'; - signal drp_drpdo_i : std_logic_vector(15 downto 0) := (others => '0'); - signal tx_disable : std_logic := '0'; - - signal counter : integer := 0; - signal probe2 : std_logic_vector(2 downto 0); - signal trig_in, trig_in_ack : std_logic := '0'; - signal rst_n, rst1, clk1 : std_logic := '0'; - signal hb_led : std_logic := '0'; - signal s_led5 : std_logic := '0'; - - -- Signals associated with the FADE core - signal my_mac : std_logic_vector(47 downto 0); - signal sender : std_logic_vector(47 downto 0); - signal peer_mac : std_logic_vector(47 downto 0); - constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; - signal transm_delay : unsigned(31 downto 0); - signal restart : std_logic; - signal fade_rst_n, fade_rst_del : std_logic := '0'; - signal fade_rst_p : std_logic; - - signal test_dta : unsigned(63 downto 0); - signal dta : std_logic_vector(63 downto 0); - signal s_dta_we, dta_we : std_logic := '0'; - signal dta_ready : std_logic; - signal snd_start : std_logic; - signal flushed : std_logic := '0'; - signal dta_eod : std_logic := '0'; - signal snd_ready : std_logic; - signal clk_user : std_logic; - signal dmem_we : std_logic; - signal dmem_addr : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); - signal dmem_dta : std_logic_vector(63 downto 0); - signal tx_mem_addr : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); - signal tx_mem_data : std_logic_vector(63 downto 0); - signal pkt_number : unsigned(31 downto 0); - signal seq_number : unsigned(15 downto 0) := (others => '0'); - signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); - -- signals related to user commands handling - signal cmd_response_in, cmd_response_out : std_logic_vector(12*8-1 downto 0) := (others => '0'); - signal cmd_start : std_logic := '0'; - signal cmd_run : std_logic := '0'; - signal cmd_retr_s : std_logic := '0'; - signal cmd_ack : std_logic := '0'; - signal cmd_code : std_logic_vector(15 downto 0) := (others => '0'); - signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0'); - signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0'); - - - -- debug signals - signal dbg : std_logic_vector(3 downto 0); - signal rx_crc : std_logic_vector(31 downto 0); - signal rx_cmd : std_logic_vector(31 downto 0); - signal rx_arg : std_logic_vector(31 downto 0); - - signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); - signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; - signal ack_fifo_dbg : pkt_ack; - signal transmit_data, td_del0, td_del1 : std_logic := '0'; - - attribute mark_debug : string; - attribute mark_debug of xgmii_txd : signal is "true"; - attribute mark_debug of xgmii_txc : signal is "true"; - - component ila_1 - port ( - clk : in std_logic; - trig_in : in std_logic; - trig_in_ack : out std_logic; - probe0 : in std_logic_vector(63 downto 0); - probe1 : in std_logic_vector(7 downto 0); - probe2 : in std_logic_vector(2 downto 0); - probe3 : in std_logic_vector(7 downto 0); - probe4 : in std_logic_vector(3 downto 0); - probe5 : in std_logic_vector(31 downto 0); - probe6 : in std_logic_vector(31 downto 0); - probe7 : in std_logic_vector(15 downto 0); - probe8 : in std_logic_vector(31 downto 0); - probe9 : in std_logic_vector(31 downto 0); - probe10 : in std_logic_vector(63 downto 0); - probe11 : in std_logic_vector(7 downto 0) - ); - end component; - -component ten_gig_eth_pcs_pma_0 is - port ( - dclk : in STD_LOGIC; - refclk_p : in STD_LOGIC; - refclk_n : in STD_LOGIC; - sim_speedup_control : in STD_LOGIC; - core_clk156_out : out STD_LOGIC; - qplloutclk_out : out STD_LOGIC; - qplloutrefclk_out : out STD_LOGIC; - qplllock_out : out STD_LOGIC; - txusrclk_out : out STD_LOGIC; - txusrclk2_out : out STD_LOGIC; - areset_clk156_out : out STD_LOGIC; - gttxreset_out : out STD_LOGIC; - gtrxreset_out : out STD_LOGIC; - txuserrdy_out : out STD_LOGIC; - reset_counter_done_out : out STD_LOGIC; - reset : in STD_LOGIC; - gt0_eyescanreset : in STD_LOGIC; - gt0_eyescantrigger : in STD_LOGIC; - gt0_rxcdrhold : in STD_LOGIC; - gt0_txprbsforceerr : in STD_LOGIC; - gt0_txpolarity : in STD_LOGIC; - gt0_rxpolarity : in STD_LOGIC; - gt0_rxrate : in STD_LOGIC_VECTOR (2 downto 0); - gt0_txpmareset : in STD_LOGIC; - gt0_rxpmareset : in STD_LOGIC; - gt0_rxdfelpmreset : in STD_LOGIC; - gt0_txprecursor : in STD_LOGIC_VECTOR (4 downto 0); - gt0_txpostcursor : in STD_LOGIC_VECTOR (4 downto 0); - gt0_txdiffctrl : in STD_LOGIC_VECTOR (3 downto 0); - gt0_rxlpmen : in STD_LOGIC; - gt0_eyescandataerror : out STD_LOGIC; - gt0_txbufstatus : out STD_LOGIC_VECTOR (1 downto 0); - gt0_txresetdone : out STD_LOGIC; - gt0_rxresetdone : out STD_LOGIC; - gt0_rxbufstatus : out STD_LOGIC_VECTOR (2 downto 0); - gt0_rxprbserr : out STD_LOGIC; - gt0_dmonitorout : out STD_LOGIC_VECTOR (7 downto 0); - xgmii_txd : in STD_LOGIC_VECTOR (63 downto 0); - xgmii_txc : in STD_LOGIC_VECTOR (7 downto 0); - xgmii_rxd : out STD_LOGIC_VECTOR (63 downto 0); - xgmii_rxc : out STD_LOGIC_VECTOR (7 downto 0); - txp : out STD_LOGIC; - txn : out STD_LOGIC; - rxp : in STD_LOGIC; - rxn : in STD_LOGIC; - configuration_vector : in STD_LOGIC_VECTOR (535 downto 0); - status_vector : out STD_LOGIC_VECTOR (447 downto 0); - core_status : out STD_LOGIC_VECTOR (7 downto 0); - resetdone : out STD_LOGIC; - signal_detect : in STD_LOGIC; - tx_fault : in STD_LOGIC; - drp_req : out STD_LOGIC; - drp_gnt : in STD_LOGIC; - drp_den_o : out STD_LOGIC; - drp_dwe_o : out STD_LOGIC; - drp_daddr_o : out STD_LOGIC_VECTOR (15 downto 0); - drp_di_o : out STD_LOGIC_VECTOR (15 downto 0); - drp_drdy_i : in STD_LOGIC; - drp_drpdo_i : in STD_LOGIC_VECTOR (15 downto 0); - drp_den_i : in STD_LOGIC; - drp_dwe_i : in STD_LOGIC; - drp_daddr_i : in STD_LOGIC_VECTOR (15 downto 0); - drp_di_i : in STD_LOGIC_VECTOR (15 downto 0); - drp_drdy_o : out STD_LOGIC; - drp_drpdo_o : out STD_LOGIC_VECTOR (15 downto 0); - pma_pmd_type : in STD_LOGIC_VECTOR (2 downto 0); - tx_disable : out STD_LOGIC); -end component ten_gig_eth_pcs_pma_0; - - component eth_receiver is - port ( - peer_mac : out std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - transmit_data : out std_logic; - restart : out std_logic; - ack_fifo_full : in std_logic; - ack_fifo_wr_en : out std_logic; - ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); - clk : in std_logic; - rst_n : in std_logic; - dbg : out std_logic_vector(3 downto 0); - crc : out std_logic_vector(31 downto 0); - cmd : out std_logic_vector(31 downto 0); - arg : out std_logic_vector(31 downto 0); - Rx_Clk : in std_logic; - RxC : in std_logic_vector(7 downto 0); - RxD : in std_logic_vector(63 downto 0)); - end component eth_receiver; - - component eth_sender is - port ( - peer_mac : in std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - pkt_number : in unsigned(31 downto 0); - seq_number : in unsigned(15 downto 0); - transm_delay : in unsigned(31 downto 0); - clk : in std_logic; - rst_n : in std_logic; - ready : out std_logic; - flushed : in std_logic; - start : in std_logic; - cmd_start : in std_logic; - tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); - tx_mem_data : in std_logic_vector(63 downto 0); - cmd_response : in std_logic_vector(12*8-1 downto 0); - Tx_Clk : in std_logic; - TxC : out std_logic_vector(7 downto 0); - TxD : out std_logic_vector(63 downto 0)); - end component eth_sender; - - component dp_ram_scl - generic ( - DATA_WIDTH : integer; - ADDR_WIDTH : integer); - port ( - clk_a : in std_logic; - we_a : in std_logic; - addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); - data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); - q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); - clk_b : in std_logic; - we_b : in std_logic; - addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); - data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); - q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); - end component; - - component ack_fifo - port ( - rst : in std_logic; - wr_clk : in std_logic; - rd_clk : in std_logic; - din : in std_logic_vector(pkt_ack_width-1 downto 0); - wr_en : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(pkt_ack_width-1 downto 0); - full : out std_logic; - empty : out std_logic); - end component; - - component cmd_proc is - port ( - cmd_code : in std_logic_vector(15 downto 0); - cmd_seq : in std_logic_vector(15 downto 0); - cmd_arg : in std_logic_vector(31 downto 0); - cmd_run : in std_logic; - cmd_ack : out std_logic; - cmd_response : out std_logic_vector(8*12-1 downto 0); - clk : in std_logic; - rst_p : in std_logic); - end component cmd_proc; - - component desc_manager is - generic ( - LOG2_N_OF_PKTS : integer; - N_OF_PKTS : integer); - port ( - dta : in std_logic_vector(63 downto 0); - dta_we : in std_logic; - dta_ready : out std_logic; - dta_eod : in std_logic; - pkt_number : out unsigned(31 downto 0); - seq_number : out unsigned(15 downto 0); - cmd_response_out : out std_logic_vector(12*8-1 downto 0); - snd_cmd_start : out std_logic; - snd_start : out std_logic; - snd_ready : in std_logic; - flushed : out std_logic; - dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); - dmem_dta : out std_logic_vector(63 downto 0); - dmem_we : out std_logic; - ack_fifo_empty : in std_logic; - ack_fifo_rd_en : out std_logic; - ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); - cmd_code : out std_logic_vector(15 downto 0); - cmd_seq : out std_logic_vector(15 downto 0); - cmd_arg : out std_logic_vector(31 downto 0); - cmd_run : out std_logic; - cmd_retr_s : out std_logic; - cmd_ack : in std_logic; - cmd_response_in : in std_logic_vector(8*12-1 downto 0); - transmit_data : in std_logic; - transm_delay : out unsigned(31 downto 0); - dbg : out std_logic_vector(3 downto 0); - clk : in std_logic; - rst_n : in std_logic); - end component desc_manager; - -begin -- beh1 - my_mac <= x"de_ad_ba_be_be_ef"; - -- Initialization vector - configuration_vector(33) <= '1'; -- training - configuration_vector(284) <= '1'; -- auto negotiation - - signal_detect <= '1'; -- allow transmission! - - rst_n <= not rst_p; - refclk_n <= gtx_refclk_n; - refclk_p <= gtx_refclk_p; - reset <= not rst_n; - - rx_crc <= std_logic_vector(pkt_number); -- To be removed! - - trig_in <= '1' when xgmii_rxc /= x"ff" else '0'; - - - ila_0_1 : ila_1 - port map ( - clk => clk1, - trig_in => trig_in, - trig_in_ack => trig_ack, - probe0 => xgmii_rxd, - probe1 => xgmii_rxc, - probe2 => probe2, - probe3 => core_status, - probe4 => dbg, - probe5 => rx_crc, - probe6 => std_logic_vector(ack_fifo_dbg.pkt), - probe7 => std_logic_vector(ack_fifo_dbg.cmd), - probe8 => rx_cmd, - probe9 => rx_arg, - probe10 => xgmii_txd, - probe11 => xgmii_txc - ); - - probe2(0) <= cmd_run; - probe2(1) <= cmd_ack; - probe2(2) <= cmd_retr_s; - ack_fifo_dbg <= stlv_to_pkt_ack(ack_fifo_din); - - ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0 - - port map ( - dclk => clk_user, - sim_speedup_control => '0', - refclk_p => refclk_p, - refclk_n => refclk_n, - reset => reset, - resetdone => s_resetdone, - core_clk156_out => core_clk156_out, - txp => gtx10g_txp, - txn => gtx10g_txn, - rxp => gtx10g_rxp, - rxn => gtx10g_rxn, - txusrclk_out => s_txusrclk_out, - txusrclk2_out => s_txusrclk2_out, - areset_clk156_out => areset_clk156_out, - gttxreset_out => gttxreset_out, - gtrxreset_out => gtrxreset_out, - txuserrdy_out => txuserrdy_out, - reset_counter_done_out => reset_counter_done_out, - qplllock_out => qplllock_out, - qplloutclk_out => qplloutclk_out, - qplloutrefclk_out => qplloutrefclk_out, - xgmii_txd => xgmii_txd, - xgmii_txc => xgmii_txc, - xgmii_rxd => xgmii_rxd, - xgmii_rxc => xgmii_rxc, - configuration_vector => configuration_vector, - status_vector => status_vector, - core_status => core_status, - signal_detect => signal_detect, - tx_fault => tx_fault, - drp_req => drp_req, - drp_gnt => drp_gnt, - drp_den_o => drp_den_o, - drp_dwe_o => drp_dwe_o, - drp_daddr_o => drp_daddr_o, - drp_di_o => drp_di_o, - drp_drdy_o => drp_drdy_o, - drp_drpdo_o => drp_drpdo_o, - drp_den_i => drp_den_i, - drp_dwe_i => drp_dwe_i, - drp_daddr_i => drp_daddr_i, - drp_di_i => drp_di_i, - drp_drdy_i => drp_drdy_i, - drp_drpdo_i => drp_drpdo_i, - tx_disable => tx_disable, - pma_pmd_type => "111", - gt0_eyescanreset => '0', - gt0_eyescandataerror => open, - gt0_txbufstatus => open, - gt0_rxbufstatus => open, - gt0_eyescantrigger => '0', - gt0_rxcdrhold => '0', - gt0_txprbsforceerr => '0', - gt0_txpolarity => '1', - gt0_rxpolarity => '1', - gt0_rxprbserr => open, - gt0_txpmareset => '0', - gt0_rxpmareset => '0', - gt0_txresetdone => open, - gt0_rxresetdone => open, - gt0_rxdfelpmreset => '0', - gt0_rxlpmen => '0', - gt0_dmonitorout => open, - gt0_rxrate => (others => '0'), - gt0_txprecursor => (others => '0'), - gt0_txpostcursor => (others => '0'), - gt0_txdiffctrl => "1110" - - ); - - drp_gnt <= drp_req; - drp_den_i <= drp_den_o; - drp_dwe_i <= drp_dwe_o; - drp_daddr_i <= drp_daddr_o; - drp_di_i <= drp_di_o; - drp_drpdo_i <= drp_drpdo_o; - - txusrclk_out <= rst_n; --s_txusrclk_out; - resetdone <= hb_led; --s_resetdone; - - rst1 <= core_status(0); - core_ready <= core_status(0); - clk1 <= core_clk156_out; - clk_user <= core_clk156_out; - - - - p1 : process (clk1, rst_n) - begin -- process p1 - if rst_n = '0' then -- asynchronous reset (active low) - heart_bit <= 0; - elsif clk1'event and clk1 = '1' then -- rising clock edge - if heart_bit < 80000000 then - heart_bit <= heart_bit + 1; - else - heart_bit <= 0; - hb_led <= not hb_led; - end if; - end if; - end process p1; - - --addr_a <= to_integer(unsigned(dmem_addr)); - --addr_b <= to_integer(unsigned(tx_mem_addr)); - - dp_ram_scl_1 : dp_ram_scl - generic map ( - DATA_WIDTH => 64, - ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT) - port map ( - clk_a => clk_user, - we_a => dmem_we, - addr_a => dmem_addr, - data_a => dmem_dta, - q_a => open, - clk_b => clk1, - we_b => '0', - addr_b => tx_mem_addr, - data_b => (others => '0'), - q_b => tx_mem_data); - - desc_manager_1 : desc_manager - generic map ( - LOG2_N_OF_PKTS => LOG2_N_OF_PKTS, - N_OF_PKTS => N_OF_PKTS) - port map ( - dta => dta, - dta_we => dta_we, - dta_eod => dta_eod, - dta_ready => dta_ready, - pkt_number => pkt_number, - seq_number => seq_number, - cmd_response_out => cmd_response_out, - snd_cmd_start => cmd_start, - snd_start => snd_start, - flushed => flushed, - snd_ready => snd_ready, - dmem_addr => dmem_addr, - dmem_dta => dmem_dta, - dmem_we => dmem_we, - ack_fifo_empty => ack_fifo_empty, - ack_fifo_rd_en => ack_fifo_rd_en, - ack_fifo_dout => ack_fifo_dout, - cmd_code => cmd_code, - cmd_seq => cmd_seq, - cmd_arg => cmd_arg, - cmd_run => cmd_run, - cmd_retr_s => cmd_retr_s, - cmd_ack => cmd_ack, - cmd_response_in => cmd_response_in, - transmit_data => transmit_data, - transm_delay => transm_delay, - dbg => dbg, - clk => clk_user, - rst_n => fade_rst_n); - - cmd_proc_1 : cmd_proc - port map ( - cmd_code => cmd_code, - cmd_seq => cmd_seq, - cmd_arg => cmd_arg, - cmd_run => cmd_run, - cmd_ack => cmd_ack, - cmd_response => cmd_response_in, - clk => clk_user, - rst_p => fade_rst_p); - - eth_sender_1 : eth_sender - port map ( - peer_mac => peer_mac, - my_mac => my_mac, - my_ether_type => my_ether_type, - pkt_number => pkt_number, - seq_number => seq_number, - transm_delay => transm_delay, - clk => clk_user, - rst_n => fade_rst_n, - ready => snd_ready, - flushed => flushed, - start => snd_start, - cmd_start => cmd_start, - tx_mem_addr => tx_mem_addr, - tx_mem_data => tx_mem_data, - cmd_response => cmd_response_out, - Tx_Clk => clk1, - TxC => xgmii_txc, - TxD => xgmii_txd); - - eth_receiver_2 : eth_receiver - port map ( - peer_mac => peer_mac, - my_mac => my_mac, - my_ether_type => my_ether_type, - transmit_data => transmit_data, - restart => restart, - ack_fifo_full => ack_fifo_full, - ack_fifo_wr_en => ack_fifo_wr_en, - ack_fifo_din => ack_fifo_din, - clk => clk_user, - rst_n => fade_rst_n, - dbg => open, - cmd => rx_cmd, - arg => rx_arg, - Rx_Clk => clk1, - RxC => xgmii_rxc, - RxD => xgmii_rxd); - - ack_fifo_1 : ack_fifo - port map ( - rst => fade_rst_p, - wr_clk => clk1, - rd_clk => Clk_user, - din => ack_fifo_din, - wr_en => ack_fifo_wr_en, - rd_en => ack_fifo_rd_en, - dout => ack_fifo_dout, - full => ack_fifo_full, - empty => ack_fifo_empty); - - - -- signal generator - - s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; - - dta_we <= s_dta_we; - - dta <= std_logic_vector(test_dta); - - process (Clk_user, rst_n) - begin -- process - if fade_rst_n = '0' then -- asynchronous reset (active low) - test_dta <= (others => '0'); - td_del0 <= '0'; - td_del1 <= '0'; - elsif Clk_user'event and Clk_user = '1' then -- rising clock edge - if s_dta_we = '1' then - test_dta <= test_dta + x"1234567809abcdef"; - end if; - -- Generate the dta_eod pulse after transmit_data - -- goes low - td_del0 <= transmit_data; - td_del1 <= td_del0; - if (td_del1 = '1') and (td_del0 = '0') then - dta_eod <= '1'; - else - dta_eod <= '0'; - end if; - end if; - end process; - - process (Clk_user, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - fade_rst_n <= '0'; - fade_rst_del <= '0'; - elsif Clk_user'event and Clk_user = '1' then -- rising clock edge - if restart = '1' then - fade_rst_n <= '0'; - fade_rst_del <= '0'; - else - fade_rst_del <= '1'; - fade_rst_n <= fade_rst_del; - end if; - end if; - end process; - - fade_rst_p <= not fade_rst_n; - -end beh1; Index: experimental_jumbo_frames_version/fpga/kc705/eth_sender64.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/eth_sender64.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/eth_sender64.vhd (nonexistent) @@ -1,399 +0,0 @@ -------------------------------------------------------------------------------- --- Title : FPGA Ethernet interface - block sending packets via XGMII Phy --- Project : -------------------------------------------------------------------------------- --- File : eth_sender64.vhd --- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) --- License : BSD License --- Company : --- Created : 2012-03-30 --- Last update: 2014-10-12 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: This file implements the state machine, which manages the --- table of packet descriptors, used to resend only not confirmed packets -------------------------------------------------------------------------------- --- Copyright (c) 2012 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2012-03-30 1.0 WZab Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.desc_mgr_pkg.all; -use work.pkg_newcrc32_d64.all; - -entity eth_sender is - - port ( - -- Configuration - peer_mac : in std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - pkt_number : in unsigned(31 downto 0); - seq_number : in unsigned(15 downto 0); - transm_delay : in unsigned(31 downto 0); - -- System interface - clk : in std_logic; - rst_n : in std_logic; - -- Control interface - ready : out std_logic; - flushed : in std_logic; - start : in std_logic; - cmd_start : in std_logic; - -- Data memory interface - tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); - tx_mem_data : in std_logic_vector(63 downto 0); - -- User command response interface - cmd_response : in std_logic_vector(12*8-1 downto 0); - -- TX Phy interface - Tx_Clk : in std_logic; - TxC : out std_logic_vector(7 downto 0); - TxD : out std_logic_vector(63 downto 0) - ); - -end eth_sender; - - -architecture beh1 of eth_sender is - - type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_PREAMB_AND_SOF, WST_SEND_CMD_HEADER, - WST_SEND_CMD_TRAILER, - WST_SEND_HEADER, WST_SEND_DATA, WST_SEND_CRC_AND_EOF, - WST_SEND_COMPLETED); - - type T_ETH_SENDER_REGS is record - state : T_ETH_SENDER_STATE; - ready : std_logic; - count : integer; - word : integer; - mem_addr : unsigned (LOG2_NWRDS_IN_PKT-1 downto 0); - crc32 : std_logic_vector(31 downto 0); - end record; - - constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := ( - state => WST_IDLE, - ready => '1', - count => 0, - word => 0, - mem_addr => (others => '0'), - crc32 => (others => '0') - ) ; - - signal r, r_n : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI; - - type T_ETH_SENDER_COMB is record - TxD : std_logic_vector(63 downto 0); - TxC : std_logic_vector(7 downto 0); - mem_addr : unsigned(LOG2_NWRDS_IN_PKT-1 downto 0); - end record; - - constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := ( - TxD => x"07_07_07_07_07_07_07_07", - TxC => (others => '1'), - mem_addr => (others => '0') - ); - - signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT; - - signal s_header : std_logic_vector(8*40-1 downto 0) := (others => '0'); - constant HEADER_LEN : integer := 5; -- 5 words, 8 bytes each - signal s_cmd_header : std_logic_vector(8*32-1 downto 0) := (others => '0'); - constant CMD_HEADER_LEN : integer := 4; -- 4 words, 8 bytes each - - signal cmd_only : std_logic := '0'; - - -- The function select_8bytes changes order of bytes, ensuring - -- that the MSB is transmitted first... - - function select_8bytes ( - constant vec : std_logic_vector; - constant chunk_num : integer) - return std_logic_vector is - variable byte_ofs : integer; - variable chunk_ofs : integer; - variable v_bytes : std_logic_vector(63 downto 0); - begin - chunk_ofs := chunk_num*64; - -- first select byte - for byte_num in 0 to 7 loop - byte_ofs := byte_num * 8; - v_bytes(byte_ofs+7 downto byte_ofs) := vec(vec'left-chunk_ofs-byte_ofs downto vec'left-chunk_ofs-byte_ofs-7); - end loop; -- byte_num - return v_bytes; - end select_8bytes; - - - function rev(a : in std_logic_vector) - return std_logic_vector is - variable result : std_logic_vector(a'range); - alias aa : std_logic_vector(a'reverse_range) is a; - begin - for i in aa'range loop - result(i) := aa(i); - end loop; - return result; - end; -- function reverse_any_bus - - signal tx_rst_n, tx_rst_n_0, tx_rst_n_1 : std_logic := '0'; - signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; - - signal start_0, tx_start, tx_start_1, tx_start_0 : std_logic := '0'; - signal tx_ready, ready_0, ready_1 : std_logic := '0'; - - type T_STATE1 is (ST1_IDLE, ST1_WAIT_NOT_READY, ST1_WAIT_NOT_START, - ST1_WAIT_READY); - signal state1 : T_STATE1; - - type T_STATE2 is (ST2_IDLE, ST2_WAIT_NOT_READY, ST2_WAIT_READY); - signal state2 : T_STATE2; - - signal dta_packet_type : std_logic_vector(15 downto 0) := (others => '0'); - -begin -- beh1 - - dta_packet_type <= x"a5a5" when flushed = '0' else x"a5a6"; - -- Headers should contain n*8 bytes - -- Data packet header - s_header <= peer_mac & my_mac & my_ether_type & x"0100" & - dta_packet_type & std_logic_vector(seq_number(15 downto 0)) & - std_logic_vector(pkt_number) & - std_logic_vector(transm_delay) & cmd_response; - -- Command response packet header - we have unused 16 bits in the response packet... - s_cmd_header <= peer_mac & my_mac & my_ether_type & x"0100" & - x"a55a" & x"0000" & cmd_response; - - -- Connection of the signals - - -- The memory address is built from the packet number (6 bits) and word - -- number (8 bits) - tx_mem_addr <= std_logic_vector(pkt_number(LOG2_N_OF_PKTS-1 downto 0)) & std_logic_vector(c.mem_addr); - - -- Main state machine used to send the packet - -- W calej maszynie trzeba jeszcze dodac obsluge kolizji!!! - -- Oprocz tego trzeba przeanalizowac poprawnosc przejsc miedzy domenami zegara - - - snd1 : process (Tx_Clk, tx_rst_n) - begin - if tx_rst_n = '0' then -- asynchronous reset (active low) - r <= ETH_SENDER_REGS_INI; - TxD <= x"07_07_07_07_07_07_07_07"; - TxC <= (others => '1'); - elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge - r <= r_n; - -- To minimize glitches and propagation delay, let's add pipeline register - TxC <= c.TxC; - TxD <= c.TxD; - end if; - end process snd1; -- snd1 - - snd2 : process (r, s_header, tx_mem_data, tx_start) - variable v_TxD : std_logic_vector(63 downto 0); - begin -- process snd1 - -- default values - c <= ETH_SENDER_COMB_DEFAULT; - r_n <= r; - case r.state is - when WST_IDLE => - c.TxD <= x"07_07_07_07_07_07_07_07"; - c.TxC <= "11111111"; - r_n.ready <= '1'; - if tx_start = '1' then - r_n.ready <= '0'; - r_n.state <= WST_SEND_PREAMB_AND_SOF; - r_n.count <= 7; - end if; - when WST_SEND_PREAMB_AND_SOF => - -- Collision detection should be added? - c.TxD <= x"d5_55_55_55_55_55_55_fb"; - c.TxC <= "00000001"; - -- Prepare for sending of header - r_n.crc32 <= (others => '1'); - if cmd_only = '1' then - r_n.state <= WST_SEND_CMD_HEADER; - else - r_n.state <= WST_SEND_HEADER; - end if; - r_n.count <= 0; - when WST_SEND_CMD_HEADER => - v_TxD := select_8bytes(s_cmd_header, r.count); - c.TxD <= v_TxD; - c.TxC <= (others => '0'); - r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); - if r.count < CMD_HEADER_LEN-1 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.word <= 0; - r_n.mem_addr <= (others => '0'); - c.mem_addr <= (others => '0'); - r_n.state <= WST_SEND_CMD_TRAILER; - end if; - when WST_SEND_CMD_TRAILER => - v_TxD := (others => '0'); - c.TxD <= v_TxD; - c.TxC <= (others => '0'); - r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); - if r.count < 8-CMD_HEADER_LEN-1 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.word <= 0; - r_n.mem_addr <= (others => '0'); - c.mem_addr <= (others => '0'); - r_n.state <= WST_SEND_CRC_AND_EOF; - end if; - when WST_SEND_HEADER => - v_TxD := select_8bytes(s_header, r.count); - c.TxD <= v_TxD; - c.TxC <= (others => '0'); - r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); - if r.count < HEADER_LEN-1 then - r_n.count <= r.count + 1; - else - r_n.count <= 0; - r_n.word <= 0; - r_n.mem_addr <= (others => '0'); - c.mem_addr <= (others => '0'); - r_n.state <= WST_SEND_DATA; - end if; - when WST_SEND_DATA => - -- send the data byte by byte - v_TxD := select_8bytes(tx_mem_data, 0); - r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); - c.TxD <= v_TxD; - c.TxC <= (others => '0'); - -- Check, if we have sent all the data - if r.mem_addr < NWRDS_IN_PKT-1 then - r_n.mem_addr <= r.mem_addr + 1; - c.mem_addr <= r.mem_addr + 1; - else - -- We send the CRC - r_n.state <= WST_SEND_CRC_AND_EOF; - end if; - when WST_SEND_CRC_AND_EOF => - -- The CRC should be send starting from the most significant bit, so - -- we don't need to reorder bytes in any way... - -- we only reverse it and complement it - v_TxD := x"07_07_07_fd" & not (rev(r.crc32)); - c.TxD <= v_TxD; - c.TxC <= "11110000"; - r_n.count <= 2; -- generate the IFG - 16 bytes = 2 words - r_n.state <= WST_SEND_COMPLETED; - when WST_SEND_COMPLETED => - c.TxD <= x"07_07_07_07_07_07_07_07"; - c.TxC <= "11111111"; - if r.count > 0 then - r_n.count <= r.count - 1; - else - r_n.ready <= '1'; - r_n.state <= WST_IDLE; - end if; - end case; - end process snd2; - - - -- Synchronization of the reset signal for the Tx_Clk domain - process (Tx_Clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - tx_rst_n_0 <= '0'; - tx_rst_n_1 <= '0'; - tx_rst_n <= '0'; - elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge - tx_rst_n_0 <= rst_n; - tx_rst_n_1 <= tx_rst_n_0; - tx_rst_n <= tx_rst_n_1; - end if; - end process; - - -- Synchronization of signals passing clock domains - -- Signal start is sent from the Clk domain. - -- When it is asserted, we must immediately deassert signal ready, - -- then generate the synchronized start and after internal ready - -- is asserted, we can output it again... - - -- Ustawienie na 1 takt zegara "clk" sygnalu start powinno zainicjowac wysylanie - -- w tym bloku musimy zadbac o stosowne wydluzenie sygnalu start i jego synchronizacje - -- miedzy domenami zegara... - process (clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - ready <= '0'; - ready_1 <= '0'; - ready_0 <= '0'; - cmd_only <= '0'; - state2 <= ST2_IDLE; - elsif clk'event and clk = '1' then -- rising clock edge - ready_1 <= tx_ready; - ready_0 <= ready_1; - case state2 is - when ST2_IDLE => - if start = '1' and ready_0 = '1' then - start_0 <= '1'; - ready <= '0'; - cmd_only <= '0'; - state2 <= ST2_WAIT_NOT_READY; - elsif cmd_start = '1' and ready_0 = '1' then - start_0 <= '1'; - ready <= '0'; - cmd_only <= '1'; - state2 <= ST2_WAIT_NOT_READY; - else - ready <= ready_0; -- Needed to provide correct start! - end if; - when ST2_WAIT_NOT_READY => - if ready_0 = '0' then - start_0 <= '0'; - state2 <= ST2_WAIT_READY; - end if; - when ST2_WAIT_READY => - if ready_0 = '1' then - ready <= '1'; - state2 <= ST2_IDLE; - end if; - when others => null; - end case; - end if; - end process; - - process (Tx_Clk, tx_rst_n) - begin -- process - if tx_rst_n = '0' then -- asynchronous reset (active low) - tx_start <= '0'; - tx_start_0 <= '0'; - state1 <= ST1_IDLE; - tx_ready <= '1'; - elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge - tx_start_0 <= start_0; - tx_start <= tx_start_0; - case state1 is - when ST1_IDLE => - if tx_start = '1' then - tx_ready <= '0'; -- this should cause tx_start to go low - state1 <= ST1_WAIT_NOT_READY; - end if; - when ST1_WAIT_NOT_READY => - if r.ready = '0' then - state1 <= ST1_WAIT_NOT_START; - end if; - when ST1_WAIT_NOT_START => - if tx_start = '0' then - state1 <= ST1_WAIT_READY; - end if; - when ST1_WAIT_READY => - if r.ready = '1' then - tx_ready <= '1'; - state1 <= ST1_IDLE; - end if; - when others => null; - end case; - end if; - end process; - -end beh1; Index: experimental_jumbo_frames_version/fpga/kc705/eth_receiver64.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/eth_receiver64.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/eth_receiver64.vhd (nonexistent) @@ -1,413 +0,0 @@ -------------------------------------------------------------------------------- --- Title : FPGA Ethernet interface - block receiving packets from MII PHY --- Project : -------------------------------------------------------------------------------- --- File : eth_receiver4.vhd --- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) --- License : BSD License --- Company : --- Created : 2012-03-30 --- Last update: 2014-10-12 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: This file implements the state machine, responsible for --- reception of packets and passing them to the acknowledgements and commands --- FIFO -------------------------------------------------------------------------------- --- Copyright (c) 2012 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2012-03-30 1.0 WZab Created -------------------------------------------------------------------------------- - --- Uwaga! Tu mamy rzeczywiste problemy z obsluga odebranych pakietow! --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library work; -use work.desc_mgr_pkg.all; -use work.pkt_ack_pkg.all; -use work.pkg_newcrc32_d64.all; -use work.pkg_newcrc32_d32.all; -use work.pkg_newcrc32_d16.all; - - -entity eth_receiver is - - port ( - -- Configuration - peer_mac : out std_logic_vector(47 downto 0); - my_mac : in std_logic_vector(47 downto 0); - my_ether_type : in std_logic_vector(15 downto 0); - transmit_data : out std_logic; - restart : out std_logic; - -- ACK FIFO interface - ack_fifo_full : in std_logic; - ack_fifo_wr_en : out std_logic; - ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); - -- System interface - clk : in std_logic; - rst_n : in std_logic; - dbg : out std_logic_vector(3 downto 0); - cmd : out std_logic_vector(31 downto 0); - arg : out std_logic_vector(31 downto 0); - crc : out std_logic_vector(31 downto 0); - -- MAC interface - Rx_Clk : in std_logic; - RxC : in std_logic_vector(7 downto 0); - RxD : in std_logic_vector(63 downto 0) - ); - -end eth_receiver; - - -architecture beh1 of eth_receiver is - - type T_STATE is (ST_RCV_IDLE, ST_RCV_PREAMB, ST_CHECK_PREAMB, - ST_RCV_HEADER1, ST_RCV_HEADER2, ST_RCV_CMD, - ST_RCV_WAIT_IDLE, ST_RCV_ARGS, ST_RCV_PROCESS, ST_RCV_UPDATE, - ST_RCV_TRAILER); - - - - function rev(a : in std_logic_vector) - return std_logic_vector is - variable result : std_logic_vector(a'range); - alias aa : std_logic_vector(a'reverse_range) is a; - begin - for i in aa'range loop - result(i) := aa(i); - end loop; - return result; - end; -- function reverse_any_bus - - constant C_PROTO_ID : std_logic_vector(31 downto 0) := x"fade0100"; - - type T_RCV_REGS is record - state : T_STATE; - swap_lanes : std_logic; - transmit_data : std_logic; - restart : std_logic; - update_flag : std_logic; - count : integer; - dbg : std_logic_vector(3 downto 0); - crc32 : std_logic_vector(31 downto 0); - cmd : std_logic_vector(31 downto 0); - arg : std_logic_vector(31 downto 0); - mac_addr : std_logic_vector(47 downto 0); - peer_mac : std_logic_vector(47 downto 0); - end record; - - constant RCV_REGS_INI : T_RCV_REGS := ( - state => ST_RCV_IDLE, - swap_lanes => '0', - transmit_data => '0', - restart => '0', - update_flag => '0', - count => 0, - dbg => (others => '0'), - crc32 => (others => '0'), - cmd => (others => '0'), - arg => (others => '0'), - mac_addr => (others => '0'), - peer_mac => (others => '0') - ); - - signal r, r_n : T_RCV_REGS := RCV_REGS_INI; - - type T_RCV_COMB is record - ack_fifo_wr_en : std_logic; - Rx_mac_rd : std_logic; - ack_fifo_din : std_logic_vector(pkt_ack_width-1 downto 0); - restart : std_logic; - end record; - - constant RCV_COMB_DEFAULT : T_RCV_COMB := ( - ack_fifo_wr_en => '0', - Rx_mac_rd => '0', - ack_fifo_din => (others => '0'), - restart => '0' - ); - - signal c : T_RCV_COMB := RCV_COMB_DEFAULT; - - signal rxd_sw, rxd_del : std_logic_vector(63 downto 0); - signal rxc_sw, rxc_del : std_logic_vector(7 downto 0); - - signal rx_rst_n, rx_rst_n_0, rx_rst_n_1 : std_logic := '0'; - signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; - -begin -- beh1 - - ack_fifo_din <= c.ack_fifo_din; - ack_fifo_wr_en <= c.ack_fifo_wr_en; - - --dbg <= r.dbg; - crc <= r.crc32; - cmd <= r.cmd; - arg <= r.arg; - -- Lane switcher processes - lsw_c1 : process (RxC, RxC(3 downto 0), RxC_del(7 downto 4), RxD, - RxD(31 downto 0), RxD_del(63 downto 32), r.swap_lanes) is - begin -- process lsw_c1 - if r.swap_lanes = '1' then - RxD_Sw(63 downto 32) <= RxD(31 downto 0); - RxD_Sw(31 downto 0) <= RxD_del(63 downto 32); - RxC_Sw(7 downto 4) <= RxC(3 downto 0); - RxC_Sw(3 downto 0) <= RxC_del(7 downto 4); - else - RxD_Sw <= RxD; - RxC_Sw <= RxC; - end if; - end process lsw_c1; - - process (Rx_Clk, rx_rst_n) is - begin -- process - if rx_rst_n = '0' then -- asynchronous reset (active low) - RxD_del <= (others => '0'); - RxC_del <= (others => '0'); - elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge - RxD_del <= RxD; - RxC_del <= RxC; - end if; - end process; - - -- Reading of ethernet data - rdp1 : process (Rx_Clk, rx_rst_n) - begin -- process rdp1 - if rx_rst_n = '0' then -- asynchronous reset (active low) - r <= RCV_REGS_INI; - elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge - r <= r_n; - end if; - end process rdp1; - - rdp2 : process (RxC, RxC_Sw, RxD, RxD_Sw, ack_fifo_full, my_ether_type, - my_mac, r, r.arg(15 downto 10), r.arg(31 downto 16), - r.cmd(15 downto 0), r.cmd(31 downto 16), r.crc32, r.dbg(0), - r.dbg(1), r.dbg(2), r.dbg(3), r.mac_addr, r.state, - r.update_flag) - - variable ack_pkt_in : pkt_ack; - variable v_mac_addr : std_logic_vector(47 downto 0); - variable v_cmd, v_arg : std_logic_vector(31 downto 0); - variable v_crc : std_logic_vector(31 downto 0); - variable v_proto : std_logic_vector(31 downto 0); - - begin -- process - c <= RCV_COMB_DEFAULT; - r_n <= r; - dbg <= "1111"; - case r.state is - when ST_RCV_IDLE => - dbg <= "0000"; - -- We must be prepared to one of two possible events - -- Either we receive the SOF in the 0-th lane (and then we proceed - -- normally) or we receive the SOF in the 4-th lane (and then we have - -- to switch lanes, delaying 4 of them). - if RxC = b"00011111" and RxD = x"55_55_55_fb_07_07_07_07" then - -- shifted lanes - -- switch on the "lane shifter" and go to the state, - -- where we can check the proper preamble after lane switching - r_n.swap_lanes <= '1'; - r_n.state <= ST_CHECK_PREAMB; - elsif RxC = b"00000001" and RxD = x"d5_55_55_55_55_55_55_fb" then - -- normal lanes - r_n.swap_lanes <= '0'; - r_n.crc32 <= (others => '1'); - r_n.state <= ST_RCV_HEADER1; - end if; - when ST_CHECK_PREAMB => - dbg <= "0001"; - if RxC_Sw = b"00000001" and RxD_Sw = x"d5_55_55_55_55_55_55_fb" then - r_n.crc32 <= (others => '1'); - r_n.state <= ST_RCV_HEADER1; - else - -- interrupted preamble reception - r_n.state <= ST_RCV_IDLE; - end if; - when ST_RCV_HEADER1 => - dbg <= "0010"; - if RxC_Sw = b"00000000" then - r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); - -- Change the order of bytes! - for i in 0 to 5 loop - v_mac_addr(47-i*8 downto 40-i*8) := RxD_Sw(i*8+7 downto i*8); - end loop; -- i - if v_mac_addr /= my_mac then - -- This packet is not for us - ignore it! - r_n.state <= ST_RCV_WAIT_IDLE; - else - -- Our packet! - r_n.count <= 0; - -- Read the lower 16 bits of the sender address - -- Again, we have to change the order of bytes! - r_n.mac_addr(39 downto 32) <= RxD_Sw(63 downto 56); - r_n.mac_addr(47 downto 40) <= RxD_Sw(55 downto 48); - r_n.state <= ST_RCV_HEADER2; - end if; - else - -- packet broken? - r_n.state <= ST_RCV_IDLE; - end if; - when ST_RCV_HEADER2 => - dbg <= "0010"; - if RxC_Sw = b"00000000" then - r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); - v_mac_addr := r.mac_addr; - for i in 0 to 3 loop - v_mac_addr(31-i*8 downto 24-i*8) := RxD_Sw(i*8+7 downto i*8); - end loop; -- i - --v_mac_addr(47 downto 16) := RxD_Sw(31 downto 0); - r_n.mac_addr <= v_mac_addr; - -- In the rest of this 64-bit word, we receive the protocol ID - -- and version - for i in 0 to 3 loop - v_proto(i*8+7 downto i*8) := RxD_Sw(63-i*8 downto 56-i*8); - end loop; -- i - -- Check if the proto id is correct - if v_proto = C_PROTO_ID then - r_n.state <= ST_RCV_CMD; - else - r_n.state <= ST_RCV_IDLE; - end if; - else - -- packet broken? - r_n.state <= ST_RCV_IDLE; - end if; - when ST_RCV_CMD => - if RxC_Sw = b"0000_0000" then - r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); - -- Copy the command, changing order of bytes! - for i in 0 to 3 loop - r_n.cmd(i*8+7 downto i*8) <= RxD_Sw(31-i*8 downto 24-i*8); - end loop; -- i - -- Copy the argument, changing order of bytes! - for i in 0 to 3 loop - r_n.arg(i*8+7 downto i*8) <= RxD_Sw(63-i*8 downto 56-i*8); - end loop; -- i - r_n.state <= ST_RCV_TRAILER; - -- Currently we ignore rest of the packet! - else - -- packet broken? - r_n.state <= ST_RCV_IDLE; - end if; - when ST_RCV_TRAILER => - -- No detection of too long frames! - dbg <= "0110"; - if RxC_Sw /= b"0000_0000" then - -- It should be a packet with the checksum - -- The EOF may be on any of 8th positions. - -- To avoid too big combinational functions, - -- we handle it in a few states (but this increases requirements - -- on IFC!) - -- Current implementation assumes fixed length of frames - -- but the optimal one should probably pass received data for further - -- checking, why this machine continues to receive next frame... - if RxC_Sw = b"1111_1100" then - v_crc := r.crc32; - v_crc := newcrc32_d16(RxD_Sw(15 downto 0), v_crc); - r_n.crc32 <= v_crc; - if (RxD_Sw(23 downto 16) = x"fd") and - (v_crc = x"c704dd7b") then - -- Correct packet, go to processing - r_n.peer_mac <= r.mac_addr; - r_n.state <= ST_RCV_PROCESS; - else - -- Wrong CRC or EOF - r_n.state <= ST_RCV_IDLE; - end if; - else - -- Wrong packet - r_n.state <= ST_RCV_IDLE; - end if; - else - -- Ignore received data, only updating the checksum - r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); - end if; - when ST_RCV_PROCESS => - dbg <= "0111"; - case to_integer(unsigned(r.cmd(31 downto 16))) is - -- Handle commands, which require immediate action - when FCMD_START => - r_n.dbg(0) <= not r.dbg(0); - -- Start transmission command - r_n.transmit_data <= '1'; - when FCMD_STOP => - r_n.dbg(1) <= not r.dbg(1); - -- Stop transmission command - r_n.transmit_data <= '0'; - when FCMD_RESET => - r_n.dbg(3) <= not r.dbg(3); - -- Restart the whole block(?) - r_n.restart <= '1'; - when others => - null; - end case; - -- All commands are written to the acknowledge and commands - -- FIFO, so that they will be handled by the descriptor manager - if ack_fifo_full = '0' then - ack_pkt_in.cmd := unsigned(r.cmd(31 downto 16)); - ack_pkt_in.pkt := unsigned(r.arg); - ack_pkt_in.seq := unsigned(r.cmd(15 downto 0)); - c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); - c.ack_fifo_wr_en <= '1'; - end if; - r_n.state <= ST_RCV_UPDATE; - when ST_RCV_UPDATE => - dbg <= "1000"; - r_n.update_flag <= not r.update_flag; - r_n.state <= ST_RCV_IDLE; - when ST_RCV_WAIT_IDLE => - dbg <= "1001"; - if RxC_Sw = b"1111_1111" then - r_n.state <= ST_RCV_IDLE; - end if; - when others => null; - end case; - end process rdp2; - - -- Synchronization of the reset signal for the Rx_Clk domain - process (Rx_Clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - rx_rst_n_0 <= '0'; - rx_rst_n_1 <= '0'; - rx_rst_n <= '0'; - elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge - rx_rst_n_0 <= rst_n; - rx_rst_n_1 <= rx_rst_n_0; - rx_rst_n <= rx_rst_n_1; - end if; - end process; - - - -- Synchronization of output signals between the clock domains - process (clk, rst_n) - begin -- process - if rst_n = '0' then -- asynchronous reset (active low) - peer_mac <= (others => '0'); - transmit_data <= '0'; - restart <= '0'; - update_flag_0 <= '0'; - update_flag_1 <= '0'; - update_flag <= '0'; - elsif clk'event and clk = '1' then -- rising clock edge - -- Synchronization of the update_flag - update_flag_0 <= r.update_flag; - update_flag_1 <= update_flag_0; - update_flag <= update_flag_1; - -- When update flag has changed, rewrite synchronized fields - if update_flag /= update_flag_1 then - peer_mac <= r.peer_mac; - transmit_data <= r.transmit_data; - restart <= r.restart; - end if; - end if; - end process; - -end beh1; Index: experimental_jumbo_frames_version/fpga/kc705/ten_gig_eth_pcs_pma_0.xci =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/ten_gig_eth_pcs_pma_0.xci (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/ten_gig_eth_pcs_pma_0.xci (nonexistent) @@ -1,61 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ten_gig_eth_pcs_pma_0 - - - ten_gig_eth_pcs_pma_0 - false - BASE-R - 64bit - GTHE3 - false - false - false - None - Time_of_day - 1 - true - X0Y0 - clk0 - kintex7 - ten_gig_eth_pcs_pma_0 - false - false - false - false - false - false - 0 - 0 - 32 - ten_gig_eth_pcs_pma_0_gt - X0Y0 - clk0 - kintex7 - xc7k325t - ffg900 - -2 - C - - VHDL - MIXED - TRUE - TRUE - xilinx.com:kc705:part0:0.9 - TRUE - 2014.3 - 0 - OUT_OF_CONTEXT - - . - . - - - - Index: experimental_jumbo_frames_version/fpga/kc705/ack_fifo.xci =================================================================== --- experimental_jumbo_frames_version/fpga/kc705/ack_fifo.xci (revision 21) +++ experimental_jumbo_frames_version/fpga/kc705/ack_fifo.xci (nonexistent) @@ -1,395 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ack_fifo - - - ack_fifo - Independent_Clocks_Block_RAM - 2 - 2 - Native - First_Word_Fall_Through - false - 64 - 512 - 64 - 512 - false - false - true - true - Asynchronous_Reset - 1 - true - 0 - false - false - false - false - Active_High - false - Active_High - false - Active_High - false - Active_High - false - false - false - false - false - 9 - false - 9 - false - 9 - false - 1 - 1 - No_Programmable_Full_Threshold - 511 - 510 - No_Programmable_Empty_Threshold - 4 - 5 - AXI4 - Common_Clock - false - Slave_Interface_Clock_Enable - READ_WRITE - 0 - 32 - 64 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 4 - true - false - false - 1 - false - 1 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - false - Active_High - false - Active_High - false - false - false - false - false - false - false - false - 0 - 0 - 9 - BlankString - 64 - 0 - 64 - 0 - kintex7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 1 - BlankString - 0 - 0 - 0 - 1 - 512x72 - 4 - 5 - 0 - 511 - 510 - 0 - 9 - 512 - 1 - 9 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 9 - 512 - 1 - 9 - 1 - 1 - 1 - 0 - 2 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 32 - 64 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 8 - 1 - 1 - 4 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 512x36 - 1kx36 - 512x36 - 512x36 - 1kx36 - 1kx18 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - 64 - 2 - 32 - 64 - 1 - 16 - 1024 - 16 - 16 - 1024 - 1024 - 4 - 10 - 4 - 4 - 10 - 10 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 0 - 0 - 0 - 0 - 0 - 0 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 0 - 0 - 0 - 0 - 0 - 0 - kintex7 - xc7k325t - ffg900 - -2 - C - - VHDL - MIXED - TRUE - TRUE - xilinx.com:kc705:part0:0.9 - TRUE - 2014.3 - 2 - OUT_OF_CONTEXT - - . - . - - - - Index: experimental_jumbo_frames_version/fpga/gen_crcs.sh =================================================================== --- experimental_jumbo_frames_version/fpga/gen_crcs.sh (revision 21) +++ experimental_jumbo_frames_version/fpga/gen_crcs.sh (nonexistent) @@ -1,5 +0,0 @@ -for i in 8 16 24 32 40 48 56 64; do - fname=pkg_newcrc32_d$i.vhd - ./crc_gen2.py newcrc32_d$i L $i 0 1 2 4 5 7 8 10 11 12 16 22 23 26 32 > $fname -done - Index: experimental_jumbo_frames_version/fpga/pkt_desc_pkg.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/pkt_desc_pkg.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/pkt_desc_pkg.vhd (nonexistent) @@ -1,57 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -package pkt_desc_pkg is - -type pkt_desc is record - pkt : unsigned(31 downto 0); - seq : unsigned(15 downto 0); - valid : std_logic; - confirmed : std_logic; - sent : std_logic; - flushed : std_logic; -end record; - -constant pkt_desc_width : integer := 52; - -function pkt_desc_to_stlv( - constant din : pkt_desc) - return std_logic_vector; - -function stlv_to_pkt_desc( - constant din : std_logic_vector) - return pkt_desc; - -end pkt_desc_pkg; - -package body pkt_desc_pkg is - -function pkt_desc_to_stlv( - constant din : pkt_desc) - return std_logic_vector is - variable res : std_logic_vector(51 downto 0); -begin - res(31 downto 0) := std_logic_vector(din.pkt); - res(47 downto 32) := std_logic_vector(din.seq); - res(48) := din.valid; - res(49) := din.confirmed; - res(50) := din.sent; - res(51) := din.flushed; - return res; -end pkt_desc_to_stlv; - -function stlv_to_pkt_desc( - constant din : std_logic_vector) - return pkt_desc is - variable res : pkt_desc; -begin - res.pkt:=unsigned(din(31 downto 0)); - res.seq:=unsigned(din(47 downto 32)); - res.valid := din(48); - res.confirmed := din(49); - res.sent := din(50); - res.flushed := din(51); - return res; -end stlv_to_pkt_desc; - -end pkt_desc_pkg; Index: experimental_jumbo_frames_version/fpga/desc.rec =================================================================== --- experimental_jumbo_frames_version/fpga/desc.rec (revision 21) +++ experimental_jumbo_frames_version/fpga/desc.rec (nonexistent) @@ -1,14 +0,0 @@ -# This is a record with packet descriptor -record pkt_desc -# Below are fields definitions -# pkt - number of the packet -pkt,unsigned,32 -# sequential number of the packet -seq,unsigned,16 -# Flags -valid,std_logic -confirmed,std_logic -sent,std_logic -flushed,std_logic -end - Index: experimental_jumbo_frames_version/fpga/cmd_proc.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/cmd_proc.vhd (revision 21) +++ experimental_jumbo_frames_version/fpga/cmd_proc.vhd (nonexistent) @@ -1,99 +0,0 @@ -------------------------------------------------------------------------------- --- Title : User command processor --- Project : -------------------------------------------------------------------------------- --- File : cmd_proc.vhd --- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) --- License : BSD License --- Company : --- Created : 2014-10-04 --- Last update: 2014-10-12 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: This block performs the user defined commands --- but also generates responses for some internal commands. --- -------------------------------------------------------------------------------- --- Copyright (c) 2014 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2014-10-04 1.0 WZab Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; -library work; -use work.pkt_ack_pkg.all; -use work.desc_mgr_pkg.all; -use work.pkt_desc_pkg.all; -entity cmd_proc is - - port ( - cmd_code : in std_logic_vector(15 downto 0); - cmd_seq : in std_logic_vector(15 downto 0); - cmd_arg : in std_logic_vector(31 downto 0); - cmd_run : in std_logic; - cmd_ack : out std_logic; - cmd_response : out std_logic_vector(8*12-1 downto 0); - clk : in std_logic; - rst_p : in std_logic - ); - -end entity cmd_proc; - -architecture beh of cmd_proc is - - signal cmd_run_0, cmd_run_1, cmd_run_2 : std_logic := '0'; - signal del_count : integer range 0 to 1000 := 0; - -begin -- architecture beh - - process (clk, rst_p) is - begin -- process - if rst_p = '1' then -- asynchronous reset (active low) - cmd_ack <= '0'; - cmd_run_0 <= '0'; - cmd_run_1 <= '0'; - cmd_run_2 <= '0'; - del_count <= 0; - cmd_response <= (others => '0'); - elsif clk'event and clk = '1' then -- rising clock edge - -- Synchronize cmd_run signals - cmd_run_2 <= cmd_run; - cmd_run_1 <= cmd_run_2; - cmd_run_0 <= cmd_run_1; - -- Detect command strobe - if cmd_run_1 /= cmd_run_0 then - -- Line cmd_run has changed its state, it means that we need - -- to execute a command - if cmd_code(15 downto 8) = x"00" then - -- For internal commands just send response immediately - cmd_response <= cmd_code & cmd_seq & -- This fields should be always - -- sent on the begining of response! - x"00000000" & x"00000000"; - cmd_ack <= cmd_run; - else - -- Now we just simulate it, so let's start delay counter - del_count <= 100; -- execution of command takes 100 ckp - end if; - end if; - -- We simulate execution of the user command, which was triggered by above - -- "if" block - if del_count > 0 then - -- Decrease del_count until it is zero - del_count <= del_count-1; - end if; - if del_count = 1 then - -- Send response to the command: - cmd_response <= cmd_code & cmd_seq & -- This fields should be always - -- sent on the begining of response! - cmd_arg & x"900dbabe"; - cmd_ack <= cmd_run; - end if; - end if; - end process; - -end architecture beh; Index: experimental_jumbo_frames_version/fpga/src/dpram_inf.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/dpram_inf.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/dpram_inf.vhd (revision 22) @@ -0,0 +1,61 @@ +-- A parameterized, inferable, true dual-port, common-clock block RAM in VHDL. +-- Original file was taken from: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ +-- No license information were provided by the original author. +-- Minimal modifications were introduced by me to make it suitable for my FPGA +-- interface. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity dp_ram_scl is + generic ( + DATA_WIDTH : integer := 72; + ADDR_WIDTH : integer := 10 + ); + port ( + -- Port A + clk_a : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + + -- Port B + clk_b : in std_logic; + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0) + ); +end dp_ram_scl; + +architecture rtl of dp_ram_scl is + -- Shared memory + type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); + shared variable mem : mem_type; +begin + +-- Port A + process(clk_a) + begin + if(clk_a'event and clk_a = '1') then + if(we_a = '1') then + mem(conv_integer(addr_a)) := data_a; + end if; + q_a <= mem(conv_integer(addr_a)); + end if; + end process; + +-- Port B + process(clk_b) + begin + if(clk_b'event and clk_b = '1') then + if(we_b = '1') then + mem(conv_integer(addr_b)) := data_b; + end if; + q_b <= mem(conv_integer(addr_b)); + end if; + end process; + +end rtl; Index: experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d32.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d32.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d32.vhd (revision 22) @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +package pkg_newcrc32_d32 is + -- CRC update for 32-bit CRC and 32-bit data (LSB first) + -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] + function newcrc32_d32( + din : std_logic_vector(31 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector; +end pkg_newcrc32_d32; + +package body pkg_newcrc32_d32 is + function newcrc32_d32( + din : std_logic_vector(31 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector is + variable c, n : std_logic_vector(31 downto 0); + variable d : std_logic_vector(31 downto 0); + begin + c := crc; + d := din; + n(0) := c(0) xor c(6) xor c(9) xor c(10) xor c(12) xor c(16) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7) xor d(15) xor d(19) xor d(21) xor d(22) xor d(25) xor d(31); + n(1) := c(0) xor c(1) xor c(6) xor c(7) xor c(9) xor c(11) xor c(12) xor c(13) xor c(16) xor c(17) xor c(24) xor c(27) xor c(28) xor d(3) xor d(4) xor d(7) xor d(14) xor d(15) xor d(18) xor d(19) xor d(20) xor d(22) xor d(24) xor d(25) xor d(30) xor d(31); + n(2) := c(0) xor c(1) xor c(2) xor c(6) xor c(7) xor c(8) xor c(9) xor c(13) xor c(14) xor c(16) xor c(17) xor c(18) xor c(24) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(7) xor d(13) xor d(14) xor d(15) xor d(17) xor d(18) xor d(22) xor d(23) xor d(24) xor d(25) xor d(29) xor d(30) xor d(31); + n(3) := c(1) xor c(2) xor c(3) xor c(7) xor c(8) xor c(9) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(25) xor c(27) xor c(31) xor d(0) xor d(4) xor d(6) xor d(12) xor d(13) xor d(14) xor d(16) xor d(17) xor d(21) xor d(22) xor d(23) xor d(24) xor d(28) xor d(29) xor d(30); + n(4) := c(0) xor c(2) xor c(3) xor c(4) xor c(6) xor c(8) xor c(11) xor c(12) xor c(15) xor c(18) xor c(19) xor c(20) xor c(24) xor c(25) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(6) xor d(7) xor d(11) xor d(12) xor d(13) xor d(16) xor d(19) xor d(20) xor d(23) xor d(25) xor d(27) xor d(28) xor d(29) xor d(31); + n(5) := c(0) xor c(1) xor c(3) xor c(4) xor c(5) xor c(6) xor c(7) xor c(10) xor c(13) xor c(19) xor c(20) xor c(21) xor c(24) xor c(28) xor c(29) xor d(2) xor d(3) xor d(7) xor d(10) xor d(11) xor d(12) xor d(18) xor d(21) xor d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(30) xor d(31); + n(6) := c(1) xor c(2) xor c(4) xor c(5) xor c(6) xor c(7) xor c(8) xor c(11) xor c(14) xor c(20) xor c(21) xor c(22) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(9) xor d(10) xor d(11) xor d(17) xor d(20) xor d(23) xor d(24) xor d(25) xor d(26) xor d(27) xor d(29) xor d(30); + n(7) := c(0) xor c(2) xor c(3) xor c(5) xor c(7) xor c(8) xor c(10) xor c(15) xor c(16) xor c(21) xor c(22) xor c(23) xor c(24) xor c(25) xor c(28) xor c(29) xor d(2) xor d(3) xor d(6) xor d(7) xor d(8) xor d(9) xor d(10) xor d(15) xor d(16) xor d(21) xor d(23) xor d(24) xor d(26) xor d(28) xor d(29) xor d(31); + n(8) := c(0) xor c(1) xor c(3) xor c(4) xor c(8) xor c(10) xor c(11) xor c(12) xor c(17) xor c(22) xor c(23) xor c(28) xor c(31) xor d(0) xor d(3) xor d(8) xor d(9) xor d(14) xor d(19) xor d(20) xor d(21) xor d(23) xor d(27) xor d(28) xor d(30) xor d(31); + n(9) := c(1) xor c(2) xor c(4) xor c(5) xor c(9) xor c(11) xor c(12) xor c(13) xor c(18) xor c(23) xor c(24) xor c(29) xor d(2) xor d(7) xor d(8) xor d(13) xor d(18) xor d(19) xor d(20) xor d(22) xor d(26) xor d(27) xor d(29) xor d(30); + n(10) := c(0) xor c(2) xor c(3) xor c(5) xor c(9) xor c(13) xor c(14) xor c(16) xor c(19) xor c(26) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(5) xor d(12) xor d(15) xor d(17) xor d(18) xor d(22) xor d(26) xor d(28) xor d(29) xor d(31); + n(11) := c(0) xor c(1) xor c(3) xor c(4) xor c(9) xor c(12) xor c(14) xor c(15) xor c(16) xor c(17) xor c(20) xor c(24) xor c(25) xor c(26) xor c(27) xor c(28) xor c(31) xor d(0) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor d(11) xor d(14) xor d(15) xor d(16) xor d(17) xor d(19) xor d(22) xor d(27) xor d(28) xor d(30) xor d(31); + n(12) := c(0) xor c(1) xor c(2) xor c(4) xor c(5) xor c(6) xor c(9) xor c(12) xor c(13) xor c(15) xor c(17) xor c(18) xor c(21) xor c(24) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4) xor d(7) xor d(10) xor d(13) xor d(14) xor d(16) xor d(18) xor d(19) xor d(22) xor d(25) xor d(26) xor d(27) xor d(29) xor d(30) xor d(31); + n(13) := c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(7) xor c(10) xor c(13) xor c(14) xor c(16) xor c(18) xor c(19) xor c(22) xor c(25) xor c(28) xor c(31) xor d(0) xor d(3) xor d(6) xor d(9) xor d(12) xor d(13) xor d(15) xor d(17) xor d(18) xor d(21) xor d(24) xor d(25) xor d(26) xor d(28) xor d(29) xor d(30); + n(14) := c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(8) xor c(11) xor c(14) xor c(15) xor c(17) xor c(19) xor c(20) xor c(23) xor c(26) xor c(29) xor d(2) xor d(5) xor d(8) xor d(11) xor d(12) xor d(14) xor d(16) xor d(17) xor d(20) xor d(23) xor d(24) xor d(25) xor d(27) xor d(28) xor d(29); + n(15) := c(3) xor c(4) xor c(5) xor c(7) xor c(8) xor c(9) xor c(12) xor c(15) xor c(16) xor c(18) xor c(20) xor c(21) xor c(24) xor c(27) xor c(30) xor d(1) xor d(4) xor d(7) xor d(10) xor d(11) xor d(13) xor d(15) xor d(16) xor d(19) xor d(22) xor d(23) xor d(24) xor d(26) xor d(27) xor d(28); + n(16) := c(0) xor c(4) xor c(5) xor c(8) xor c(12) xor c(13) xor c(17) xor c(19) xor c(21) xor c(22) xor c(24) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5) xor d(7) xor d(9) xor d(10) xor d(12) xor d(14) xor d(18) xor d(19) xor d(23) xor d(26) xor d(27) xor d(31); + n(17) := c(1) xor c(5) xor c(6) xor c(9) xor c(13) xor c(14) xor c(18) xor c(20) xor c(22) xor c(23) xor c(25) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4) xor d(6) xor d(8) xor d(9) xor d(11) xor d(13) xor d(17) xor d(18) xor d(22) xor d(25) xor d(26) xor d(30); + n(18) := c(2) xor c(6) xor c(7) xor c(10) xor c(14) xor c(15) xor c(19) xor c(21) xor c(23) xor c(24) xor c(26) xor c(28) xor c(31) xor d(0) xor d(3) xor d(5) xor d(7) xor d(8) xor d(10) xor d(12) xor d(16) xor d(17) xor d(21) xor d(24) xor d(25) xor d(29); + n(19) := c(3) xor c(7) xor c(8) xor c(11) xor c(15) xor c(16) xor c(20) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor d(2) xor d(4) xor d(6) xor d(7) xor d(9) xor d(11) xor d(15) xor d(16) xor d(20) xor d(23) xor d(24) xor d(28); + n(20) := c(4) xor c(8) xor c(9) xor c(12) xor c(16) xor c(17) xor c(21) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor d(1) xor d(3) xor d(5) xor d(6) xor d(8) xor d(10) xor d(14) xor d(15) xor d(19) xor d(22) xor d(23) xor d(27); + n(21) := c(5) xor c(9) xor c(10) xor c(13) xor c(17) xor c(18) xor c(22) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(9) xor d(13) xor d(14) xor d(18) xor d(21) xor d(22) xor d(26); + n(22) := c(0) xor c(9) xor c(11) xor c(12) xor c(14) xor c(16) xor c(18) xor c(19) xor c(23) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(8) xor d(12) xor d(13) xor d(15) xor d(17) xor d(19) xor d(20) xor d(22) xor d(31); + n(23) := c(0) xor c(1) xor c(6) xor c(9) xor c(13) xor c(15) xor c(16) xor c(17) xor c(19) xor c(20) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(11) xor d(12) xor d(14) xor d(15) xor d(16) xor d(18) xor d(22) xor d(25) xor d(30) xor d(31); + n(24) := c(1) xor c(2) xor c(7) xor c(10) xor c(14) xor c(16) xor c(17) xor c(18) xor c(20) xor c(21) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(10) xor d(11) xor d(13) xor d(14) xor d(15) xor d(17) xor d(21) xor d(24) xor d(29) xor d(30); + n(25) := c(2) xor c(3) xor c(8) xor c(11) xor c(15) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14) xor d(16) xor d(20) xor d(23) xor d(28) xor d(29); + n(26) := c(0) xor c(3) xor c(4) xor c(6) xor c(10) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(25) xor c(26) xor c(28) xor c(31) xor d(0) xor d(3) xor d(5) xor d(6) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13) xor d(21) xor d(25) xor d(27) xor d(28) xor d(31); + n(27) := c(1) xor c(4) xor c(5) xor c(7) xor c(11) xor c(19) xor c(20) xor c(21) xor c(23) xor c(24) xor c(25) xor c(26) xor c(27) xor c(29) xor d(2) xor d(4) xor d(5) xor d(6) xor d(7) xor d(8) xor d(10) xor d(11) xor d(12) xor d(20) xor d(24) xor d(26) xor d(27) xor d(30); + n(28) := c(2) xor c(5) xor c(6) xor c(8) xor c(12) xor c(20) xor c(21) xor c(22) xor c(24) xor c(25) xor c(26) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor d(9) xor d(10) xor d(11) xor d(19) xor d(23) xor d(25) xor d(26) xor d(29); + n(29) := c(3) xor c(6) xor c(7) xor c(9) xor c(13) xor c(21) xor c(22) xor c(23) xor c(25) xor c(26) xor c(27) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(8) xor d(9) xor d(10) xor d(18) xor d(22) xor d(24) xor d(25) xor d(28); + n(30) := c(4) xor c(7) xor c(8) xor c(10) xor c(14) xor c(22) xor c(23) xor c(24) xor c(26) xor c(27) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(7) xor d(8) xor d(9) xor d(17) xor d(21) xor d(23) xor d(24) xor d(27); + n(31) := c(5) xor c(8) xor c(9) xor c(11) xor c(15) xor c(23) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(7) xor d(8) xor d(16) xor d(20) xor d(22) xor d(23) xor d(26); + return n; + end newcrc32_d32; +end pkg_newcrc32_d32; + Index: experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d16.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d16.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d16.vhd (revision 22) @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +package pkg_newcrc32_d16 is + -- CRC update for 32-bit CRC and 16-bit data (LSB first) + -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] + function newcrc32_d16( + din : std_logic_vector(15 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector; +end pkg_newcrc32_d16; + +package body pkg_newcrc32_d16 is + function newcrc32_d16( + din : std_logic_vector(15 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector is + variable c, n : std_logic_vector(31 downto 0); + variable d : std_logic_vector(15 downto 0); + begin + c := crc; + d := din; + n(0) := c(16) xor c(22) xor c(25) xor c(26) xor c(28) xor d(3) xor d(5) xor d(6) xor d(9) xor d(15); + n(1) := c(16) xor c(17) xor c(22) xor c(23) xor c(25) xor c(27) xor c(28) xor c(29) xor d(2) xor d(3) xor d(4) xor d(6) xor d(8) xor d(9) xor d(14) xor d(15); + n(2) := c(16) xor c(17) xor c(18) xor c(22) xor c(23) xor c(24) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(7) xor d(8) xor d(9) xor d(13) xor d(14) xor d(15); + n(3) := c(17) xor c(18) xor c(19) xor c(23) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(6) xor d(7) xor d(8) xor d(12) xor d(13) xor d(14); + n(4) := c(16) xor c(18) xor c(19) xor c(20) xor c(22) xor c(24) xor c(27) xor c(28) xor c(31) xor d(0) xor d(3) xor d(4) xor d(7) xor d(9) xor d(11) xor d(12) xor d(13) xor d(15); + n(5) := c(16) xor c(17) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(26) xor c(29) xor d(2) xor d(5) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(14) xor d(15); + n(6) := c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(27) xor c(30) xor d(1) xor d(4) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14); + n(7) := c(16) xor c(18) xor c(19) xor c(21) xor c(23) xor c(24) xor c(26) xor c(31) xor d(0) xor d(5) xor d(7) xor d(8) xor d(10) xor d(12) xor d(13) xor d(15); + n(8) := c(16) xor c(17) xor c(19) xor c(20) xor c(24) xor c(26) xor c(27) xor c(28) xor d(3) xor d(4) xor d(5) xor d(7) xor d(11) xor d(12) xor d(14) xor d(15); + n(9) := c(17) xor c(18) xor c(20) xor c(21) xor c(25) xor c(27) xor c(28) xor c(29) xor d(2) xor d(3) xor d(4) xor d(6) xor d(10) xor d(11) xor d(13) xor d(14); + n(10) := c(16) xor c(18) xor c(19) xor c(21) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(10) xor d(12) xor d(13) xor d(15); + n(11) := c(16) xor c(17) xor c(19) xor c(20) xor c(25) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(6) xor d(11) xor d(12) xor d(14) xor d(15); + n(12) := c(16) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(25) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(6) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14) xor d(15); + n(13) := c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(23) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5) xor d(8) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14); + n(14) := c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13); + n(15) := c(19) xor c(20) xor c(21) xor c(23) xor c(24) xor c(25) xor c(28) xor c(31) xor d(0) xor d(3) xor d(6) xor d(7) xor d(8) xor d(10) xor d(11) xor d(12); + n(16) := c(0) xor c(16) xor c(20) xor c(21) xor c(24) xor c(28) xor c(29) xor d(2) xor d(3) xor d(7) xor d(10) xor d(11) xor d(15); + n(17) := c(1) xor c(17) xor c(21) xor c(22) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6) xor d(9) xor d(10) xor d(14); + n(18) := c(2) xor c(18) xor c(22) xor c(23) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(8) xor d(9) xor d(13); + n(19) := c(3) xor c(19) xor c(23) xor c(24) xor c(27) xor c(31) xor d(0) xor d(4) xor d(7) xor d(8) xor d(12); + n(20) := c(4) xor c(20) xor c(24) xor c(25) xor c(28) xor d(3) xor d(6) xor d(7) xor d(11); + n(21) := c(5) xor c(21) xor c(25) xor c(26) xor c(29) xor d(2) xor d(5) xor d(6) xor d(10); + n(22) := c(6) xor c(16) xor c(25) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(6) xor d(15); + n(23) := c(7) xor c(16) xor c(17) xor c(22) xor c(25) xor c(29) xor c(31) xor d(0) xor d(2) xor d(6) xor d(9) xor d(14) xor d(15); + n(24) := c(8) xor c(17) xor c(18) xor c(23) xor c(26) xor c(30) xor d(1) xor d(5) xor d(8) xor d(13) xor d(14); + n(25) := c(9) xor c(18) xor c(19) xor c(24) xor c(27) xor c(31) xor d(0) xor d(4) xor d(7) xor d(12) xor d(13); + n(26) := c(10) xor c(16) xor c(19) xor c(20) xor c(22) xor c(26) xor d(5) xor d(9) xor d(11) xor d(12) xor d(15); + n(27) := c(11) xor c(17) xor c(20) xor c(21) xor c(23) xor c(27) xor d(4) xor d(8) xor d(10) xor d(11) xor d(14); + n(28) := c(12) xor c(18) xor c(21) xor c(22) xor c(24) xor c(28) xor d(3) xor d(7) xor d(9) xor d(10) xor d(13); + n(29) := c(13) xor c(19) xor c(22) xor c(23) xor c(25) xor c(29) xor d(2) xor d(6) xor d(8) xor d(9) xor d(12); + n(30) := c(14) xor c(20) xor c(23) xor c(24) xor c(26) xor c(30) xor d(1) xor d(5) xor d(7) xor d(8) xor d(11); + n(31) := c(15) xor c(21) xor c(24) xor c(25) xor c(27) xor c(31) xor d(0) xor d(4) xor d(6) xor d(7) xor d(10); + return n; + end newcrc32_d16; +end pkg_newcrc32_d16; + Index: experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d64.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d64.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d64.vhd (revision 22) @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +package pkg_newcrc32_d64 is + -- CRC update for 32-bit CRC and 64-bit data (LSB first) + -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] + function newcrc32_d64( + din : std_logic_vector(63 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector; +end pkg_newcrc32_d64; + +package body pkg_newcrc32_d64 is + function newcrc32_d64( + din : std_logic_vector(63 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector is + variable c, n : std_logic_vector(31 downto 0); + variable d : std_logic_vector(63 downto 0); + begin + c := crc; + d := din; + n(0) := c(0) xor c(2) xor c(5) xor c(12) xor c(13) xor c(15) xor c(16) xor c(18) xor c(21) xor c(22) xor c(23) xor c(26) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(5) xor d(8) xor d(9) xor d(10) xor d(13) xor d(15) xor d(16) xor d(18) xor d(19) xor d(26) xor d(29) xor d(31) xor d(32) xor d(33) xor d(34) xor d(35) xor d(37) xor d(38) xor d(39) xor d(47) xor d(51) xor d(53) xor d(54) xor d(57) xor d(63); + n(1) := c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(12) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(21) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(4) xor d(5) xor d(7) xor d(10) xor d(12) xor d(13) xor d(14) xor d(16) xor d(17) xor d(19) xor d(25) xor d(26) xor d(28) xor d(29) xor d(30) xor d(35) xor d(36) xor d(39) xor d(46) xor d(47) xor d(50) xor d(51) xor d(52) xor d(54) xor d(56) xor d(57) xor d(62) xor d(63); + n(2) := c(0) xor c(3) xor c(4) xor c(5) xor c(6) xor c(7) xor c(12) xor c(19) xor c(20) xor c(21) xor c(23) xor c(25) xor c(26) xor c(27) xor d(4) xor d(5) xor d(6) xor d(8) xor d(10) xor d(11) xor d(12) xor d(19) xor d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(31) xor d(32) xor d(33) xor d(37) xor d(39) xor d(45) xor d(46) xor d(47) xor d(49) xor d(50) xor d(54) xor d(55) xor d(56) xor d(57) xor d(61) xor d(62) xor d(63); + n(3) := c(0) xor c(1) xor c(4) xor c(5) xor c(6) xor c(7) xor c(8) xor c(13) xor c(20) xor c(21) xor c(22) xor c(24) xor c(26) xor c(27) xor c(28) xor d(3) xor d(4) xor d(5) xor d(7) xor d(9) xor d(10) xor d(11) xor d(18) xor d(23) xor d(24) xor d(25) xor d(26) xor d(27) xor d(30) xor d(31) xor d(32) xor d(36) xor d(38) xor d(44) xor d(45) xor d(46) xor d(48) xor d(49) xor d(53) xor d(54) xor d(55) xor d(56) xor d(60) xor d(61) xor d(62); + n(4) := c(1) xor c(6) xor c(7) xor c(8) xor c(9) xor c(12) xor c(13) xor c(14) xor c(15) xor c(16) xor c(18) xor c(25) xor c(26) xor c(27) xor c(31) xor d(0) xor d(4) xor d(5) xor d(6) xor d(13) xor d(15) xor d(16) xor d(17) xor d(18) xor d(19) xor d(22) xor d(23) xor d(24) xor d(25) xor d(30) xor d(32) xor d(33) xor d(34) xor d(38) xor d(39) xor d(43) xor d(44) xor d(45) xor d(48) xor d(51) xor d(52) xor d(55) xor d(57) xor d(59) xor d(60) xor d(61) xor d(63); + n(5) := c(5) xor c(7) xor c(8) xor c(9) xor c(10) xor c(12) xor c(14) xor c(17) xor c(18) xor c(19) xor c(21) xor c(22) xor c(23) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(8) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14) xor d(17) xor d(19) xor d(21) xor d(22) xor d(23) xor d(24) xor d(26) xor d(34) xor d(35) xor d(39) xor d(42) xor d(43) xor d(44) xor d(50) xor d(53) xor d(56) xor d(57) xor d(58) xor d(59) xor d(60) xor d(62) xor d(63); + n(6) := c(6) xor c(8) xor c(9) xor c(10) xor c(11) xor c(13) xor c(15) xor c(18) xor c(19) xor c(20) xor c(22) xor c(23) xor c(24) xor c(28) xor c(30) xor d(1) xor d(3) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13) xor d(16) xor d(18) xor d(20) xor d(21) xor d(22) xor d(23) xor d(25) xor d(33) xor d(34) xor d(38) xor d(41) xor d(42) xor d(43) xor d(49) xor d(52) xor d(55) xor d(56) xor d(57) xor d(58) xor d(59) xor d(61) xor d(62); + n(7) := c(0) xor c(2) xor c(5) xor c(7) xor c(9) xor c(10) xor c(11) xor c(13) xor c(14) xor c(15) xor c(18) xor c(19) xor c(20) xor c(22) xor c(24) xor c(25) xor c(26) xor c(28) xor d(3) xor d(5) xor d(6) xor d(7) xor d(9) xor d(11) xor d(12) xor d(13) xor d(16) xor d(17) xor d(18) xor d(20) xor d(21) xor d(22) xor d(24) xor d(26) xor d(29) xor d(31) xor d(34) xor d(35) xor d(38) xor d(39) xor d(40) xor d(41) xor d(42) xor d(47) xor d(48) xor d(53) xor d(55) xor d(56) xor d(58) xor d(60) xor d(61) xor d(63); + n(8) := c(0) xor c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(8) xor c(10) xor c(11) xor c(13) xor c(14) xor c(18) xor c(19) xor c(20) xor c(22) xor c(25) xor c(27) xor c(28) xor c(31) xor d(0) xor d(3) xor d(4) xor d(6) xor d(9) xor d(11) xor d(12) xor d(13) xor d(17) xor d(18) xor d(20) xor d(21) xor d(23) xor d(25) xor d(26) xor d(28) xor d(29) xor d(30) xor d(31) xor d(32) xor d(35) xor d(40) xor d(41) xor d(46) xor d(51) xor d(52) xor d(53) xor d(55) xor d(59) xor d(60) xor d(62) xor d(63); + n(9) := c(0) xor c(1) xor c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(9) xor c(11) xor c(12) xor c(14) xor c(15) xor c(19) xor c(20) xor c(21) xor c(23) xor c(26) xor c(28) xor c(29) xor d(2) xor d(3) xor d(5) xor d(8) xor d(10) xor d(11) xor d(12) xor d(16) xor d(17) xor d(19) xor d(20) xor d(22) xor d(24) xor d(25) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31) xor d(34) xor d(39) xor d(40) xor d(45) xor d(50) xor d(51) xor d(52) xor d(54) xor d(58) xor d(59) xor d(61) xor d(62); + n(10) := c(0) xor c(1) xor c(3) xor c(4) xor c(7) xor c(8) xor c(10) xor c(18) xor c(20) xor c(23) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(4) xor d(5) xor d(7) xor d(8) xor d(11) xor d(13) xor d(21) xor d(23) xor d(24) xor d(27) xor d(28) xor d(30) xor d(31) xor d(32) xor d(34) xor d(35) xor d(37) xor d(44) xor d(47) xor d(49) xor d(50) xor d(54) xor d(58) xor d(60) xor d(61) xor d(63); + n(11) := c(1) xor c(4) xor c(8) xor c(9) xor c(11) xor c(12) xor c(13) xor c(15) xor c(16) xor c(18) xor c(19) xor c(22) xor c(23) xor c(24) xor c(25) xor c(26) xor c(27) xor d(4) xor d(5) xor d(6) xor d(7) xor d(8) xor d(9) xor d(12) xor d(13) xor d(15) xor d(16) xor d(18) xor d(19) xor d(20) xor d(22) xor d(23) xor d(27) xor d(30) xor d(32) xor d(35) xor d(36) xor d(37) xor d(38) xor d(39) xor d(43) xor d(46) xor d(47) xor d(48) xor d(49) xor d(51) xor d(54) xor d(59) xor d(60) xor d(62) xor d(63); + n(12) := c(9) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(19) xor c(20) xor c(21) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(6) xor d(7) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(16) xor d(17) xor d(21) xor d(22) xor d(32) xor d(33) xor d(36) xor d(39) xor d(42) xor d(45) xor d(46) xor d(48) xor d(50) xor d(51) xor d(54) xor d(57) xor d(58) xor d(59) xor d(61) xor d(62) xor d(63); + n(13) := c(0) xor c(10) xor c(11) xor c(15) xor c(16) xor c(18) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor d(1) xor d(3) xor d(5) xor d(6) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(15) xor d(16) xor d(20) xor d(21) xor d(31) xor d(32) xor d(35) xor d(38) xor d(41) xor d(44) xor d(45) xor d(47) xor d(49) xor d(50) xor d(53) xor d(56) xor d(57) xor d(58) xor d(60) xor d(61) xor d(62); + n(14) := c(0) xor c(1) xor c(11) xor c(12) xor c(16) xor c(17) xor c(19) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(14) xor d(15) xor d(19) xor d(20) xor d(30) xor d(31) xor d(34) xor d(37) xor d(40) xor d(43) xor d(44) xor d(46) xor d(48) xor d(49) xor d(52) xor d(55) xor d(56) xor d(57) xor d(59) xor d(60) xor d(61); + n(15) := c(1) xor c(2) xor c(12) xor c(13) xor c(17) xor c(18) xor c(20) xor c(21) xor c(22) xor c(23) xor c(24) xor c(25) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(6) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14) xor d(18) xor d(19) xor d(29) xor d(30) xor d(33) xor d(36) xor d(39) xor d(42) xor d(43) xor d(45) xor d(47) xor d(48) xor d(51) xor d(54) xor d(55) xor d(56) xor d(58) xor d(59) xor d(60); + n(16) := c(0) xor c(3) xor c(5) xor c(12) xor c(14) xor c(15) xor c(16) xor c(19) xor c(24) xor c(25) xor d(6) xor d(7) xor d(12) xor d(15) xor d(16) xor d(17) xor d(19) xor d(26) xor d(28) xor d(31) xor d(33) xor d(34) xor d(37) xor d(39) xor d(41) xor d(42) xor d(44) xor d(46) xor d(50) xor d(51) xor d(55) xor d(58) xor d(59) xor d(63); + n(17) := c(1) xor c(4) xor c(6) xor c(13) xor c(15) xor c(16) xor c(17) xor c(20) xor c(25) xor c(26) xor d(5) xor d(6) xor d(11) xor d(14) xor d(15) xor d(16) xor d(18) xor d(25) xor d(27) xor d(30) xor d(32) xor d(33) xor d(36) xor d(38) xor d(40) xor d(41) xor d(43) xor d(45) xor d(49) xor d(50) xor d(54) xor d(57) xor d(58) xor d(62); + n(18) := c(0) xor c(2) xor c(5) xor c(7) xor c(14) xor c(16) xor c(17) xor c(18) xor c(21) xor c(26) xor c(27) xor d(4) xor d(5) xor d(10) xor d(13) xor d(14) xor d(15) xor d(17) xor d(24) xor d(26) xor d(29) xor d(31) xor d(32) xor d(35) xor d(37) xor d(39) xor d(40) xor d(42) xor d(44) xor d(48) xor d(49) xor d(53) xor d(56) xor d(57) xor d(61); + n(19) := c(0) xor c(1) xor c(3) xor c(6) xor c(8) xor c(15) xor c(17) xor c(18) xor c(19) xor c(22) xor c(27) xor c(28) xor d(3) xor d(4) xor d(9) xor d(12) xor d(13) xor d(14) xor d(16) xor d(23) xor d(25) xor d(28) xor d(30) xor d(31) xor d(34) xor d(36) xor d(38) xor d(39) xor d(41) xor d(43) xor d(47) xor d(48) xor d(52) xor d(55) xor d(56) xor d(60); + n(20) := c(1) xor c(2) xor c(4) xor c(7) xor c(9) xor c(16) xor c(18) xor c(19) xor c(20) xor c(23) xor c(28) xor c(29) xor d(2) xor d(3) xor d(8) xor d(11) xor d(12) xor d(13) xor d(15) xor d(22) xor d(24) xor d(27) xor d(29) xor d(30) xor d(33) xor d(35) xor d(37) xor d(38) xor d(40) xor d(42) xor d(46) xor d(47) xor d(51) xor d(54) xor d(55) xor d(59); + n(21) := c(2) xor c(3) xor c(5) xor c(8) xor c(10) xor c(17) xor c(19) xor c(20) xor c(21) xor c(24) xor c(29) xor c(30) xor d(1) xor d(2) xor d(7) xor d(10) xor d(11) xor d(12) xor d(14) xor d(21) xor d(23) xor d(26) xor d(28) xor d(29) xor d(32) xor d(34) xor d(36) xor d(37) xor d(39) xor d(41) xor d(45) xor d(46) xor d(50) xor d(53) xor d(54) xor d(58); + n(22) := c(2) xor c(3) xor c(4) xor c(5) xor c(6) xor c(9) xor c(11) xor c(12) xor c(13) xor c(15) xor c(16) xor c(20) xor c(23) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(8) xor d(11) xor d(15) xor d(16) xor d(18) xor d(19) xor d(20) xor d(22) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(32) xor d(34) xor d(36) xor d(37) xor d(39) xor d(40) xor d(44) xor d(45) xor d(47) xor d(49) xor d(51) xor d(52) xor d(54) xor d(63); + n(23) := c(2) xor c(3) xor c(4) xor c(6) xor c(7) xor c(10) xor c(14) xor c(15) xor c(17) xor c(18) xor c(22) xor c(23) xor c(24) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(7) xor d(8) xor d(9) xor d(13) xor d(14) xor d(16) xor d(17) xor d(21) xor d(24) xor d(25) xor d(27) xor d(28) xor d(29) xor d(32) xor d(34) xor d(36) xor d(37) xor d(43) xor d(44) xor d(46) xor d(47) xor d(48) xor d(50) xor d(54) xor d(57) xor d(62) xor d(63); + n(24) := c(0) xor c(3) xor c(4) xor c(5) xor c(7) xor c(8) xor c(11) xor c(15) xor c(16) xor c(18) xor c(19) xor c(23) xor c(24) xor c(25) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(6) xor d(7) xor d(8) xor d(12) xor d(13) xor d(15) xor d(16) xor d(20) xor d(23) xor d(24) xor d(26) xor d(27) xor d(28) xor d(31) xor d(33) xor d(35) xor d(36) xor d(42) xor d(43) xor d(45) xor d(46) xor d(47) xor d(49) xor d(53) xor d(56) xor d(61) xor d(62); + n(25) := c(1) xor c(4) xor c(5) xor c(6) xor c(8) xor c(9) xor c(12) xor c(16) xor c(17) xor c(19) xor c(20) xor c(24) xor c(25) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5) xor d(6) xor d(7) xor d(11) xor d(12) xor d(14) xor d(15) xor d(19) xor d(22) xor d(23) xor d(25) xor d(26) xor d(27) xor d(30) xor d(32) xor d(34) xor d(35) xor d(41) xor d(42) xor d(44) xor d(45) xor d(46) xor d(48) xor d(52) xor d(55) xor d(60) xor d(61); + n(26) := c(6) xor c(7) xor c(9) xor c(10) xor c(12) xor c(15) xor c(16) xor c(17) xor c(20) xor c(22) xor c(23) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(8) xor d(9) xor d(11) xor d(14) xor d(15) xor d(16) xor d(19) xor d(21) xor d(22) xor d(24) xor d(25) xor d(32) xor d(35) xor d(37) xor d(38) xor d(39) xor d(40) xor d(41) xor d(43) xor d(44) xor d(45) xor d(53) xor d(57) xor d(59) xor d(60) xor d(63); + n(27) := c(0) xor c(7) xor c(8) xor c(10) xor c(11) xor c(13) xor c(16) xor c(17) xor c(18) xor c(21) xor c(23) xor c(24) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(7) xor d(8) xor d(10) xor d(13) xor d(14) xor d(15) xor d(18) xor d(20) xor d(21) xor d(23) xor d(24) xor d(31) xor d(34) xor d(36) xor d(37) xor d(38) xor d(39) xor d(40) xor d(42) xor d(43) xor d(44) xor d(52) xor d(56) xor d(58) xor d(59) xor d(62); + n(28) := c(1) xor c(8) xor c(9) xor c(11) xor c(12) xor c(14) xor c(17) xor c(18) xor c(19) xor c(22) xor c(24) xor c(25) xor c(27) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(4) xor d(6) xor d(7) xor d(9) xor d(12) xor d(13) xor d(14) xor d(17) xor d(19) xor d(20) xor d(22) xor d(23) xor d(30) xor d(33) xor d(35) xor d(36) xor d(37) xor d(38) xor d(39) xor d(41) xor d(42) xor d(43) xor d(51) xor d(55) xor d(57) xor d(58) xor d(61); + n(29) := c(2) xor c(9) xor c(10) xor c(12) xor c(13) xor c(15) xor c(18) xor c(19) xor c(20) xor c(23) xor c(25) xor c(26) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(5) xor d(6) xor d(8) xor d(11) xor d(12) xor d(13) xor d(16) xor d(18) xor d(19) xor d(21) xor d(22) xor d(29) xor d(32) xor d(34) xor d(35) xor d(36) xor d(37) xor d(38) xor d(40) xor d(41) xor d(42) xor d(50) xor d(54) xor d(56) xor d(57) xor d(60); + n(30) := c(0) xor c(3) xor c(10) xor c(11) xor c(13) xor c(14) xor c(16) xor c(19) xor c(20) xor c(21) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor d(10) xor d(11) xor d(12) xor d(15) xor d(17) xor d(18) xor d(20) xor d(21) xor d(28) xor d(31) xor d(33) xor d(34) xor d(35) xor d(36) xor d(37) xor d(39) xor d(40) xor d(41) xor d(49) xor d(53) xor d(55) xor d(56) xor d(59); + n(31) := c(1) xor c(4) xor c(11) xor c(12) xor c(14) xor c(15) xor c(17) xor c(20) xor c(21) xor c(22) xor c(25) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(6) xor d(9) xor d(10) xor d(11) xor d(14) xor d(16) xor d(17) xor d(19) xor d(20) xor d(27) xor d(30) xor d(32) xor d(33) xor d(34) xor d(35) xor d(36) xor d(38) xor d(39) xor d(40) xor d(48) xor d(52) xor d(54) xor d(55) xor d(58); + return n; + end newcrc32_d64; +end pkg_newcrc32_d64; + Index: experimental_jumbo_frames_version/fpga/src/desc.rec =================================================================== --- experimental_jumbo_frames_version/fpga/src/desc.rec (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/desc.rec (revision 22) @@ -0,0 +1,14 @@ +# This is a record with packet descriptor +record pkt_desc +# Below are fields definitions +# pkt - number of the packet +pkt,unsigned,32 +# sequential number of the packet +seq,unsigned,16 +# Flags +valid,std_logic +confirmed,std_logic +sent,std_logic +flushed,std_logic +end + Index: experimental_jumbo_frames_version/fpga/src/kc705/ack_fifo/ack_fifo.xci =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/ack_fifo/ack_fifo.xci (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/ack_fifo/ack_fifo.xci (revision 22) @@ -0,0 +1,395 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ack_fifo + + + ack_fifo + Independent_Clocks_Block_RAM + 2 + 2 + Native + First_Word_Fall_Through + false + 64 + 512 + 64 + 512 + false + false + true + true + Asynchronous_Reset + 1 + true + 0 + false + false + false + false + Active_High + false + Active_High + false + Active_High + false + Active_High + false + false + false + false + false + 9 + false + 9 + false + 9 + false + 1 + 1 + No_Programmable_Full_Threshold + 511 + 510 + No_Programmable_Empty_Threshold + 4 + 5 + AXI4 + Common_Clock + false + Slave_Interface_Clock_Enable + READ_WRITE + 0 + 32 + 64 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 4 + true + false + false + 1 + false + 1 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 16 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 1024 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 16 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 16 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 1024 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 1024 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + false + Active_High + false + Active_High + false + false + false + false + false + false + false + false + 0 + 0 + 9 + BlankString + 64 + 0 + 64 + 0 + kintex7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 1 + BlankString + 0 + 0 + 0 + 1 + 512x72 + 4 + 5 + 0 + 511 + 510 + 0 + 9 + 512 + 1 + 9 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 9 + 512 + 1 + 9 + 1 + 1 + 1 + 0 + 2 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 32 + 64 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 8 + 1 + 1 + 4 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 512x36 + 1kx36 + 512x36 + 512x36 + 1kx36 + 1kx18 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + 64 + 2 + 32 + 64 + 1 + 16 + 1024 + 16 + 16 + 1024 + 1024 + 4 + 10 + 4 + 4 + 10 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + xc7k325t + ffg900 + -2 + C + + VHDL + MIXED + TRUE + TRUE + xilinx.com:kc705:part0:0.9 + TRUE + 2014.3 + 2 + OUT_OF_CONTEXT + + . + . + + + + Index: experimental_jumbo_frames_version/fpga/src/kc705/ila_1/ila_1.xci =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/ila_1/ila_1.xci (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/ila_1/ila_1.xci (revision 22) @@ -0,0 +1,2124 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ila_1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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NUM_OF_PROBES=12,DATA_DEPTH=1024,PROBE0_WIDTH=64,PROBE0_MU_CNT=1,PROBE1_WIDTH=8,PROBE1_MU_CNT=1,PROBE2_WIDTH=3,PROBE2_MU_CNT=1,PROBE3_WIDTH=8,PROBE3_MU_CNT=1,PROBE4_WIDTH=4,PROBE4_MU_CNT=1,PROBE5_WIDTH=32,PROBE5_MU_CNT=1,PROBE6_WIDTH=32,PROBE6_MU_CNT=1,PROBE7_WIDTH=16,PROBE7_MU_CNT=1,PROBE8_WIDTH=32,PROBE8_MU_CNT=1,PROBE9_WIDTH=32,PROBE9_MU_CNT=1,PROBE10_WIDTH=64,PROBE10_MU_CNT=1,PROBE11_WIDTH=8,PROBE11_MU_CNT=1,PROBE12_WIDTH=1,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1,PROBE64_WIDTH=1,PROBE64_MU_CNT=1,PROBE65_WIDTH=1,PROBE65_MU_CNT=1,PROBE66_WIDTH=1,PROBE66_MU_CNT=1,PROBE67_WIDTH=1,PROBE67_MU_CNT=1,PROBE68_WIDTH=1,PROBE68_MU_CNT=1,PROBE69_WIDTH=1,PROBE69_MU_CNT=1,PROBE70_WIDTH=1,PROBE70_MU_CNT=1,PROBE71_WIDTH=1,PROBE71_MU_CNT=1,PROBE72_WIDTH=1,PROBE72_MU_CNT=1,PROBE73_WIDTH=1,PROBE73_MU_CNT=1,PROBE74_WIDTH=1,PROBE74_MU_CNT=1,PROBE75_WIDTH=1,PROBE75_MU_CNT=1,PROBE76_WIDTH=1,PROBE76_MU_CNT=1,PROBE77_WIDTH=1,PROBE77_MU_CNT=1,PROBE78_WIDTH=1,PROBE78_MU_CNT=1,PROBE79_WIDTH=1,PROBE79_MU_CNT=1,PROBE80_WIDTH=1,PROBE80_MU_CNT=1,PROBE81_WIDTH=1,PROBE81_MU_CNT=1,PROBE82_WIDTH=1,PROBE82_MU_CNT=1,PROBE83_WIDTH=1,PROBE83_MU_CNT=1,PROBE84_WIDTH=1,PROBE84_MU_CNT=1,PROBE85_WIDTH=1,PROBE85_MU_CNT=1,PROBE86_WIDTH=1,PROBE86_MU_CNT=1,PROBE87_WIDTH=1,PROBE87_MU_CNT=1,PROBE88_WIDTH=1,PROBE88_MU_CNT=1,PROBE89_WIDTH=1,PROBE89_MU_CNT=1,PROBE90_WIDTH=1,PROBE90_MU_CNT=1,PROBE91_WIDTH=1,PROBE91_MU_CNT=1,PROBE92_WIDTH=1,PROBE92_MU_CNT=1,PROBE93_WIDTH=1,PROBE93_MU_CNT=1,PROBE94_WIDTH=1,PROBE94_MU_CNT=1,PROBE95_WIDTH=1,PROBE95_MU_CNT=1,PROBE96_WIDTH=1,PROBE96_MU_CNT=1,PROBE97_WIDTH=1,PROBE97_MU_CNT=1,PROBE98_WIDTH=1,PROBE98_MU_CNT=1,PROBE99_WIDTH=1,PROBE99_MU_CNT=1,PROBE100_WIDTH=1,PROBE100_MU_CNT=1,PROBE101_WIDTH=1,PROBE101_MU_CNT=1,PROBE102_WIDTH=1,PROBE102_MU_CNT=1,PROBE103_WIDTH=1,PROBE103_MU_CNT=1,PROBE104_WIDTH=1,PROBE104_MU_CNT=1,PROBE105_WIDTH=1,PROBE105_MU_CNT=1,PROBE106_WIDTH=1,PROBE106_MU_CNT=1,PROBE107_WIDTH=1,PROBE107_MU_CNT=1,PROBE108_WIDTH=1,PROBE108_MU_CNT=1,PROBE109_WIDTH=1,PROBE109_MU_CNT=1,PROBE110_WIDTH=1,PROBE110_MU_CNT=1,PROBE111_WIDTH=1,PROBE111_MU_CNT=1,PROBE112_WIDTH=1,PROBE112_MU_CNT=1,PROBE113_WIDTH=1,PROBE113_MU_CNT=1,PROBE114_WIDTH=1,PROBE114_MU_CNT=1,PROBE115_WIDTH=1,PROBE115_MU_CNT=1,PROBE116_WIDTH=1,PROBE116_MU_CNT=1,PROBE117_WIDTH=1,PROBE117_MU_CNT=1,PROBE118_WIDTH=1,PROBE118_MU_CNT=1,PROBE119_WIDTH=1,PROBE119_MU_CNT=1,PROBE120_WIDTH=1,PROBE120_MU_CNT=1,PROBE121_WIDTH=1,PROBE121_MU_CNT=1,PROBE122_WIDTH=1,PROBE122_MU_CNT=1,PROBE123_WIDTH=1,PROBE123_MU_CNT=1,PROBE124_WIDTH=1,PROBE124_MU_CNT=1,PROBE125_WIDTH=1,PROBE125_MU_CNT=1,PROBE126_WIDTH=1,PROBE126_MU_CNT=1,PROBE127_WIDTH=1,PROBE127_MU_CNT=1,PROBE128_WIDTH=1,PROBE128_MU_CNT=1,PROBE129_WIDTH=1,PROBE129_MU_CNT=1,PROBE130_WIDTH=1,PROBE130_MU_CNT=1,PROBE131_WIDTH=1,PROBE131_MU_CNT=1,PROBE132_WIDTH=1,PROBE132_MU_CNT=1,PROBE133_WIDTH=1,PROBE133_MU_CNT=1,PROBE134_WIDTH=1,PROBE134_MU_CNT=1,PROBE135_WIDTH=1,PROBE135_MU_CNT=1,PROBE136_WIDTH=1,PROBE136_MU_CNT=1,PROBE137_WIDTH=1,PROBE137_MU_CNT=1,PROBE138_WIDTH=1,PROBE138_MU_CNT=1,PROBE139_WIDTH=1,PROBE139_MU_CNT=1,PROBE140_WIDTH=1,PROBE140_MU_CNT=1,PROBE141_WIDTH=1,PROBE141_MU_CNT=1,PROBE142_WIDTH=1,PROBE142_MU_CNT=1,PROBE143_WIDTH=1,PROBE143_MU_CNT=1,PROBE144_WIDTH=1,PROBE144_MU_CNT=1,PROBE145_WIDTH=1,PROBE145_MU_CNT=1,PROBE146_WIDTH=1,PROBE146_MU_CNT=1,PROBE147_WIDTH=1,PROBE147_MU_CNT=1,PROBE148_WIDTH=1,PROBE148_MU_CNT=1,PROBE149_WIDTH=1,PROBE149_MU_CNT=1,PROBE150_WIDTH=1,PROBE150_MU_CNT=1,PROBE151_WIDTH=1,PROBE151_MU_CNT=1,PROBE152_WIDTH=1,PROBE152_MU_CNT=1,PROBE153_WIDTH=1,PROBE153_MU_CNT=1,PROBE154_WIDTH=1,PROBE154_MU_CNT=1,PROBE155_WIDTH=1,PROBE155_MU_CNT=1,PROBE156_WIDTH=1,PROBE156_MU_CNT=1,PROBE157_WIDTH=1,PROBE157_MU_CNT=1,PROBE158_WIDTH=1,PROBE158_MU_CNT=1,PROBE159_WIDTH=1,PROBE159_MU_CNT=1,PROBE160_WIDTH=1,PROBE160_MU_CNT=1,PROBE161_WIDTH=1,PROBE161_MU_CNT=1,PROBE162_WIDTH=1,PROBE162_MU_CNT=1,PROBE163_WIDTH=1,PROBE163_MU_CNT=1,PROBE164_WIDTH=1,PROBE164_MU_CNT=1,PROBE165_WIDTH=1,PROBE165_MU_CNT=1,PROBE166_WIDTH=1,PROBE166_MU_CNT=1,PROBE167_WIDTH=1,PROBE167_MU_CNT=1,PROBE168_WIDTH=1,PROBE168_MU_CNT=1,PROBE169_WIDTH=1,PROBE169_MU_CNT=1,PROBE170_WIDTH=1,PROBE170_MU_CNT=1,PROBE171_WIDTH=1,PROBE171_MU_CNT=1,PROBE172_WIDTH=1,PROBE172_MU_CNT=1,PROBE173_WIDTH=1,PROBE173_MU_CNT=1,PROBE174_WIDTH=1,PROBE174_MU_CNT=1,PROBE175_WIDTH=1,PROBE175_MU_CNT=1,PROBE176_WIDTH=1,PROBE176_MU_CNT=1,PROBE177_WIDTH=1,PROBE177_MU_CNT=1,PROBE178_WIDTH=1,PROBE178_MU_CNT=1,PROBE179_WIDTH=1,PROBE179_MU_CNT=1,PROBE180_WIDTH=1,PROBE180_MU_CNT=1,PROBE181_WIDTH=1,PROBE181_MU_CNT=1,PROBE182_WIDTH=1,PROBE182_MU_CNT=1,PROBE183_WIDTH=1,PROBE183_MU_CNT=1,PROBE184_WIDTH=1,PROBE184_MU_CNT=1,PROBE185_WIDTH=1,PROBE185_MU_CNT=1,PROBE186_WIDTH=1,PROBE186_MU_CNT=1,PROBE187_WIDTH=1,PROBE187_MU_CNT=1,PROBE188_WIDTH=1,PROBE188_MU_CNT=1,PROBE189_WIDTH=1,PROBE189_MU_CNT=1,PROBE190_WIDTH=1,PROBE190_MU_CNT=1,PROBE191_WIDTH=1,PROBE191_MU_CNT=1,PROBE192_WIDTH=1,PROBE192_MU_CNT=1,PROBE193_WIDTH=1,PROBE193_MU_CNT=1,PROBE194_WIDTH=1,PROBE194_MU_CNT=1,PROBE195_WIDTH=1,PROBE195_MU_CNT=1,PROBE196_WIDTH=1,PROBE196_MU_CNT=1,PROBE197_WIDTH=1,PROBE197_MU_CNT=1,PROBE198_WIDTH=1,PROBE198_MU_CNT=1,PROBE199_WIDTH=1,PROBE199_MU_CNT=1,PROBE200_WIDTH=1,PROBE200_MU_CNT=1,PROBE201_WIDTH=1,PROBE201_MU_CNT=1,PROBE202_WIDTH=1,PROBE202_MU_CNT=1,PROBE203_WIDTH=1,PROBE203_MU_CNT=1,PROBE204_WIDTH=1,PROBE204_MU_CNT=1,PROBE205_WIDTH=1,PROBE205_MU_CNT=1,PROBE206_WIDTH=1,PROBE206_MU_CNT=1,PROBE207_WIDTH=1,PROBE207_MU_CNT=1,PROBE208_WIDTH=1,PROBE208_MU_CNT=1,PROBE209_WIDTH=1,PROBE209_MU_CNT=1,PROBE210_WIDTH=1,PROBE210_MU_CNT=1,PROBE211_WIDTH=1,PROBE211_MU_CNT=1,PROBE212_WIDTH=1,PROBE212_MU_CNT=1,PROBE213_WIDTH=1,PROBE213_MU_CNT=1,PROBE214_WIDTH=1,PROBE214_MU_CNT=1,PROBE215_WIDTH=1,PROBE215_MU_CNT=1,PROBE216_WIDTH=1,PROBE216_MU_CNT=1,PROBE217_WIDTH=1,PROBE217_MU_CNT=1,PROBE218_WIDTH=1,PROBE218_MU_CNT=1,PROBE219_WIDTH=1,PROBE219_MU_CNT=1,PROBE220_WIDTH=1,PROBE220_MU_CNT=1,PROBE221_WIDTH=1,PROBE221_MU_CNT=1,PROBE222_WIDTH=1,PROBE222_MU_CNT=1,PROBE223_WIDTH=1,PROBE223_MU_CNT=1,PROBE224_WIDTH=1,PROBE224_MU_CNT=1,PROBE225_WIDTH=1,PROBE225_MU_CNT=1,PROBE226_WIDTH=1,PROBE226_MU_CNT=1,PROBE227_WIDTH=1,PROBE227_MU_CNT=1,PROBE228_WIDTH=1,PROBE228_MU_CNT=1,PROBE229_WIDTH=1,PROBE229_MU_CNT=1,PROBE230_WIDTH=1,PROBE230_MU_CNT=1,PROBE231_WIDTH=1,PROBE231_MU_CNT=1,PROBE232_WIDTH=1,PROBE232_MU_CNT=1,PROBE233_WIDTH=1,PROBE233_MU_CNT=1,PROBE234_WIDTH=1,PROBE234_MU_CNT=1,PROBE235_WIDTH=1,PROBE235_MU_CNT=1,PROBE236_WIDTH=1,PROBE236_MU_CNT=1,PROBE237_WIDTH=1,PROBE237_MU_CNT=1,PROBE238_WIDTH=1,PROBE238_MU_CNT=1,PROBE239_WIDTH=1,PROBE239_MU_CNT=1,PROBE240_WIDTH=1,PROBE240_MU_CNT=1,PROBE241_WIDTH=1,PROBE241_MU_CNT=1,PROBE242_WIDTH=1,PROBE242_MU_CNT=1,PROBE243_WIDTH=1,PROBE243_MU_CNT=1,PROBE244_WIDTH=1,PROBE244_MU_CNT=1,PROBE245_WIDTH=1,PROBE245_MU_CNT=1,PROBE246_WIDTH=1,PROBE246_MU_CNT=1,PROBE247_WIDTH=1,PROBE247_MU_CNT=1,PROBE248_WIDTH=1,PROBE248_MU_CNT=1,PROBE249_WIDTH=1,PROBE249_MU_CNT=1,PROBE250_WIDTH=1,PROBE250_MU_CNT=1,PROBE251_WIDTH=1,PROBE251_MU_CNT=1,PROBE252_WIDTH=1,PROBE252_MU_CNT=1,PROBE253_WIDTH=1,PROBE253_MU_CNT=1,PROBE254_WIDTH=1,PROBE254_MU_CNT=1,PROBE255_WIDTH=1,PROBE255_MU_CNT=1,PROBE256_WIDTH=1,PROBE256_MU_CNT=1,PROBE257_WIDTH=1,PROBE257_MU_CNT=1,PROBE258_WIDTH=1,PROBE258_MU_CNT=1,PROBE259_WIDTH=1,PROBE259_MU_CNT=1,PROBE260_WIDTH=1,PROBE260_MU_CNT=1,PROBE261_WIDTH=1,PROBE261_MU_CNT=1,PROBE262_WIDTH=1,PROBE262_MU_CNT=1,PROBE263_WIDTH=1,PROBE263_MU_CNT=1,PROBE264_WIDTH=1,PROBE264_MU_CNT=1,PROBE265_WIDTH=1,PROBE265_MU_CNT=1,PROBE266_WIDTH=1,PROBE266_MU_CNT=1,PROBE267_WIDTH=1,PROBE267_MU_CNT=1,PROBE268_WIDTH=1,PROBE268_MU_CNT=1,PROBE269_WIDTH=1,PROBE269_MU_CNT=1,PROBE270_WIDTH=1,PROBE270_MU_CNT=1,PROBE271_WIDTH=1,PROBE271_MU_CNT=1,PROBE272_WIDTH=1,PROBE272_MU_CNT=1,PROBE273_WIDTH=1,PROBE273_MU_CNT=1,PROBE274_WIDTH=1,PROBE274_MU_CNT=1,PROBE275_WIDTH=1,PROBE275_MU_CNT=1,PROBE276_WIDTH=1,PROBE276_MU_CNT=1,PROBE277_WIDTH=1,PROBE277_MU_CNT=1,PROBE278_WIDTH=1,PROBE278_MU_CNT=1,PROBE279_WIDTH=1,PROBE279_MU_CNT=1,PROBE280_WIDTH=1,PROBE280_MU_CNT=1,PROBE281_WIDTH=1,PROBE281_MU_CNT=1,PROBE282_WIDTH=1,PROBE282_MU_CNT=1,PROBE283_WIDTH=1,PROBE283_MU_CNT=1,PROBE284_WIDTH=1,PROBE284_MU_CNT=1,PROBE285_WIDTH=1,PROBE285_MU_CNT=1,PROBE286_WIDTH=1,PROBE286_MU_CNT=1,PROBE287_WIDTH=1,PROBE287_MU_CNT=1,PROBE288_WIDTH=1,PROBE288_MU_CNT=1,PROBE289_WIDTH=1,PROBE289_MU_CNT=1,PROBE290_WIDTH=1,PROBE290_MU_CNT=1,PROBE291_WIDTH=1,PROBE291_MU_CNT=1,PROBE292_WIDTH=1,PROBE292_MU_CNT=1,PROBE293_WIDTH=1,PROBE293_MU_CNT=1,PROBE294_WIDTH=1,PROBE294_MU_CNT=1,PROBE295_WIDTH=1,PROBE295_MU_CNT=1,PROBE296_WIDTH=1,PROBE296_MU_CNT=1,PROBE297_WIDTH=1,PROBE297_MU_CNT=1,PROBE298_WIDTH=1,PROBE298_MU_CNT=1,PROBE299_WIDTH=1,PROBE299_MU_CNT=1,PROBE300_WIDTH=1,PROBE300_MU_CNT=1,PROBE301_WIDTH=1,PROBE301_MU_CNT=1,PROBE302_WIDTH=1,PROBE302_MU_CNT=1,PROBE303_WIDTH=1,PROBE303_MU_CNT=1,PROBE304_WIDTH=1,PROBE304_MU_CNT=1,PROBE305_WIDTH=1,PROBE305_MU_CNT=1,PROBE306_WIDTH=1,PROBE306_MU_CNT=1,PROBE307_WIDTH=1,PROBE307_MU_CNT=1,PROBE308_WIDTH=1,PROBE308_MU_CNT=1,PROBE309_WIDTH=1,PROBE309_MU_CNT=1,PROBE310_WIDTH=1,PROBE310_MU_CNT=1,PROBE311_WIDTH=1,PROBE311_MU_CNT=1,PROBE312_WIDTH=1,PROBE312_MU_CNT=1,PROBE313_WIDTH=1,PROBE313_MU_CNT=1,PROBE314_WIDTH=1,PROBE314_MU_CNT=1,PROBE315_WIDTH=1,PROBE315_MU_CNT=1,PROBE316_WIDTH=1,PROBE316_MU_CNT=1,PROBE317_WIDTH=1,PROBE317_MU_CNT=1,PROBE318_WIDTH=1,PROBE318_MU_CNT=1,PROBE319_WIDTH=1,PROBE319_MU_CNT=1,PROBE320_WIDTH=1,PROBE320_MU_CNT=1,PROBE321_WIDTH=1,PROBE321_MU_CNT=1,PROBE322_WIDTH=1,PROBE322_MU_CNT=1,PROBE323_WIDTH=1,PROBE323_MU_CNT=1,PROBE324_WIDTH=1,PROBE324_MU_CNT=1,PROBE325_WIDTH=1,PROBE325_MU_CNT=1,PROBE326_WIDTH=1,PROBE326_MU_CNT=1,PROBE327_WIDTH=1,PROBE327_MU_CNT=1,PROBE328_WIDTH=1,PROBE328_MU_CNT=1,PROBE329_WIDTH=1,PROBE329_MU_CNT=1,PROBE330_WIDTH=1,PROBE330_MU_CNT=1,PROBE331_WIDTH=1,PROBE331_MU_CNT=1,PROBE332_WIDTH=1,PROBE332_MU_CNT=1,PROBE333_WIDTH=1,PROBE333_MU_CNT=1,PROBE334_WIDTH=1,PROBE334_MU_CNT=1,PROBE335_WIDTH=1,PROBE335_MU_CNT=1,PROBE336_WIDTH=1,PROBE336_MU_CNT=1,PROBE337_WIDTH=1,PROBE337_MU_CNT=1,PROBE338_WIDTH=1,PROBE338_MU_CNT=1,PROBE339_WIDTH=1,PROBE339_MU_CNT=1,PROBE340_WIDTH=1,PROBE340_MU_CNT=1,PROBE341_WIDTH=1,PROBE341_MU_CNT=1,PROBE342_WIDTH=1,PROBE342_MU_CNT=1,PROBE343_WIDTH=1,PROBE343_MU_CNT=1,PROBE344_WIDTH=1,PROBE344_MU_CNT=1,PROBE345_WIDTH=1,PROBE345_MU_CNT=1,PROBE346_WIDTH=1,PROBE346_MU_CNT=1,PROBE347_WIDTH=1,PROBE347_MU_CNT=1,PROBE348_WIDTH=1,PROBE348_MU_CNT=1,PROBE349_WIDTH=1,PROBE349_MU_CNT=1,PROBE350_WIDTH=1,PROBE350_MU_CNT=1,PROBE351_WIDTH=1,PROBE351_MU_CNT=1,PROBE352_WIDTH=1,PROBE352_MU_CNT=1,PROBE353_WIDTH=1,PROBE353_MU_CNT=1,PROBE354_WIDTH=1,PROBE354_MU_CNT=1,PROBE355_WIDTH=1,PROBE355_MU_CNT=1,PROBE356_WIDTH=1,PROBE356_MU_CNT=1,PROBE357_WIDTH=1,PROBE357_MU_CNT=1,PROBE358_WIDTH=1,PROBE358_MU_CNT=1,PROBE359_WIDTH=1,PROBE359_MU_CNT=1,PROBE360_WIDTH=1,PROBE360_MU_CNT=1,PROBE361_WIDTH=1,PROBE361_MU_CNT=1,PROBE362_WIDTH=1,PROBE362_MU_CNT=1,PROBE363_WIDTH=1,PROBE363_MU_CNT=1,PROBE364_WIDTH=1,PROBE364_MU_CNT=1,PROBE365_WIDTH=1,PROBE365_MU_CNT=1,PROBE366_WIDTH=1,PROBE366_MU_CNT=1,PROBE367_WIDTH=1,PROBE367_MU_CNT=1,PROBE368_WIDTH=1,PROBE368_MU_CNT=1,PROBE369_WIDTH=1,PROBE369_MU_CNT=1,PROBE370_WIDTH=1,PROBE370_MU_CNT=1,PROBE371_WIDTH=1,PROBE371_MU_CNT=1,PROBE372_WIDTH=1,PROBE372_MU_CNT=1,PROBE373_WIDTH=1,PROBE373_MU_CNT=1,PROBE374_WIDTH=1,PROBE374_MU_CNT=1,PROBE375_WIDTH=1,PROBE375_MU_CNT=1,PROBE376_WIDTH=1,PROBE376_MU_CNT=1,PROBE377_WIDTH=1,PROBE377_MU_CNT=1,PROBE378_WIDTH=1,PROBE378_MU_CNT=1,PROBE379_WIDTH=1,PROBE379_MU_CNT=1,PROBE380_WIDTH=1,PROBE380_MU_CNT=1,PROBE381_WIDTH=1,PROBE381_MU_CNT=1,PROBE382_WIDTH=1,PROBE382_MU_CNT=1,PROBE383_WIDTH=1,PROBE383_MU_CNT=1,PROBE384_WIDTH=1,PROBE384_MU_CNT=1,PROBE385_WIDTH=1,PROBE385_MU_CNT=1,PROBE386_WIDTH=1,PROBE386_MU_CNT=1,PROBE387_WIDTH=1,PROBE387_MU_CNT=1,PROBE388_WIDTH=1,PROBE388_MU_CNT=1,PROBE389_WIDTH=1,PROBE389_MU_CNT=1,PROBE390_WIDTH=1,PROBE390_MU_CNT=1,PROBE391_WIDTH=1,PROBE391_MU_CNT=1,PROBE392_WIDTH=1,PROBE392_MU_CNT=1,PROBE393_WIDTH=1,PROBE393_MU_CNT=1,PROBE394_WIDTH=1,PROBE394_MU_CNT=1,PROBE395_WIDTH=1,PROBE395_MU_CNT=1,PROBE396_WIDTH=1,PROBE396_MU_CNT=1,PROBE397_WIDTH=1,PROBE397_MU_CNT=1,PROBE398_WIDTH=1,PROBE398_MU_CNT=1,PROBE399_WIDTH=1,PROBE399_MU_CNT=1,PROBE400_WIDTH=1,PROBE400_MU_CNT=1,PROBE401_WIDTH=1,PROBE401_MU_CNT=1,PROBE402_WIDTH=1,PROBE402_MU_CNT=1,PROBE403_WIDTH=1,PROBE403_MU_CNT=1,PROBE404_WIDTH=1,PROBE404_MU_CNT=1,PROBE405_WIDTH=1,PROBE405_MU_CNT=1,PROBE406_WIDTH=1,PROBE406_MU_CNT=1,PROBE407_WIDTH=1,PROBE407_MU_CNT=1,PROBE408_WIDTH=1,PROBE408_MU_CNT=1,PROBE409_WIDTH=1,PROBE409_MU_CNT=1,PROBE410_WIDTH=1,PROBE410_MU_CNT=1,PROBE411_WIDTH=1,PROBE411_MU_CNT=1,PROBE412_WIDTH=1,PROBE412_MU_CNT=1,PROBE413_WIDTH=1,PROBE413_MU_CNT=1,PROBE414_WIDTH=1,PROBE414_MU_CNT=1,PROBE415_WIDTH=1,PROBE415_MU_CNT=1,PROBE416_WIDTH=1,PROBE416_MU_CNT=1,PROBE417_WIDTH=1,PROBE417_MU_CNT=1,PROBE418_WIDTH=1,PROBE418_MU_CNT=1,PROBE419_WIDTH=1,PROBE419_MU_CNT=1,PROBE420_WIDTH=1,PROBE420_MU_CNT=1,PROBE421_WIDTH=1,PROBE421_MU_CNT=1,PROBE422_WIDTH=1,PROBE422_MU_CNT=1,PROBE423_WIDTH=1,PROBE423_MU_CNT=1,PROBE424_WIDTH=1,PROBE424_MU_CNT=1,PROBE425_WIDTH=1,PROBE425_MU_CNT=1,PROBE426_WIDTH=1,PROBE426_MU_CNT=1,PROBE427_WIDTH=1,PROBE427_MU_CNT=1,PROBE428_WIDTH=1,PROBE428_MU_CNT=1,PROBE429_WIDTH=1,PROBE429_MU_CNT=1,PROBE430_WIDTH=1,PROBE430_MU_CNT=1,PROBE431_WIDTH=1,PROBE431_MU_CNT=1,PROBE432_WIDTH=1,PROBE432_MU_CNT=1,PROBE433_WIDTH=1,PROBE433_MU_CNT=1,PROBE434_WIDTH=1,PROBE434_MU_CNT=1,PROBE435_WIDTH=1,PROBE435_MU_CNT=1,PROBE436_WIDTH=1,PROBE436_MU_CNT=1,PROBE437_WIDTH=1,PROBE437_MU_CNT=1,PROBE438_WIDTH=1,PROBE438_MU_CNT=1,PROBE439_WIDTH=1,PROBE439_MU_CNT=1,PROBE440_WIDTH=1,PROBE440_MU_CNT=1,PROBE441_WIDTH=1,PROBE441_MU_CNT=1,PROBE442_WIDTH=1,PROBE442_MU_CNT=1,PROBE443_WIDTH=1,PROBE443_MU_CNT=1,PROBE444_WIDTH=1,PROBE444_MU_CNT=1,PROBE445_WIDTH=1,PROBE445_MU_CNT=1,PROBE446_WIDTH=1,PROBE446_MU_CNT=1,PROBE447_WIDTH=1,PROBE447_MU_CNT=1,PROBE448_WIDTH=1,PROBE448_MU_CNT=1,PROBE449_WIDTH=1,PROBE449_MU_CNT=1,PROBE450_WIDTH=1,PROBE450_MU_CNT=1,PROBE451_WIDTH=1,PROBE451_MU_CNT=1,PROBE452_WIDTH=1,PROBE452_MU_CNT=1,PROBE453_WIDTH=1,PROBE453_MU_CNT=1,PROBE454_WIDTH=1,PROBE454_MU_CNT=1,PROBE455_WIDTH=1,PROBE455_MU_CNT=1,PROBE456_WIDTH=1,PROBE456_MU_CNT=1,PROBE457_WIDTH=1,PROBE457_MU_CNT=1,PROBE458_WIDTH=1,PROBE458_MU_CNT=1,PROBE459_WIDTH=1,PROBE459_MU_CNT=1,PROBE460_WIDTH=1,PROBE460_MU_CNT=1,PROBE461_WIDTH=1,PROBE461_MU_CNT=1,PROBE462_WIDTH=1,PROBE462_MU_CNT=1,PROBE463_WIDTH=1,PROBE463_MU_CNT=1,PROBE464_WIDTH=1,PROBE464_MU_CNT=1,PROBE465_WIDTH=1,PROBE465_MU_CNT=1,PROBE466_WIDTH=1,PROBE466_MU_CNT=1,PROBE467_WIDTH=1,PROBE467_MU_CNT=1,PROBE468_WIDTH=1,PROBE468_MU_CNT=1,PROBE469_WIDTH=1,PROBE469_MU_CNT=1,PROBE470_WIDTH=1,PROBE470_MU_CNT=1,PROBE471_WIDTH=1,PROBE471_MU_CNT=1,PROBE472_WIDTH=1,PROBE472_MU_CNT=1,PROBE473_WIDTH=1,PROBE473_MU_CNT=1,PROBE474_WIDTH=1,PROBE474_MU_CNT=1,PROBE475_WIDTH=1,PROBE475_MU_CNT=1,PROBE476_WIDTH=1,PROBE476_MU_CNT=1,PROBE477_WIDTH=1,PROBE477_MU_CNT=1,PROBE478_WIDTH=1,PROBE478_MU_CNT=1,PROBE479_WIDTH=1,PROBE479_MU_CNT=1,PROBE480_WIDTH=1,PROBE480_MU_CNT=1,PROBE481_WIDTH=1,PROBE481_MU_CNT=1,PROBE482_WIDTH=1,PROBE482_MU_CNT=1,PROBE483_WIDTH=1,PROBE483_MU_CNT=1,PROBE484_WIDTH=1,PROBE484_MU_CNT=1,PROBE485_WIDTH=1,PROBE485_MU_CNT=1,PROBE486_WIDTH=1,PROBE486_MU_CNT=1,PROBE487_WIDTH=1,PROBE487_MU_CNT=1,PROBE488_WIDTH=1,PROBE488_MU_CNT=1,PROBE489_WIDTH=1,PROBE489_MU_CNT=1,PROBE490_WIDTH=1,PROBE490_MU_CNT=1,PROBE491_WIDTH=1,PROBE491_MU_CNT=1,PROBE492_WIDTH=1,PROBE492_MU_CNT=1,PROBE493_WIDTH=1,PROBE493_MU_CNT=1,PROBE494_WIDTH=1,PROBE494_MU_CNT=1,PROBE495_WIDTH=1,PROBE495_MU_CNT=1,PROBE496_WIDTH=1,PROBE496_MU_CNT=1,PROBE497_WIDTH=1,PROBE497_MU_CNT=1,PROBE498_WIDTH=1,PROBE498_MU_CNT=1,PROBE499_WIDTH=1,PROBE499_MU_CNT=1,PROBE500_WIDTH=1,PROBE500_MU_CNT=1,PROBE501_WIDTH=1,PROBE501_MU_CNT=1,PROBE502_WIDTH=1,PROBE502_MU_CNT=1,PROBE503_WIDTH=1,PROBE503_MU_CNT=1,PROBE504_WIDTH=1,PROBE504_MU_CNT=1,PROBE505_WIDTH=1,PROBE505_MU_CNT=1,PROBE506_WIDTH=1,PROBE506_MU_CNT=1,PROBE507_WIDTH=1,PROBE507_MU_CNT=1,PROBE508_WIDTH=1,PROBE508_MU_CNT=1,PROBE509_WIDTH=1,PROBE509_MU_CNT=1,PROBE510_WIDTH=1,PROBE510_MU_CNT=1,PROBE511_WIDTH=1,PROBE511_MU_CNT=1,PROBE512_WIDTH=1,PROBE512_MU_CNT=1,PROBE513_WIDTH=1,PROBE513_MU_CNT=1,PROBE514_WIDTH=1,PROBE514_MU_CNT=1,PROBE515_WIDTH=1,PROBE515_MU_CNT=1,PROBE516_WIDTH=1,PROBE516_MU_CNT=1,PROBE517_WIDTH=1,PROBE517_MU_CNT=1,PROBE518_WIDTH=1,PROBE518_MU_CNT=1,PROBE519_WIDTH=1,PROBE519_MU_CNT=1,PROBE520_WIDTH=1,PROBE520_MU_CNT=1,PROBE521_WIDTH=1,PROBE521_MU_CNT=1,PROBE522_WIDTH=1,PROBE522_MU_CNT=1,PROBE523_WIDTH=1,PROBE523_MU_CNT=1,PROBE524_WIDTH=1,PROBE524_MU_CNT=1,PROBE525_WIDTH=1,PROBE525_MU_CNT=1,PROBE526_WIDTH=1,PROBE526_MU_CNT=1,PROBE527_WIDTH=1,PROBE527_MU_CNT=1,PROBE528_WIDTH=1,PROBE528_MU_CNT=1,PROBE529_WIDTH=1,PROBE529_MU_CNT=1,PROBE530_WIDTH=1,PROBE530_MU_CNT=1,PROBE531_WIDTH=1,PROBE531_MU_CNT=1,PROBE532_WIDTH=1,PROBE532_MU_CNT=1,PROBE533_WIDTH=1,PROBE533_MU_CNT=1,PROBE534_WIDTH=1,PROBE534_MU_CNT=1,PROBE535_WIDTH=1,PROBE535_MU_CNT=1,PROBE536_WIDTH=1,PROBE536_MU_CNT=1,PROBE537_WIDTH=1,PROBE537_MU_CNT=1,PROBE538_WIDTH=1,PROBE538_MU_CNT=1,PROBE539_WIDTH=1,PROBE539_MU_CNT=1,PROBE540_WIDTH=1,PROBE540_MU_CNT=1,PROBE541_WIDTH=1,PROBE541_MU_CNT=1,PROBE542_WIDTH=1,PROBE542_MU_CNT=1,PROBE543_WIDTH=1,PROBE543_MU_CNT=1,PROBE544_WIDTH=1,PROBE544_MU_CNT=1,PROBE545_WIDTH=1,PROBE545_MU_CNT=1,PROBE546_WIDTH=1,PROBE546_MU_CNT=1,PROBE547_WIDTH=1,PROBE547_MU_CNT=1,PROBE548_WIDTH=1,PROBE548_MU_CNT=1,PROBE549_WIDTH=1,PROBE549_MU_CNT=1,PROBE550_WIDTH=1,PROBE550_MU_CNT=1,PROBE551_WIDTH=1,PROBE551_MU_CNT=1,PROBE552_WIDTH=1,PROBE552_MU_CNT=1,PROBE553_WIDTH=1,PROBE553_MU_CNT=1,PROBE554_WIDTH=1,PROBE554_MU_CNT=1,PROBE555_WIDTH=1,PROBE555_MU_CNT=1,PROBE556_WIDTH=1,PROBE556_MU_CNT=1,PROBE557_WIDTH=1,PROBE557_MU_CNT=1,PROBE558_WIDTH=1,PROBE558_MU_CNT=1,PROBE559_WIDTH=1,PROBE559_MU_CNT=1,PROBE560_WIDTH=1,PROBE560_MU_CNT=1,PROBE561_WIDTH=1,PROBE561_MU_CNT=1,PROBE562_WIDTH=1,PROBE562_MU_CNT=1,PROBE563_WIDTH=1,PROBE563_MU_CNT=1,PROBE564_WIDTH=1,PROBE564_MU_CNT=1,PROBE565_WIDTH=1,PROBE565_MU_CNT=1,PROBE566_WIDTH=1,PROBE566_MU_CNT=1,PROBE567_WIDTH=1,PROBE567_MU_CNT=1,PROBE568_WIDTH=1,PROBE568_MU_CNT=1,PROBE569_WIDTH=1,PROBE569_MU_CNT=1,PROBE570_WIDTH=1,PROBE570_MU_CNT=1,PROBE571_WIDTH=1,PROBE571_MU_CNT=1,PROBE572_WIDTH=1,PROBE572_MU_CNT=1,PROBE573_WIDTH=1,PROBE573_MU_CNT=1,PROBE574_WIDTH=1,PROBE574_MU_CNT=1,PROBE575_WIDTH=1,PROBE575_MU_CNT=1,PROBE576_WIDTH=1,PROBE576_MU_CNT=1,PROBE577_WIDTH=1,PROBE577_MU_CNT=1,PROBE578_WIDTH=1,PROBE578_MU_CNT=1,PROBE579_WIDTH=1,PROBE579_MU_CNT=1,PROBE580_WIDTH=1,PROBE580_MU_CNT=1,PROBE581_WIDTH=1,PROBE581_MU_CNT=1,PROBE582_WIDTH=1,PROBE582_MU_CNT=1,PROBE583_WIDTH=1,PROBE583_MU_CNT=1,PROBE584_WIDTH=1,PROBE584_MU_CNT=1,PROBE585_WIDTH=1,PROBE585_MU_CNT=1,PROBE586_WIDTH=1,PROBE586_MU_CNT=1,PROBE587_WIDTH=1,PROBE587_MU_CNT=1,PROBE588_WIDTH=1,PROBE588_MU_CNT=1,PROBE589_WIDTH=1,PROBE589_MU_CNT=1,PROBE590_WIDTH=1,PROBE590_MU_CNT=1,PROBE591_WIDTH=1,PROBE591_MU_CNT=1,PROBE592_WIDTH=1,PROBE592_MU_CNT=1,PROBE593_WIDTH=1,PROBE593_MU_CNT=1,PROBE594_WIDTH=1,PROBE594_MU_CNT=1,PROBE595_WIDTH=1,PROBE595_MU_CNT=1,PROBE596_WIDTH=1,PROBE596_MU_CNT=1,PROBE597_WIDTH=1,PROBE597_MU_CNT=1,PROBE598_WIDTH=1,PROBE598_MU_CNT=1,PROBE599_WIDTH=1,PROBE599_MU_CNT=1,PROBE600_WIDTH=1,PROBE600_MU_CNT=1,PROBE601_WIDTH=1,PROBE601_MU_CNT=1,PROBE602_WIDTH=1,PROBE602_MU_CNT=1,PROBE603_WIDTH=1,PROBE603_MU_CNT=1,PROBE604_WIDTH=1,PROBE604_MU_CNT=1,PROBE605_WIDTH=1,PROBE605_MU_CNT=1,PROBE606_WIDTH=1,PROBE606_MU_CNT=1,PROBE607_WIDTH=1,PROBE607_MU_CNT=1,PROBE608_WIDTH=1,PROBE608_MU_CNT=1,PROBE609_WIDTH=1,PROBE609_MU_CNT=1,PROBE610_WIDTH=1,PROBE610_MU_CNT=1,PROBE611_WIDTH=1,PROBE611_MU_CNT=1,PROBE612_WIDTH=1,PROBE612_MU_CNT=1,PROBE613_WIDTH=1,PROBE613_MU_CNT=1,PROBE614_WIDTH=1,PROBE614_MU_CNT=1,PROBE615_WIDTH=1,PROBE615_MU_CNT=1,PROBE616_WIDTH=1,PROBE616_MU_CNT=1,PROBE617_WIDTH=1,PROBE617_MU_CNT=1,PROBE618_WIDTH=1,PROBE618_MU_CNT=1,PROBE619_WIDTH=1,PROBE619_MU_CNT=1,PROBE620_WIDTH=1,PROBE620_MU_CNT=1,PROBE621_WIDTH=1,PROBE621_MU_CNT=1,PROBE622_WIDTH=1,PROBE622_MU_CNT=1,PROBE623_WIDTH=1,PROBE623_MU_CNT=1,PROBE624_WIDTH=1,PROBE624_MU_CNT=1,PROBE625_WIDTH=1,PROBE625_MU_CNT=1,PROBE626_WIDTH=1,PROBE626_MU_CNT=1,PROBE627_WIDTH=1,PROBE627_MU_CNT=1,PROBE628_WIDTH=1,PROBE628_MU_CNT=1,PROBE629_WIDTH=1,PROBE629_MU_CNT=1,PROBE630_WIDTH=1,PROBE630_MU_CNT=1,PROBE631_WIDTH=1,PROBE631_MU_CNT=1,PROBE632_WIDTH=1,PROBE632_MU_CNT=1,PROBE633_WIDTH=1,PROBE633_MU_CNT=1,PROBE634_WIDTH=1,PROBE634_MU_CNT=1,PROBE635_WIDTH=1,PROBE635_MU_CNT=1,PROBE636_WIDTH=1,PROBE636_MU_CNT=1,PROBE637_WIDTH=1,PROBE637_MU_CNT=1,PROBE638_WIDTH=1,PROBE638_MU_CNT=1,PROBE639_WIDTH=1,PROBE639_MU_CNT=1,PROBE640_WIDTH=1,PROBE640_MU_CNT=1,PROBE641_WIDTH=1,PROBE641_MU_CNT=1,PROBE642_WIDTH=1,PROBE642_MU_CNT=1,PROBE643_WIDTH=1,PROBE643_MU_CNT=1,PROBE644_WIDTH=1,PROBE644_MU_CNT=1,PROBE645_WIDTH=1,PROBE645_MU_CNT=1,PROBE646_WIDTH=1,PROBE646_MU_CNT=1,PROBE647_WIDTH=1,PROBE647_MU_CNT=1,PROBE648_WIDTH=1,PROBE648_MU_CNT=1,PROBE649_WIDTH=1,PROBE649_MU_CNT=1,PROBE650_WIDTH=1,PROBE650_MU_CNT=1,PROBE651_WIDTH=1,PROBE651_MU_CNT=1,PROBE652_WIDTH=1,PROBE652_MU_CNT=1,PROBE653_WIDTH=1,PROBE653_MU_CNT=1,PROBE654_WIDTH=1,PROBE654_MU_CNT=1,PROBE655_WIDTH=1,PROBE655_MU_CNT=1,PROBE656_WIDTH=1,PROBE656_MU_CNT=1,PROBE657_WIDTH=1,PROBE657_MU_CNT=1,PROBE658_WIDTH=1,PROBE658_MU_CNT=1,PROBE659_WIDTH=1,PROBE659_MU_CNT=1,PROBE660_WIDTH=1,PROBE660_MU_CNT=1,PROBE661_WIDTH=1,PROBE661_MU_CNT=1,PROBE662_WIDTH=1,PROBE662_MU_CNT=1,PROBE663_WIDTH=1,PROBE663_MU_CNT=1,PROBE664_WIDTH=1,PROBE664_MU_CNT=1,PROBE665_WIDTH=1,PROBE665_MU_CNT=1,PROBE666_WIDTH=1,PROBE666_MU_CNT=1,PROBE667_WIDTH=1,PROBE667_MU_CNT=1,PROBE668_WIDTH=1,PROBE668_MU_CNT=1,PROBE669_WIDTH=1,PROBE669_MU_CNT=1,PROBE670_WIDTH=1,PROBE670_MU_CNT=1,PROBE671_WIDTH=1,PROBE671_MU_CNT=1,PROBE672_WIDTH=1,PROBE672_MU_CNT=1,PROBE673_WIDTH=1,PROBE673_MU_CNT=1,PROBE674_WIDTH=1,PROBE674_MU_CNT=1,PROBE675_WIDTH=1,PROBE675_MU_CNT=1,PROBE676_WIDTH=1,PROBE676_MU_CNT=1,PROBE677_WIDTH=1,PROBE677_MU_CNT=1,PROBE678_WIDTH=1,PROBE678_MU_CNT=1,PROBE679_WIDTH=1,PROBE679_MU_CNT=1,PROBE680_WIDTH=1,PROBE680_MU_CNT=1,PROBE681_WIDTH=1,PROBE681_MU_CNT=1,PROBE682_WIDTH=1,PROBE682_MU_CNT=1,PROBE683_WIDTH=1,PROBE683_MU_CNT=1,PROBE684_WIDTH=1,PROBE684_MU_CNT=1,PROBE685_WIDTH=1,PROBE685_MU_CNT=1,PROBE686_WIDTH=1,PROBE686_MU_CNT=1,PROBE687_WIDTH=1,PROBE687_MU_CNT=1,PROBE688_WIDTH=1,PROBE688_MU_CNT=1,PROBE689_WIDTH=1,PROBE689_MU_CNT=1,PROBE690_WIDTH=1,PROBE690_MU_CNT=1,PROBE691_WIDTH=1,PROBE691_MU_CNT=1,PROBE692_WIDTH=1,PROBE692_MU_CNT=1,PROBE693_WIDTH=1,PROBE693_MU_CNT=1,PROBE694_WIDTH=1,PROBE694_MU_CNT=1,PROBE695_WIDTH=1,PROBE695_MU_CNT=1,PROBE696_WIDTH=1,PROBE696_MU_CNT=1,PROBE697_WIDTH=1,PROBE697_MU_CNT=1,PROBE698_WIDTH=1,PROBE698_MU_CNT=1,PROBE699_WIDTH=1,PROBE699_MU_CNT=1,PROBE700_WIDTH=1,PROBE700_MU_CNT=1,PROBE701_WIDTH=1,PROBE701_MU_CNT=1,PROBE702_WIDTH=1,PROBE702_MU_CNT=1,PROBE703_WIDTH=1,PROBE703_MU_CNT=1,PROBE704_WIDTH=1,PROBE704_MU_CNT=1,PROBE705_WIDTH=1,PROBE705_MU_CNT=1,PROBE706_WIDTH=1,PROBE706_MU_CNT=1,PROBE707_WIDTH=1,PROBE707_MU_CNT=1,PROBE708_WIDTH=1,PROBE708_MU_CNT=1,PROBE709_WIDTH=1,PROBE709_MU_CNT=1,PROBE710_WIDTH=1,PROBE710_MU_CNT=1,PROBE711_WIDTH=1,PROBE711_MU_CNT=1,PROBE712_WIDTH=1,PROBE712_MU_CNT=1,PROBE713_WIDTH=1,PROBE713_MU_CNT=1,PROBE714_WIDTH=1,PROBE714_MU_CNT=1,PROBE715_WIDTH=1,PROBE715_MU_CNT=1,PROBE716_WIDTH=1,PROBE716_MU_CNT=1,PROBE717_WIDTH=1,PROBE717_MU_CNT=1,PROBE718_WIDTH=1,PROBE718_MU_CNT=1,PROBE719_WIDTH=1,PROBE719_MU_CNT=1,PROBE720_WIDTH=1,PROBE720_MU_CNT=1,PROBE721_WIDTH=1,PROBE721_MU_CNT=1,PROBE722_WIDTH=1,PROBE722_MU_CNT=1,PROBE723_WIDTH=1,PROBE723_MU_CNT=1,PROBE724_WIDTH=1,PROBE724_MU_CNT=1,PROBE725_WIDTH=1,PROBE725_MU_CNT=1,PROBE726_WIDTH=1,PROBE726_MU_CNT=1,PROBE727_WIDTH=1,PROBE727_MU_CNT=1,PROBE728_WIDTH=1,PROBE728_MU_CNT=1,PROBE729_WIDTH=1,PROBE729_MU_CNT=1,PROBE730_WIDTH=1,PROBE730_MU_CNT=1,PROBE731_WIDTH=1,PROBE731_MU_CNT=1,PROBE732_WIDTH=1,PROBE732_MU_CNT=1,PROBE733_WIDTH=1,PROBE733_MU_CNT=1,PROBE734_WIDTH=1,PROBE734_MU_CNT=1,PROBE735_WIDTH=1,PROBE735_MU_CNT=1,PROBE736_WIDTH=1,PROBE736_MU_CNT=1,PROBE737_WIDTH=1,PROBE737_MU_CNT=1,PROBE738_WIDTH=1,PROBE738_MU_CNT=1,PROBE739_WIDTH=1,PROBE739_MU_CNT=1,PROBE740_WIDTH=1,PROBE740_MU_CNT=1,PROBE741_WIDTH=1,PROBE741_MU_CNT=1,PROBE742_WIDTH=1,PROBE742_MU_CNT=1,PROBE743_WIDTH=1,PROBE743_MU_CNT=1,PROBE744_WIDTH=1,PROBE744_MU_CNT=1,PROBE745_WIDTH=1,PROBE745_MU_CNT=1,PROBE746_WIDTH=1,PROBE746_MU_CNT=1,PROBE747_WIDTH=1,PROBE747_MU_CNT=1,PROBE748_WIDTH=1,PROBE748_MU_CNT=1,PROBE749_WIDTH=1,PROBE749_MU_CNT=1,PROBE750_WIDTH=1,PROBE750_MU_CNT=1,PROBE751_WIDTH=1,PROBE751_MU_CNT=1,PROBE752_WIDTH=1,PROBE752_MU_CNT=1,PROBE753_WIDTH=1,PROBE753_MU_CNT=1,PROBE754_WIDTH=1,PROBE754_MU_CNT=1,PROBE755_WIDTH=1,PROBE755_MU_CNT=1,PROBE756_WIDTH=1,PROBE756_MU_CNT=1,PROBE757_WIDTH=1,PROBE757_MU_CNT=1,PROBE758_WIDTH=1,PROBE758_MU_CNT=1,PROBE759_WIDTH=1,PROBE759_MU_CNT=1,PROBE760_WIDTH=1,PROBE760_MU_CNT=1,PROBE761_WIDTH=1,PROBE761_MU_CNT=1,PROBE762_WIDTH=1,PROBE762_MU_CNT=1,PROBE763_WIDTH=1,PROBE763_MU_CNT=1,PROBE764_WIDTH=1,PROBE764_MU_CNT=1,PROBE765_WIDTH=1,PROBE765_MU_CNT=1,PROBE766_WIDTH=1,PROBE766_MU_CNT=1,PROBE767_WIDTH=1,PROBE767_MU_CNT=1,PROBE768_WIDTH=1,PROBE768_MU_CNT=1,PROBE769_WIDTH=1,PROBE769_MU_CNT=1,PROBE770_WIDTH=1,PROBE770_MU_CNT=1,PROBE771_WIDTH=1,PROBE771_MU_CNT=1,PROBE772_WIDTH=1,PROBE772_MU_CNT=1,PROBE773_WIDTH=1,PROBE773_MU_CNT=1,PROBE774_WIDTH=1,PROBE774_MU_CNT=1,PROBE775_WIDTH=1,PROBE775_MU_CNT=1,PROBE776_WIDTH=1,PROBE776_MU_CNT=1,PROBE777_WIDTH=1,PROBE777_MU_CNT=1,PROBE778_WIDTH=1,PROBE778_MU_CNT=1,PROBE779_WIDTH=1,PROBE779_MU_CNT=1,PROBE780_WIDTH=1,PROBE780_MU_CNT=1,PROBE781_WIDTH=1,PROBE781_MU_CNT=1,PROBE782_WIDTH=1,PROBE782_MU_CNT=1,PROBE783_WIDTH=1,PROBE783_MU_CNT=1,PROBE784_WIDTH=1,PROBE784_MU_CNT=1,PROBE785_WIDTH=1,PROBE785_MU_CNT=1,PROBE786_WIDTH=1,PROBE786_MU_CNT=1,PROBE787_WIDTH=1,PROBE787_MU_CNT=1,PROBE788_WIDTH=1,PROBE788_MU_CNT=1,PROBE789_WIDTH=1,PROBE789_MU_CNT=1,PROBE790_WIDTH=1,PROBE790_MU_CNT=1,PROBE791_WIDTH=1,PROBE791_MU_CNT=1,PROBE792_WIDTH=1,PROBE792_MU_CNT=1,PROBE793_WIDTH=1,PROBE793_MU_CNT=1,PROBE794_WIDTH=1,PROBE794_MU_CNT=1,PROBE795_WIDTH=1,PROBE795_MU_CNT=1,PROBE796_WIDTH=1,PROBE796_MU_CNT=1,PROBE797_WIDTH=1,PROBE797_MU_CNT=1,PROBE798_WIDTH=1,PROBE798_MU_CNT=1,PROBE799_WIDTH=1,PROBE799_MU_CNT=1,PROBE800_WIDTH=1,PROBE800_MU_CNT=1,PROBE801_WIDTH=1,PROBE801_MU_CNT=1,PROBE802_WIDTH=1,PROBE802_MU_CNT=1,PROBE803_WIDTH=1,PROBE803_MU_CNT=1,PROBE804_WIDTH=1,PROBE804_MU_CNT=1,PROBE805_WIDTH=1,PROBE805_MU_CNT=1,PROBE806_WIDTH=1,PROBE806_MU_CNT=1,PROBE807_WIDTH=1,PROBE807_MU_CNT=1,PROBE808_WIDTH=1,PROBE808_MU_CNT=1,PROBE809_WIDTH=1,PROBE809_MU_CNT=1,PROBE810_WIDTH=1,PROBE810_MU_CNT=1,PROBE811_WIDTH=1,PROBE811_MU_CNT=1,PROBE812_WIDTH=1,PROBE812_MU_CNT=1,PROBE813_WIDTH=1,PROBE813_MU_CNT=1,PROBE814_WIDTH=1,PROBE814_MU_CNT=1,PROBE815_WIDTH=1,PROBE815_MU_CNT=1,PROBE816_WIDTH=1,PROBE816_MU_CNT=1,PROBE817_WIDTH=1,PROBE817_MU_CNT=1,PROBE818_WIDTH=1,PROBE818_MU_CNT=1,PROBE819_WIDTH=1,PROBE819_MU_CNT=1,PROBE820_WIDTH=1,PROBE820_MU_CNT=1,PROBE821_WIDTH=1,PROBE821_MU_CNT=1,PROBE822_WIDTH=1,PROBE822_MU_CNT=1,PROBE823_WIDTH=1,PROBE823_MU_CNT=1,PROBE824_WIDTH=1,PROBE824_MU_CNT=1,PROBE825_WIDTH=1,PROBE825_MU_CNT=1,PROBE826_WIDTH=1,PROBE826_MU_CNT=1,PROBE827_WIDTH=1,PROBE827_MU_CNT=1,PROBE828_WIDTH=1,PROBE828_MU_CNT=1,PROBE829_WIDTH=1,PROBE829_MU_CNT=1,PROBE830_WIDTH=1,PROBE830_MU_CNT=1,PROBE831_WIDTH=1,PROBE831_MU_CNT=1,PROBE832_WIDTH=1,PROBE832_MU_CNT=1,PROBE833_WIDTH=1,PROBE833_MU_CNT=1,PROBE834_WIDTH=1,PROBE834_MU_CNT=1,PROBE835_WIDTH=1,PROBE835_MU_CNT=1,PROBE836_WIDTH=1,PROBE836_MU_CNT=1,PROBE837_WIDTH=1,PROBE837_MU_CNT=1,PROBE838_WIDTH=1,PROBE838_MU_CNT=1,PROBE839_WIDTH=1,PROBE839_MU_CNT=1,PROBE840_WIDTH=1,PROBE840_MU_CNT=1,PROBE841_WIDTH=1,PROBE841_MU_CNT=1,PROBE842_WIDTH=1,PROBE842_MU_CNT=1,PROBE843_WIDTH=1,PROBE843_MU_CNT=1,PROBE844_WIDTH=1,PROBE844_MU_CNT=1,PROBE845_WIDTH=1,PROBE845_MU_CNT=1,PROBE846_WIDTH=1,PROBE846_MU_CNT=1,PROBE847_WIDTH=1,PROBE847_MU_CNT=1,PROBE848_WIDTH=1,PROBE848_MU_CNT=1,PROBE849_WIDTH=1,PROBE849_MU_CNT=1,PROBE850_WIDTH=1,PROBE850_MU_CNT=1,PROBE851_WIDTH=1,PROBE851_MU_CNT=1,PROBE852_WIDTH=1,PROBE852_MU_CNT=1,PROBE853_WIDTH=1,PROBE853_MU_CNT=1,PROBE854_WIDTH=1,PROBE854_MU_CNT=1,PROBE855_WIDTH=1,PROBE855_MU_CNT=1,PROBE856_WIDTH=1,PROBE856_MU_CNT=1,PROBE857_WIDTH=1,PROBE857_MU_CNT=1,PROBE858_WIDTH=1,PROBE858_MU_CNT=1,PROBE859_WIDTH=1,PROBE859_MU_CNT=1,PROBE860_WIDTH=1,PROBE860_MU_CNT=1,PROBE861_WIDTH=1,PROBE861_MU_CNT=1,PROBE862_WIDTH=1,PROBE862_MU_CNT=1,PROBE863_WIDTH=1,PROBE863_MU_CNT=1,PROBE864_WIDTH=1,PROBE864_MU_CNT=1,PROBE865_WIDTH=1,PROBE865_MU_CNT=1,PROBE866_WIDTH=1,PROBE866_MU_CNT=1,PROBE867_WIDTH=1,PROBE867_MU_CNT=1,PROBE868_WIDTH=1,PROBE868_MU_CNT=1,PROBE869_WIDTH=1,PROBE869_MU_CNT=1,PROBE870_WIDTH=1,PROBE870_MU_CNT=1,PROBE871_WIDTH=1,PROBE871_MU_CNT=1,PROBE872_WIDTH=1,PROBE872_MU_CNT=1,PROBE873_WIDTH=1,PROBE873_MU_CNT=1,PROBE874_WIDTH=1,PROBE874_MU_CNT=1,PROBE875_WIDTH=1,PROBE875_MU_CNT=1,PROBE876_WIDTH=1,PROBE876_MU_CNT=1,PROBE877_WIDTH=1,PROBE877_MU_CNT=1,PROBE878_WIDTH=1,PROBE878_MU_CNT=1,PROBE879_WIDTH=1,PROBE879_MU_CNT=1,PROBE880_WIDTH=1,PROBE880_MU_CNT=1,PROBE881_WIDTH=1,PROBE881_MU_CNT=1,PROBE882_WIDTH=1,PROBE882_MU_CNT=1,PROBE883_WIDTH=1,PROBE883_MU_CNT=1,PROBE884_WIDTH=1,PROBE884_MU_CNT=1,PROBE885_WIDTH=1,PROBE885_MU_CNT=1,PROBE886_WIDTH=1,PROBE886_MU_CNT=1,PROBE887_WIDTH=1,PROBE887_MU_CNT=1,PROBE888_WIDTH=1,PROBE888_MU_CNT=1,PROBE889_WIDTH=1,PROBE889_MU_CNT=1,PROBE890_WIDTH=1,PROBE890_MU_CNT=1,PROBE891_WIDTH=1,PROBE891_MU_CNT=1,PROBE892_WIDTH=1,PROBE892_MU_CNT=1,PROBE893_WIDTH=1,PROBE893_MU_CNT=1,PROBE894_WIDTH=1,PROBE894_MU_CNT=1,PROBE895_WIDTH=1,PROBE895_MU_CNT=1,PROBE896_WIDTH=1,PROBE896_MU_CNT=1,PROBE897_WIDTH=1,PROBE897_MU_CNT=1,PROBE898_WIDTH=1,PROBE898_MU_CNT=1,PROBE899_WIDTH=1,PROBE899_MU_CNT=1,PROBE900_WIDTH=1,PROBE900_MU_CNT=1,PROBE901_WIDTH=1,PROBE901_MU_CNT=1,PROBE902_WIDTH=1,PROBE902_MU_CNT=1,PROBE903_WIDTH=1,PROBE903_MU_CNT=1,PROBE904_WIDTH=1,PROBE904_MU_CNT=1,PROBE905_WIDTH=1,PROBE905_MU_CNT=1,PROBE906_WIDTH=1,PROBE906_MU_CNT=1,PROBE907_WIDTH=1,PROBE907_MU_CNT=1,PROBE908_WIDTH=1,PROBE908_MU_CNT=1,PROBE909_WIDTH=1,PROBE909_MU_CNT=1,PROBE910_WIDTH=1,PROBE910_MU_CNT=1,PROBE911_WIDTH=1,PROBE911_MU_CNT=1,PROBE912_WIDTH=1,PROBE912_MU_CNT=1,PROBE913_WIDTH=1,PROBE913_MU_CNT=1,PROBE914_WIDTH=1,PROBE914_MU_CNT=1,PROBE915_WIDTH=1,PROBE915_MU_CNT=1,PROBE916_WIDTH=1,PROBE916_MU_CNT=1,PROBE917_WIDTH=1,PROBE917_MU_CNT=1,PROBE918_WIDTH=1,PROBE918_MU_CNT=1,PROBE919_WIDTH=1,PROBE919_MU_CNT=1,PROBE920_WIDTH=1,PROBE920_MU_CNT=1,PROBE921_WIDTH=1,PROBE921_MU_CNT=1,PROBE922_WIDTH=1,PROBE922_MU_CNT=1,PROBE923_WIDTH=1,PROBE923_MU_CNT=1,PROBE924_WIDTH=1,PROBE924_MU_CNT=1,PROBE925_WIDTH=1,PROBE925_MU_CNT=1,PROBE926_WIDTH=1,PROBE926_MU_CNT=1,PROBE927_WIDTH=1,PROBE927_MU_CNT=1,PROBE928_WIDTH=1,PROBE928_MU_CNT=1,PROBE929_WIDTH=1,PROBE929_MU_CNT=1,PROBE930_WIDTH=1,PROBE930_MU_CNT=1,PROBE931_WIDTH=1,PROBE931_MU_CNT=1,PROBE932_WIDTH=1,PROBE932_MU_CNT=1,PROBE933_WIDTH=1,PROBE933_MU_CNT=1,PROBE934_WIDTH=1,PROBE934_MU_CNT=1,PROBE935_WIDTH=1,PROBE935_MU_CNT=1,PROBE936_WIDTH=1,PROBE936_MU_CNT=1,PROBE937_WIDTH=1,PROBE937_MU_CNT=1,PROBE938_WIDTH=1,PROBE938_MU_CNT=1,PROBE939_WIDTH=1,PROBE939_MU_CNT=1,PROBE940_WIDTH=1,PROBE940_MU_CNT=1,PROBE941_WIDTH=1,PROBE941_MU_CNT=1,PROBE942_WIDTH=1,PROBE942_MU_CNT=1,PROBE943_WIDTH=1,PROBE943_MU_CNT=1,PROBE944_WIDTH=1,PROBE944_MU_CNT=1,PROBE945_WIDTH=1,PROBE945_MU_CNT=1,PROBE946_WIDTH=1,PROBE946_MU_CNT=1,PROBE947_WIDTH=1,PROBE947_MU_CNT=1,PROBE948_WIDTH=1,PROBE948_MU_CNT=1,PROBE949_WIDTH=1,PROBE949_MU_CNT=1,PROBE950_WIDTH=1,PROBE950_MU_CNT=1,PROBE951_WIDTH=1,PROBE951_MU_CNT=1,PROBE952_WIDTH=1,PROBE952_MU_CNT=1,PROBE953_WIDTH=1,PROBE953_MU_CNT=1,PROBE954_WIDTH=1,PROBE954_MU_CNT=1,PROBE955_WIDTH=1,PROBE955_MU_CNT=1,PROBE956_WIDTH=1,PROBE956_MU_CNT=1,PROBE957_WIDTH=1,PROBE957_MU_CNT=1,PROBE958_WIDTH=1,PROBE958_MU_CNT=1,PROBE959_WIDTH=1,PROBE959_MU_CNT=1,PROBE960_WIDTH=1,PROBE960_MU_CNT=1,PROBE961_WIDTH=1,PROBE961_MU_CNT=1,PROBE962_WIDTH=1,PROBE962_MU_CNT=1,PROBE963_WIDTH=1,PROBE963_MU_CNT=1,PROBE964_WIDTH=1,PROBE964_MU_CNT=1,PROBE965_WIDTH=1,PROBE965_MU_CNT=1,PROBE966_WIDTH=1,PROBE966_MU_CNT=1,PROBE967_WIDTH=1,PROBE967_MU_CNT=1,PROBE968_WIDTH=1,PROBE968_MU_CNT=1,PROBE969_WIDTH=1,PROBE969_MU_CNT=1,PROBE970_WIDTH=1,PROBE970_MU_CNT=1,PROBE971_WIDTH=1,PROBE971_MU_CNT=1,PROBE972_WIDTH=1,PROBE972_MU_CNT=1,PROBE973_WIDTH=1,PROBE973_MU_CNT=1,PROBE974_WIDTH=1,PROBE974_MU_CNT=1,PROBE975_WIDTH=1,PROBE975_MU_CNT=1,PROBE976_WIDTH=1,PROBE976_MU_CNT=1,PROBE977_WIDTH=1,PROBE977_MU_CNT=1,PROBE978_WIDTH=1,PROBE978_MU_CNT=1,PROBE979_WIDTH=1,PROBE979_MU_CNT=1,PROBE980_WIDTH=1,PROBE980_MU_CNT=1,PROBE981_WIDTH=1,PROBE981_MU_CNT=1,PROBE982_WIDTH=1,PROBE982_MU_CNT=1,PROBE983_WIDTH=1,PROBE983_MU_CNT=1,PROBE984_WIDTH=1,PROBE984_MU_CNT=1,PROBE985_WIDTH=1,PROBE985_MU_CNT=1,PROBE986_WIDTH=1,PROBE986_MU_CNT=1,PROBE987_WIDTH=1,PROBE987_MU_CNT=1,PROBE988_WIDTH=1,PROBE988_MU_CNT=1,PROBE989_WIDTH=1,PROBE989_MU_CNT=1,PROBE990_WIDTH=1,PROBE990_MU_CNT=1,PROBE991_WIDTH=1,PROBE991_MU_CNT=1,PROBE992_WIDTH=1,PROBE992_MU_CNT=1,PROBE993_WIDTH=1,PROBE993_MU_CNT=1,PROBE994_WIDTH=1,PROBE994_MU_CNT=1,PROBE995_WIDTH=1,PROBE995_MU_CNT=1,PROBE996_WIDTH=1,PROBE996_MU_CNT=1,PROBE997_WIDTH=1,PROBE997_MU_CNT=1,PROBE998_WIDTH=1,PROBE998_MU_CNT=1,PROBE999_WIDTH=1,PROBE999_MU_CNT=1,PROBE1000_WIDTH=1,PROBE1000_MU_CNT=1,PROBE1001_WIDTH=1,PROBE1001_MU_CNT=1,PROBE1002_WIDTH=1,PROBE1002_MU_CNT=1,PROBE1003_WIDTH=1,PROBE1003_MU_CNT=1,PROBE1004_WIDTH=1,PROBE1004_MU_CNT=1,PROBE1005_WIDTH=1,PROBE1005_MU_CNT=1,PROBE1006_WIDTH=1,PROBE1006_MU_CNT=1,PROBE1007_WIDTH=1,PROBE1007_MU_CNT=1,PROBE1008_WIDTH=1,PROBE1008_MU_CNT=1,PROBE1009_WIDTH=1,PROBE1009_MU_CNT=1,PROBE1010_WIDTH=1,PROBE1010_MU_CNT=1,PROBE1011_WIDTH=1,PROBE1011_MU_CNT=1,PROBE1012_WIDTH=1,PROBE1012_MU_CNT=1,PROBE1013_WIDTH=1,PROBE1013_MU_CNT=1,PROBE1014_WIDTH=1,PROBE1014_MU_CNT=1,PROBE1015_WIDTH=1,PROBE1015_MU_CNT=1,PROBE1016_WIDTH=1,PROBE1016_MU_CNT=1,PROBE1017_WIDTH=1,PROBE1017_MU_CNT=1,PROBE1018_WIDTH=1,PROBE1018_MU_CNT=1,PROBE1019_WIDTH=1,PROBE1019_MU_CNT=1,PROBE1020_WIDTH=1,PROBE1020_MU_CNT=1,PROBE1021_WIDTH=1,PROBE1021_MU_CNT=1,PROBE1022_WIDTH=1,PROBE1022_MU_CNT=1,PROBE1023_WIDTH=1,PROBE1023_MU_CNT=1 + kintex7 + AXI4 + 1 + 0 + 12 + 1024 + 2013 + 3 + 4 + 0 + 1 + 0 + 0 + 0 + kintex7 + xc7k325t + ffg900 + -2 + C + + VHDL + MIXED + TRUE + TRUE + xilinx.com:kc705:part0:0.9 + TRUE + 2014.3 + 0 + OUT_OF_CONTEXT + + . + . + + + + Index: experimental_jumbo_frames_version/fpga/src/kc705/ten_gig_eth/ten_gig_eth_pcs_pma_0.xci =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/ten_gig_eth/ten_gig_eth_pcs_pma_0.xci (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/ten_gig_eth/ten_gig_eth_pcs_pma_0.xci (revision 22) @@ -0,0 +1,61 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ten_gig_eth_pcs_pma_0 + + + ten_gig_eth_pcs_pma_0 + false + BASE-R + 64bit + GTHE3 + false + false + false + None + Time_of_day + 1 + true + X0Y0 + clk0 + kintex7 + ten_gig_eth_pcs_pma_0 + false + false + false + false + false + false + 0 + 0 + 32 + ten_gig_eth_pcs_pma_0_gt + X0Y0 + clk0 + kintex7 + xc7k325t + ffg900 + -2 + C + + VHDL + MIXED + TRUE + TRUE + xilinx.com:kc705:part0:0.9 + TRUE + 2014.3 + 0 + OUT_OF_CONTEXT + + . + . + + + + Index: experimental_jumbo_frames_version/fpga/src/kc705/kc705_fade_top.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/kc705_fade_top.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/kc705_fade_top.vhd (revision 22) @@ -0,0 +1,665 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +entity kc705_10g_2 is + + port ( + gtx10g_txn : out std_logic; + gtx10g_txp : out std_logic; + gtx10g_rxn : in std_logic; + gtx10g_rxp : in std_logic; + gtx_refclk_n : in std_logic; + gtx_refclk_p : in std_logic; + --xgmii_txd : in std_logic_vector(63 downto 0); + --xgmii_txc : in std_logic_vector(7 downto 0); + --xgmii_rxd : out std_logic_vector(63 downto 0); + --xgmii_rxc : out std_logic_vector(7 downto 0); + txusrclk_out : out std_logic; + txusrclk2_out : out std_logic; + resetdone : out std_logic; + core_ready : out std_logic; + trig_ack : out std_logic; + led5 : out std_logic; + clk_2 : in std_logic; + start : in std_logic; + rst_p : in std_logic); + +end kc705_10g_2; + +architecture beh1 of kc705_10g_2 is + + signal heart_bit : integer := 0; + + signal refclk_p : std_logic := '0'; + signal refclk_n : std_logic := '0'; + signal reset : std_logic := '0'; + signal s_resetdone : std_logic := '0'; + signal core_clk156_out : std_logic := '0'; + signal txp : std_logic := '0'; + signal txn : std_logic := '0'; + signal rxp : std_logic := '0'; + signal rxn : std_logic := '0'; + signal dclk_out : std_logic := '0'; + signal s_txusrclk_out : std_logic := '0'; + signal s_txusrclk2_out : std_logic := '0'; + signal areset_clk156_out : std_logic := '0'; + signal gttxreset_out : std_logic := '0'; + signal gtrxreset_out : std_logic := '0'; + signal txuserrdy_out : std_logic := '0'; + signal reset_counter_done_out : std_logic := '0'; + signal qplllock_out : std_logic := '0'; + signal qplloutclk_out : std_logic := '0'; + signal qplloutrefclk_out : std_logic := '0'; + signal xgmii_txd : std_logic_vector(63 downto 0) := (others => '0'); + signal xgmii_txc : std_logic_vector(7 downto 0) := (others => '0'); + signal xgmii_rxd : std_logic_vector(63 downto 0) := (others => '0'); + signal xgmii_rxc : std_logic_vector(7 downto 0) := (others => '0'); + signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0'); + signal status_vector : std_logic_vector(447 downto 0) := (others => '0'); + signal core_status : std_logic_vector(7 downto 0) := (others => '0'); + signal signal_detect : std_logic := '0'; + signal tx_fault : std_logic := '0'; + signal drp_req : std_logic := '0'; + signal drp_gnt : std_logic := '0'; + signal drp_den_o : std_logic := '0'; + signal drp_dwe_o : std_logic := '0'; + signal drp_daddr_o : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_di_o : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_drdy_o : std_logic := '0'; + signal drp_drpdo_o : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_den_i : std_logic := '0'; + signal drp_dwe_i : std_logic := '0'; + signal drp_daddr_i : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_di_i : std_logic_vector(15 downto 0) := (others => '0'); + signal drp_drdy_i : std_logic := '0'; + signal drp_drpdo_i : std_logic_vector(15 downto 0) := (others => '0'); + signal tx_disable : std_logic := '0'; + + signal counter : integer := 0; + signal probe2 : std_logic_vector(2 downto 0); + signal trig_in, trig_in_ack : std_logic := '0'; + signal rst_n, rst1, clk1 : std_logic := '0'; + signal hb_led : std_logic := '0'; + signal s_led5 : std_logic := '0'; + + -- Signals associated with the FADE core + signal my_mac : std_logic_vector(47 downto 0); + signal sender : std_logic_vector(47 downto 0); + signal peer_mac : std_logic_vector(47 downto 0); + constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; + signal transm_delay : unsigned(31 downto 0); + signal restart : std_logic; + signal fade_rst_n, fade_rst_del : std_logic := '0'; + signal fade_rst_p : std_logic; + + signal test_dta : unsigned(63 downto 0); + signal dta : std_logic_vector(63 downto 0); + signal s_dta_we, dta_we : std_logic := '0'; + signal dta_ready : std_logic; + signal snd_start : std_logic; + signal flushed : std_logic := '0'; + signal dta_eod : std_logic := '0'; + signal snd_ready : std_logic; + signal clk_user : std_logic; + signal dmem_we : std_logic; + signal dmem_addr : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + signal dmem_dta : std_logic_vector(63 downto 0); + signal tx_mem_addr : std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + signal tx_mem_data : std_logic_vector(63 downto 0); + signal pkt_number : unsigned(31 downto 0); + signal seq_number : unsigned(15 downto 0) := (others => '0'); + signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); + -- signals related to user commands handling + signal cmd_response_in, cmd_response_out : std_logic_vector(12*8-1 downto 0) := (others => '0'); + signal cmd_start : std_logic := '0'; + signal cmd_run : std_logic := '0'; + signal cmd_retr_s : std_logic := '0'; + signal cmd_ack : std_logic := '0'; + signal cmd_code : std_logic_vector(15 downto 0) := (others => '0'); + signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0'); + signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0'); + + + -- debug signals + signal dbg : std_logic_vector(3 downto 0); + signal rx_crc : std_logic_vector(31 downto 0); + signal rx_cmd : std_logic_vector(31 downto 0); + signal rx_arg : std_logic_vector(31 downto 0); + + signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); + signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; + signal ack_fifo_dbg : pkt_ack; + signal transmit_data, td_del0, td_del1 : std_logic := '0'; + + attribute mark_debug : string; + attribute mark_debug of xgmii_txd : signal is "true"; + attribute mark_debug of xgmii_txc : signal is "true"; + + component ila_1 + port ( + clk : in std_logic; + trig_in : in std_logic; + trig_in_ack : out std_logic; + probe0 : in std_logic_vector(63 downto 0); + probe1 : in std_logic_vector(7 downto 0); + probe2 : in std_logic_vector(2 downto 0); + probe3 : in std_logic_vector(7 downto 0); + probe4 : in std_logic_vector(3 downto 0); + probe5 : in std_logic_vector(31 downto 0); + probe6 : in std_logic_vector(31 downto 0); + probe7 : in std_logic_vector(15 downto 0); + probe8 : in std_logic_vector(31 downto 0); + probe9 : in std_logic_vector(31 downto 0); + probe10 : in std_logic_vector(63 downto 0); + probe11 : in std_logic_vector(7 downto 0) + ); + end component; + +component ten_gig_eth_pcs_pma_0 is + port ( + dclk : in STD_LOGIC; + refclk_p : in STD_LOGIC; + refclk_n : in STD_LOGIC; + sim_speedup_control : in STD_LOGIC; + core_clk156_out : out STD_LOGIC; + qplloutclk_out : out STD_LOGIC; + qplloutrefclk_out : out STD_LOGIC; + qplllock_out : out STD_LOGIC; + txusrclk_out : out STD_LOGIC; + txusrclk2_out : out STD_LOGIC; + areset_clk156_out : out STD_LOGIC; + gttxreset_out : out STD_LOGIC; + gtrxreset_out : out STD_LOGIC; + txuserrdy_out : out STD_LOGIC; + reset_counter_done_out : out STD_LOGIC; + reset : in STD_LOGIC; + gt0_eyescanreset : in STD_LOGIC; + gt0_eyescantrigger : in STD_LOGIC; + gt0_rxcdrhold : in STD_LOGIC; + gt0_txprbsforceerr : in STD_LOGIC; + gt0_txpolarity : in STD_LOGIC; + gt0_rxpolarity : in STD_LOGIC; + gt0_rxrate : in STD_LOGIC_VECTOR (2 downto 0); + gt0_txpmareset : in STD_LOGIC; + gt0_rxpmareset : in STD_LOGIC; + gt0_rxdfelpmreset : in STD_LOGIC; + gt0_txprecursor : in STD_LOGIC_VECTOR (4 downto 0); + gt0_txpostcursor : in STD_LOGIC_VECTOR (4 downto 0); + gt0_txdiffctrl : in STD_LOGIC_VECTOR (3 downto 0); + gt0_rxlpmen : in STD_LOGIC; + gt0_eyescandataerror : out STD_LOGIC; + gt0_txbufstatus : out STD_LOGIC_VECTOR (1 downto 0); + gt0_txresetdone : out STD_LOGIC; + gt0_rxresetdone : out STD_LOGIC; + gt0_rxbufstatus : out STD_LOGIC_VECTOR (2 downto 0); + gt0_rxprbserr : out STD_LOGIC; + gt0_dmonitorout : out STD_LOGIC_VECTOR (7 downto 0); + xgmii_txd : in STD_LOGIC_VECTOR (63 downto 0); + xgmii_txc : in STD_LOGIC_VECTOR (7 downto 0); + xgmii_rxd : out STD_LOGIC_VECTOR (63 downto 0); + xgmii_rxc : out STD_LOGIC_VECTOR (7 downto 0); + txp : out STD_LOGIC; + txn : out STD_LOGIC; + rxp : in STD_LOGIC; + rxn : in STD_LOGIC; + configuration_vector : in STD_LOGIC_VECTOR (535 downto 0); + status_vector : out STD_LOGIC_VECTOR (447 downto 0); + core_status : out STD_LOGIC_VECTOR (7 downto 0); + resetdone : out STD_LOGIC; + signal_detect : in STD_LOGIC; + tx_fault : in STD_LOGIC; + drp_req : out STD_LOGIC; + drp_gnt : in STD_LOGIC; + drp_den_o : out STD_LOGIC; + drp_dwe_o : out STD_LOGIC; + drp_daddr_o : out STD_LOGIC_VECTOR (15 downto 0); + drp_di_o : out STD_LOGIC_VECTOR (15 downto 0); + drp_drdy_i : in STD_LOGIC; + drp_drpdo_i : in STD_LOGIC_VECTOR (15 downto 0); + drp_den_i : in STD_LOGIC; + drp_dwe_i : in STD_LOGIC; + drp_daddr_i : in STD_LOGIC_VECTOR (15 downto 0); + drp_di_i : in STD_LOGIC_VECTOR (15 downto 0); + drp_drdy_o : out STD_LOGIC; + drp_drpdo_o : out STD_LOGIC_VECTOR (15 downto 0); + pma_pmd_type : in STD_LOGIC_VECTOR (2 downto 0); + tx_disable : out STD_LOGIC); +end component ten_gig_eth_pcs_pma_0; + + component eth_receiver is + port ( + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + clk : in std_logic; + rst_n : in std_logic; + dbg : out std_logic_vector(3 downto 0); + crc : out std_logic_vector(31 downto 0); + cmd : out std_logic_vector(31 downto 0); + arg : out std_logic_vector(31 downto 0); + Rx_Clk : in std_logic; + RxC : in std_logic_vector(7 downto 0); + RxD : in std_logic_vector(63 downto 0)); + end component eth_receiver; + + component eth_sender is + port ( + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + pkt_number : in unsigned(31 downto 0); + seq_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic; + ready : out std_logic; + flushed : in std_logic; + start : in std_logic; + cmd_start : in std_logic; + tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + tx_mem_data : in std_logic_vector(63 downto 0); + cmd_response : in std_logic_vector(12*8-1 downto 0); + Tx_Clk : in std_logic; + TxC : out std_logic_vector(7 downto 0); + TxD : out std_logic_vector(63 downto 0)); + end component eth_sender; + + component dp_ram_scl + generic ( + DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + clk_a : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + clk_b : in std_logic; + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); + end component; + + component ack_fifo + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(pkt_ack_width-1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(pkt_ack_width-1 downto 0); + full : out std_logic; + empty : out std_logic); + end component; + + component cmd_proc is + port ( + cmd_code : in std_logic_vector(15 downto 0); + cmd_seq : in std_logic_vector(15 downto 0); + cmd_arg : in std_logic_vector(31 downto 0); + cmd_run : in std_logic; + cmd_ack : out std_logic; + cmd_response : out std_logic_vector(8*12-1 downto 0); + clk : in std_logic; + rst_p : in std_logic); + end component cmd_proc; + + component desc_manager is + generic ( + LOG2_N_OF_PKTS : integer; + N_OF_PKTS : integer); + port ( + dta : in std_logic_vector(63 downto 0); + dta_we : in std_logic; + dta_ready : out std_logic; + dta_eod : in std_logic; + pkt_number : out unsigned(31 downto 0); + seq_number : out unsigned(15 downto 0); + cmd_response_out : out std_logic_vector(12*8-1 downto 0); + snd_cmd_start : out std_logic; + snd_start : out std_logic; + snd_ready : in std_logic; + flushed : out std_logic; + dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); + dmem_dta : out std_logic_vector(63 downto 0); + dmem_we : out std_logic; + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + cmd_code : out std_logic_vector(15 downto 0); + cmd_seq : out std_logic_vector(15 downto 0); + cmd_arg : out std_logic_vector(31 downto 0); + cmd_run : out std_logic; + cmd_retr_s : out std_logic; + cmd_ack : in std_logic; + cmd_response_in : in std_logic_vector(8*12-1 downto 0); + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + dbg : out std_logic_vector(3 downto 0); + clk : in std_logic; + rst_n : in std_logic); + end component desc_manager; + +begin -- beh1 + my_mac <= x"de_ad_ba_be_be_ef"; + -- Initialization vector + configuration_vector(33) <= '1'; -- training + configuration_vector(284) <= '1'; -- auto negotiation + + signal_detect <= '1'; -- allow transmission! + + rst_n <= not rst_p; + refclk_n <= gtx_refclk_n; + refclk_p <= gtx_refclk_p; + reset <= not rst_n; + + rx_crc <= std_logic_vector(pkt_number); -- To be removed! + + trig_in <= '1' when xgmii_rxc /= x"ff" else '0'; + + + ila_0_1 : ila_1 + port map ( + clk => clk1, + trig_in => trig_in, + trig_in_ack => trig_ack, + probe0 => xgmii_rxd, + probe1 => xgmii_rxc, + probe2 => probe2, + probe3 => core_status, + probe4 => dbg, + probe5 => rx_crc, + probe6 => std_logic_vector(ack_fifo_dbg.pkt), + probe7 => std_logic_vector(ack_fifo_dbg.cmd), + probe8 => rx_cmd, + probe9 => rx_arg, + probe10 => xgmii_txd, + probe11 => xgmii_txc + ); + + probe2(0) <= cmd_run; + probe2(1) <= cmd_ack; + probe2(2) <= cmd_retr_s; + ack_fifo_dbg <= stlv_to_pkt_ack(ack_fifo_din); + + ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0 + + port map ( + dclk => clk_user, + sim_speedup_control => '0', + refclk_p => refclk_p, + refclk_n => refclk_n, + reset => reset, + resetdone => s_resetdone, + core_clk156_out => core_clk156_out, + txp => gtx10g_txp, + txn => gtx10g_txn, + rxp => gtx10g_rxp, + rxn => gtx10g_rxn, + txusrclk_out => s_txusrclk_out, + txusrclk2_out => s_txusrclk2_out, + areset_clk156_out => areset_clk156_out, + gttxreset_out => gttxreset_out, + gtrxreset_out => gtrxreset_out, + txuserrdy_out => txuserrdy_out, + reset_counter_done_out => reset_counter_done_out, + qplllock_out => qplllock_out, + qplloutclk_out => qplloutclk_out, + qplloutrefclk_out => qplloutrefclk_out, + xgmii_txd => xgmii_txd, + xgmii_txc => xgmii_txc, + xgmii_rxd => xgmii_rxd, + xgmii_rxc => xgmii_rxc, + configuration_vector => configuration_vector, + status_vector => status_vector, + core_status => core_status, + signal_detect => signal_detect, + tx_fault => tx_fault, + drp_req => drp_req, + drp_gnt => drp_gnt, + drp_den_o => drp_den_o, + drp_dwe_o => drp_dwe_o, + drp_daddr_o => drp_daddr_o, + drp_di_o => drp_di_o, + drp_drdy_o => drp_drdy_o, + drp_drpdo_o => drp_drpdo_o, + drp_den_i => drp_den_i, + drp_dwe_i => drp_dwe_i, + drp_daddr_i => drp_daddr_i, + drp_di_i => drp_di_i, + drp_drdy_i => drp_drdy_i, + drp_drpdo_i => drp_drpdo_i, + tx_disable => tx_disable, + pma_pmd_type => "111", + gt0_eyescanreset => '0', + gt0_eyescandataerror => open, + gt0_txbufstatus => open, + gt0_rxbufstatus => open, + gt0_eyescantrigger => '0', + gt0_rxcdrhold => '0', + gt0_txprbsforceerr => '0', + gt0_txpolarity => '1', + gt0_rxpolarity => '1', + gt0_rxprbserr => open, + gt0_txpmareset => '0', + gt0_rxpmareset => '0', + gt0_txresetdone => open, + gt0_rxresetdone => open, + gt0_rxdfelpmreset => '0', + gt0_rxlpmen => '0', + gt0_dmonitorout => open, + gt0_rxrate => (others => '0'), + gt0_txprecursor => (others => '0'), + gt0_txpostcursor => (others => '0'), + gt0_txdiffctrl => "1110" + + ); + + drp_gnt <= drp_req; + drp_den_i <= drp_den_o; + drp_dwe_i <= drp_dwe_o; + drp_daddr_i <= drp_daddr_o; + drp_di_i <= drp_di_o; + drp_drpdo_i <= drp_drpdo_o; + + txusrclk_out <= rst_n; --s_txusrclk_out; + resetdone <= hb_led; --s_resetdone; + + rst1 <= core_status(0); + core_ready <= core_status(0); + clk1 <= core_clk156_out; + clk_user <= core_clk156_out; + + + + p1 : process (clk1, rst_n) + begin -- process p1 + if rst_n = '0' then -- asynchronous reset (active low) + heart_bit <= 0; + elsif clk1'event and clk1 = '1' then -- rising clock edge + if heart_bit < 80000000 then + heart_bit <= heart_bit + 1; + else + heart_bit <= 0; + hb_led <= not hb_led; + end if; + end if; + end process p1; + + --addr_a <= to_integer(unsigned(dmem_addr)); + --addr_b <= to_integer(unsigned(tx_mem_addr)); + + dp_ram_scl_1 : dp_ram_scl + generic map ( + DATA_WIDTH => 64, + ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT) + port map ( + clk_a => clk_user, + we_a => dmem_we, + addr_a => dmem_addr, + data_a => dmem_dta, + q_a => open, + clk_b => clk1, + we_b => '0', + addr_b => tx_mem_addr, + data_b => (others => '0'), + q_b => tx_mem_data); + + desc_manager_1 : desc_manager + generic map ( + LOG2_N_OF_PKTS => LOG2_N_OF_PKTS, + N_OF_PKTS => N_OF_PKTS) + port map ( + dta => dta, + dta_we => dta_we, + dta_eod => dta_eod, + dta_ready => dta_ready, + pkt_number => pkt_number, + seq_number => seq_number, + cmd_response_out => cmd_response_out, + snd_cmd_start => cmd_start, + snd_start => snd_start, + flushed => flushed, + snd_ready => snd_ready, + dmem_addr => dmem_addr, + dmem_dta => dmem_dta, + dmem_we => dmem_we, + ack_fifo_empty => ack_fifo_empty, + ack_fifo_rd_en => ack_fifo_rd_en, + ack_fifo_dout => ack_fifo_dout, + cmd_code => cmd_code, + cmd_seq => cmd_seq, + cmd_arg => cmd_arg, + cmd_run => cmd_run, + cmd_retr_s => cmd_retr_s, + cmd_ack => cmd_ack, + cmd_response_in => cmd_response_in, + transmit_data => transmit_data, + transm_delay => transm_delay, + dbg => dbg, + clk => clk_user, + rst_n => fade_rst_n); + + cmd_proc_1 : cmd_proc + port map ( + cmd_code => cmd_code, + cmd_seq => cmd_seq, + cmd_arg => cmd_arg, + cmd_run => cmd_run, + cmd_ack => cmd_ack, + cmd_response => cmd_response_in, + clk => clk_user, + rst_p => fade_rst_p); + + eth_sender_1 : eth_sender + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + pkt_number => pkt_number, + seq_number => seq_number, + transm_delay => transm_delay, + clk => clk_user, + rst_n => fade_rst_n, + ready => snd_ready, + flushed => flushed, + start => snd_start, + cmd_start => cmd_start, + tx_mem_addr => tx_mem_addr, + tx_mem_data => tx_mem_data, + cmd_response => cmd_response_out, + Tx_Clk => clk1, + TxC => xgmii_txc, + TxD => xgmii_txd); + + eth_receiver_2 : eth_receiver + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + transmit_data => transmit_data, + restart => restart, + ack_fifo_full => ack_fifo_full, + ack_fifo_wr_en => ack_fifo_wr_en, + ack_fifo_din => ack_fifo_din, + clk => clk_user, + rst_n => fade_rst_n, + dbg => open, + cmd => rx_cmd, + arg => rx_arg, + Rx_Clk => clk1, + RxC => xgmii_rxc, + RxD => xgmii_rxd); + + ack_fifo_1 : ack_fifo + port map ( + rst => fade_rst_p, + wr_clk => clk1, + rd_clk => Clk_user, + din => ack_fifo_din, + wr_en => ack_fifo_wr_en, + rd_en => ack_fifo_rd_en, + dout => ack_fifo_dout, + full => ack_fifo_full, + empty => ack_fifo_empty); + + + -- signal generator + + s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; + + dta_we <= s_dta_we; + + dta <= std_logic_vector(test_dta); + + process (Clk_user, rst_n) + begin -- process + if fade_rst_n = '0' then -- asynchronous reset (active low) + test_dta <= (others => '0'); + td_del0 <= '0'; + td_del1 <= '0'; + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if s_dta_we = '1' then + test_dta <= test_dta + x"1234567809abcdef"; + end if; + -- Generate the dta_eod pulse after transmit_data + -- goes low + td_del0 <= transmit_data; + td_del1 <= td_del0; + if (td_del1 = '1') and (td_del0 = '0') then + dta_eod <= '1'; + else + dta_eod <= '0'; + end if; + end if; + end process; + + process (Clk_user, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + fade_rst_n <= '0'; + fade_rst_del <= '0'; + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if restart = '1' then + fade_rst_n <= '0'; + fade_rst_del <= '0'; + else + fade_rst_del <= '1'; + fade_rst_n <= fade_rst_del; + end if; + end if; + end process; + + fade_rst_p <= not fade_rst_n; + +end beh1; Index: experimental_jumbo_frames_version/fpga/src/kc705/eth_sender64.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/eth_sender64.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/eth_sender64.vhd (revision 22) @@ -0,0 +1,399 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block sending packets via XGMII Phy +-- Project : +------------------------------------------------------------------------------- +-- File : eth_sender64.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-10-12 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.desc_mgr_pkg.all; +use work.pkg_newcrc32_d64.all; + +entity eth_sender is + + port ( + -- Configuration + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + pkt_number : in unsigned(31 downto 0); + seq_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + -- Control interface + ready : out std_logic; + flushed : in std_logic; + start : in std_logic; + cmd_start : in std_logic; + -- Data memory interface + tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + tx_mem_data : in std_logic_vector(63 downto 0); + -- User command response interface + cmd_response : in std_logic_vector(12*8-1 downto 0); + -- TX Phy interface + Tx_Clk : in std_logic; + TxC : out std_logic_vector(7 downto 0); + TxD : out std_logic_vector(63 downto 0) + ); + +end eth_sender; + + +architecture beh1 of eth_sender is + + type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_PREAMB_AND_SOF, WST_SEND_CMD_HEADER, + WST_SEND_CMD_TRAILER, + WST_SEND_HEADER, WST_SEND_DATA, WST_SEND_CRC_AND_EOF, + WST_SEND_COMPLETED); + + type T_ETH_SENDER_REGS is record + state : T_ETH_SENDER_STATE; + ready : std_logic; + count : integer; + word : integer; + mem_addr : unsigned (LOG2_NWRDS_IN_PKT-1 downto 0); + crc32 : std_logic_vector(31 downto 0); + end record; + + constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := ( + state => WST_IDLE, + ready => '1', + count => 0, + word => 0, + mem_addr => (others => '0'), + crc32 => (others => '0') + ) ; + + signal r, r_n : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI; + + type T_ETH_SENDER_COMB is record + TxD : std_logic_vector(63 downto 0); + TxC : std_logic_vector(7 downto 0); + mem_addr : unsigned(LOG2_NWRDS_IN_PKT-1 downto 0); + end record; + + constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := ( + TxD => x"07_07_07_07_07_07_07_07", + TxC => (others => '1'), + mem_addr => (others => '0') + ); + + signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT; + + signal s_header : std_logic_vector(8*40-1 downto 0) := (others => '0'); + constant HEADER_LEN : integer := 5; -- 5 words, 8 bytes each + signal s_cmd_header : std_logic_vector(8*32-1 downto 0) := (others => '0'); + constant CMD_HEADER_LEN : integer := 4; -- 4 words, 8 bytes each + + signal cmd_only : std_logic := '0'; + + -- The function select_8bytes changes order of bytes, ensuring + -- that the MSB is transmitted first... + + function select_8bytes ( + constant vec : std_logic_vector; + constant chunk_num : integer) + return std_logic_vector is + variable byte_ofs : integer; + variable chunk_ofs : integer; + variable v_bytes : std_logic_vector(63 downto 0); + begin + chunk_ofs := chunk_num*64; + -- first select byte + for byte_num in 0 to 7 loop + byte_ofs := byte_num * 8; + v_bytes(byte_ofs+7 downto byte_ofs) := vec(vec'left-chunk_ofs-byte_ofs downto vec'left-chunk_ofs-byte_ofs-7); + end loop; -- byte_num + return v_bytes; + end select_8bytes; + + + function rev(a : in std_logic_vector) + return std_logic_vector is + variable result : std_logic_vector(a'range); + alias aa : std_logic_vector(a'reverse_range) is a; + begin + for i in aa'range loop + result(i) := aa(i); + end loop; + return result; + end; -- function reverse_any_bus + + signal tx_rst_n, tx_rst_n_0, tx_rst_n_1 : std_logic := '0'; + signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; + + signal start_0, tx_start, tx_start_1, tx_start_0 : std_logic := '0'; + signal tx_ready, ready_0, ready_1 : std_logic := '0'; + + type T_STATE1 is (ST1_IDLE, ST1_WAIT_NOT_READY, ST1_WAIT_NOT_START, + ST1_WAIT_READY); + signal state1 : T_STATE1; + + type T_STATE2 is (ST2_IDLE, ST2_WAIT_NOT_READY, ST2_WAIT_READY); + signal state2 : T_STATE2; + + signal dta_packet_type : std_logic_vector(15 downto 0) := (others => '0'); + +begin -- beh1 + + dta_packet_type <= x"a5a5" when flushed = '0' else x"a5a6"; + -- Headers should contain n*8 bytes + -- Data packet header + s_header <= peer_mac & my_mac & my_ether_type & x"0100" & + dta_packet_type & std_logic_vector(seq_number(15 downto 0)) & + std_logic_vector(pkt_number) & + std_logic_vector(transm_delay) & cmd_response; + -- Command response packet header - we have unused 16 bits in the response packet... + s_cmd_header <= peer_mac & my_mac & my_ether_type & x"0100" & + x"a55a" & x"0000" & cmd_response; + + -- Connection of the signals + + -- The memory address is built from the packet number (6 bits) and word + -- number (8 bits) + tx_mem_addr <= std_logic_vector(pkt_number(LOG2_N_OF_PKTS-1 downto 0)) & std_logic_vector(c.mem_addr); + + -- Main state machine used to send the packet + -- W calej maszynie trzeba jeszcze dodac obsluge kolizji!!! + -- Oprocz tego trzeba przeanalizowac poprawnosc przejsc miedzy domenami zegara + + + snd1 : process (Tx_Clk, tx_rst_n) + begin + if tx_rst_n = '0' then -- asynchronous reset (active low) + r <= ETH_SENDER_REGS_INI; + TxD <= x"07_07_07_07_07_07_07_07"; + TxC <= (others => '1'); + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + r <= r_n; + -- To minimize glitches and propagation delay, let's add pipeline register + TxC <= c.TxC; + TxD <= c.TxD; + end if; + end process snd1; -- snd1 + + snd2 : process (r, s_header, tx_mem_data, tx_start) + variable v_TxD : std_logic_vector(63 downto 0); + begin -- process snd1 + -- default values + c <= ETH_SENDER_COMB_DEFAULT; + r_n <= r; + case r.state is + when WST_IDLE => + c.TxD <= x"07_07_07_07_07_07_07_07"; + c.TxC <= "11111111"; + r_n.ready <= '1'; + if tx_start = '1' then + r_n.ready <= '0'; + r_n.state <= WST_SEND_PREAMB_AND_SOF; + r_n.count <= 7; + end if; + when WST_SEND_PREAMB_AND_SOF => + -- Collision detection should be added? + c.TxD <= x"d5_55_55_55_55_55_55_fb"; + c.TxC <= "00000001"; + -- Prepare for sending of header + r_n.crc32 <= (others => '1'); + if cmd_only = '1' then + r_n.state <= WST_SEND_CMD_HEADER; + else + r_n.state <= WST_SEND_HEADER; + end if; + r_n.count <= 0; + when WST_SEND_CMD_HEADER => + v_TxD := select_8bytes(s_cmd_header, r.count); + c.TxD <= v_TxD; + c.TxC <= (others => '0'); + r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); + if r.count < CMD_HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.word <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_CMD_TRAILER; + end if; + when WST_SEND_CMD_TRAILER => + v_TxD := (others => '0'); + c.TxD <= v_TxD; + c.TxC <= (others => '0'); + r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); + if r.count < 8-CMD_HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.word <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_CRC_AND_EOF; + end if; + when WST_SEND_HEADER => + v_TxD := select_8bytes(s_header, r.count); + c.TxD <= v_TxD; + c.TxC <= (others => '0'); + r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); + if r.count < HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.word <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_DATA; + end if; + when WST_SEND_DATA => + -- send the data byte by byte + v_TxD := select_8bytes(tx_mem_data, 0); + r_n.crc32 <= newcrc32_d64(v_TxD, r.crc32); + c.TxD <= v_TxD; + c.TxC <= (others => '0'); + -- Check, if we have sent all the data + if r.mem_addr < NWRDS_IN_PKT-1 then + r_n.mem_addr <= r.mem_addr + 1; + c.mem_addr <= r.mem_addr + 1; + else + -- We send the CRC + r_n.state <= WST_SEND_CRC_AND_EOF; + end if; + when WST_SEND_CRC_AND_EOF => + -- The CRC should be send starting from the most significant bit, so + -- we don't need to reorder bytes in any way... + -- we only reverse it and complement it + v_TxD := x"07_07_07_fd" & not (rev(r.crc32)); + c.TxD <= v_TxD; + c.TxC <= "11110000"; + r_n.count <= 2; -- generate the IFG - 16 bytes = 2 words + r_n.state <= WST_SEND_COMPLETED; + when WST_SEND_COMPLETED => + c.TxD <= x"07_07_07_07_07_07_07_07"; + c.TxC <= "11111111"; + if r.count > 0 then + r_n.count <= r.count - 1; + else + r_n.ready <= '1'; + r_n.state <= WST_IDLE; + end if; + end case; + end process snd2; + + + -- Synchronization of the reset signal for the Tx_Clk domain + process (Tx_Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + tx_rst_n_0 <= '0'; + tx_rst_n_1 <= '0'; + tx_rst_n <= '0'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + tx_rst_n_0 <= rst_n; + tx_rst_n_1 <= tx_rst_n_0; + tx_rst_n <= tx_rst_n_1; + end if; + end process; + + -- Synchronization of signals passing clock domains + -- Signal start is sent from the Clk domain. + -- When it is asserted, we must immediately deassert signal ready, + -- then generate the synchronized start and after internal ready + -- is asserted, we can output it again... + + -- Ustawienie na 1 takt zegara "clk" sygnalu start powinno zainicjowac wysylanie + -- w tym bloku musimy zadbac o stosowne wydluzenie sygnalu start i jego synchronizacje + -- miedzy domenami zegara... + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + ready <= '0'; + ready_1 <= '0'; + ready_0 <= '0'; + cmd_only <= '0'; + state2 <= ST2_IDLE; + elsif clk'event and clk = '1' then -- rising clock edge + ready_1 <= tx_ready; + ready_0 <= ready_1; + case state2 is + when ST2_IDLE => + if start = '1' and ready_0 = '1' then + start_0 <= '1'; + ready <= '0'; + cmd_only <= '0'; + state2 <= ST2_WAIT_NOT_READY; + elsif cmd_start = '1' and ready_0 = '1' then + start_0 <= '1'; + ready <= '0'; + cmd_only <= '1'; + state2 <= ST2_WAIT_NOT_READY; + else + ready <= ready_0; -- Needed to provide correct start! + end if; + when ST2_WAIT_NOT_READY => + if ready_0 = '0' then + start_0 <= '0'; + state2 <= ST2_WAIT_READY; + end if; + when ST2_WAIT_READY => + if ready_0 = '1' then + ready <= '1'; + state2 <= ST2_IDLE; + end if; + when others => null; + end case; + end if; + end process; + + process (Tx_Clk, tx_rst_n) + begin -- process + if tx_rst_n = '0' then -- asynchronous reset (active low) + tx_start <= '0'; + tx_start_0 <= '0'; + state1 <= ST1_IDLE; + tx_ready <= '1'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + tx_start_0 <= start_0; + tx_start <= tx_start_0; + case state1 is + when ST1_IDLE => + if tx_start = '1' then + tx_ready <= '0'; -- this should cause tx_start to go low + state1 <= ST1_WAIT_NOT_READY; + end if; + when ST1_WAIT_NOT_READY => + if r.ready = '0' then + state1 <= ST1_WAIT_NOT_START; + end if; + when ST1_WAIT_NOT_START => + if tx_start = '0' then + state1 <= ST1_WAIT_READY; + end if; + when ST1_WAIT_READY => + if r.ready = '1' then + tx_ready <= '1'; + state1 <= ST1_IDLE; + end if; + when others => null; + end case; + end if; + end process; + +end beh1; Index: experimental_jumbo_frames_version/fpga/src/kc705/eth_receiver64.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/eth_receiver64.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/eth_receiver64.vhd (revision 22) @@ -0,0 +1,413 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block receiving packets from MII PHY +-- Project : +------------------------------------------------------------------------------- +-- File : eth_receiver4.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-10-12 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, responsible for +-- reception of packets and passing them to the acknowledgements and commands +-- FIFO +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- + +-- Uwaga! Tu mamy rzeczywiste problemy z obsluga odebranych pakietow! +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.desc_mgr_pkg.all; +use work.pkt_ack_pkg.all; +use work.pkg_newcrc32_d64.all; +use work.pkg_newcrc32_d32.all; +use work.pkg_newcrc32_d16.all; + + +entity eth_receiver is + + port ( + -- Configuration + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + -- ACK FIFO interface + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + dbg : out std_logic_vector(3 downto 0); + cmd : out std_logic_vector(31 downto 0); + arg : out std_logic_vector(31 downto 0); + crc : out std_logic_vector(31 downto 0); + -- MAC interface + Rx_Clk : in std_logic; + RxC : in std_logic_vector(7 downto 0); + RxD : in std_logic_vector(63 downto 0) + ); + +end eth_receiver; + + +architecture beh1 of eth_receiver is + + type T_STATE is (ST_RCV_IDLE, ST_RCV_PREAMB, ST_CHECK_PREAMB, + ST_RCV_HEADER1, ST_RCV_HEADER2, ST_RCV_CMD, + ST_RCV_WAIT_IDLE, ST_RCV_ARGS, ST_RCV_PROCESS, ST_RCV_UPDATE, + ST_RCV_TRAILER); + + + + function rev(a : in std_logic_vector) + return std_logic_vector is + variable result : std_logic_vector(a'range); + alias aa : std_logic_vector(a'reverse_range) is a; + begin + for i in aa'range loop + result(i) := aa(i); + end loop; + return result; + end; -- function reverse_any_bus + + constant C_PROTO_ID : std_logic_vector(31 downto 0) := x"fade0100"; + + type T_RCV_REGS is record + state : T_STATE; + swap_lanes : std_logic; + transmit_data : std_logic; + restart : std_logic; + update_flag : std_logic; + count : integer; + dbg : std_logic_vector(3 downto 0); + crc32 : std_logic_vector(31 downto 0); + cmd : std_logic_vector(31 downto 0); + arg : std_logic_vector(31 downto 0); + mac_addr : std_logic_vector(47 downto 0); + peer_mac : std_logic_vector(47 downto 0); + end record; + + constant RCV_REGS_INI : T_RCV_REGS := ( + state => ST_RCV_IDLE, + swap_lanes => '0', + transmit_data => '0', + restart => '0', + update_flag => '0', + count => 0, + dbg => (others => '0'), + crc32 => (others => '0'), + cmd => (others => '0'), + arg => (others => '0'), + mac_addr => (others => '0'), + peer_mac => (others => '0') + ); + + signal r, r_n : T_RCV_REGS := RCV_REGS_INI; + + type T_RCV_COMB is record + ack_fifo_wr_en : std_logic; + Rx_mac_rd : std_logic; + ack_fifo_din : std_logic_vector(pkt_ack_width-1 downto 0); + restart : std_logic; + end record; + + constant RCV_COMB_DEFAULT : T_RCV_COMB := ( + ack_fifo_wr_en => '0', + Rx_mac_rd => '0', + ack_fifo_din => (others => '0'), + restart => '0' + ); + + signal c : T_RCV_COMB := RCV_COMB_DEFAULT; + + signal rxd_sw, rxd_del : std_logic_vector(63 downto 0); + signal rxc_sw, rxc_del : std_logic_vector(7 downto 0); + + signal rx_rst_n, rx_rst_n_0, rx_rst_n_1 : std_logic := '0'; + signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; + +begin -- beh1 + + ack_fifo_din <= c.ack_fifo_din; + ack_fifo_wr_en <= c.ack_fifo_wr_en; + + --dbg <= r.dbg; + crc <= r.crc32; + cmd <= r.cmd; + arg <= r.arg; + -- Lane switcher processes + lsw_c1 : process (RxC, RxC(3 downto 0), RxC_del(7 downto 4), RxD, + RxD(31 downto 0), RxD_del(63 downto 32), r.swap_lanes) is + begin -- process lsw_c1 + if r.swap_lanes = '1' then + RxD_Sw(63 downto 32) <= RxD(31 downto 0); + RxD_Sw(31 downto 0) <= RxD_del(63 downto 32); + RxC_Sw(7 downto 4) <= RxC(3 downto 0); + RxC_Sw(3 downto 0) <= RxC_del(7 downto 4); + else + RxD_Sw <= RxD; + RxC_Sw <= RxC; + end if; + end process lsw_c1; + + process (Rx_Clk, rx_rst_n) is + begin -- process + if rx_rst_n = '0' then -- asynchronous reset (active low) + RxD_del <= (others => '0'); + RxC_del <= (others => '0'); + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + RxD_del <= RxD; + RxC_del <= RxC; + end if; + end process; + + -- Reading of ethernet data + rdp1 : process (Rx_Clk, rx_rst_n) + begin -- process rdp1 + if rx_rst_n = '0' then -- asynchronous reset (active low) + r <= RCV_REGS_INI; + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + r <= r_n; + end if; + end process rdp1; + + rdp2 : process (RxC, RxC_Sw, RxD, RxD_Sw, ack_fifo_full, my_ether_type, + my_mac, r, r.arg(15 downto 10), r.arg(31 downto 16), + r.cmd(15 downto 0), r.cmd(31 downto 16), r.crc32, r.dbg(0), + r.dbg(1), r.dbg(2), r.dbg(3), r.mac_addr, r.state, + r.update_flag) + + variable ack_pkt_in : pkt_ack; + variable v_mac_addr : std_logic_vector(47 downto 0); + variable v_cmd, v_arg : std_logic_vector(31 downto 0); + variable v_crc : std_logic_vector(31 downto 0); + variable v_proto : std_logic_vector(31 downto 0); + + begin -- process + c <= RCV_COMB_DEFAULT; + r_n <= r; + dbg <= "1111"; + case r.state is + when ST_RCV_IDLE => + dbg <= "0000"; + -- We must be prepared to one of two possible events + -- Either we receive the SOF in the 0-th lane (and then we proceed + -- normally) or we receive the SOF in the 4-th lane (and then we have + -- to switch lanes, delaying 4 of them). + if RxC = b"00011111" and RxD = x"55_55_55_fb_07_07_07_07" then + -- shifted lanes + -- switch on the "lane shifter" and go to the state, + -- where we can check the proper preamble after lane switching + r_n.swap_lanes <= '1'; + r_n.state <= ST_CHECK_PREAMB; + elsif RxC = b"00000001" and RxD = x"d5_55_55_55_55_55_55_fb" then + -- normal lanes + r_n.swap_lanes <= '0'; + r_n.crc32 <= (others => '1'); + r_n.state <= ST_RCV_HEADER1; + end if; + when ST_CHECK_PREAMB => + dbg <= "0001"; + if RxC_Sw = b"00000001" and RxD_Sw = x"d5_55_55_55_55_55_55_fb" then + r_n.crc32 <= (others => '1'); + r_n.state <= ST_RCV_HEADER1; + else + -- interrupted preamble reception + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_HEADER1 => + dbg <= "0010"; + if RxC_Sw = b"00000000" then + r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); + -- Change the order of bytes! + for i in 0 to 5 loop + v_mac_addr(47-i*8 downto 40-i*8) := RxD_Sw(i*8+7 downto i*8); + end loop; -- i + if v_mac_addr /= my_mac then + -- This packet is not for us - ignore it! + r_n.state <= ST_RCV_WAIT_IDLE; + else + -- Our packet! + r_n.count <= 0; + -- Read the lower 16 bits of the sender address + -- Again, we have to change the order of bytes! + r_n.mac_addr(39 downto 32) <= RxD_Sw(63 downto 56); + r_n.mac_addr(47 downto 40) <= RxD_Sw(55 downto 48); + r_n.state <= ST_RCV_HEADER2; + end if; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_HEADER2 => + dbg <= "0010"; + if RxC_Sw = b"00000000" then + r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); + v_mac_addr := r.mac_addr; + for i in 0 to 3 loop + v_mac_addr(31-i*8 downto 24-i*8) := RxD_Sw(i*8+7 downto i*8); + end loop; -- i + --v_mac_addr(47 downto 16) := RxD_Sw(31 downto 0); + r_n.mac_addr <= v_mac_addr; + -- In the rest of this 64-bit word, we receive the protocol ID + -- and version + for i in 0 to 3 loop + v_proto(i*8+7 downto i*8) := RxD_Sw(63-i*8 downto 56-i*8); + end loop; -- i + -- Check if the proto id is correct + if v_proto = C_PROTO_ID then + r_n.state <= ST_RCV_CMD; + else + r_n.state <= ST_RCV_IDLE; + end if; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_CMD => + if RxC_Sw = b"0000_0000" then + r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); + -- Copy the command, changing order of bytes! + for i in 0 to 3 loop + r_n.cmd(i*8+7 downto i*8) <= RxD_Sw(31-i*8 downto 24-i*8); + end loop; -- i + -- Copy the argument, changing order of bytes! + for i in 0 to 3 loop + r_n.arg(i*8+7 downto i*8) <= RxD_Sw(63-i*8 downto 56-i*8); + end loop; -- i + r_n.state <= ST_RCV_TRAILER; + -- Currently we ignore rest of the packet! + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_TRAILER => + -- No detection of too long frames! + dbg <= "0110"; + if RxC_Sw /= b"0000_0000" then + -- It should be a packet with the checksum + -- The EOF may be on any of 8th positions. + -- To avoid too big combinational functions, + -- we handle it in a few states (but this increases requirements + -- on IFC!) + -- Current implementation assumes fixed length of frames + -- but the optimal one should probably pass received data for further + -- checking, why this machine continues to receive next frame... + if RxC_Sw = b"1111_1100" then + v_crc := r.crc32; + v_crc := newcrc32_d16(RxD_Sw(15 downto 0), v_crc); + r_n.crc32 <= v_crc; + if (RxD_Sw(23 downto 16) = x"fd") and + (v_crc = x"c704dd7b") then + -- Correct packet, go to processing + r_n.peer_mac <= r.mac_addr; + r_n.state <= ST_RCV_PROCESS; + else + -- Wrong CRC or EOF + r_n.state <= ST_RCV_IDLE; + end if; + else + -- Wrong packet + r_n.state <= ST_RCV_IDLE; + end if; + else + -- Ignore received data, only updating the checksum + r_n.crc32 <= newcrc32_d64(RxD_Sw, r.crc32); + end if; + when ST_RCV_PROCESS => + dbg <= "0111"; + case to_integer(unsigned(r.cmd(31 downto 16))) is + -- Handle commands, which require immediate action + when FCMD_START => + r_n.dbg(0) <= not r.dbg(0); + -- Start transmission command + r_n.transmit_data <= '1'; + when FCMD_STOP => + r_n.dbg(1) <= not r.dbg(1); + -- Stop transmission command + r_n.transmit_data <= '0'; + when FCMD_RESET => + r_n.dbg(3) <= not r.dbg(3); + -- Restart the whole block(?) + r_n.restart <= '1'; + when others => + null; + end case; + -- All commands are written to the acknowledge and commands + -- FIFO, so that they will be handled by the descriptor manager + if ack_fifo_full = '0' then + ack_pkt_in.cmd := unsigned(r.cmd(31 downto 16)); + ack_pkt_in.pkt := unsigned(r.arg); + ack_pkt_in.seq := unsigned(r.cmd(15 downto 0)); + c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); + c.ack_fifo_wr_en <= '1'; + end if; + r_n.state <= ST_RCV_UPDATE; + when ST_RCV_UPDATE => + dbg <= "1000"; + r_n.update_flag <= not r.update_flag; + r_n.state <= ST_RCV_IDLE; + when ST_RCV_WAIT_IDLE => + dbg <= "1001"; + if RxC_Sw = b"1111_1111" then + r_n.state <= ST_RCV_IDLE; + end if; + when others => null; + end case; + end process rdp2; + + -- Synchronization of the reset signal for the Rx_Clk domain + process (Rx_Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + rx_rst_n_0 <= '0'; + rx_rst_n_1 <= '0'; + rx_rst_n <= '0'; + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + rx_rst_n_0 <= rst_n; + rx_rst_n_1 <= rx_rst_n_0; + rx_rst_n <= rx_rst_n_1; + end if; + end process; + + + -- Synchronization of output signals between the clock domains + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + peer_mac <= (others => '0'); + transmit_data <= '0'; + restart <= '0'; + update_flag_0 <= '0'; + update_flag_1 <= '0'; + update_flag <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + -- Synchronization of the update_flag + update_flag_0 <= r.update_flag; + update_flag_1 <= update_flag_0; + update_flag <= update_flag_1; + -- When update flag has changed, rewrite synchronized fields + if update_flag /= update_flag_1 then + peer_mac <= r.peer_mac; + transmit_data <= r.transmit_data; + restart <= r.restart; + end if; + end if; + end process; + +end beh1; Index: experimental_jumbo_frames_version/fpga/src/kc705/wzconstr.xdc =================================================================== --- experimental_jumbo_frames_version/fpga/src/kc705/wzconstr.xdc (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/kc705/wzconstr.xdc (revision 22) @@ -0,0 +1,35 @@ +set_property PACKAGE_PIN H2 [get_ports gtx10g_txp] +set_property PACKAGE_PIN J8 [get_ports gtx_refclk_p] +set_property IOSTANDARD LVCMOS18 [get_ports clk_2] +set_property IOSTANDARD LVCMOS18 [get_ports resetdone] +set_property IOSTANDARD LVCMOS18 [get_ports start] +set_property IOSTANDARD LVCMOS18 [get_ports txusrclk2_out] +set_property IOSTANDARD LVCMOS18 [get_ports txusrclk_out] + + +set_property PACKAGE_PIN AG5 [get_ports start] +set_property PACKAGE_PIN AE20 [get_ports clk_2] +set_property PACKAGE_PIN AB8 [get_ports txusrclk2_out] +set_property PACKAGE_PIN AA8 [get_ports txusrclk_out] +set_property PACKAGE_PIN AC9 [get_ports resetdone] +set_property PACKAGE_PIN AB12 [get_ports rst_p] + + +set_property PACKAGE_PIN AB9 [get_ports core_ready] +set_property IOSTANDARD LVCMOS18 [get_ports core_ready] + + +set_property IOSTANDARD LVCMOS18 [get_ports rst_p] + +create_clock -period 6.400 -name clk156 -waveform {0.000 3.200} [get_nets *156*] + +create_clock -period 6.400 -name gtx_refclk -waveform {0.000 3.200} [get_ports {gtx_refclk_n gtx_refclk_p}] + +set_property PACKAGE_PIN AE26 [get_ports trig_ack] + +set_property IOSTANDARD LVCMOS18 [get_ports trig_ack] +set_property LOC BSCAN_X0Y0 [get_cells dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst] + +set_property PACKAGE_PIN G19 [get_ports led5] +set_property IOSTANDARD LVCMOS18 [get_ports led5] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] Index: experimental_jumbo_frames_version/fpga/src/atlys/eth_sender8.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/atlys/eth_sender8.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/atlys/eth_sender8.vhd (revision 22) @@ -0,0 +1,396 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block sending packets via GMII Phy +-- Project : +------------------------------------------------------------------------------- +-- File : eth_sender8.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-10-19 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkg_newcrc32_d8.all; +use work.desc_mgr_pkg.all; + +entity eth_sender is + + port ( + -- Configuration + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + pkt_number : in unsigned(31 downto 0); + seq_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + -- Control interface + ready : out std_logic; + flushed : in std_logic; + start : in std_logic; + cmd_start : in std_logic; + -- Data memory interface + tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + tx_mem_data : in std_logic_vector(63 downto 0); + -- User command response interface + cmd_response : in std_logic_vector(12*8-1 downto 0); + -- TX Phy interface + Tx_Clk : in std_logic; + Tx_En : out std_logic; + TxD : out std_logic_vector(7 downto 0) + ); + +end eth_sender; + + +architecture beh1 of eth_sender is + + type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_PREAMB, WST_SEND_SOF, + WST_SEND_HEADER, WST_SEND_CMD_HEADER, WST_SEND_CMD_TRAILER, + WST_SEND_DATA, WST_SEND_CRC, + WST_SEND_COMPLETED); + + type T_ETH_SENDER_REGS is record + state : T_ETH_SENDER_STATE; + ready : std_logic; + count : integer; + byte : integer; + mem_addr : unsigned (LOG2_NWRDS_IN_PKT-1 downto 0); + crc32 : std_logic_vector(31 downto 0); + end record; + + constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := ( + state => WST_IDLE, + ready => '1', + count => 0, + byte => 0, + mem_addr => (others => '0'), + crc32 => (others => '0') + ) ; + + signal r, r_n : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI; + + type T_ETH_SENDER_COMB is record + TxD : std_logic_vector(7 downto 0); + Tx_En : std_logic; + mem_addr : unsigned(LOG2_NWRDS_IN_PKT-1 downto 0); + end record; + + constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := ( + TxD => (others => '0'), + Tx_En => '0', + mem_addr => (others => '0') + ); + + signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT; + + signal s_header : std_logic_vector(8*40-1 downto 0) := (others => '0'); + constant HEADER_LEN : integer := 40; -- 40 bytes + signal s_cmd_header : std_logic_vector(8*32-1 downto 0) := (others => '0'); + constant CMD_HEADER_LEN : integer := 32; -- 32 bytes + + signal cmd_only : std_logic := '0'; + + function select_byte ( + constant vec : std_logic_vector; + constant byte_num : integer) + return std_logic_vector is + variable v_byte : std_logic_vector(7 downto 0); + begin + -- first select byte + v_byte := vec(vec'left-byte_num*8 downto vec'left-byte_num*8-7); + return v_byte; + end select_byte; + + function rev(a : in std_logic_vector) + return std_logic_vector is + variable result : std_logic_vector(a'range); + alias aa : std_logic_vector(a'reverse_range) is a; + begin + for i in aa'range loop + result(i) := aa(i); + end loop; + return result; + end; -- function reverse_any_bus + + signal tx_rst_n, tx_rst_n_0, tx_rst_n_1 : std_logic := '0'; + signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; + + signal start_0, tx_start, tx_start_1, tx_start_0 : std_logic := '0'; + signal tx_ready, ready_0, ready_1 : std_logic := '0'; + + type T_STATE1 is (ST1_IDLE, ST1_WAIT_NOT_READY, ST1_WAIT_NOT_START, + ST1_WAIT_READY); + signal state1 : T_STATE1; + + type T_STATE2 is (ST2_IDLE, ST2_WAIT_NOT_READY, ST2_WAIT_READY); + signal state2 : T_STATE2; + signal dta_packet_type : std_logic_vector(15 downto 0) := (others => '0'); + +begin -- beh1 + dta_packet_type <= x"a5a5" when flushed = '0' else x"a5a6"; + -- Packet header + s_header <= peer_mac & my_mac & my_ether_type & x"0100" & + dta_packet_type & std_logic_vector(seq_number(15 downto 0)) & + std_logic_vector(pkt_number) & std_logic_vector(transm_delay) & cmd_response; + -- Command response packet header - we have unused 16 bits in the response packet... + s_cmd_header <= peer_mac & my_mac & my_ether_type & x"0100" & + x"a55a" & x"0000" & cmd_response; + + -- Connection of the signals + + -- The memory address is built from the packet number (6 bits) and word + -- number (8 bits) + tx_mem_addr <= std_logic_vector(pkt_number(LOG2_N_OF_PKTS-1 downto 0)) & std_logic_vector(c.mem_addr); + + -- Main state machine used to send the packet + -- W calej maszynie trzeba jeszcze dodac obsluge kolizji!!! + -- Oprocz tego trzeba przeanalizowac poprawnosc przejsc miedzy domenami zegara + + + snd1 : process (Tx_Clk, tx_rst_n) + begin + if tx_rst_n = '0' then -- asynchronous reset (active low) + r <= ETH_SENDER_REGS_INI; + TxD <= (others => '0'); + Tx_En <= '0'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + r <= r_n; + -- To minimize glitches and propagation delay, let's add pipeline register + Tx_En <= c.Tx_En; + TxD <= c.TxD; + end if; + end process snd1; -- snd1 + + snd2 : process (r, s_header, tx_mem_data, tx_start) + variable v_TxD : std_logic_vector(7 downto 0); + begin -- process snd1 + -- default values + c <= ETH_SENDER_COMB_DEFAULT; + r_n <= r; + case r.state is + when WST_IDLE => + r_n.ready <= '1'; + if tx_start = '1' then + r_n.ready <= '0'; + r_n.state <= WST_SEND_PREAMB; + r_n.count <= 7; + end if; + when WST_SEND_PREAMB => + -- Trzeba dodac wykrywanie kolizji! + c.TxD <= x"55"; + c.Tx_En <= '1'; + r_n.count <= r.count - 1; + if r.count = 1 then + r_n.state <= WST_SEND_SOF; + end if; + when WST_SEND_SOF => + c.TxD <= x"D5"; + c.Tx_En <= '1'; + -- Prepare for sending of header + r_n.crc32 <= (others => '1'); + if cmd_only = '1' then + r_n.state <= WST_SEND_CMD_HEADER; + else + r_n.state <= WST_SEND_HEADER; + end if; + r_n.count <= 0; + when WST_SEND_CMD_HEADER => + v_TxD := select_byte(s_cmd_header, r.count); + c.TxD <= v_TxD; + c.Tx_En <= '1'; + r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); + if r.count < CMD_HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.byte <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_CMD_TRAILER; + end if; + when WST_SEND_CMD_TRAILER => + v_TxD := (others => '0'); + c.TxD <= v_TxD; + c.Tx_En <= '1'; + r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); + if r.count < 64-CMD_HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.byte <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_CRC; + end if; + when WST_SEND_HEADER => + v_TxD := select_byte(s_header, r.count); + c.TxD <= v_TxD; + c.Tx_En <= '1'; + r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); + if r.count < HEADER_LEN-1 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.byte <= 0; + r_n.mem_addr <= (others => '0'); + c.mem_addr <= (others => '0'); + r_n.state <= WST_SEND_DATA; + end if; + when WST_SEND_DATA => + -- send the data byte by byte + v_TxD := select_byte(tx_mem_data, r.byte); + c.TxD <= v_TxD; + c.Tx_En <= '1'; + r_n.crc32 <= newcrc32_d8(v_TxD, r.crc32); + if r.byte < 7 then + r_n.byte <= r.byte + 1; + c.mem_addr <= r.mem_addr; + else + r_n.byte <= 0; + -- Check, if we have sent all the data + -- We send 8192 bytes, which takes 1024 64-bit words + if r.mem_addr < 1023 then + r_n.mem_addr <= r.mem_addr + 1; + c.mem_addr <= r.mem_addr + 1; + else + -- We send the CRC + r_n.state <= WST_SEND_CRC; + end if; + end if; + when WST_SEND_CRC => + v_TxD := r.crc32(31-r.byte*8 downto 24-r.byte*4); + c.TxD <= not rev(v_TxD); + c.Tx_En <= '1'; + if r.byte < 3 then + r_n.byte <= r.byte + 1; + else + r_n.count <= 12; -- generate the IFG - 12 bytes = 96 + -- bits + r_n.state <= WST_SEND_COMPLETED; + end if; + when WST_SEND_COMPLETED => + if r.count > 0 then + r_n.count <= r.count - 1; + else + r_n.ready <= '1'; + r_n.state <= WST_IDLE; + end if; + end case; + end process snd2; + + + -- Synchronization of the reset signal for the Tx_Clk domain + process (Tx_Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + tx_rst_n_0 <= '0'; + tx_rst_n_1 <= '0'; + tx_rst_n <= '0'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + tx_rst_n_0 <= rst_n; + tx_rst_n_1 <= tx_rst_n_0; + tx_rst_n <= tx_rst_n_1; + end if; + end process; + + -- Synchronization of signals passing clock domains + -- Signal start is sent from the Clk domain. + -- When it is asserted, we must immediately deassert signal ready, + -- then generate the synchronized start and after internal ready + -- is asserted, we can output it again... + + -- Ustawienie na 1 takt zegara "clk" sygnalu start powinno zainicjowac wysylanie + -- w tym bloku musimy zadbac o stosowne wydluzenie sygnalu start i jego synchronizacje + -- miedzy domenami zegara... + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + ready <= '0'; + ready_1 <= '0'; + ready_0 <= '0'; + state2 <= ST2_IDLE; + elsif clk'event and clk = '1' then -- rising clock edge + ready_1 <= tx_ready; + ready_0 <= ready_1; + case state2 is + when ST2_IDLE => + if start = '1' and ready_0 = '1' then + cmd_only <= '0'; + start_0 <= '1'; + ready <= '0'; + state2 <= ST2_WAIT_NOT_READY; + elsif cmd_start = '1' and ready_0 = '1' then + cmd_only <= '1'; + start_0 <= '1'; + ready <= '0'; + state2 <= ST2_WAIT_NOT_READY; + else + ready <= ready_0; -- Needed to provide correct start! + end if; + when ST2_WAIT_NOT_READY => + if ready_0 = '0' then + start_0 <= '0'; + state2 <= ST2_WAIT_READY; + end if; + when ST2_WAIT_READY => + if ready_0 = '1' then + ready <= '1'; + state2 <= ST2_IDLE; + end if; + when others => null; + end case; + end if; + end process; + + process (Tx_Clk, tx_rst_n) + begin -- process + if tx_rst_n = '0' then -- asynchronous reset (active low) + tx_start <= '0'; + tx_start_0 <= '0'; + state1 <= ST1_IDLE; + tx_ready <= '1'; + elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge + tx_start_0 <= start_0; + tx_start <= tx_start_0; + case state1 is + when ST1_IDLE => + if tx_start = '1' then + tx_ready <= '0'; -- this should cause tx_start to go low + state1 <= ST1_WAIT_NOT_READY; + end if; + when ST1_WAIT_NOT_READY => + if r.ready = '0' then + state1 <= ST1_WAIT_NOT_START; + end if; + when ST1_WAIT_NOT_START => + if tx_start = '0' then + state1 <= ST1_WAIT_READY; + end if; + when ST1_WAIT_READY => + if r.ready = '1' then + tx_ready <= '1'; + state1 <= ST1_IDLE; + end if; + when others => null; + end case; + end if; + end process; + +end beh1; Index: experimental_jumbo_frames_version/fpga/src/atlys/eth_receiver8.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/atlys/eth_receiver8.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/atlys/eth_receiver8.vhd (revision 22) @@ -0,0 +1,350 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block receiving packets from MII PHY +-- Project : +------------------------------------------------------------------------------- +-- File : eth_receiver4.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-10-19 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- + +-- Uwaga! Tu mamy rzeczywiste problemy z obsluga odebranych pakietow! +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.desc_mgr_pkg.all; +use work.pkt_ack_pkg.all; +use work.pkg_newcrc32_d8.all; + +entity eth_receiver is + + port ( + -- Configuration + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + -- ACK FIFO interface + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + dbg : out std_logic_vector(3 downto 0); + -- MAC inerface + Rx_Clk : in std_logic; + Rx_Er : in std_logic; + Rx_Dv : in std_logic; + RxD : in std_logic_vector(7 downto 0) + ); + +end eth_receiver; + + +architecture beh1 of eth_receiver is + + type T_STATE is (ST_RCV_IDLE, ST_RCV_PREAMB, ST_RCV_DEST, ST_RCV_SOURCE, ST_RCV_CMD, + ST_RCV_PROTO, ST_RCV_WAIT_IDLE, ST_RCV_ARGS, ST_RCV_PROCESS, ST_RCV_UPDATE, + ST_RCV_TRAILER); + + + + function rev(a : in std_logic_vector) + return std_logic_vector is + variable result : std_logic_vector(a'range); + alias aa : std_logic_vector(a'reverse_range) is a; + begin + for i in aa'range loop + result(i) := aa(i); + end loop; + return result; + end; -- function reverse_any_bus + + + type T_RCV_REGS is record + state : T_STATE; + transmit_data : std_logic; + restart : std_logic; + update_flag : std_logic; + count : integer range 0 to 256; + dbg : std_logic_vector(3 downto 0); + crc32 : std_logic_vector(31 downto 0); + cmd : std_logic_vector(63 downto 0); + mac_addr : std_logic_vector(47 downto 0); + peer_mac : std_logic_vector(47 downto 0); + end record; + + constant RCV_REGS_INI : T_RCV_REGS := ( + state => ST_RCV_IDLE, + transmit_data => '0', + restart => '0', + update_flag => '0', + count => 0, + dbg => (others => '0'), + crc32 => (others => '0'), + cmd => (others => '0'), + mac_addr => (others => '0'), + peer_mac => (others => '0') + ); + + + signal r, r_n : T_RCV_REGS := RCV_REGS_INI; + + type T_RCV_COMB is record + ack_fifo_wr_en : std_logic; + ack_fifo_din : std_logic_vector(pkt_ack_width-1 downto 0); + Rx_mac_rd : std_logic; + restart : std_logic; + end record; + + constant RCV_COMB_DEFAULT : T_RCV_COMB := ( + ack_fifo_wr_en => '0', + ack_fifo_din => (others => '0'), + Rx_mac_rd => '0', + restart => '0' + ); + + signal c : T_RCV_COMB := RCV_COMB_DEFAULT; + + signal rx_rst_n, rx_rst_n_0, rx_rst_n_1 : std_logic := '0'; + signal update_flag_0, update_flag_1, update_flag : std_logic := '0'; + + constant proto_id : std_logic_vector(31 downto 0) := x"fade0100"; + +begin -- beh1 + + ack_fifo_din <= c.ack_fifo_din; + ack_fifo_wr_en <= c.ack_fifo_wr_en; + + dbg <= r.dbg; + + -- Reading of ethernet data + rdp1 : process (Rx_Clk, rx_rst_n) + begin -- process rdp1 + if rx_rst_n = '0' then -- asynchronous reset (active low) + r <= RCV_REGS_INI; + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + r <= r_n; + end if; + end process rdp1; + + rdp2 : process (RxD, Rx_Dv, ack_fifo_full, my_ether_type, my_mac, r, + update_flag) + + variable ack_pkt_in : pkt_ack; + variable v_mac_addr : std_logic_vector(47 downto 0); + variable v_cmd : std_logic_vector(63 downto 0); + + begin -- process + c <= RCV_COMB_DEFAULT; + r_n <= r; + --dbg <= "1111"; + case r.state is + when ST_RCV_IDLE => + --dbg <= "0000"; + if Rx_Dv = '1' then + if RxD = x"55" then + r_n.count <= 1; + r_n.state <= ST_RCV_PREAMB; + end if; + end if; + when ST_RCV_PREAMB => + --dbg <= "0001"; + if Rx_Dv = '0' then + -- interrupted preamble reception + r_n.state <= ST_RCV_IDLE; + elsif RxD = x"55" then + if r.count < 7 then + r_n.count <= r.count + 1; + end if; + elsif (RxD = x"d5") and (r.count = 7) then --D + -- We start reception of the packet + r_n.crc32 <= (others => '1'); + r_n.count <= 0; + -- First we receive the sender address + r_n.state <= ST_RCV_DEST; + else + -- something wrong happened during preamble detection + r_n.state <= ST_RCV_WAIT_IDLE; + end if; + when ST_RCV_DEST => + --dbg <= "0010"; + if Rx_Dv = '1' then + r_n.crc32 <= newcrc32_d8(RxD, r.crc32); + if my_mac(47-r.count*8 downto 40-r.count*8) /= RxD then + -- Not our address, return to IDLE! + r_n.state <= ST_RCV_WAIT_IDLE; + elsif r.count < 5 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.state <= ST_RCV_SOURCE; + -- Our address! Receive the sender + end if; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_SOURCE => + --dbg <= "0011"; + if Rx_Dv = '1' then + r_n.crc32 <= newcrc32_d8(RxD, r.crc32); + v_mac_addr := r.mac_addr; + v_mac_addr(47-r.count*8 downto 40-r.count*8) := RxD; + r_n.mac_addr <= v_mac_addr; + if r.count < 5 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.state <= ST_RCV_PROTO; + end if; + else + -- packet broken? + r_n.state <= ST_RCV_IDLE; + end if; + when ST_RCV_PROTO => + if Rx_Dv = '1' then + r_n.crc32 <= newcrc32_d8(RxD, r.crc32); + if proto_id(31-r.count*8 downto 24-r.count*8) /= RxD then + -- Incorrect type of frame or protocol ID + r_n.state <= ST_RCV_IDLE; + elsif r.count < 3 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.state <= ST_RCV_CMD; + end if; + end if; + when ST_RCV_CMD => + --dbg <= "0100"; + if Rx_Dv = '1' then + r_n.crc32 <= newcrc32_d8(RxD, r.crc32); + v_cmd := r.cmd; + v_cmd(63-r.count*8 downto 56-r.count*8) := RxD; + r_n.cmd <= v_cmd; + if r.count < 7 then + r_n.count <= r.count + 1; + else + r_n.count <= 0; + r_n.state <= ST_RCV_TRAILER; + end if; + end if; + when ST_RCV_TRAILER => + -- No detection of too long frames! + --dbg <= "0110"; + if Rx_Dv = '0' then + -- End of packet, check the checksum + if r.crc32 /= x"c704dd7b" then + -- Wrong checksum, ignore packet + r_n.state <= ST_RCV_IDLE; + else + -- Checksum OK, process the packet + r_n.state <= ST_RCV_PROCESS; + end if; + else + r_n.crc32 <= newcrc32_d8(RxD, r.crc32); + end if; + when ST_RCV_PROCESS => + --For ACK + --dbg <= "0111"; + -- We can copy the sender + r_n.peer_mac <= r.mac_addr; + case to_integer(unsigned(r.cmd(63 downto 48))) is + -- Handle commands, which require immediate action + when FCMD_START => + r_n.dbg(0) <= not r.dbg(0); + -- Start transmission command + r_n.transmit_data <= '1'; + when FCMD_STOP => + r_n.dbg(1) <= not r.dbg(1); + -- Stop transmission command + r_n.transmit_data <= '0'; + when FCMD_RESET => + r_n.dbg(3) <= not r.dbg(3); + -- Stop transmission and retransmission + r_n.restart <= '1'; + when others => + null; + end case; + -- All commands are written to the acknowledge and commands + -- FIFO, so they will be handled by the descriptor manager + -- Handle the user commands + if ack_fifo_full = '0' then + ack_pkt_in.cmd := unsigned(r.cmd(63 downto 48)); + ack_pkt_in.seq := unsigned(r.cmd(47 downto 32)); + ack_pkt_in.pkt := unsigned(r.cmd(31 downto 0)); + c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); + c.ack_fifo_wr_en <= '1'; + end if; + r_n.state <= ST_RCV_UPDATE; + when ST_RCV_UPDATE => + --dbg <= "1000"; + r_n.update_flag <= not r.update_flag; + r_n.state <= ST_RCV_IDLE; + when ST_RCV_WAIT_IDLE => + --dbg <= "1001"; + if Rx_Dv = '0' then + r_n.state <= ST_RCV_IDLE; + end if; + when others => null; + end case; + end process rdp2; + + -- Synchronization of the reset signal for the Rx_Clk domain + process (Rx_Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + rx_rst_n_0 <= '0'; + rx_rst_n_1 <= '0'; + rx_rst_n <= '0'; + elsif Rx_Clk'event and Rx_Clk = '1' then -- rising clock edge + rx_rst_n_0 <= rst_n; + rx_rst_n_1 <= rx_rst_n_0; + rx_rst_n <= rx_rst_n_1; + end if; + end process; + + + -- Synchronization of output signals between the clock domains + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + peer_mac <= (others => '0'); + transmit_data <= '0'; + restart <= '0'; + update_flag_0 <= '0'; + update_flag_1 <= '0'; + update_flag <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + -- Synchronization of the update_flag + update_flag_0 <= r.update_flag; + update_flag_1 <= update_flag_0; + update_flag <= update_flag_1; + -- When update flag has changed, rewrite synchronized fields + if update_flag /= update_flag_1 then + peer_mac <= r.peer_mac; + transmit_data <= r.transmit_data; + restart <= r.restart; + end if; + end if; + end process; + +end beh1; Index: experimental_jumbo_frames_version/fpga/src/atlys/atlys_eth_top.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/atlys/atlys_eth_top.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/atlys/atlys_eth_top.vhd (revision 22) @@ -0,0 +1,583 @@ +------------------------------------------------------------------------------- +-- Title : L3 FADE protocol demo for Digilent Atlys board +-- Project : +------------------------------------------------------------------------------- +-- File : atlys_eth_top.vhd +-- Author : Wojciech M. Zabolotny +-- License : BSD License +-- Company : +-- Created : 2010-08-03 +-- Last update: 2014-10-20 +-- Platform : +-- Standard : VHDL +------------------------------------------------------------------------------- +-- Description: +-- This file implements the top entity, integrating all component +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +-- This is public domain code!!! +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2010-08-03 1.0 wzab Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +entity atlys_eth is + + port ( + cpu_reset : in std_logic; +-- -- DDR2 interface +-- ddr2_a : out std_logic_vector(12 downto 0); +-- ddr2_ba : out std_logic_vector(2 downto 0); +-- ddr2_cas_b : out std_logic; +-- ddr2_cke : out std_logic; +-- ddr2_clk_n : out std_logic; +-- ddr2_clk_p : out std_logic; +-- ddr2_dq : inout std_logic_vector(15 downto 0); +-- ddr2_ldm : out std_logic; +-- ddr2_ldqs_n : out std_logic; +-- ddr2_ldqs_p : out std_logic; +-- ddr2_odt : out std_logic; +-- ddr2_ras_b : out std_logic; +-- ddr2_udm : out std_logic; +-- ddr2_udqs_n : out std_logic; +-- ddr2_udqs_p : out std_logic; +-- ddr2_we_b : out std_logic; +-- -- FLASH interface +-- flash_a : out std_logic_vector(24 downto 0); +-- flash_ce_b : out std_logic; +-- flash_d : inout std_logic_vector(7 downto 0); +-- flash_oe_b : out std_logic; +-- flash_we_b : out std_logic; +-- -- FMC interface +-- fmc_la28_n : out std_logic; +-- fmc_la28_p : out std_logic; +-- fmc_la29_n : out std_logic; +-- fmc_la29_p : out std_logic; +-- fmc_la30_n : out std_logic; +-- fmc_la30_p : out std_logic; +-- fmc_la31_n : out std_logic; +-- fmc_la31_p : out std_logic; +-- iic_scl_main : out std_logic; +-- iic_sda_main : out std_logic; + + --gpio_hdr : in std_logic_vector(7 downto 0); + +-- fmc_clk0_m2c_n : out std_logic; +-- fmc_clk0_m2c_p : out std_logic; +-- fmc_clk1_m2c_n : out std_logic; +-- fmc_clk1_m2c_p : out std_logic; +-- fmc_la00_cc_n : out std_logic; +-- fmc_la00_cc_p : out std_logic; +-- fmc_la01_cc_n : out std_logic; +-- fmc_la01_cc_p : out std_logic; +-- fmc_la02_n : out std_logic; +-- fmc_la02_p : out std_logic; +-- fmc_la03_n : out std_logic; +-- fmc_la03_p : out std_logic; +-- fmc_la04_n : out std_logic; +-- fmc_la04_p : out std_logic; +-- led : out std_logic_vector(3 downto 0); + switches : in std_logic_vector(7 downto 0); +-- flash_oen : out std_logic; +-- flash_wen : out std_logic; +-- flash_cen : out std_logic; + gpio_led : out std_logic_vector(7 downto 0); + -- PHY interface + phy_col : in std_logic; + phy_crs : in std_logic; + phy_int : in std_logic; + phy_mdc : out std_logic; + phy_mdio : inout std_logic; + phy_reset : out std_logic; + phy_rxclk : in std_logic; + phy_rxctl_rxdv : in std_logic; + phy_rxd : in std_logic_vector(7 downto 0); + phy_rxer : in std_logic; + phy_txclk : in std_logic; + phy_txctl_txen : out std_logic; + phy_txc_gtxclk : out std_logic; + phy_txd : out std_logic_vector(7 downto 0); + phy_txer : out std_logic; + sysclk : in std_logic + ); + +end atlys_eth; + +architecture beh of atlys_eth is + + component dp_ram_scl + generic ( + DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + clk_a : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + clk_b : in std_logic; + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); + end component; + + component ack_fifo + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(pkt_ack_width-1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(pkt_ack_width-1 downto 0); + full : out std_logic; + empty : out std_logic); + end component; + + component dcm1 + port ( + CLK_IN1 : in std_logic; + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + CLK_OUT3 : out std_logic; + RESET : in std_logic; + LOCKED : out std_logic); + end component; + + component desc_manager is + generic ( + LOG2_N_OF_PKTS : integer; + N_OF_PKTS : integer); + port ( + dta : in std_logic_vector(63 downto 0); + dta_we : in std_logic; + dta_eod : in std_logic; + dta_ready : out std_logic; + pkt_number : out unsigned(31 downto 0); + seq_number : out unsigned(15 downto 0); + cmd_response_out : out std_logic_vector(12*8-1 downto 0); + snd_cmd_start : out std_logic; + snd_start : out std_logic; + flushed : out std_logic; + snd_ready : in std_logic; + dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); + dmem_dta : out std_logic_vector(63 downto 0); + dmem_we : out std_logic; + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + cmd_code : out std_logic_vector(15 downto 0); + cmd_seq : out std_logic_vector(15 downto 0); + cmd_arg : out std_logic_vector(31 downto 0); + cmd_run : out std_logic; + cmd_retr_s : out std_logic; + cmd_ack : in std_logic; + cmd_response_in : in std_logic_vector(8*12-1 downto 0); + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + dbg : out std_logic_vector(3 downto 0); + clk : in std_logic; + rst_n : in std_logic); + end component desc_manager; + + component cmd_proc is + port ( + cmd_code : in std_logic_vector(15 downto 0); + cmd_seq : in std_logic_vector(15 downto 0); + cmd_arg : in std_logic_vector(31 downto 0); + cmd_run : in std_logic; + cmd_ack : out std_logic; + cmd_response : out std_logic_vector(8*12-1 downto 0); + clk : in std_logic; + rst_p : in std_logic); + end component cmd_proc; + + component eth_sender is + port ( + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + pkt_number : in unsigned(31 downto 0); + seq_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic; + ready : out std_logic; + flushed : in std_logic; + start : in std_logic; + cmd_start : in std_logic; + tx_mem_addr : out std_logic_vector(LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT-1 downto 0); + tx_mem_data : in std_logic_vector(63 downto 0); + cmd_response : in std_logic_vector(12*8-1 downto 0); + Tx_Clk : in std_logic; + Tx_En : out std_logic; + TxD : out std_logic_vector(7 downto 0)); + end component eth_sender; + + component eth_receiver + port ( + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + clk : in std_logic; + rst_n : in std_logic; + dbg : out std_logic_vector(3 downto 0); + Rx_Clk : in std_logic; + Rx_Er : in std_logic; + Rx_Dv : in std_logic; + RxD : in std_logic_vector(7 downto 0)); + end component; + + component jtag_bus_ctl + generic ( + d_width : integer; + a_width : integer); + port ( + din : in std_logic_vector((d_width-1) downto 0); + dout : out std_logic_vector((d_width-1) downto 0); + addr : out std_logic_vector((a_width-1) downto 0); + nwr : out std_logic; + nrd : out std_logic); + end component; + + + signal my_mac : std_logic_vector(47 downto 0); + constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; + signal transm_delay : unsigned(31 downto 0); + signal restart : std_logic; + signal dta : std_logic_vector(63 downto 0); + signal dta_we : std_logic := '0'; + signal dta_ready : std_logic; + signal snd_start : std_logic; + signal snd_ready : std_logic; + signal flushed : std_logic := '0'; + signal dta_eod : std_logic := '0'; + signal dmem_addr : std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); + signal dmem_dta : std_logic_vector(63 downto 0); + signal dmem_we : std_logic; + signal addr_a, addr_b : integer; + signal test_dta : unsigned(63 downto 0); + signal tx_mem_addr : std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); + signal tx_mem_data : std_logic_vector(63 downto 0); + + signal arg1, arg2, res1 : unsigned(7 downto 0); + signal res2 : unsigned(15 downto 0); + signal sender : std_logic_vector(47 downto 0); + signal peer_mac : std_logic_vector(47 downto 0); + signal inputs, din, dout : std_logic_vector(7 downto 0); + signal addr, leds : std_logic_vector(3 downto 0); + signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic; + signal not_cpu_reset, rst_del : std_logic; + + signal set_number : unsigned(15 downto 0); + signal pkt_number : unsigned(31 downto 0); + signal seq_number : unsigned(15 downto 0) := (others => '0'); + signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); + + + signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); + signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; + signal transmit_data, td_del0, td_del1 : std_logic := '0'; + + signal read_addr : std_logic_vector(15 downto 0); + signal read_data : std_logic_vector(15 downto 0); + signal read_done, read_in_progress : std_logic; + + signal dbg : std_logic_vector(3 downto 0); + + signal led_counter : integer := 0; + signal tx_counter : integer := 10000; + signal Reset : std_logic; + signal Clk_125M : std_logic; + signal Clk_user : std_logic; + signal Clk_reg : std_logic; + signal Speed : std_logic_vector(2 downto 0); + signal Rx_mac_ra : std_logic; + signal Rx_mac_rd : std_logic; + signal Rx_mac_data : std_logic_vector(31 downto 0); + signal Rx_mac_BE : std_logic_vector(1 downto 0); + signal Rx_mac_pa : std_logic; + signal Rx_mac_sop : std_logic; + signal Rx_mac_eop : std_logic; + signal Tx_mac_wa : std_logic; + signal Tx_mac_wr : std_logic; + signal Tx_mac_data : std_logic_vector(31 downto 0); + signal Tx_mac_BE : std_logic_vector(1 downto 0); + signal Tx_mac_sop : std_logic; + signal Tx_mac_eop : std_logic; + signal Pkg_lgth_fifo_rd : std_logic; + signal Pkg_lgth_fifo_ra : std_logic; + signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0); + signal Gtx_clk : std_logic; + signal Rx_clk : std_logic; + signal Tx_clk : std_logic; + signal Tx_er : std_logic; + signal Tx_en : std_logic; + signal Txd : std_logic_vector(7 downto 0); + signal Rx_er : std_logic; + signal Rx_dv : std_logic; + signal Rxd : std_logic_vector(7 downto 0); + signal Crs : std_logic; + signal Col : std_logic; + signal CSB : std_logic := '1'; + signal WRB : std_logic := '1'; + signal CD_in : std_logic_vector(15 downto 0) := (others => '0'); + signal CD_out : std_logic_vector(15 downto 0) := (others => '0'); + signal CA : std_logic_vector(7 downto 0) := (others => '0'); + signal s_Mdo : std_logic; + signal s_MdoEn : std_logic; + signal s_Mdi : std_logic; + + signal s_dta_we : std_logic; + + -- signals related to user commands handling + signal cmd_response_in, cmd_response_out : std_logic_vector(12*8-1 downto 0) := (others => '0'); + signal cmd_start : std_logic := '0'; + signal cmd_run : std_logic := '0'; + signal cmd_retr_s : std_logic := '0'; + signal cmd_ack : std_logic := '0'; + signal cmd_code : std_logic_vector(15 downto 0) := (others => '0'); + signal cmd_seq : std_logic_vector(15 downto 0) := (others => '0'); + signal cmd_arg : std_logic_vector(31 downto 0) := (others => '0'); + + +begin -- beh + + -- Allow selection of MAC with the DIP switch to allow testing + -- with multiple boards! + with switches(1 downto 0) select + my_mac <= + x"de_ad_ba_be_be_ef" when "00", + x"de_ad_ba_be_be_e1" when "01", + x"de_ad_ba_be_be_e2" when "10", + x"de_ad_ba_be_be_e3" when "11"; + + +-- iic_sda_main <= 'Z'; +-- iic_scl_main <= 'Z'; + + not_cpu_reset <= not cpu_reset; + rst_p <= not rst_n; + +-- flash_oe_b <= '1'; +-- flash_we_b <= '1'; +-- flash_ce_b <= '1'; + + tx_clk <= Clk_125M; + rx_clk <= phy_rxclk; + + Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra; + + addr_a <= to_integer(unsigned(dmem_addr)); + addr_b <= to_integer(unsigned(tx_mem_addr)); + + dp_ram_scl_1 : dp_ram_scl + generic map ( + DATA_WIDTH => 64, + ADDR_WIDTH => LOG2_N_OF_PKTS+LOG2_NWRDS_IN_PKT) + port map ( + clk_a => clk_user, + we_a => dmem_we, + addr_a => dmem_addr, + data_a => dmem_dta, + q_a => open, + clk_b => Tx_clk, + we_b => '0', + addr_b => tx_mem_addr, + data_b => (others => '0'), + q_b => tx_mem_data); + + desc_manager_1 : desc_manager + generic map ( + LOG2_N_OF_PKTS => LOG2_N_OF_PKTS, + N_OF_PKTS => N_OF_PKTS) + port map ( + dta => dta, + dta_we => dta_we, + dta_ready => dta_ready, + pkt_number => pkt_number, + seq_number => seq_number, + cmd_response_out => cmd_response_out, + snd_start => snd_start, + flushed => flushed, + snd_cmd_start => cmd_start, + snd_ready => snd_ready, + dta_eod => dta_eod, + dmem_addr => dmem_addr, + dmem_dta => dmem_dta, + dmem_we => dmem_we, + ack_fifo_empty => ack_fifo_empty, + ack_fifo_rd_en => ack_fifo_rd_en, + ack_fifo_dout => ack_fifo_dout, + cmd_code => cmd_code, + cmd_seq => cmd_seq, + cmd_arg => cmd_arg, + cmd_run => cmd_run, + cmd_retr_s => cmd_retr_s, + cmd_ack => cmd_ack, + cmd_response_in => cmd_response_in, + transmit_data => transmit_data, + transm_delay => transm_delay, + dbg => dbg, + clk => clk_user, + rst_n => rst_n); + + cmd_proc_1 : cmd_proc + port map ( + cmd_code => cmd_code, + cmd_seq => cmd_seq, + cmd_arg => cmd_arg, + cmd_run => cmd_run, + cmd_ack => cmd_ack, + cmd_response => cmd_response_in, + clk => clk_user, + rst_p => rst_p); + + eth_sender_1 : eth_sender + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + pkt_number => pkt_number, + seq_number => seq_number, + transm_delay => transm_delay, + clk => clk_user, + rst_n => rst_n, + ready => snd_ready, + flushed => flushed, + start => snd_start, + cmd_start => cmd_start, + tx_mem_addr => tx_mem_addr, + tx_mem_data => tx_mem_data, + cmd_response => cmd_response_out, + Tx_Clk => tx_clk, + Tx_En => phy_txctl_txen, + TxD => PHY_Txd); + + eth_receiver_2 : eth_receiver + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + transmit_data => transmit_data, + restart => restart, + ack_fifo_full => ack_fifo_full, + ack_fifo_wr_en => ack_fifo_wr_en, + ack_fifo_din => ack_fifo_din, + clk => clk_user, + rst_n => rst_n, + dbg => open, --dbg, + Rx_Clk => rx_clk, + Rx_Er => PHY_Rxer, + Rx_Dv => phy_rxctl_rxdv, + RxD => PHY_Rxd); + + dcm1_1 : dcm1 + port map ( + CLK_IN1 => sysclk, + CLK_OUT1 => Clk_125M, + CLK_OUT2 => Clk_user, + CLK_OUT3 => Clk_reg, + RESET => not_cpu_reset, + LOCKED => dcm_locked); + + process (Clk_user, not_cpu_reset) + begin -- process + if not_cpu_reset = '1' then -- asynchronous reset (active low) + rst_n <= '0'; + rst_del <= '0'; + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if restart = '1' then + rst_n <= '0'; + rst_del <= '0'; + else + if dcm_locked = '1' then + rst_del <= '1'; + rst_n <= rst_del; + end if; + end if; + end if; + end process; + + -- reset + + phy_reset <= rst_n; + + -- Connection of MDI + --s_Mdi <= PHY_MDIO; + --PHY_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo; + + phy_txer <= '0'; + phy_mdio <= 'Z'; + phy_mdc <= '0'; + + phy_txc_gtxclk <= tx_clk; + + ack_fifo_1 : ack_fifo + port map ( + rst => rst_p, + wr_clk => rx_clk, + rd_clk => Clk_user, + din => ack_fifo_din, + wr_en => ack_fifo_wr_en, + rd_en => ack_fifo_rd_en, + dout => ack_fifo_dout, + full => ack_fifo_full, + empty => ack_fifo_empty); + + --E_TXD <= s_Txd(3 downto 0); + --s_Rxd <= "0000" & E_RXD; + + -- signal generator + + dta <= std_logic_vector(test_dta); + s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; + dta_we <= s_dta_we; + + process (Clk_user, rst_n) + begin -- process + + if rst_n = '0' then -- asynchronous reset (active low) + td_del0 <= '0'; + td_del1 <= '0'; + test_dta <= (others => '0'); + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if s_dta_we = '1' then + test_dta <= test_dta + x"1234567809abcdef"; + end if; + -- Generate the dta_eod pulse after transmit_data + -- goes low + td_del0 <= transmit_data; + td_del1 <= td_del0; + if (td_del1 = '1') and (td_del0 = '0') then + dta_eod <= '1'; + else + dta_eod <= '0'; + end if; + end if; + end process; + + -- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2)); + gpio_led(0) <= snd_ready; + gpio_led(1) <= transmit_data; + gpio_led(2) <= flushed; + gpio_led(3) <= Tx_mac_wa; + gpio_led(7 downto 4) <= dbg; +--gpio_led(6) <= ack_fifo_full; +--gpio_led(7) <= not ack_fifo_empty; +end beh; Index: experimental_jumbo_frames_version/fpga/src/atlys/atlys_eth.ucf =================================================================== --- experimental_jumbo_frames_version/fpga/src/atlys/atlys_eth.ucf (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/atlys/atlys_eth.ucf (revision 22) @@ -0,0 +1,118 @@ +#@ NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10 +#@ NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10 +#@ NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10 +NET "GPIO_LED<0>" LOC = "U18"; ## 2 on DS11 LED +NET "GPIO_LED<1>" LOC = "M14"; ## 2 on DS12 LED +NET "GPIO_LED<2>" LOC = "N14"; ## 2 on DS13 LED +NET "GPIO_LED<3>" LOC = "L14"; ## 2 on DS14 LED +NET "GPIO_LED<4>" LOC = "M13"; ## 2 on DS11 LED +NET "GPIO_LED<5>" LOC = "D4"; ## 2 on DS12 LED +NET "GPIO_LED<6>" LOC = "P16"; ## 2 on DS13 LED +NET "GPIO_LED<7>" LOC = "N12"; ## 2 on DS14 LED +NET "SWITCHES<0>" LOC = "A10"; +NET "SWITCHES<1>" LOC = "D14"; +NET "SWITCHES<2>" LOC = "C14"; +NET "SWITCHES<3>" LOC = "P15"; +NET "SWITCHES<4>" LOC = "P12"; +NET "SWITCHES<5>" LOC = "R5"; +NET "SWITCHES<6>" LOC = "T5"; +NET "SWITCHES<7>" LOC = "E4"; + +## +NET "CPU_RESET" LOC = "T15"; ## 2 on SW9 pushbutton +## +NET "PHY_COL" LOC = "C17"; ## 114 on U3 +NET "PHY_CRS" LOC = "C18"; ## 115 on U3 +NET "PHY_INT" LOC = "L16"; ## 32 on U3 +NET "PHY_MDC" LOC = "F16"; ## 35 on U3 +NET "PHY_MDIO" LOC = "N17"; ## 33 on U3 +NET "PHY_RESET" LOC = "G13"; ## 36 on U3 +NET "PHY_RXCLK" LOC = "K15"; ## 7 on U3 +NET "PHY_RXCTL_RXDV" LOC = "F17"; ## 4 on U3 +NET "PHY_RXD<0>" LOC = "G16"; ## 3 on U3 +NET "PHY_RXD<1>" LOC = "H14"; ## 128 on U3 +NET "PHY_RXD<2>" LOC = "E16"; ## 126 on U3 +NET "PHY_RXD<3>" LOC = "F15"; ## 125 on U3 +NET "PHY_RXD<4>" LOC = "F14"; ## 124 on U3 +NET "PHY_RXD<5>" LOC = "E18"; ## 123 on U3 +NET "PHY_RXD<6>" LOC = "D18"; ## 121 on U3 +NET "PHY_RXD<7>" LOC = "D17"; ## 120 on U3 +NET "PHY_RXER" LOC = "F18"; ## 8 on U3 +NET "PHY_TXCLK" LOC = "K16"; ## 10 on U3 +NET "PHY_TXCTL_TXEN" LOC = "H15"; ## 16 on U3 +NET "PHY_TXC_GTXCLK" LOC = "L12"; ## 14 on U3 +NET "PHY_TXD<0>" LOC = "H16"; ## 18 on U3 +NET "PHY_TXD<1>" LOC = "H13"; ## 19 on U3 +NET "PHY_TXD<2>" LOC = "K14"; ## 20 on U3 +NET "PHY_TXD<3>" LOC = "K13"; ## 24 on U3 +NET "PHY_TXD<4>" LOC = "J13"; ## 25 on U3 +NET "PHY_TXD<5>" LOC = "G14"; ## 26 on U3 +NET "PHY_TXD<6>" LOC = "H12"; ## 28 on U3 +NET "PHY_TXD<7>" LOC = "K12"; ## 29 on U3 +NET "PHY_TXER" LOC = "G18"; ## 13 on U3 +## +NET "SYSCLK" LOC = "L15"; +## +#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1 +#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1 +#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1 +#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1 +#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1 +#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1 +#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1 +#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1 +# +#@ NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm) +#@ NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm) +#@ NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm) +#@ NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm) +#@ NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm) +#@ NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm) +#@ NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm) +#@ NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm) +# +#@ NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16 +#@ NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16 +# +#@ PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; + +#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04 +NET "sysclk" TNM_NET = sysclk; +TIMESPEC TS_sysclk = PERIOD "sysclk" 10 ns HIGH 50%; +#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30 +NET "phy_rxclk" TNM_NET = phy_rxclk; +TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%; +NET "phy_txclk" TNM_NET = phy_txclk; +TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 8 ns HIGH 50%; +NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk; +TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%; + +INST "phy_col" TNM = phy_inputs; +INST "phy_crs" TNM = phy_inputs; +INST "phy_int" TNM = phy_inputs; +INST "phy_mdio" TNM = phy_inputs; +INST "phy_rxctl_rxdv" TNM = phy_inputs; +INST "phy_rxd<0>" TNM = phy_inputs; +INST "phy_rxd<1>" TNM = phy_inputs; +INST "phy_rxd<2>" TNM = phy_inputs; +INST "phy_rxd<3>" TNM = phy_inputs; +INST "phy_rxd<4>" TNM = phy_inputs; +INST "phy_rxd<5>" TNM = phy_inputs; +INST "phy_rxd<6>" TNM = phy_inputs; +INST "phy_rxd<7>" TNM = phy_inputs; +INST "phy_rxer" TNM = phy_inputs; +TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_rxclk"; +TIMEGRP "phy_inputs" OFFSET = IN 3 ns VALID 8 ns BEFORE "phy_txclk"; +INST "phy_txctl_txen" TNM = phy_outputs; +INST "phy_txd<0>" TNM = phy_outputs; +INST "phy_txd<1>" TNM = phy_outputs; +INST "phy_txd<2>" TNM = phy_outputs; +INST "phy_txd<3>" TNM = phy_outputs; +INST "phy_txd<4>" TNM = phy_outputs; +INST "phy_txd<5>" TNM = phy_outputs; +INST "phy_txd<6>" TNM = phy_outputs; +INST "phy_txd<7>" TNM = phy_outputs; +INST "phy_txer" TNM = phy_outputs; +TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_rxclk"; +TIMEGRP "phy_outputs" OFFSET = OUT 3 ns AFTER "phy_txclk"; Index: experimental_jumbo_frames_version/fpga/src/atlys/ack_fifo.xco =================================================================== --- experimental_jumbo_frames_version/fpga/src/atlys/ack_fifo.xco (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/atlys/ack_fifo.xco (revision 22) @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Sun Oct 5 18:40:09 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=ack_fifo +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=510 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=64 +CSET input_depth=512 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=64 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: d1e681fd Index: experimental_jumbo_frames_version/fpga/src/atlys/dcm1.xco =================================================================== --- experimental_jumbo_frames_version/fpga/src/atlys/dcm1.xco (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/atlys/dcm1.xco (revision 22) @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Sun Sep 28 17:26:58 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=100.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=125.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=64.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=64.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=dcm1 +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=4 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=10.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=5 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=10.000 +CSET pll_clkout0_divide=4 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=8 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=8 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=100.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: fdec5cf3 Index: experimental_jumbo_frames_version/fpga/src/gen_crcs.sh =================================================================== --- experimental_jumbo_frames_version/fpga/src/gen_crcs.sh (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/gen_crcs.sh (revision 22) @@ -0,0 +1,5 @@ +for i in 8 16 24 32 40 48 56 64; do + fname=pkg_newcrc32_d$i.vhd + ./crc_gen2.py newcrc32_d$i L $i 0 1 2 4 5 7 8 10 11 12 16 22 23 26 32 > $fname +done + Index: experimental_jumbo_frames_version/fpga/src/pkt_ack_pkg.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/pkt_ack_pkg.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/pkt_ack_pkg.vhd (revision 22) @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +package pkt_ack_pkg is + +type pkt_ack is record + pkt : unsigned(31 downto 0); + seq : unsigned(15 downto 0); + cmd : unsigned(15 downto 0); +end record; + +constant pkt_ack_width : integer := 64; + +function pkt_ack_to_stlv( + constant din : pkt_ack) + return std_logic_vector; + +function stlv_to_pkt_ack( + constant din : std_logic_vector) + return pkt_ack; + +end pkt_ack_pkg; + +package body pkt_ack_pkg is + +function pkt_ack_to_stlv( + constant din : pkt_ack) + return std_logic_vector is + variable res : std_logic_vector(63 downto 0); +begin + res(31 downto 0) := std_logic_vector(din.pkt); + res(47 downto 32) := std_logic_vector(din.seq); + res(63 downto 48) := std_logic_vector(din.cmd); + return res; +end pkt_ack_to_stlv; + +function stlv_to_pkt_ack( + constant din : std_logic_vector) + return pkt_ack is + variable res : pkt_ack; +begin + res.pkt:=unsigned(din(31 downto 0)); + res.seq:=unsigned(din(47 downto 32)); + res.cmd:=unsigned(din(63 downto 48)); + return res; +end stlv_to_pkt_ack; + +end pkt_ack_pkg; Index: experimental_jumbo_frames_version/fpga/src/desc_manager_simple.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/desc_manager_simple.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/desc_manager_simple.vhd (revision 22) @@ -0,0 +1,676 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - descriptor manager +-- Project : +------------------------------------------------------------------------------- +-- File : desc_manager.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2014-10-20 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; +use work.pkt_desc_pkg.all; + +entity desc_memory is + + port ( + clk : in std_logic; + desc_we : in std_logic; + desc_addr : in integer range 0 to N_OF_PKTS-1; + desc_out : in pkt_desc; + desc_in : out pkt_desc); + +end desc_memory; + +architecture beh1 of desc_memory is + + type T_PKT_DESC_MEM is array (0 to N_OF_PKTS-1) of std_logic_vector(pkt_desc_width-1 downto 0); + signal desc_mem : T_PKT_DESC_MEM := (others => (others => '0')); + signal din : std_logic_vector(pkt_desc_width-1 downto 0) := (others => '0'); + signal dout : std_logic_vector(pkt_desc_width-1 downto 0) := (others => '0'); + signal rdaddr : integer range 0 to N_OF_PKTS-1; + + +begin -- beh1 + + din <= pkt_desc_to_stlv(desc_out); + desc_in <= stlv_to_pkt_desc(dout); + + process (clk) + begin -- process + if (clk'event and clk = '1') then -- rising clock edge + if (desc_we = '1') then + desc_mem(desc_addr) <= din; + end if; + rdaddr <= desc_addr; + end if; + end process; + dout <= desc_mem(rdaddr); + +end beh1; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; +use work.pkt_desc_pkg.all; + +entity desc_manager is + + generic ( + LOG2_N_OF_PKTS : integer := LOG2_N_OF_PKTS; + N_OF_PKTS : integer := N_OF_PKTS + ); -- Number of packet_logi buffers + + port ( + -- Data input interface + dta : in std_logic_vector(63 downto 0); + dta_we : in std_logic; + dta_eod : in std_logic; + dta_ready : out std_logic; + -- ETH Sender interface + pkt_number : out unsigned(31 downto 0); + seq_number : out unsigned(15 downto 0); + cmd_response_out : out std_logic_vector(12*8-1 downto 0); + snd_cmd_start : out std_logic; + snd_start : out std_logic; + flushed : out std_logic; + snd_ready : in std_logic; + + -- Data memory interface + dmem_addr : out std_logic_vector(LOG2_NWRDS_IN_PKT+LOG2_N_OF_PKTS-1 downto 0); + dmem_dta : out std_logic_vector(63 downto 0); + dmem_we : out std_logic; + -- Interface to the ACK FIFO + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + -- User command interface + cmd_code : out std_logic_vector(15 downto 0); + cmd_seq : out std_logic_vector(15 downto 0); + cmd_arg : out std_logic_vector(31 downto 0); + cmd_run : out std_logic; + cmd_retr_s : out std_logic; + cmd_ack : in std_logic; + cmd_response_in : in std_logic_vector(8*12-1 downto 0); + -- + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + -- + dbg : out std_logic_vector(3 downto 0); + -- + clk : in std_logic; + rst_n : in std_logic); + +end desc_manager; + +architecture dmgr_a1 of desc_manager is + + constant PKT_CNT_MAX : integer := 3000; + + + function is_bigger ( + constant v1, v2 : unsigned(15 downto 0)) + return boolean is + variable res : boolean; + variable tmp : unsigned(15 downto 0); + begin -- function is_bigger + -- subtract v2-v1 modulo 2**16 + tmp := v2-v1; + -- if the result is "negative" - bit 15 is '1' + -- and we consider v1 to be "bigger" (in modulo sense) than v2 + if tmp(15) = '1' then + return true; + else + return false; + end if; + + end function is_bigger; + + -- To simplify description of state machines, all registers are grouped + -- in a record : + + type T_DESC_MGR_REGS is record + cmd_ack : std_logic; + cmd_ack_0 : std_logic; + cmd_run : std_logic; + cmd_retr : std_logic; + cmd_code : unsigned(15 downto 0); + cmd_seq : unsigned(15 downto 0); + cmd_arg : unsigned(31 downto 0); + pkt : unsigned(31 downto 0); + cur_pkt : unsigned(31 downto 0); + seq : unsigned(15 downto 0); + ack_seq : unsigned(15 downto 0); + retr_flag : std_logic; + flushed : std_logic; + all_pkt_count : integer range 0 to PKT_CNT_MAX; + retr_pkt_count : integer range 0 to PKT_CNT_MAX; + retr_delay : unsigned(31 downto 0); + transm_delay : unsigned(31 downto 0); + nxt : unsigned(LOG2_N_OF_PKTS-1 downto 0); + tail_ptr : unsigned(LOG2_N_OF_PKTS-1 downto 0); + head_ptr : unsigned(LOG2_N_OF_PKTS-1 downto 0); + retr_ptr : unsigned(LOG2_N_OF_PKTS-1 downto 0); -- Number of the packet buffer, which is retransmitted + -- when equal to head_ptr - + -- retransmission is finished + retr_nxt : unsigned(LOG2_N_OF_PKTS-1 downto 0); -- buffer, which will be + -- retransmitted next + -- when equal to head_ptr -- no retransmission + -- is performed + end record; + + constant DESC_MGR_REGS_INI : T_DESC_MGR_REGS := ( + retr_delay => (others => '0'), + transm_delay => to_unsigned(10000, 32), + all_pkt_count => 0, + retr_pkt_count => 0, + cmd_ack_0 => '0', + cmd_ack => '0', + cmd_run => '0', + cmd_retr => '0', + cmd_code => (others => '0'), + cmd_seq => (others => '0'), + cmd_arg => (others => '0'), + pkt => (others => '0'), + seq => (others => '0'), + ack_seq => (others => '0'), + retr_flag => '0', + flushed => '0', + cur_pkt => (others => '0'), + nxt => (others => '0'), + tail_ptr => (others => '0'), + head_ptr => (others => '0'), + retr_ptr => (others => '0'), + retr_nxt => (others => '0') + ); + + -- To simplify setting of outputs of my Mealy state machine, all combinatorial + -- outputs are grouped in a record + type T_DESC_MGR_COMB is record + dta_buf_free : std_logic; + desc_addr : unsigned(LOG2_N_OF_PKTS-1 downto 0); + desc_we : std_logic; + ack_rd : std_logic; + snd_start : std_logic; + snd_cmd_start : std_logic; + desc_out : pkt_desc; + end record; + + constant DESC_MGR_COMB_DEFAULT : T_DESC_MGR_COMB := + ( + dta_buf_free => '0', + desc_addr => (others => '0'), + desc_we => '0', + ack_rd => '0', + snd_start => '0', + snd_cmd_start => '0', + desc_out => ( + confirmed => '0', + valid => '0', + sent => '0', + flushed => '0', + pkt => (others => '0'), + seq => (others => '0') + ) + ); + + type T_DESC_MGR_STATE is (ST_DMGR_IDLE, ST_DMGR_CMD, ST_DMGR_START, ST_DMGR_RST, ST_DMGR_RST1, + ST_DMGR_ACK1, ST_DMGR_INS1, ST_DMGR_INS2, ST_DMGR_ACK_TAIL, + ST_DMGR_ACK_TAIL_1, + ST_DMGR_RETR, ST_DMGR_RETR_2); + + signal desc_in : pkt_desc; + + signal r, r_i : T_DESC_MGR_REGS := DESC_MGR_REGS_INI; + signal c : T_DESC_MGR_COMB; + signal dmgr_state, dmgr_state_next : T_DESC_MGR_STATE := ST_DMGR_RST; + attribute keep : string; + attribute keep of dmgr_state : signal is "true"; + + signal dta_buf_full : std_logic := '0'; + signal dta_buf_flush : std_logic := '0'; + signal stored_dta_eod : std_logic := '0'; + + signal ack_pkt_in : pkt_ack; + + signal wrd_addr : integer range 0 to NWRDS_IN_PKT-1; -- We use 64-bit words, so the + -- data word address is between + -- 0 and 1023 + + component desc_memory + port ( + clk : in std_logic; + desc_we : in std_logic; + desc_addr : in integer range 0 to N_OF_PKTS-1; + desc_out : in pkt_desc; + desc_in : out pkt_desc); + end component; + + +begin -- dmgr_a1 + + transm_delay <= r.transm_delay; + pkt_number <= r.pkt; + seq_number <= r.seq; + flushed <= r.flushed; + dta_ready <= not dta_buf_full; + snd_start <= c.snd_start; + ack_fifo_rd_en <= c.ack_rd; + + cmd_code <= std_logic_vector(r.cmd_code); + cmd_seq <= std_logic_vector(r.cmd_seq); + cmd_arg <= std_logic_vector(r.cmd_arg); + cmd_run <= r.cmd_run; + cmd_retr_s <= r.cmd_retr; + snd_cmd_start <= c.snd_cmd_start; + + ack_pkt_in <= stlv_to_pkt_ack(ack_fifo_dout); + + -- Transmit command response only when the command is completed + -- (to avoid transmiting unstable values, which could e.g. affect + -- packet CRC calculations) + cmd_response_out <= cmd_response_in when r.cmd_ack = r.cmd_run else (others => '0'); + + -- Packet descriptors are stored in the desc_memory + + desc_memory_1 : desc_memory + port map ( + clk => clk, + desc_we => c.desc_we, + desc_addr => to_integer(c.desc_addr), + desc_out => c.desc_out, + desc_in => desc_in); + + -- Process used to fill the buffer memory with the data to be transmitted + -- We simply write words to the memory buffer pointed by r.head_ptr + -- When we write the last (0xff-th) word, we signal that the buffer + -- is full. + -- Additionally, when the buffer is partially filled, but the transmission + -- is stopped, we should also signal, that the buffer must be transmitted. + -- However in this case we should also inform the recipient about it. + -- How we can do it? + dta_rcv : process (clk, rst_n) + begin -- process dta_rcv + if rst_n = '0' then -- asynchronous reset (active low) + wrd_addr <= 0; + dta_buf_flush <= '0'; + dta_buf_full <= '0'; + dmem_we <= '0'; + stored_dta_eod <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + dmem_we <= '0'; + -- if we signalled "data full", we are only waiting for + -- dta_buf_free; + -- However even in this state we must receive the "dta_eod" signal + if dta_buf_full = '1' then + if dta_eod = '1' then + stored_dta_eod <= '1'; + end if; + if c.dta_buf_free = '1' then + dta_buf_full <= '0'; + dta_buf_flush <= '0'; + wrd_addr <= 0; + end if; + else + -- end of data is signalled, mark the last buffer as full + if (dta_eod = '1') or (stored_dta_eod = '1') then + -- Clear the stored eod + stored_dta_eod <= '0'; + -- In the last word of the packet, write the number of written words + dmem_addr <= std_logic_vector(r.head_ptr) & + std_logic_vector(to_unsigned(NWRDS_IN_PKT-1, LOG2_NWRDS_IN_PKT)); + dmem_dta <= std_logic_vector(to_unsigned(wrd_addr, 64)); + dmem_we <= '1'; + dta_buf_flush <= '1'; + dta_buf_full <= '1'; + -- if data write requested - write it + elsif dta_we = '1' then + dmem_addr <= std_logic_vector(r.head_ptr) & + std_logic_vector(to_unsigned(wrd_addr, LOG2_NWRDS_IN_PKT)); + dmem_we <= '1'; + dmem_dta <= dta; + if wrd_addr < NWRDS_IN_PKT-1 then + wrd_addr <= wrd_addr + 1; + else + dta_buf_flush <= '0'; + dta_buf_full <= '1'; + end if; + end if; + end if; + end if; + end process dta_rcv; + + + c1 : process (ack_fifo_empty, ack_pkt_in, cmd_ack, desc_in, + dmgr_state, dta_buf_full, dta_buf_flush, r, snd_ready) + begin -- process c1 + c <= DESC_MGR_COMB_DEFAULT; -- set defaults + r_i <= r; -- avoid latches + -- Synchronize command acknowledge lines + r_i.cmd_ack_0 <= cmd_ack; + r_i.cmd_ack <= r.cmd_ack_0; + if r.retr_delay /= to_unsigned(0, r.retr_delay'length) then + r_i.retr_delay <= r.retr_delay-1; + end if; + dmgr_state_next <= dmgr_state; + -- State machine + case dmgr_state is + when ST_DMGR_RST => + dbg <= x"1"; + dmgr_state_next <= ST_DMGR_RST1; + when ST_DMGR_RST1 => + -- We should initialize the 0th position of list descriptors + dbg <= x"2"; + c.desc_addr <= r.head_ptr; + c.desc_out <= desc_in; + c.desc_out.confirmed <= '0'; + c.desc_out.valid <= '0'; + c.desc_out.sent <= '0'; + c.desc_out.pkt <= to_unsigned(0, 32); + c.desc_we <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + when ST_DMGR_IDLE => + dbg <= x"3"; + -- First we check, if there are any packets to acknowledge + -- or commands to execute + if ack_fifo_empty = '0' then + if (to_integer(ack_pkt_in.cmd) = FCMD_ACK) or + (to_integer(ack_pkt_in.cmd) = FCMD_NACK) then + -- Prepare for reading of the command. + c.desc_addr <= ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0); + dmgr_state_next <= ST_DMGR_ACK1; + else + -- This is a command which requires sending of response. + -- This will be handled by the cmd_proc block (in case + -- of START and STOP it is not the most efficient way, + -- but still sufficient). + -- Always request transmission of result + r_i.cmd_retr <= '1'; + -- Check if this is a new command (just checking the sequence number, + -- to avoid more complex logic) + if ack_pkt_in.seq /= r.cmd_seq then + -- If no, store the command and it's argument, and order it to be executed + r_i.cmd_code <= ack_pkt_in.cmd; + r_i.cmd_seq <= ack_pkt_in.seq; + r_i.cmd_arg <= ack_pkt_in.pkt; + end if; + c.ack_rd <= '1'; -- Confirm, that the command was read + dmgr_state_next <= ST_DMGR_CMD; + end if; + elsif dta_buf_full = '1' then + -- We should handle reception of data. + -- If the previously filled buffer is full, pass it for transmission, + -- and allocate the next one. + -- + -- Calculate the number of the packet, which shoud be the next "head" + -- packet. We utilize the fact, that calculations are performed modulo + -- N_OF_PKTS (because pointers have length of LOG2_N_OF_PKTS) + r_i.nxt <= r.head_ptr + 1; + -- Prepare for reading of the current "head" descriptor + c.desc_addr <= r.head_ptr; + dmgr_state_next <= ST_DMGR_INS1; + elsif (r.tail_ptr /= r.head_ptr) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then + -- We need to (re)transmit some buffers + -- prepare reading of the descriptor, which should be transmitted + c.desc_addr <= r.retr_nxt; + dmgr_state_next <= ST_DMGR_RETR; + elsif r.cmd_retr = '1' and (r.cmd_ack = r.cmd_run) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then + -- No data waiting for transmission, and the command response should + -- be transmitted + if snd_ready = '1' then + r_i.retr_delay <= r.transm_delay; + r_i.cmd_retr <= '0'; + c.snd_cmd_start <= '1'; + end if; + end if; + when ST_DMGR_CMD => + r_i.cmd_run <= not r.cmd_run; + dmgr_state_next <= ST_DMGR_IDLE; + when ST_DMGR_INS1 => + dbg <= x"4"; + -- First we check, if there is free space, r.nxt is the number of the + -- future head packet. + if (r.nxt = r.tail_ptr) then + -- No free place! The packet, which we would like to fill is still + -- occupied. + -- Return to idle, waiting until something is freed. + -- In this case we should also force retransmission + if r.retr_delay = 0 then + c.desc_addr <= r.retr_nxt; + dmgr_state_next <= ST_DMGR_RETR; + else + dmgr_state_next <= ST_DMGR_IDLE; + end if; + else + -- We can fill the next buffer + -- First we mark the previous head packet + -- as valid and not confirmed + -- We also set the "flushed" status appropriately + c.desc_addr <= r.head_ptr; + c.desc_out <= desc_in; + c.desc_out.confirmed <= '0'; + c.desc_out.valid <= '1'; + if dta_buf_flush = '1' then + c.desc_out.flushed <= '1'; + else + c.desc_out.flushed <= '0'; + end if; + c.desc_we <= '1'; + -- Now we move the "head" pointer + r_i.head_ptr <= r.nxt; + -- Increase the packet number! + -- We utilize the fact, that packet number automatically + -- wraps to 0 after sending of 2**32 packets! + r_i.cur_pkt <= r.cur_pkt + 1; + dmgr_state_next <= ST_DMGR_INS2; + end if; + when ST_DMGR_INS2 => + dbg <= x"5"; + -- We fill the new head descriptor + c.desc_addr <= r.head_ptr; + c.desc_out.pkt <= r.cur_pkt; + c.desc_out.confirmed <= '0'; + c.desc_out.valid <= '0'; + c.desc_out.sent <= '0'; + c.desc_out.flushed <= '0'; + c.desc_we <= '1'; + -- Signal, that the buffer is freed + c.dta_buf_free <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + when ST_DMGR_ACK1 => + dbg <= x"6"; + -- In this state the desc memory should respond with the data of the + -- buffered packet, so we can state, if this packet is really correctly + -- acknowledged (here we also ignore the NACK packets! + case to_integer(ack_pkt_in.cmd) is + when FCMD_ACK => + if (ack_pkt_in.pkt = desc_in.pkt) and + (desc_in.valid = '1') then + -- This is really correct, unconfirmed packet + -- Increase the counter of not-repeated ACK packets + -- Write the confirmation + c.desc_addr <= ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0); + c.desc_out <= desc_in; + c.desc_out.valid <= '0'; + c.desc_out.confirmed <= '1'; + c.desc_we <= '1'; + -- Here we also handle the case, if the acknowledged packet was + -- the one which is now scheduled for retransmission... + if ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0) = r.retr_nxt then + r_i.retr_nxt <= r.retr_nxt + 1; + end if; + -- Check, if we need to update the "tail" pointer + if r.tail_ptr = ack_pkt_in.pkt(LOG2_N_OF_PKTS-1 downto 0) then + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_ACK_TAIL; + else + -- If this is not the tail pointer, it means, that some packets + -- or acknowledgements have been lost + -- We trigger retransmission of those packets + r_i.ack_seq <= ack_pkt_in.seq; + r_i.retr_nxt <= r.tail_ptr; + -- Set the flag stating that only "earlier" packets should be retransmitted + r_i.retr_flag <= '1'; + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + end if; + else + -- This packet was already confirmed + -- just flush the ack_fifo + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + end if; + when FCMD_NACK=> + -- This was a NACK command, currently we simply ignore it + -- (later on we will use it to trigger retransmission). + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + when others => null; + end case; + when ST_DMGR_ACK_TAIL => + dbg <= x"7"; + c.desc_addr <= r.tail_ptr; + dmgr_state_next <= ST_DMGR_ACK_TAIL_1; + when ST_DMGR_ACK_TAIL_1 => + dbg <= x"8"; + -- In this state we update the "tail" pointer if necessary + if r.tail_ptr /= r.head_ptr then + if desc_in.confirmed = '1' then + r_i.tail_ptr <= r.tail_ptr + 1; -- it will wrap to 0 automatically! + c.desc_addr <= r.tail_ptr + 1; + -- We remain in that state, to check the next packet descriptor + else + -- We return to idle + dmgr_state_next <= ST_DMGR_IDLE; + end if; + else + -- Buffer is empty - return to idle + dmgr_state_next <= ST_DMGR_IDLE; + end if; + when ST_DMGR_RETR => + dbg <= x"9"; + -- Here we handle the transmission of a new packet, + -- retransmission of not confirmed packet + -- We must be sure, that the transmitter is ready + if snd_ready = '0' then + -- transmitter not ready, return to idle + dmgr_state_next <= ST_DMGR_IDLE; + else + -- We will be able to send the next packet, but let's check if + -- this is not the currently filled packet + if r.retr_nxt = r.head_ptr then + -- All packets (re)transmitted, go to the begining of the list + r_i.retr_nxt <= r.tail_ptr; + -- Clear the flag stating that only packets older than the last + -- acknowledged should be transmitted + r_i.retr_flag <= '0'; + -- and return to idle. + dmgr_state_next <= ST_DMGR_IDLE; + else + -- before jumping to ST_DMGR_RETR, the address bus + -- was set to the address of r.retr_nxt, so now + -- we can read the descriptor, and check if the packet + -- needs to be retransmitted at all... + r_i.pkt <= desc_in.pkt; + r_i.flushed <= desc_in.flushed; + r_i.retr_ptr <= r.retr_nxt; + r_i.retr_nxt <= r.retr_nxt + 1; + if desc_in.valid = '1' and desc_in.confirmed = '0' and + ((r.retr_flag = '0') or is_bigger(r.ack_seq, desc_in.seq)) then + if desc_in.sent = '1' then + -- Increase count of retransmitted packets for + -- adaptive adjustment of delay + if r.retr_pkt_count < PKT_CNT_MAX then + r_i.retr_pkt_count <= r.retr_pkt_count + 1; + end if; + end if; + -- Increase count of all packets for adaptive adjustment + -- of delay + if r.all_pkt_count < PKT_CNT_MAX then + r_i.all_pkt_count <= r.all_pkt_count + 1; + end if; + -- Mark the packet as sent + c.desc_addr <= r.retr_nxt; + c.desc_out <= desc_in; + c.desc_out.sent <= '1'; + -- increase the sequential number + r_i.seq <= r.seq + 1; + -- store the packet sequential number + c.desc_out.seq <= r.seq + 1; + c.desc_we <= '1'; + dmgr_state_next <= ST_DMGR_RETR_2; + else + dmgr_state_next <= ST_DMGR_IDLE; + end if; + end if; + end if; + when ST_DMGR_RETR_2 => + dbg <= x"a"; + -- In this state, we simply trigger the sender! + c.snd_start <= '1'; + if r.cmd_ack = r.cmd_run then + -- command response will be transmitted, so clear the related flag + r_i.cmd_retr <= '0'; + end if; + r_i.retr_delay <= r.transm_delay; + -- And we update the delay using the packet statistics + -- You may change the constants used in expressions + -- below to change speed of adjustment + if r.all_pkt_count >= PKT_CNT_MAX then + if r.retr_pkt_count < PKT_CNT_MAX/32 then + if r.transm_delay > 16 then + r_i.transm_delay <= r.transm_delay-r.transm_delay/16; + end if; + elsif r.retr_pkt_count > PKT_CNT_MAX/8 then + if r.transm_delay < 1000000 then + r_i.transm_delay <= r.transm_delay+r.transm_delay/4; + end if; + end if; + r_i.all_pkt_count <= 0; + r_i.retr_pkt_count <= 0; + end if; + dmgr_state_next <= ST_DMGR_IDLE; + when others => null; + end case; + end process c1; + +-- Synchronous process + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + r <= DESC_MGR_REGS_INI; + dmgr_state <= ST_DMGR_RST; + elsif clk'event and clk = '1' then -- rising clock edge + r <= r_i; + dmgr_state <= dmgr_state_next; + end if; + end process; + +end dmgr_a1; + + + Index: experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d8.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d8.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/pkg_newcrc32_d8.vhd (revision 22) @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +package pkg_newcrc32_d8 is + -- CRC update for 32-bit CRC and 8-bit data (LSB first) + -- The CRC polynomial exponents: [0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26, 32] + function newcrc32_d8( + din : std_logic_vector(7 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector; +end pkg_newcrc32_d8; + +package body pkg_newcrc32_d8 is + function newcrc32_d8( + din : std_logic_vector(7 downto 0); + crc : std_logic_vector(31 downto 0)) + return std_logic_vector is + variable c, n : std_logic_vector(31 downto 0); + variable d : std_logic_vector(7 downto 0); + begin + c := crc; + d := din; + n(0) := c(24) xor c(30) xor d(1) xor d(7); + n(1) := c(24) xor c(25) xor c(30) xor c(31) xor d(0) xor d(1) xor d(6) xor d(7); + n(2) := c(24) xor c(25) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5) xor d(6) xor d(7); + n(3) := c(25) xor c(26) xor c(27) xor c(31) xor d(0) xor d(4) xor d(5) xor d(6); + n(4) := c(24) xor c(26) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(5) xor d(7); + n(5) := c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(7); + n(6) := c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6); + n(7) := c(24) xor c(26) xor c(27) xor c(29) xor c(31) xor d(0) xor d(2) xor d(4) xor d(5) xor d(7); + n(8) := c(0) xor c(24) xor c(25) xor c(27) xor c(28) xor d(3) xor d(4) xor d(6) xor d(7); + n(9) := c(1) xor c(25) xor c(26) xor c(28) xor c(29) xor d(2) xor d(3) xor d(5) xor d(6); + n(10) := c(2) xor c(24) xor c(26) xor c(27) xor c(29) xor d(2) xor d(4) xor d(5) xor d(7); + n(11) := c(3) xor c(24) xor c(25) xor c(27) xor c(28) xor d(3) xor d(4) xor d(6) xor d(7); + n(12) := c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7); + n(13) := c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31) xor d(0) xor d(1) xor d(2) xor d(4) xor d(5) xor d(6); + n(14) := c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31) xor d(0) xor d(1) xor d(3) xor d(4) xor d(5); + n(15) := c(7) xor c(27) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(4); + n(16) := c(8) xor c(24) xor c(28) xor c(29) xor d(2) xor d(3) xor d(7); + n(17) := c(9) xor c(25) xor c(29) xor c(30) xor d(1) xor d(2) xor d(6); + n(18) := c(10) xor c(26) xor c(30) xor c(31) xor d(0) xor d(1) xor d(5); + n(19) := c(11) xor c(27) xor c(31) xor d(0) xor d(4); + n(20) := c(12) xor c(28) xor d(3); + n(21) := c(13) xor c(29) xor d(2); + n(22) := c(14) xor c(24) xor d(7); + n(23) := c(15) xor c(24) xor c(25) xor c(30) xor d(1) xor d(6) xor d(7); + n(24) := c(16) xor c(25) xor c(26) xor c(31) xor d(0) xor d(5) xor d(6); + n(25) := c(17) xor c(26) xor c(27) xor d(4) xor d(5); + n(26) := c(18) xor c(24) xor c(27) xor c(28) xor c(30) xor d(1) xor d(3) xor d(4) xor d(7); + n(27) := c(19) xor c(25) xor c(28) xor c(29) xor c(31) xor d(0) xor d(2) xor d(3) xor d(6); + n(28) := c(20) xor c(26) xor c(29) xor c(30) xor d(1) xor d(2) xor d(5); + n(29) := c(21) xor c(27) xor c(30) xor c(31) xor d(0) xor d(1) xor d(4); + n(30) := c(22) xor c(28) xor c(31) xor d(0) xor d(3); + n(31) := c(23) xor c(29) xor d(2); + return n; + end newcrc32_d8; +end pkg_newcrc32_d8; + Index: experimental_jumbo_frames_version/fpga/src/rec_to_pkg.py =================================================================== --- experimental_jumbo_frames_version/fpga/src/rec_to_pkg.py (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/rec_to_pkg.py (revision 22) @@ -0,0 +1,139 @@ +#!/usr/bin/python +# The script below is written by Wojciech M. Zabolotny +# wzabise.pw.edu.pl 27.09.2014 +# it is published as PUBLIC DOMAIN +import sys +class field: + last_bit = 0; + def __init__(self,field_desc): + fd = field_desc.split(",") + self.fname = fd[0] + #"std_logic" is handled in a special way + if fd[1]=="std_logic": + self.ftype = fd[1] + self.b1=0 + self.b2=0 + elif not fd[1] in ["signed","unsigned","std_logic_vector"]: + raise Exception("Wrong field type") + else: + self.ftype = fd[1] + if len(fd)==3: + self.b1=int(fd[2])-1 + self.b2=0 + elif len(fd)==4: + self.b1=int(fd[2]) + self.b2=int(fd[3]) + else: + raise Exception("Syntax error in line: "+field_desc) + #Assign vector bits + self.v1=field.last_bit + self.v2=field.last_bit+abs(self.b2-self.b1) + field.last_bit = self.v2+1 + +if len(sys.argv) != 2: + print """ +The rec_to_pkg scripts creates VHDL package for conversion +between the VHDL records containing "signed", "unsigned", +"std_logic_vector" and "std_logic" fields and std_logic_vectors. +It should be called as: rec_to_pkg.py description_file +where the description file should have the following syntax: + +#Optional comment line +record record_name +#optional comment lines +#[...] +field_name,signed_or_unsigned,width +#or +field_name,signed_or_unsigned,left_bit_nr,right_bit_nr +end + +The generated package is written to the record_name_pkg.vhd file +""" + exit(0) +fin=open(sys.argv[1]) +#Read the full description of the type +type_desc=[l.strip() for l in fin.readlines() if len(l) > 0 and l[0] != "#" ] +#The first line should contain the record name +l=type_desc[0].split(" ") +if l[0] != "record": + raise Exception("Syntax error! The first line should have form \"record name_of_type\"") +type_name=l[1] +pkg_name=type_name+"_pkg" +#Prepare for analysis of fields +msb=0 +fields=[] +end_found = False +#Find the field definitions +for l in type_desc[1:]: + if l=="end": + end_found=True + break + fields.append(field(l)) +if not end_found: + raise Exception("Syntax error: no \"end\" found") +#If we got here, probably the syntax was correct +#Lets generate the package +p="""\ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +""" +p+="package "+pkg_name+" is\n\n" +p+="type "+type_name+" is record\n" +for f in fields: + if f.ftype=="std_logic": + s=" "+f.fname+" : "+f.ftype+";\n" + else: + s=" "+f.fname+" : "+f.ftype+"(" + if f.b1 > f.b2: + s=s+str(f.b1)+" downto "+str(f.b2)+");\n" + else: + s=s+str(f.b1)+" to "+str(f.b2)+");\n" + p+=s +p+="end record;\n\n" +#Write width of our type +p+="constant "+type_name+"_width : integer := "+str(field.last_bit)+";\n\n" +#Write headers of conversion functions +p+="function "+type_name+"_to_stlv(\n" +p+=" constant din : "+type_name+")\n" +p+=" return std_logic_vector;\n\n" +p+="function stlv_to_"+type_name+"(\n" +p+=" constant din : std_logic_vector)\n" +p+=" return "+type_name+";\n\n" +p+="end "+pkg_name+";\n\n" +#Now the body of the package - the conversion functions +p+="package body "+pkg_name+" is\n\n" +# +p+="function "+type_name+"_to_stlv(\n" +p+=" constant din : "+type_name+")\n" +p+=" return std_logic_vector is\n" +p+=" variable res : std_logic_vector("+str(field.last_bit-1)+" downto 0);\n" +p+="begin\n" +for f in fields: + if f.ftype=="std_logic": + p+=" res("+str(f.v1)+") := din."+f.fname+";\n" + else: + p+=" res("+str(f.v2)+" downto "+str(f.v1)+ ") := std_logic_vector(din."+f.fname+");\n" +p+=" return res;\n" +p+="end "+type_name+"_to_stlv;\n\n" +# +p+="function stlv_to_"+type_name+"(\n" +p+=" constant din : std_logic_vector)\n" +p+=" return "+type_name+" is\n" +p+=" variable res : "+type_name+";\n" +p+="begin\n" +for f in fields: + if f.ftype=="std_logic": + p+=" res."+f.fname+" := din("+str(f.v1)+");\n" + else: + p+=" res."+f.fname+":="+f.ftype+"(din("+str(f.v2)+" downto "+str(f.v1)+"));\n" +p+=" return res;\n" +p+="end stlv_to_"+type_name+";\n\n" +p+="end "+pkg_name+";\n" + +#The output file name +fout_name=type_name+"_pkg.vhd" +fout=open(fout_name,"w") +fout.write(p) +fout.close() +

experimental_jumbo_frames_version/fpga/src/rec_to_pkg.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: experimental_jumbo_frames_version/fpga/src/desc_mgr_pkg.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/desc_mgr_pkg.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/desc_mgr_pkg.vhd (revision 22) @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +use ieee.std_logic_textio.all; +library work; +use work.pkt_ack_pkg.all; + +package desc_mgr_pkg is + + constant LOG2_N_OF_PKTS : integer := 4; + constant N_OF_PKTS : integer := 2**LOG2_N_OF_PKTS; + constant LOG2_NWRDS_IN_PKT : integer := 10; + constant NWRDS_IN_PKT : integer := 1024; + constant N_OF_SETS : integer := 65536; + + -- Commands + constant FCMD_START : integer := 1; + constant FCMD_STOP : integer := 2; + constant FCMD_ACK : integer := 3; + constant FCMD_NACK : integer := 4; + constant FCMD_RESET : integer := 5; + +end desc_mgr_pkg; + Index: experimental_jumbo_frames_version/fpga/src/ack.rec =================================================================== --- experimental_jumbo_frames_version/fpga/src/ack.rec (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/ack.rec (revision 22) @@ -0,0 +1,12 @@ +# This is a test record - packet acknowledgment +record pkt_ack +# Below are fields definitions +# First two pointers fo linked list +# pkt - number of the packet +pkt,unsigned,32 +# seq - sequential number of the packet +seq,unsigned,16 +# cmd - command - 1 for ACK +cmd,unsigned,16 +end + Index: experimental_jumbo_frames_version/fpga/src/cmd_proc.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/cmd_proc.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/cmd_proc.vhd (revision 22) @@ -0,0 +1,99 @@ +------------------------------------------------------------------------------- +-- Title : User command processor +-- Project : +------------------------------------------------------------------------------- +-- File : cmd_proc.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2014-10-04 +-- Last update: 2014-10-12 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: This block performs the user defined commands +-- but also generates responses for some internal commands. +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2014 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2014-10-04 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; +use work.pkt_desc_pkg.all; +entity cmd_proc is + + port ( + cmd_code : in std_logic_vector(15 downto 0); + cmd_seq : in std_logic_vector(15 downto 0); + cmd_arg : in std_logic_vector(31 downto 0); + cmd_run : in std_logic; + cmd_ack : out std_logic; + cmd_response : out std_logic_vector(8*12-1 downto 0); + clk : in std_logic; + rst_p : in std_logic + ); + +end entity cmd_proc; + +architecture beh of cmd_proc is + + signal cmd_run_0, cmd_run_1, cmd_run_2 : std_logic := '0'; + signal del_count : integer range 0 to 1000 := 0; + +begin -- architecture beh + + process (clk, rst_p) is + begin -- process + if rst_p = '1' then -- asynchronous reset (active low) + cmd_ack <= '0'; + cmd_run_0 <= '0'; + cmd_run_1 <= '0'; + cmd_run_2 <= '0'; + del_count <= 0; + cmd_response <= (others => '0'); + elsif clk'event and clk = '1' then -- rising clock edge + -- Synchronize cmd_run signals + cmd_run_2 <= cmd_run; + cmd_run_1 <= cmd_run_2; + cmd_run_0 <= cmd_run_1; + -- Detect command strobe + if cmd_run_1 /= cmd_run_0 then + -- Line cmd_run has changed its state, it means that we need + -- to execute a command + if cmd_code(15 downto 8) = x"00" then + -- For internal commands just send response immediately + cmd_response <= cmd_code & cmd_seq & -- This fields should be always + -- sent on the begining of response! + x"00000000" & x"00000000"; + cmd_ack <= cmd_run; + else + -- Now we just simulate it, so let's start delay counter + del_count <= 100; -- execution of command takes 100 ckp + end if; + end if; + -- We simulate execution of the user command, which was triggered by above + -- "if" block + if del_count > 0 then + -- Decrease del_count until it is zero + del_count <= del_count-1; + end if; + if del_count = 1 then + -- Send response to the command: + cmd_response <= cmd_code & cmd_seq & -- This fields should be always + -- sent on the begining of response! + cmd_arg & x"900dbabe"; + cmd_ack <= cmd_run; + end if; + end if; + end process; + +end architecture beh; Index: experimental_jumbo_frames_version/fpga/src/crc_gen2.py =================================================================== --- experimental_jumbo_frames_version/fpga/src/crc_gen2.py (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/crc_gen2.py (revision 22) @@ -0,0 +1,136 @@ +#!/usr/bin/python +# This is the public domain code written by Wojciech M. Zabolotny +# ( wzab(at)ise.pw.edu.pl ) +# The functionality has been inspired by the CRC Tool available +# at http://www.easics.com/webtools/crctool , however the code +# has been written independently. +# In fact I have decided to write this code, when I was not able to +# generate CRC with the crctool for a particular non-typical length +# of data word. +# The program crc_gen.py generates the VHDL code for CRC update for given +# length of the data vector. +# The length of the CRC results from the coefficient of the CRC polynomial. +# The arguments are as follows: +# 1st: Function name. The package name is created by prefixing it with +# pkg_ +# 2nd: L - for data fed LSB first, M for data fed MSB first +# 3rd: the width of the data bus, +# 4th and next: the coefficients of the polynomial (the exponents in fact). +# For example, to generate the expression for CRC7 for 12bit data transmitted LSB first +# you should call: +# crc_gen.py crc7_d12 L 12 7 3 0 +# To generate CRC-12 for 16 bit data transmitted MSB first, you should call: +# crc_gen.py crc12_d16 M 16 12 11 3 2 1 0 +# The generated code implements a package with the function calculating +# the new value of the CRC from the previous value of the CRC and +# the data word. +import sys +fun_name=sys.argv[1] +pkg_name = "pkg_"+fun_name +data_order=sys.argv[2] +if data_order != 'L' and data_order != 'M': + print "The second argument must be 'L' or 'M', not the '"+data_order+"'" + sys.exit(1) +data_len=int(sys.argv[3]) +poly=[] +for i in range(4,len(sys.argv)): + poly.append(int(sys.argv[i])) +crc_len=max(poly) + +#The class "xor_result" implements result of xor-ing of multiple +# CRC and DATA bits +# dirty trick: the class relies on global variables crc_len and data_len +class xor_result: + def __init__(self,c=-1,d=-1): + self.c=crc_len*[0] + self.d=data_len*[0] + if(c>-1): + self.c[c]=1 + if(d>-1): + self.d[d]=1 + def copy(self): + res=xor_result() + for i in range(0,crc_len): + res.c[i]=self.c[i] + for i in range(0,data_len): + res.d[i]=self.d[i] + return res + # The new XOR operator + def __xor__(self,x): + res=xor_result() + for i in range(0,crc_len): + res.c[i]=self.c[i]^x.c[i] + for i in range(0,data_len): + res.d[i]=self.d[i]^x.d[i] + return res + def tostr(self): + res="" + for i in range(0,crc_len): + if self.c[i]==1: + if res=="": + res+="c("+str(i)+")" + else: + res+=" xor c("+str(i)+")" + for i in range(0,data_len): + if self.d[i]==1: + if res=="": + res+="d("+str(i)+")" + else: + res+=" xor d("+str(i)+")" + return res + + +#Now we create the CRC vector, which initially contains only the bits +#of the initial value of the CRC +CRC=[ xor_result(c=i) for i in range(0,crc_len) ] +#And the data vector +DATA=[ xor_result(d=i) for i in range(0,data_len) ] +#Now we pass the data through the CRC polynomial +if data_order == 'L': + d_range = range(0,data_len) + ord_name = "LSB" +elif data_order == 'M': + d_range = range(data_len-1,-1,-1) + ord_name = "MSB" +else: + print "Internal error" + sys.exit(1) +for i in d_range: + #We create the vector for the new CRC + NCRC = [ xor_result() for k in range(0,crc_len) ] + #First - the basic shift operation + for j in range(1,crc_len): + NCRC[j]=CRC[j-1].copy() + #Now we add the feedback + FB=DATA[i] ^ CRC[crc_len-1] + for j in poly: + if j == crc_len: + # This does not require any action + pass + else: + NCRC[j]=NCRC[j] ^ FB + CRC=NCRC +pkg_text = '''library ieee; +use ieee.std_logic_1164.all; +package ''' + pkg_name +" is\n" +pkg_text += " -- CRC update for "+str(crc_len)+"-bit CRC and "+\ + str(data_len)+"-bit data ("+ord_name+" first)\n" +pkg_text += " -- The CRC polynomial exponents: "+str(poly)+"\n" +fun_decl = ' function ' + fun_name +"(\n" +\ +' din : std_logic_vector('+str(data_len-1)+' downto 0);\n'+\ +' crc : std_logic_vector('+str(crc_len-1)+' downto 0))\n'+\ +' return std_logic_vector' +pkg_text += fun_decl+';\n' +pkg_text += 'end '+pkg_name+';\n\n' +pkg_text += "package body " + pkg_name +" is\n" +pkg_text += fun_decl + ' is \n' +pkg_text += ' variable c,n : std_logic_vector(' + str(crc_len-1)+' downto 0);\n' +pkg_text += ' variable d : std_logic_vector(' + str(data_len-1)+' downto 0);\n' +pkg_text += ' begin\n' +pkg_text += ' c := crc;\n d := din; \n' +for i in range(0,len(CRC)): + pkg_text += " n("+str(i)+") := "+CRC[i].tostr()+";\n" +pkg_text += ' return n;\n' +pkg_text += ' end '+fun_name+";\n" +pkg_text += 'end '+pkg_name+";\n" +print pkg_text

experimental_jumbo_frames_version/fpga/src/crc_gen2.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: experimental_jumbo_frames_version/fpga/src/pkt_desc_pkg.vhd =================================================================== --- experimental_jumbo_frames_version/fpga/src/pkt_desc_pkg.vhd (nonexistent) +++ experimental_jumbo_frames_version/fpga/src/pkt_desc_pkg.vhd (revision 22) @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +package pkt_desc_pkg is + +type pkt_desc is record + pkt : unsigned(31 downto 0); + seq : unsigned(15 downto 0); + valid : std_logic; + confirmed : std_logic; + sent : std_logic; + flushed : std_logic; +end record; + +constant pkt_desc_width : integer := 52; + +function pkt_desc_to_stlv( + constant din : pkt_desc) + return std_logic_vector; + +function stlv_to_pkt_desc( + constant din : std_logic_vector) + return pkt_desc; + +end pkt_desc_pkg; + +package body pkt_desc_pkg is + +function pkt_desc_to_stlv( + constant din : pkt_desc) + return std_logic_vector is + variable res : std_logic_vector(51 downto 0); +begin + res(31 downto 0) := std_logic_vector(din.pkt); + res(47 downto 32) := std_logic_vector(din.seq); + res(48) := din.valid; + res(49) := din.confirmed; + res(50) := din.sent; + res(51) := din.flushed; + return res; +end pkt_desc_to_stlv; + +function stlv_to_pkt_desc( + constant din : std_logic_vector) + return pkt_desc is + variable res : pkt_desc; +begin + res.pkt:=unsigned(din(31 downto 0)); + res.seq:=unsigned(din(47 downto 32)); + res.valid := din(48); + res.confirmed := din(49); + res.sent := din(50); + res.flushed := din(51); + return res; +end stlv_to_pkt_desc; + +end pkt_desc_pkg;