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URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

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/trunk/linux/fpga_l3_fade.h
0,0 → 1,59
/*
* fpga_l3_fade - header for L3 communication protocol with FPGA based system
* Copyright (C) 2012 by Wojciech M. Zabolotny
* Institute of Electronic Systems, Warsaw University of Technology
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Additionally I (Wojciech Zabolotny) allow you to include this header file
* to compile your closed source applications (however yo should check, that
* license terms of other include files used by this one allow you to do it...).
*/
 
#ifndef _FPGA_L3_FADE_H_
 
 
#include <linux/socket.h>
#include <linux/if_ether.h>
#include <linux/if.h>
 
struct l3_v1_buf_pointers {
int head;
int tail;
} __attribute__ ((__packed__));
 
struct l3_v1_slave {
unsigned char mac[ETH_ALEN];
char devname[IFNAMSIZ];
} __attribute__ ((__packed__));
 
#define L3_V1_IOC_MAGIC 0xa5
 
#define L3_V1_IOC_SETWAKEUP _IO(L3_V1_IOC_MAGIC,0x30)
#define L3_V1_IOC_GETBUFLEN _IO(L3_V1_IOC_MAGIC,0x31)
#define L3_V1_IOC_READPTRS _IOR(L3_V1_IOC_MAGIC,0x32,struct l3_v1_buf_pointers)
#define L3_V1_IOC_WRITEPTRS _IO(L3_V1_IOC_MAGIC,0x33)
#define L3_V1_IOC_STARTMAC _IOW(L3_V1_IOC_MAGIC,0x34,struct l3_v1_slave)
#define L3_V1_IOC_STOPMAC _IO(L3_V1_IOC_MAGIC,0x35)
 
/* Error flags */
#define FADE_ERR_INCORRECT_PACKET_TYPE (1<<0)
#define FADE_ERR_INCORRECT_SET (1<<1)
#define FADE_ERR_INCORRECT_LENGTH (1<<2)
 
 
 
#define _FPGA_L3_FADE_H_
#endif
/trunk/linux/receiver2.c
0,0 → 1,142
/*
* fpga_l3_fade - driver for L3 communication protocol with FPGA based system
* Copyright (C) 2012 by Wojciech M. Zabolotny
* Institute of Electronic Systems, Warsaw University of Technology
*
* This code is PUBLIC DOMAIN
*/
 
#include<termios.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <poll.h>
#include <unistd.h>
#include <stdio.h>
#include <strings.h>
#include <stdlib.h>
#include <stdint.h>
 
#include <sys/socket.h>
#include <linux/serial.h>
#include <sched.h>
#include "fpga_l3_fade.h"
#include <sys/time.h>
 
void main()
{
struct l3_v1_buf_pointers bp;
struct l3_v1_slave sl[3] = {
{
.mac = {0xde, 0xad, 0xba, 0xbe, 0xbe,0xef},
.devname = "eth0"
},
{
.mac = {0xde, 0xad, 0xba, 0xbe, 0xbe,0xe1},
.devname = "eth0"
},
{
.mac = {0xde, 0xad, 0xba, 0xbe, 0xbe,0xe2},
.devname = "eth0"
}
};
int i,j;
int res;
int blen[3];
uint32_t data[3] = {0,0,0};
long long total_len[3]={0,0,0};
unsigned char * v[3];
int frs[3]={-1,-1,-1};
struct timeval tv;
double tstart=0.0 , tend=0.0;
int stop;
struct sched_param s;
s.sched_priority = 90;
printf("sched=%d\n",sched_setscheduler(0,SCHED_RR,&s));
//Prepare all slaves to work
for(i=0;i<3;i++) {
char devname[30];
sprintf(devname,"/dev/l3_fpga%d",i);
frs[i]=open(devname,O_RDONLY);
if(frs[i]<0) {
printf("I can't open device %s\b",devname);
perror("");
exit(1);
}
//Get the length of the buffer
blen[i] = ioctl(frs[i],L3_V1_IOC_GETBUFLEN,NULL);
//Set the wakeup threshold
res=ioctl(frs[i],L3_V1_IOC_SETWAKEUP,2000000);
printf("length of buffer: %d, result of set wakeup: %d\n",blen[i],res);
v[i]=(unsigned char *)mmap(0,blen[i],PROT_READ,MAP_PRIVATE,frs[i],0);
if(!v[i]) {
printf("mmap for device %s failed\n",devname);
exit(1);
}
}
//Start the transmission
gettimeofday(&tv, NULL);
tstart=tv.tv_sec+1.0e-6*tv.tv_usec;
stop=tv.tv_sec+60;
for(i=0;i<=2;i++) {
res = ioctl(frs[i],L3_V1_IOC_STARTMAC,&sl[i]);
printf("Result of start for slave %d : %d\n",i,res);
}
int first_served=0;
do{
struct pollfd pfd[3] = {{.fd = frs[0], .events = POLLIN, .revents = 0},
{.fd = frs[1], .events = POLLIN, .revents = 0},
{.fd = frs[2], .events = POLLIN, .revents = 0},
};
int ptr=0;
int len=0;
int pres;
//Wait for data using "poll"
pres = poll(pfd,3,-1);
if(pres<0) {
perror("Error in poll:");
exit(1);
}
first_served = (first_served+1) %3; //Rotate priority of slaves
for(j=0;j<3;j++) {
i=(j+first_served) % 3;
if(pfd[i].revents) {
len = ioctl(frs[i],L3_V1_IOC_READPTRS,&bp);
total_len[i] += len;
printf("i=%d len=%d total=%lld head:%d tail: %d\n",i,len,total_len[i],bp.head, bp.tail);
//OK. The data are read, let's analyze them
while (bp.head != bp.tail) {
uint32_t c;
c = *(uint32_t *)(v[i]+bp.tail);
c = ntohl(c);
bp.tail=(bp.tail+4) & (blen[i]-1); //Adjust tail pointer modulo blen[i]-1
if(c != data[i]) {
printf("Error! received: %8.8x expected: %8.8x \n",c,data[i]);
exit(1);
}
data[i] ++;
}
ioctl(frs[i],L3_V1_IOC_WRITEPTRS,len);
}
}
fflush(stdout);
gettimeofday(&tv, NULL);
if(tv.tv_sec > stop) {
tend=tv.tv_sec+1.0e-6*tv.tv_usec;
break;
}
} while (1);
tend=tend-tstart;
for(i=0;i<3;i++) {
printf("total data %d=%lld time=%g throughput=%g [Mb/s]\n",i,total_len[i], tend, total_len[i]/tend*8.0);
}
for(i=0;i<=2;i++) {
res = ioctl(frs[i],L3_V1_IOC_STOPMAC,0);
munmap(v[i],blen[i]);
close(frs[i]);
}
}
/trunk/linux/fpga_l3_fade.c
0,0 → 1,824
/*
* fpga_l3_fade - driver for L3 communication protocol with FPGA based system
* Copyright (C) 2012 by Wojciech M. Zabolotny
* Institute of Electronic Systems, Warsaw University of Technology
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
 
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/uaccess.h>
 
MODULE_LICENSE("GPL v2");
 
#include <linux/device.h>
#include <linux/netdevice.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/poll.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <asm/uaccess.h> /* for put_user */
 
#include "fpga_l3_fade.h"
 
#define SUCCESS 0
#define DEVICE_NAME "fpga_l3_fade"
 
/* Maximum number of packets' set (the set counter will wrap
* after this number is reached) should be power of two!*/
#define SET_NUMBER (1<<16)
#define SET_NUMBER_MASK (SET_NUMBER-1)
 
/* Number of packets in set - this number depends on amount of RAM
* in the FPGA - all set must fit in the FPGA RAM
* Should be power of two! */
#define PKTS_IN_SET (1<<5)
#define PKT_IN_SET_MASK (PKTS_IN_SET-1)
 
/* Capacity of kernel buffer (mmapped into user space) measured in
* number of sets - should be equal to power of two, to simplify
* the modulo operation (replacing it by binary AND) */
#define SETS_IN_BUFFER (1<<8)
 
#define MY_BUF_LEN (SETS_IN_BUFFER * PKTS_IN_SET * 1024)
#define MY_BUF_LEN_MASK (MY_BUF_LEN-1)
 
/* Length of the user header in the packet -
* command - 2 bytes
* set number - 2 bytes,
* packet number and retry number (not used
* yet) 2 bytes
* current inter-packet delay (used to monitor the
* process of delay adaptation) 4 bytes
*/
#define USER_HDR_LEN 10
 
/* Number of bytes of user data in a packet */
#define USER_LEN 1024
#define PAYL_LEN ( USER_HDR_LEN + USER_LEN )
 
/* Length of the acknowledment packet and command packets */
#define MY_ACK_LEN 64
 
/* Number of bytes to be copied from data packet to ack packet */
#define MY_ACK_COPIED 4
 
/* The Ethernet type of our packet. This is NOT OFFICIALLY REGISTERED type,
* however our protocol is:
* 1. experimental,
* 2. supposed to be used only in private networks
*/
#define MY_PROTO_ID 0xfade
 
static int max_slaves = 4;
module_param(max_slaves,int,1);
MODULE_PARM_DESC(max_slaves,"Maximum number of slave FPGA devices serviced by the system.");
 
static int proto_registered = 0; //Was the protocol registred? Should be deregistered at exit?
 
DEFINE_RWLOCK(slave_table_lock); //Used to protect table of slaves
 
/* Structure used to store offset of two currently serviced sets in the data buffer */
struct pkt_map {
int num;
int offset;
};
 
typedef struct
{
// fields related to the circular buffer
volatile int head;
volatile int tail;
rwlock_t ptrs_lock; //Used to protect the head and tail pointers
 
unsigned char * buffer;
 
rwlock_t pkts_rwlock; //Protects the pkts table and last_pkt
int last_pkt; /* position of the last packet, which is still
replaced with the packet from the next set */
int pkts[PKTS_IN_SET];
 
rwlock_t maps_rwlock; //Protects the maps table
struct pkt_map maps[2];
 
rwlock_t flags_lock; //Protects other fields of the slave_data struct
char err_flag;
char active;
char is_open;
int rx_wakeup_thr;
unsigned char mac[ETH_ALEN];
struct net_device * dev;
} slave_data;
 
/*
* The array pkts holds the number of set, from which we expect the particulal packet
* (so we can safely start with this array filled with zeroes).
* After the packet is sent and acknowledged, we increase the number corresponding
* to this packet.
* At each moment this table may be filled with two different values - n, and n+1
* because we service two consecutive sets
*/
static slave_data * slave_table = NULL;
 
static int my_proto_rcv(struct sk_buff * skb, struct net_device * dev, struct packet_type * pt,
struct net_device * orig_dev);
 
static struct packet_type my_proto_pt __read_mostly = {
.type = cpu_to_be16(MY_PROTO_ID),
.dev = NULL,
.func = my_proto_rcv,
};
 
// Prototypes of functions defined in module
void cleanup_my_proto1( void );
int init_my_proto1( void );
static int my_proto1_open(struct inode *inode, struct file *file);
static int my_proto1_release(struct inode *inode, struct file *file);
static long my_proto1_ioctl (struct file *filp, unsigned int cmd, unsigned long arg);
int my_proto1_mmap(struct file *filp, struct vm_area_struct *vma);
unsigned int my_proto1_poll(struct file *filp,poll_table *wait);
 
//Wait queue for user application
DECLARE_WAIT_QUEUE_HEAD (read_queue);
 
dev_t my_dev=0;
struct cdev * my_cdev = NULL;
static struct class *class_my_proto = NULL;
 
struct file_operations Fops = {
.owner = THIS_MODULE,
.open=my_proto1_open,
.release=my_proto1_release, /* a.k.a. close */
.poll = my_proto1_poll,
.unlocked_ioctl=my_proto1_ioctl,
.mmap=my_proto1_mmap
};
 
static long my_proto1_ioctl (struct file *filp,
unsigned int cmd, unsigned long arg)
{
slave_data * sd = filp->private_data;
if (_IOC_TYPE(cmd) != L3_V1_IOC_MAGIC) {
return -EINVAL;
}
switch (cmd) {
case L3_V1_IOC_SETWAKEUP:
if (arg > MY_BUF_LEN/2)
return -EINVAL; //Don't allow to set too high read threshold!
write_lock_bh(&sd->flags_lock);
sd->rx_wakeup_thr = arg;
write_unlock_bh(&sd->flags_lock);
return 0;
case L3_V1_IOC_GETBUFLEN:
/* Inform the user application about the length of the buffer */
return MY_BUF_LEN;
case L3_V1_IOC_READPTRS:
{
void * res = (void *) arg;
struct l3_v1_buf_pointers bp;
if (!access_ok(VERIFY_WRITE,res,sizeof(bp))) {
return -EFAULT;
} else {
read_lock_bh(&sd->ptrs_lock);
bp.head=sd->head;
bp.tail=sd->tail;
read_unlock_bh(&sd->ptrs_lock);
__copy_to_user(res,&bp,sizeof(bp));
if (sd->err_flag)
return -EIO; /* In this case user must him/herself
calculate the number of available bytes */
else
return (bp.head-bp.tail) & MY_BUF_LEN_MASK;
/* Return the number of available bytes */
}
}
case L3_V1_IOC_WRITEPTRS:
/* Update the read pointer
* The argument contains information about the number of bytes
* consumed by the application
*/
{
int rptr;
int wptr;
int available_data;
//We need to check if the amount of consumed data is correct
write_lock_bh(&sd->ptrs_lock);
wptr = sd->head;
rptr = sd->tail;
available_data = (wptr - rptr) & MY_BUF_LEN_MASK;
if (arg>available_data)
{
write_unlock_bh(&sd->ptrs_lock);
return -EINVAL;
}
//If the number of consumed bytes is correct, update the number of bytes
sd->tail = (rptr + arg) & MY_BUF_LEN_MASK;
write_unlock_bh(&sd->ptrs_lock);
return SUCCESS;
}
case L3_V1_IOC_STARTMAC: //Open the slave
{
void * source = (void *) arg;
struct l3_v1_slave sl;
struct sk_buff *newskb = NULL;
struct net_device *dev = NULL;
char * my_data = NULL;
if (!access_ok(VERIFY_READ,source,sizeof(sl))) {
return -EFAULT;
}
/* First deactivate the slave to avoid situation where data are modified
* while slave is active */
if (sd->active) sd->active = 0;
/* Prepare the data structure for reception of packets */
write_lock_bh(&sd->maps_rwlock);
sd->maps[0].num = 0;
sd->maps[0].offset = 0;
sd->maps[1].num=1;
sd->maps[1].offset = PKTS_IN_SET*USER_LEN;
write_unlock_bh(&sd->maps_rwlock);
write_lock_bh(&sd->pkts_rwlock);
memset(&sd->pkts,0,sizeof(sd->pkts));
sd->last_pkt=0;
write_unlock_bh(&sd->pkts_rwlock);
__copy_from_user(&sl,source,sizeof(sl));
write_lock_bh(&slave_table_lock);
/* Copy the MAC address */
memcpy(&sd->mac,sl.mac,ETH_ALEN);
sd->active = 1;
write_unlock_bh(&slave_table_lock);
/* Now send the "start transmission" packet to the slave */
/* Find the net device */
sl.devname[IFNAMSIZ-1]=0; // Protect against incorrect device name
if (sd->dev) {
//Maybe there was no STOPMAC call after previous STARTMAC?
dev_put(sd->dev);
sd->dev=NULL;
}
dev = dev_get_by_name(&init_net,sl.devname);
if (!dev) return -ENODEV;
sd->dev = dev;
newskb = alloc_skb(LL_RESERVED_SPACE(dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(dev));
skb_reset_network_header(newskb);
newskb->dev = dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Based on http://lxr.linux.no/#linux+v3.3.4/net/ipv4/arp.c#L586 !
if (dev_hard_header(newskb,dev,MY_PROTO_ID,&sl.mac,dev->dev_addr,MY_ACK_LEN+ETH_HLEN) < 0) {
kfree_skb(newskb);
return -EINVAL;
}
//Put the "start" command to the packet
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 1;
my_data = skb_put(newskb,MY_ACK_LEN -2);
memset(my_data,0xa5,MY_ACK_LEN - 2);
#ifdef FADE_DEBUG
printk(KERN_INFO "skb_nh: %x, skb_dt: %x, skb_nh2: %x, skb_t: %x\n tail: %d head: %d\n",skb_network_header(newskb),newskb->data,
newskb->network_header,newskb->tail, sd->tail, sd->head) ;
#endif
dev_queue_xmit(newskb);
return SUCCESS;
}
case L3_V1_IOC_STOPMAC: //Close the slave and reset it to stop transmission immediately
{
struct sk_buff *newskb = NULL;
char * my_data = NULL;
write_lock_bh(&slave_table_lock);
/* Clear the MAC address */
sd->active = 0;
memset(&sd->mac,0,ETH_ALEN);
write_unlock_bh(&slave_table_lock);
/* Now send the "stop transmission" packet to the slave */
/* Find the net device */
if (!sd->dev) return -ENODEV;
newskb = alloc_skb(LL_RESERVED_SPACE(sd->dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(sd->dev));
skb_reset_network_header(newskb);
newskb->dev = sd->dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Based on http://lxr.linux.no/#linux+v3.3.4/net/ipv4/arp.c#L586 !
if (dev_hard_header(newskb,sd->dev,MY_PROTO_ID,&sd->mac,sd->dev->dev_addr,MY_ACK_LEN+ETH_HLEN) < 0) {
kfree_skb(newskb);
return -EINVAL;
}
//Put the "stop" command to the packet
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 5;
my_data = skb_put(newskb,MY_ACK_LEN -2);
memset(my_data,0xa5,MY_ACK_LEN - 2);
#ifdef FADE_DEBUG
printk(KERN_INFO "skb_nh: %x, skb_dt: %x, skb_nh2: %x, skb_t: %x\n tail: %d head: %d\n",skb_network_header(newskb),newskb->data,
newskb->network_header,newskb->tail, sd->tail, sd->head) ;
#endif
dev_queue_xmit(newskb);
dev_put(sd->dev);
sd->dev=NULL;
return SUCCESS;
}
}
return -EINVAL;
}
/*
Implementation of the poll method
*/
unsigned int my_proto1_poll(struct file *filp,poll_table *wait)
{
unsigned int mask =0;
slave_data * sd = filp->private_data;
unsigned int data_available;
poll_wait(filp,&read_queue,wait);
read_lock_bh(&sd->ptrs_lock);
data_available = (sd->head - sd->tail) & MY_BUF_LEN_MASK;
if (data_available>=sd->rx_wakeup_thr) mask |= POLLIN |POLLRDNORM;
#ifdef FADE_DEBUG
printk(KERN_INFO "poll head: %d tail: %d data: %d prog: %d.\n",sd->head,sd->tail,data_available,sd->rx_wakeup_thr);
#endif
//Check if the error occured
if (sd->err_flag) mask |= POLLERR;
read_unlock_bh(&sd->ptrs_lock);
return mask;
}
 
/* Module initialization */
int init_my_proto1( void )
{
int res;
int i;
/* Create the device class for udev */
class_my_proto = class_create(THIS_MODULE, "my_proto");
if (IS_ERR(class_my_proto)) {
printk(KERN_ERR "Error creating my_proto class.\n");
res=PTR_ERR(class_my_proto);
goto err1;
}
/* Allocate the device number */
res=alloc_chrdev_region(&my_dev, 0, max_slaves, DEVICE_NAME);
if (res) {
printk (KERN_ERR "Alocation of the device number for %s failed\n",
DEVICE_NAME);
goto err1;
};
/* Allocate the character device structure */
my_cdev = cdev_alloc( );
if (my_cdev == NULL) {
printk (KERN_ERR "Allocation of cdev for %s failed\n",
DEVICE_NAME);
goto err1;
}
my_cdev->ops = &Fops;
my_cdev->owner = THIS_MODULE;
/* Add the character device to the system */
res=cdev_add(my_cdev, my_dev, max_slaves);
if (res) {
printk (KERN_ERR "Registration of the device number for %s failed\n",
DEVICE_NAME);
goto err1;
};
/* Create our devices in the system */
for (i=0;i<max_slaves;i++) {
device_create(class_my_proto,NULL,MKDEV(MAJOR(my_dev),MINOR(my_dev)+i),NULL,"l3_fpga%d",i);
}
printk (KERN_ERR "%s The major device number is %d.\n",
"Registration is a success.",
MAJOR(my_dev));
//Prepare the table of slaves
slave_table = kzalloc(sizeof(slave_data)*max_slaves, GFP_KERNEL);
if (!slave_table) return -ENOMEM;
for (i=0;i<max_slaves;i++) {
slave_data * sd = &slave_table[i];
sd->active=0; //Entry not used
sd->dev=NULL;
rwlock_init(&sd->maps_rwlock);
rwlock_init(&sd->pkts_rwlock);
rwlock_init(&sd->ptrs_lock);
rwlock_init(&sd->flags_lock);
}
//Install our protocol sniffer
dev_add_pack(&my_proto_pt);
proto_registered = 1;
return SUCCESS;
err1:
/* In case of error free all allocated resources */
cleanup_my_proto1();
return res;
}
 
module_init(init_my_proto1);
 
/* Clean-up when removing the module */
void cleanup_my_proto1( void )
{
/* Unregister the protocol sniffer */
if (proto_registered) dev_remove_pack(&my_proto_pt);
/* Free the slave table */
if (slave_table) {
int i;
for (i=0;i<max_slaves;i++) {
if (slave_table[i].buffer) {
vfree(slave_table[i].buffer);
slave_table[i].buffer = NULL;
}
if (slave_table[i].dev) {
dev_put(slave_table[i].dev);
slave_table[i].dev=NULL;
}
if (slave_table[i].active) {
slave_table[i].active = 0;
}
}
kfree(slave_table);
slave_table=NULL;
}
/* Remove device from the class */
if (my_dev && class_my_proto) {
int i;
for (i=0;i<max_slaves;i++) {
device_destroy(class_my_proto,MKDEV(MAJOR(my_dev),MINOR(my_dev)+i));
}
}
/* Deregister device */
if (my_cdev) cdev_del(my_cdev);
my_cdev=NULL;
/* Free the device number */
unregister_chrdev_region(my_dev, max_slaves);
/* Deregister class */
if (class_my_proto) {
class_destroy(class_my_proto);
class_my_proto=NULL;
}
 
}
module_exit(cleanup_my_proto1);
/*
Function, which receives my packet, copies the data and acknowledges the packet
as soon as possible...
I've tried to allow this function to handle multiple packets in parallel
in the SMP system, however I've used rwlocks for that.
Probably it should be improved, according to the last tendency to avoid
rwlocks in the kernel...
*/
 
static int my_proto_rcv(struct sk_buff * skb, struct net_device * dev, struct packet_type * pt,
struct net_device * orig_dev)
{
struct sk_buff *newskb = NULL;
struct ethhdr * rcv_hdr = NULL;
//unsigned int head;
//unsigned int tail;
int res;
unsigned int set_number;
unsigned int packet_number;
int ns; //Number of slave
slave_data * sd = NULL;
int set_num_diff;
unsigned int buf_free = 0;
char * my_data = NULL;
unsigned char tmp_buf[USER_HDR_LEN];
char ack_packet = 0; //Should we acknowledge the packet?
//Extract the MAC header from the received packet
rcv_hdr=eth_hdr(skb);
//First we try to identify the sender so we search the table of active slaves
//The table is protected during the search, so it should not be changed
#ifdef FADE_DEBUG
printk("snd: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",(int)rcv_hdr->h_source[0],
(int)rcv_hdr->h_source[1],(int)rcv_hdr->h_source[2],(int)rcv_hdr->h_source[3],
(int)rcv_hdr->h_source[4],(int)rcv_hdr->h_source[5]);
#endif
read_lock_bh(&slave_table_lock);
for (ns=0;ns<max_slaves;ns++) {
#ifdef FADE_DEBUG
printk("slv: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x act: %d\n",
(int)slave_table[ns].mac[0],(int)slave_table[ns].mac[1],(int)slave_table[ns].mac[2],
(int)slave_table[ns].mac[3],(int)slave_table[ns].mac[4],(int)slave_table[ns].mac[5],
(int)slave_table[ns].active);
#endif
if (
slave_table[ns].active!=0 &&
memcmp(slave_table[ns].mac,rcv_hdr->h_source, sizeof(slave_table[0].mac))==0
) break;
}
read_unlock_bh(&slave_table_lock);
//Now we know which slave sent us the packet (ns<max_slaves) or that
//the packet came from an unknown slave (ns==max_slaves)
if (unlikely(ns==max_slaves)) {
printk(KERN_WARNING " Received packet from incorrect slave!\n");
//Sender is not opened, so ignore the packet, and send
//to the sender request to stop the transmission immediately
newskb = alloc_skb(LL_RESERVED_SPACE(dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(dev));
skb_reset_network_header(newskb);
newskb->dev = dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Here is shown how to build a packet: http://lxr.linux.no/linux+*/net/ipv4/arp.c#L586
if (dev_hard_header(newskb,dev,MY_PROTO_ID,&rcv_hdr->h_source,&rcv_hdr->h_dest,MY_ACK_LEN+ETH_HLEN) < 0)
goto error;
//Put the "restart" command to the packet
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 5;
my_data = skb_put(newskb,MY_ACK_LEN -2);
memset(my_data,0xa5,MY_ACK_LEN - 2);
dev_queue_xmit(newskb);
kfree_skb(skb);
return NET_RX_DROP;
}
sd = &slave_table[ns]; //To speed up access to the data describing state of the slave
#ifdef FADE_DEBUG
printk(KERN_INFO " Received packet!\n");
#endif
//Now we should analyze the origin and meaning of the packet
//To avoid problems with scattered packets, we copy initial part of data to the buffer
//using the skb_copy_bits
skb_copy_bits(skb,0,tmp_buf,USER_HDR_LEN);
/* We extract the information from the user header
* First we check if this is a data packet: */
if (unlikely((tmp_buf[0] != 0xa5) ||
(tmp_buf[1] != 0xa5))) {
kfree_skb(skb);
write_lock_bh(&sd->flags_lock);
sd->err_flag |= FADE_ERR_INCORRECT_PACKET_TYPE;
write_unlock_bh(&sd->flags_lock);
return NET_RX_DROP;
}
/* Now we check the set number and the packet number:
PLEASE NOTE, THAT THIS MUST TIGHTLY CORRESPOND
TO YOUR FPGA IMPLEMENTATION! */
set_number = (int)tmp_buf[2]*256+tmp_buf[3];
packet_number = ((int)tmp_buf[4]>>2);
#ifdef FADE_DEBUG
printk(KERN_INFO "set=%d pkt=%d\n",set_number,packet_number);
#endif
/* To know if this is a new packet, we compare the set number
* in the received packet with the expected set number,
* calculating the difference between those two numbers: */
read_lock_bh(&sd->pkts_rwlock);
set_num_diff=(set_number - sd->pkts[packet_number]) & SET_NUMBER_MASK;
read_unlock_bh(&sd->pkts_rwlock);
if (likely(set_num_diff==0)) {
/* This is the expected data packet. */
int set = -1;
/* Because we often handle two sets of packets
simultaneously, we use "set" variable to store the relative set number */
int needed_space;
/* We determine the relative set number: 1 or 0 */
read_lock_bh(&sd->maps_rwlock);
if (set_number == sd->maps[0].num) set = 0;
else if (set_number == sd->maps[1].num) set = 1;
//Set equal to -1 should never happen!
if (set==-1) {
printk(KERN_WARNING "Incorrect set number in received packet!\n");
read_unlock_bh(&sd->maps_rwlock);
write_lock_bh(&sd->flags_lock);
sd->err_flag |= FADE_ERR_INCORRECT_SET;
write_unlock_bh(&sd->flags_lock);
kfree_skb(skb);
return NET_RX_DROP;
}
/* Now we can calculate how much free space requires this packet
Amount of space is calculated between the byte after the received packet
and the byte pointed by the head pointer */
needed_space = (sd->maps[set].offset + USER_LEN*(packet_number+1) - sd->head) & MY_BUF_LEN_MASK;
read_unlock_bh(&sd->maps_rwlock); //We stop to use the "maps" table
read_lock_bh(&sd->ptrs_lock);
buf_free=( sd->tail - sd->head -1 ) & MY_BUF_LEN_MASK;
#ifdef FADE_DEBUG
printk(KERN_INFO "Offset: %d packet_nr: %d Free buffer: %d needed space: %d set=%d offset=%d head=%d last=%d\n",
sd->maps[set].offset, packet_number, buf_free, needed_space,set,sd->maps[set].offset,sd->head,sd->last_pkt);
#endif
read_unlock_bh(&sd->ptrs_lock);
if ( buf_free > needed_space ) {
int ackd_set_nr;
//Packet fits in the buffer!
// Length of the payload should be 1024+header???
if (skb->len != PAYL_LEN) {
printk(KERN_ERR "Error! Length of data should be %d but is %d!\n",PAYL_LEN, skb->len);
sd->err_flag |= FADE_ERR_INCORRECT_LENGTH;
kfree_skb(skb);
return NET_RX_DROP;
}
// We can safely copy all the packet to the buffer:
// As buffer's boundary never is located in the middle of the packet set,
// we can simply calculate the begining of the data in the buffer
// as &sd->buffer[sd->maps[set].offset+USER_LEN*packet_number
res = skb_copy_bits(skb,10,&sd->buffer[sd->maps[set].offset+USER_LEN*packet_number],USER_LEN);
#ifdef FADE_DEBUG
printk(KERN_INFO " skb_copy_bits: %d", res);
#endif
//Packet was copied, so note, that we should confirm it
if (res>=0) {
ack_packet=1;
/* We modify the expected set number for the packet, to modify the
* pkts table, we must close pkts_rwlock for writing */
write_lock_bh(&sd->pkts_rwlock);
ackd_set_nr = (set_number + 1) & SET_NUMBER_MASK;
sd->pkts[packet_number]= ackd_set_nr;
if (packet_number == sd->last_pkt) {
/* If our packet was the last, which prevented shifting of the head pointer,
* we can try now to move the head pointer.
* We browse the pkts table, looking for the first uncorfirmed packet.
*/
while ((++(sd->last_pkt)) < PKTS_IN_SET) {
if (sd->pkts[sd->last_pkt] != ackd_set_nr) break; //Packet not confirmed
}
if (sd->last_pkt == PKTS_IN_SET) {
/* All packets from the "old" set are received, so we can change
* the set_nr
*/
sd->last_pkt = 0;
/* Update the maps table. Remove the 0th set, move the 1st to the 0th.
* Add the new set as the 1st one */
write_lock_bh(&sd->maps_rwlock);
memcpy(&sd->maps[0],&sd->maps[1],sizeof(sd->maps[0]));
sd->maps[1].num = (sd->maps[1].num + 1) & SET_NUMBER_MASK;
sd->maps[1].offset = (sd->maps[1].offset + USER_LEN*PKTS_IN_SET) & MY_BUF_LEN_MASK;
write_unlock_bh(&sd->maps_rwlock);
/* Now we need to check for confirmed packet from the next set */
ackd_set_nr+=1;
while (sd->last_pkt < PKTS_IN_SET) {
if (sd->pkts[sd->last_pkt] != ackd_set_nr) break; //Packet not cofirmed
else sd->last_pkt++;
}
write_unlock_bh(&sd->pkts_rwlock);
} else {
//No need to change packet sets, simply release the lock
write_unlock_bh(&sd->pkts_rwlock);
}
/* Now we can move the head position right after the last serviced packet */
write_lock_bh(&sd->ptrs_lock);
sd->head = sd->maps[0].offset+sd->last_pkt*USER_LEN;
/* When we have moved the head pointer, we can try to wake up the reading processes */
wake_up_interruptible(&read_queue);
write_unlock_bh(&sd->ptrs_lock);
} else {
// It was not the last packet, no need to move the head pointer
write_unlock_bh(&sd->pkts_rwlock);
}
}
}
} else {
/* This packet has incorrect set number. If the number is too low, we ignore the packet,
* but send the confirmation (ack was received too late, or was lost?) */
if (set_num_diff>(SET_NUMBER/2)) {
/* In fact it means, that set_num_diff is negative, but we calculate
* it modulo SET_NUMBER! */
ack_packet = 1;
#ifdef FADE_DEBUG
printk(KERN_INFO "Packet already confirmed: pkt=%d set=%d expect=%d last=%d\n",packet_number, set_number, sd->pkts[packet_number], sd->last_pkt);
#endif
} else {
/* This is a packet with too high set number (packet "from the future"
* it my be a symptom of serious communication problem! */
printk(KERN_ERR "Packet from the future! number: %d expected: %d\n", set_number, sd->pkts[packet_number]);
}
}
//Now send the confirmation
if (likely(ack_packet)) {
newskb = alloc_skb(LL_RESERVED_SPACE(dev)+MY_ACK_LEN, GFP_ATOMIC);
skb_reserve(newskb,LL_RESERVED_SPACE(dev));
skb_reset_network_header(newskb);
newskb->dev = dev;
newskb->protocol = htons(MY_PROTO_ID);
//Build the MAC header for the new packet
// Tu http://lxr.linux.no/linux+*/net/ipv4/arp.c#L586 jest pokazane jak zbudować pakiet!
if (dev_hard_header(newskb,dev,MY_PROTO_ID,&rcv_hdr->h_source,&rcv_hdr->h_dest,MY_ACK_LEN+ETH_HLEN) < 0)
goto error;
//Put the "ACKNOWLEDGE" type
my_data = skb_put(newskb,2);
*(my_data++) = 0;
*(my_data++) = 3; //ACK!
//Copy the begining of the received packet to the acknowledge packet
my_data = skb_put(newskb,MY_ACK_COPIED);
res = skb_copy_bits(skb,2,my_data,MY_ACK_COPIED);
my_data = skb_put(newskb,MY_ACK_LEN -MY_ACK_COPIED-2);
memset(my_data,0xa5,MY_ACK_LEN - MY_ACK_COPIED-2);
#ifdef FADE_DEBUG
printk(KERN_INFO " skb_nh: %x, skb_dt: %x, skb_nh2: %x, skb_t: %x\n tail: %d head: %d\n",skb_network_header(newskb),newskb->data,
newskb->network_header,newskb->tail, sd->tail, sd->head) ;
#endif
dev_queue_xmit(newskb);
}
kfree_skb(skb);
return NET_RX_SUCCESS;
 
error:
if (newskb) kfree_skb(newskb);
if (skb) kfree_skb(skb);
return NET_RX_DROP;
}
 
/*
Implementation of the "device open" function
*/
static int my_proto1_open(struct inode *inode,
struct file *file)
{
int i;
slave_data * sd = NULL;
unsigned long flags;
i=iminor(inode)-MINOR(my_dev);
if (i >= max_slaves) {
printk(KERN_WARNING "Trying to access %s slave with too high minor number: %d\n",
DEVICE_NAME, i);
return -ENODEV;
}
read_lock_irqsave(&slave_table_lock,flags);
sd = &slave_table[i];
//Each device may be opened only once!
if (sd->is_open) {
return -EBUSY;
read_unlock_irqrestore(&slave_table_lock,flags);
}
//Prepare slave_table for operation
read_unlock_irqrestore(&slave_table_lock,flags);
sd->buffer = vmalloc_user(MY_BUF_LEN);
if (!sd->buffer) return -ENOMEM;
//Set the MAC address to 0
memset(sd->mac,0,sizeof(sd->mac));
sd->head = 0;
sd->tail = 0;
sd->err_flag = 0;
sd->last_pkt = 0;
sd->rx_wakeup_thr = 1;
sd->active = 0;
sd->is_open = 1;
file->private_data=sd;
return SUCCESS;
}
 
 
static int my_proto1_release(struct inode *inode,
struct file *file)
{
slave_data * sd = file->private_data;
#ifdef FADE_DEBUG
printk (KERN_INFO "device_release(%p,%p)\n", inode, file);
#endif
//Release resources associated with servicing of the particular device
if (sd) {
if (sd->is_open) {
sd->is_open = 0; //It can be dangerous! Before freeing the buffer, we must be sure, that
//no our packet is being processed!
if (sd->active) {
sd->active = 0;
}
if (sd->buffer) {
vfree(sd->buffer);
sd->buffer = NULL;
}
}
}
return SUCCESS;
}
 
/* Memory mapping */
void my_proto1_vma_open (struct vm_area_struct * area)
{ }
 
void my_proto1_vma_close (struct vm_area_struct * area)
{ }
 
static struct vm_operations_struct my_proto1_vm_ops = {
my_proto1_vma_open,
my_proto1_vma_close,
};
 
/*
mmap method implementation
*/
int my_proto1_mmap(struct file *filp,
struct vm_area_struct *vma)
{
slave_data * sd = filp->private_data;
unsigned long vsize = vma->vm_end - vma->vm_start;
unsigned long psize = MY_BUF_LEN;
if (vsize>psize)
return -EINVAL;
remap_vmalloc_range(vma,sd->buffer, 0);
if (vma->vm_ops)
return -EINVAL; //It should never happen...
vma->vm_ops = &my_proto1_vm_ops;
my_proto1_vma_open(vma); //No open(vma) was called, we have called it ourselves
return 0;
}
 
/trunk/linux/Makefile
0,0 → 1,9
ifneq ($(KERNELRELEASE),)
obj-m := fpga_l3_fade.o
else
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
gcc -O2 -o receiver2 receiver2.c
endif
/trunk/desc.txt
0,0 → 1,134
DESCRIPTION
 
This archive implements the simple and light protocol for transmission
of data from low resources FPGA connected to the Ethernet MAC
and an embedded system running Linux OS.
The main goal was to assure the reliable transmission over unreliable
Ethernet link without need to buffer significant amount of data
in the FPGA. This created a need to obtain possibly early
acknowledgment of received packets from the embedded system,
and therefore the protocol had to be implemented in layer 3.
 
The Ethernet type 0xfade was used (unregistered, but as this
protocol should be used only in a small private networks,
without routers, with switches only, it should not be a problem).
 
We assume, that the FPGA is capable to store one "set" of packets
(in the example design length of this set is equal to 32).
To start the transmission, receiver sends the "start transmission"
packet:
TGT,SRC,0xfade,0x0001,pad to 64 bytes
 
After reception of the "start transmission" packet, the transmitter
(FPGA) starts to send the data packets:
TGT,SRC,0xfade,0xa5a5,set & packet number, delay, 1024 bytes of data
 
 
After reception of the correct data packet, the receiver sends the
"acknowledge" packet:
TGT,SRC,0xfade,0x0003,set & packet number, pad to 64 bytes
 
Another packet may be used to request immediate stop of transmission:
TGT,SRC,0xfade,0x0005, pad to 64 bytes
 
When first packets from the current set buffered in FPGA are
transmitted and acknowledged, they may be replaced with the packets
from the next set - the current state of transmission is stored
in desc_memory in the desc_manager entity.
 
When particular packet is not acknowledged, it is transmitted once
again. In current example design each packet has simple attributes:
1. set number
2. valid (ready to be sent)
3. sent (has been sent at least once - used for delay adaptation)
4. confirmed (reception has been confirmed, packet may be replaced
with the same packet from the next set)
 
List of packets is cyclically browsed to move the "head" and "tail"
pointers.
I've also tried another approach with more sophisticated packet
manager based on linked lists, but it is not fully debugged and not
ready for release yet. However the approach with cyclic browsing is
sufficient, as anyway an additional delay between packets had to be
introduced to achieve optimal transmission.
 
If the data packets are sent too quickly, the acknowledge
packets from the embedded system are received too late,
and the packet is retransmitted before acknowledge arrives.
The same may occur if the embedded system is overloaded
with packets from different slaves and drops some packets.
 
Therefore paradoxically resending of packets as soon as possible
does not provide the maximal throughput, and a delay between
packets must be introduced.
Of course if this delay is too big, the transmission also slows down.
 
To find the optimal delay, I have implemented a simple adaptive
algorithm based on analysis of the ratio between number of all sent
packets and of retransmitted packets: Nretr/Nall
If the data packets are sent too quickly, the ratio of Nretr/Nall
increases indicating, that the delay should be higher.
If the ratio Nretr/Nall is near to 0, we may reduce the delay.
Such a simple algorithm works quite satisfactory.
 
In the embedded system, the fpga_l3_fade.ko driver allows you
to service multiple FPGA slaves connected to different network
interfaces.
The "max_slaves" parameter lets you to set the maximum number of
slaves, when module is loaded.
 
After that, you can open /dev/l3_fpga0, /dev/l3_fpga1 ...
devices, to connect different slaves.
To connect one of those devices to particular FPGA slave,
you need to use the ioctl command L3_V1_IOC_STARTMAC
(please see the attached receiver2.c application for
an example).
The data received from the FPGA are placed in a kernel
buffer (each subdevice has its own buffer) which may be mmapped
to the user space application, providing very quick access
to the data. Another ioctl commands: L3_V1_IOC_READPTRS
and L3_V1_IOC_WRITEPTRS allow you to read the head and tail
pointers in this buffer and to confirm reception of data.
The attached receiver2.c application uses the described
mechanisms and simply tests, if the connected FPGA slave
sends consecutive 32-bit integers.
 
DISCLAIMER:
The published sources are "the first iteration". They work for me,
but I do not provide any warranty. You can use it only on your
own risk!
 
I hope to prepare the new, more mature version, which will be
described in a "official" publication (I'll send the reference,
when it is ready).
 
I'll also publish further versions of sources on my website:
http://www.ise.pw.edu.pl/~wzab/fpga_l3_fade
 
 
LICENSING:
1. My kernel driver is released under the GPL license
2. My user space application is public domain
3. My FPGA code is published with BSD license
4. I include also very slightly modified Ethernet MAC
http://opencores.org/project,ethernet_tri_mode
which is published under LGPL.
5. Due to licensing issues I can include only xco files for blocks
generated by Xilinx tools (in case of sources for
Spartan 3E Starter Kit instead of binary dcm1.xaw file
I had to include the generated dcm1.vhd file to avoid binary
attachment in shar archive).
I hope that you'll be able to rebuild my design with them
 
REBUILDING of FPGA CORES
My sources have been tested with three boards: SP601, Atlys and
Spartan-3E Starter Kit. In the FPGA subdirectory there are
three subdirectories: sp601, atlys and sk3e. In each of those
subdirectories you there is the "build.sh" script, which
should recreate the .bit file needed to configure particular
board.
 
If you create something basing on this my work, I'll be glad if you
provide information about my project (especially if you cite my
article, after it is ready and published)
 
/trunk/FPGA/sk3e/desc_manager_simple.vhd
0,0 → 1,584
-------------------------------------------------------------------------------
-- Title : FPGA Ethernet interface - descriptor manager
-- Project :
-------------------------------------------------------------------------------
-- File : desc_manager.vhd
-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl)
-- License : BSD License
-- Company :
-- Created : 2012-03-30
-- Last update: 2012-08-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This file implements the state machine, which manages the
-- table of packet descriptors, used to resend only not confirmed packets
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-30 1.0 WZab Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
library work;
use work.pkt_ack_pkg.all;
 
package desc_mgr_pkg is
 
constant N_OF_PKTS : integer := 32;
constant N_OF_SETS : integer := 65536;
 
type T_PKT_DESC is record
set : integer range 0 to N_OF_SETS-1; -- number of sets
confirmed : std_logic;
valid : std_logic;
sent : std_logic;
end record;
 
end desc_mgr_pkg;
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
 
-- The below implementation of the descriptor memory is awfull,
-- but seemed to be necessary to force XST to infer it as an
-- single port BRAM.
-- I simply provide vector long enough to accomodate my T_PKT_DESC
-- type, and hope that the synthesis tool (XST) will optimize out
-- unused bits.should be inferred as block memory (so be carefull
-- when modifying the below process)!
 
entity desc_memory is
 
port (
clk : in std_logic;
desc_we : in std_logic;
desc_addr : in integer range 0 to N_OF_PKTS-1;
desc_out : in T_PKT_DESC;
desc_in : out T_PKT_DESC);
 
end desc_memory;
 
architecture beh1 of desc_memory is
 
type T_PKT_DESC_MEM is array (0 to N_OF_PKTS-1) of unsigned(22 downto 0);
signal desc_mem : T_PKT_DESC_MEM := (others => (others => '0'));
signal din : unsigned(22 downto 0) := (others => '0');
signal dout : unsigned(22 downto 0) := (others => '0');
signal rdaddr : integer range 0 to N_OF_PKTS-1;
begin -- beh1
 
process (desc_out, dout)
begin -- process
din <= (others => '0');
din(22) <= desc_out.valid;
din(21) <= desc_out.confirmed;
din(20) <= desc_out.sent;
din(19 downto 0) <= to_unsigned(desc_out.set, 20);
desc_in.valid <= dout(22);
desc_in.confirmed <= dout(21);
desc_in.sent <= dout(20);
desc_in.set <= to_integer(dout(19 downto 0));
end process;
 
process (clk)
begin -- process
if (clk'event and clk = '1') then -- rising clock edge
if (desc_we = '1') then
desc_mem(desc_addr) <= din;
end if;
rdaddr <= desc_addr;
end if;
end process;
dout <= desc_mem(rdaddr);
 
end beh1;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
 
entity desc_manager is
generic (
N_OF_PKTS : integer := 64); -- Number of packet_logi buffers
 
port (
-- Data input interface
dta : in std_logic_vector(31 downto 0);
dta_we : in std_logic;
dta_ready : out std_logic;
-- ETH Sender interface
set_number : out unsigned(15 downto 0);
pkt_number : out unsigned(15 downto 0);
snd_start : out std_logic;
snd_ready : in std_logic;
 
-- Data memory interface
dmem_addr : out std_logic_vector(13 downto 0);
dmem_dta : out std_logic_vector(31 downto 0);
dmem_we : out std_logic;
-- Interface to the ACK FIFO
ack_fifo_empty : in std_logic;
ack_fifo_rd_en : out std_logic;
ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0);
 
--
transmit_data : in std_logic;
transm_delay : out unsigned(31 downto 0);
 
--
clk : in std_logic;
rst_n : in std_logic);
 
end desc_manager;
 
architecture dmgr_a1 of desc_manager is
 
constant PKT_CNT_MAX : integer := 10000;
 
-- To simplify description of state machines, all registers are grouped
-- in a record:
 
type T_DESC_MGR_REGS is record
set : integer range 0 to N_OF_SETS-1;
cur_set : integer range 0 to N_OF_SETS-1;
all_pkt_count : integer range 0 to PKT_CNT_MAX;
retr_pkt_count : integer range 0 to PKT_CNT_MAX;
retr_delay : unsigned(31 downto 0);
transm_delay : unsigned(31 downto 0);
nxt : integer range 0 to N_OF_PKTS-1;
tail_ptr : integer range 0 to N_OF_PKTS-1;
head_ptr : integer range 0 to N_OF_PKTS-1;
retr_ptr : integer range 0 to N_OF_PKTS-1; -- buffer, which is retransmitted
-- when equal to head_ptr -
-- retransmission is finished
retr_nxt : integer range 0 to N_OF_PKTS-1; -- buffer, which will be
-- retransmitted next
-- when equal to head_ptr -- no retransmission
-- is performed
end record;
 
constant DESC_MGR_REGS_INI : T_DESC_MGR_REGS := (
retr_delay => (others => '0'),
transm_delay => to_unsigned(10000, 32),
all_pkt_count => 0,
retr_pkt_count => 0,
set => 0,
cur_set => 0,
nxt => 0,
tail_ptr => 0,
head_ptr => 0,
retr_ptr => 0,
retr_nxt => 0
);
 
-- To simplify setting of outputs of my Mealy state machine, all combinatorial
-- outputs are grouped in a record
type T_DESC_MGR_COMB is record
dta_buf_free : std_logic;
desc_addr : integer range 0 to N_OF_PKTS-1;
desc_we : std_logic;
ack_rd : std_logic;
snd_start : std_logic;
desc_out : T_PKT_DESC;
end record;
constant DESC_MGR_COMB_DEFAULT : T_DESC_MGR_COMB := (
dta_buf_free => '0',
desc_addr => 0,
desc_we => '0',
ack_rd => '0',
snd_start => '0',
desc_out => (confirmed => '0', valid => '0', sent => '0', set => 0)
);
 
type T_DESC_MGR_STATE is (ST_DMGR_IDLE, ST_DMGR_START, ST_DMGR_RST, ST_DMGR_RST1,
ST_DMGR_ACK1, ST_DMGR_INS1, ST_DMGR_INS2, ST_DMGR_ACK_TAIL,
ST_DMGR_ACK_TAIL_1,
ST_DMGR_RETR, ST_DMGR_RETR_2);
 
signal desc_in : T_PKT_DESC;
 
signal r, r_i : T_DESC_MGR_REGS := DESC_MGR_REGS_INI;
signal c : T_DESC_MGR_COMB;
signal dmgr_state, dmgr_state_next : T_DESC_MGR_STATE := ST_DMGR_RST;
attribute keep : string;
attribute keep of dmgr_state : signal is "true";
 
signal dta_buf_full : std_logic := '0';
 
signal ack_pkt_in : pkt_ack;
 
signal wrd_addr : integer range 0 to 255;
 
component desc_memory
port (
clk : in std_logic;
desc_we : in std_logic;
desc_addr : in integer range 0 to N_OF_PKTS-1;
desc_out : in T_PKT_DESC;
desc_in : out T_PKT_DESC);
end component;
 
 
begin -- dmgr_a1
 
transm_delay <= r.transm_delay;
set_number <= to_unsigned(r.set, 16);
pkt_number <= to_unsigned(r.retr_ptr, 16);
dta_ready <= not dta_buf_full;
snd_start <= c.snd_start;
ack_fifo_rd_en <= c.ack_rd;
 
ack_pkt_in <= stlv_to_pkt_ack(ack_fifo_dout);
 
 
-- Packet descriptors are stored in the desc_memory
 
desc_memory_1 : desc_memory
port map (
clk => clk,
desc_we => c.desc_we,
desc_addr => c.desc_addr,
desc_out => c.desc_out,
desc_in => desc_in);
 
-- Process used to fill the buffer memory with the data to be transmitted
-- We simply write words to the memory buffer pointed by r.head_ptr
-- When we write the last (0xff-th) word, we signal that the buffer
-- is full. Only after reception of
dta_rcv : process (clk, rst_n)
begin -- process dta_rcv
if rst_n = '0' then -- asynchronous reset (active low)
wrd_addr <= 0;
dta_buf_full <= '0';
dmem_we <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
dmem_we <= '0';
-- if we signalled "data full", we are only waiting for
-- dta_buf_free;
if dta_buf_full = '1' then
if c.dta_buf_free = '1' then
dta_buf_full <= '0';
wrd_addr <= 0;
end if;
else
-- if data write requested - write it
if dta_we = '1' then
dmem_addr <= std_logic_vector(to_unsigned(r.head_ptr, 6)) &
std_logic_vector(to_unsigned(wrd_addr, 8));
dmem_we <= '1';
dmem_dta <= dta;
if wrd_addr < 255 then
wrd_addr <= wrd_addr + 1;
else
dta_buf_full <= '1';
end if;
end if;
end if;
end if;
end process dta_rcv;
 
 
c1 : process (ack_fifo_empty, ack_pkt_in, desc_in, dmgr_state, dta_buf_full,
r, snd_ready)
begin -- process c1
c <= DESC_MGR_COMB_DEFAULT; -- set defaults
r_i <= r; -- avoid latches
 
if r.retr_delay /= to_unsigned(0, r.retr_delay'length) then
r_i.retr_delay <= r.retr_delay-1;
end if;
dmgr_state_next <= dmgr_state;
-- State machine
case dmgr_state is
when ST_DMGR_RST =>
dmgr_state_next <= ST_DMGR_RST1;
when ST_DMGR_RST1 =>
-- We should initialize the 0th position of list descriptors
c.desc_addr <= r.head_ptr;
c.desc_out <= desc_in;
c.desc_out.confirmed <= '0';
c.desc_out.valid <= '0';
c.desc_out.sent <= '0';
c.desc_out.set <= 0;
c.desc_we <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
when ST_DMGR_IDLE =>
-- First we check, if there are any packets to acknowledge
if ack_fifo_empty = '0' then
-- Read the description of the acknowledged packet
c.desc_addr <= to_integer(ack_pkt_in.pkt);
dmgr_state_next <= ST_DMGR_ACK1;
elsif dta_buf_full = '1' then
-- We should handle reception of data.
-- If the previously filled buffer is full, pass it for transmission,
-- and allocate the next one.
--
-- Calculate the number of the packet, which shoud be the next "head"
-- packet.
if r.head_ptr = N_OF_PKTS-1 then
r_i.nxt <= 0;
else
r_i.nxt <= r.head_ptr + 1;
end if;
-- Prepare for reading of the current "head" descriptor
c.desc_addr <= r.head_ptr;
dmgr_state_next <= ST_DMGR_INS1;
elsif (r.tail_ptr /= r.head_ptr) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then
-- We need to (re)transmit some buffers
-- prepare reading of the descriptor, which should be transmitted
c.desc_addr <= r.retr_nxt;
dmgr_state_next <= ST_DMGR_RETR;
end if;
when ST_DMGR_INS1 =>
-- First we check, if there is free space, r.nxt is the number of the
-- future head packet.
if (r.nxt = r.tail_ptr) then
-- No free place! The packet, which we would like to fill is still
-- occupied.
-- Return to idle, waiting until something is freed.
-- In this case we should also force retransmission
if r.retr_delay = 0 then
c.desc_addr <= r.retr_nxt;
dmgr_state_next <= ST_DMGR_RETR;
else
dmgr_state_next <= ST_DMGR_IDLE;
end if;
else
-- We can fill the next buffer
-- First we mark the previous head packet
-- as valid and not confirmed
c.desc_addr <= r.head_ptr;
c.desc_out <= desc_in;
c.desc_out.confirmed <= '0';
c.desc_out.valid <= '1';
c.desc_we <= '1';
-- Now we move the "head" pointer
r_i.head_ptr <= r.nxt;
-- Increase the set number if we wrapped around
if r.nxt = 0 then
if r.cur_set = N_OF_SETS-1 then
r_i.cur_set <= 0;
else
r_i.cur_set <= r.cur_set + 1;
end if;
end if;
dmgr_state_next <= ST_DMGR_INS2;
end if;
when ST_DMGR_INS2 =>
-- We fill the new head descriptor
c.desc_addr <= r.head_ptr;
c.desc_out.set <= r.cur_set;
c.desc_out.confirmed <= '0';
c.desc_out.valid <= '0';
c.desc_out.sent <= '0';
c.desc_we <= '1';
-- Signal, that the buffer is freed
c.dta_buf_free <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
when ST_DMGR_ACK1 =>
-- In this state the desc memory should respond with the data of the
-- buffered packet, so we can state, if this packet is really correctly
-- acknowledged
if (ack_pkt_in.set = desc_in.set) and
(desc_in.valid = '1') then
-- This is really correct, unconfirmed packet
-- Increase the counter of not-repeated ACK packets
-- Write the confirmation
c.desc_addr <= to_integer(ack_pkt_in.pkt);
c.desc_out <= desc_in;
c.desc_out.valid <= '0';
c.desc_out.confirmed <= '1';
c.desc_we <= '1';
-- Here we also handle the case, if the acknowledged packet was
-- the one which is now scheduled for retransmission...
if ack_pkt_in.pkt = r.retr_nxt then
if r.retr_nxt < N_OF_PKTS-1 then
r_i.retr_nxt <= r.retr_nxt + 1;
else
r_i.retr_nxt <= 0;
end if;
end if;
-- Check, if we need to update the "tail" pointer
if r.tail_ptr = ack_pkt_in.pkt then
c.ack_rd <= '1';
dmgr_state_next <= ST_DMGR_ACK_TAIL;
else
c.ack_rd <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
end if;
else
-- This packet was already confirmed
-- just flush the ack_fifo
c.ack_rd <= '1';
dmgr_state_next <= ST_DMGR_IDLE;
end if;
when ST_DMGR_ACK_TAIL =>
c.desc_addr <= r.tail_ptr;
dmgr_state_next <= ST_DMGR_ACK_TAIL_1;
when ST_DMGR_ACK_TAIL_1 =>
-- In this state we update the "tail" pointer if necessary
if r.tail_ptr /= r.head_ptr then
if desc_in.confirmed = '1' then
if r.tail_ptr < N_OF_PKTS-1 then
r_i.tail_ptr <= r.tail_ptr + 1;
c.desc_addr <= r.tail_ptr + 1;
else
r_i.tail_ptr <= 0;
c.desc_addr <= 0;
end if;
-- We remain in that state, to check the next packet descriptor
else
-- We return to idle
dmgr_state_next <= ST_DMGR_IDLE;
end if;
else
-- Buffer is empty - return to idle
dmgr_state_next <= ST_DMGR_IDLE;
end if;
when ST_DMGR_RETR =>
-- Here we handle the transmission of a new packet,
-- retransmission of not confirmed packet
-- We must be sure, that the transmitter is ready
if snd_ready = '0' then
-- transmitter not ready, return to idle
dmgr_state_next <= ST_DMGR_IDLE;
else
-- We will be able to send the next packet, but let's check if
-- this is not the currently filled packet
if r.retr_nxt = r.head_ptr then
-- All packets (re)transmitted, go to the begining of the list
-- and return to idle.
r_i.retr_nxt <= r.tail_ptr;
dmgr_state_next <= ST_DMGR_IDLE;
else
-- before jumping to ST_DMGR_RETR, the address bus
-- was set to the address of r.retr_nxt, so now
-- we can read the descriptor, and check if the packet
-- needs to be retransmitted at all...
r_i.set <= desc_in.set;
r_i.retr_ptr <= r.retr_nxt;
if r.retr_nxt < N_OF_PKTS-1 then
r_i.retr_nxt <= r.retr_nxt + 1;
else
r_i.retr_nxt <= 0;
end if;
if desc_in.valid = '1' and desc_in.confirmed = '0' then
if desc_in.sent = '1' then
-- Increase count of retransmitted packets for
-- adaptive adjustment of delay
if r.retr_pkt_count < PKT_CNT_MAX then
r_i.retr_pkt_count <= r.retr_pkt_count + 1;
end if;
end if;
-- Increase count of all packets for adaptive adjustment
-- of delay
if r.all_pkt_count < PKT_CNT_MAX then
r_i.all_pkt_count <= r.all_pkt_count + 1;
end if;
-- Mark the packet as sent
c.desc_addr <= r.retr_nxt;
c.desc_out <= desc_in;
c.desc_out.sent <= '1';
c.desc_we <= '1';
dmgr_state_next <= ST_DMGR_RETR_2;
else
dmgr_state_next <= ST_DMGR_IDLE;
end if;
end if;
end if;
when ST_DMGR_RETR_2 =>
-- In this state, we simply trigger the sender!
c.snd_start <= '1';
r_i.retr_delay <= r.transm_delay;
-- And we update the delay using the packet statistics
-- You may change the constants used in expressions
-- below to change speed of adjustment
if r.all_pkt_count >= PKT_CNT_MAX then
if r.retr_pkt_count < PKT_CNT_MAX/32 then
if r.transm_delay > 32 then
r_i.transm_delay <= r.transm_delay-r.transm_delay/4;
end if;
elsif r.retr_pkt_count > PKT_CNT_MAX/8 then
if r.transm_delay < 1000000 then
r_i.transm_delay <= r.transm_delay+r.transm_delay/4;
end if;
end if;
r_i.all_pkt_count <= 0;
r_i.retr_pkt_count <= 0;
end if;
dmgr_state_next <= ST_DMGR_IDLE;
when others => null;
end case;
end process c1;
 
-- Synchronous process
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
r <= DESC_MGR_REGS_INI;
dmgr_state <= ST_DMGR_RST;
elsif clk'event and clk = '1' then -- rising clock edge
r <= r_i;
dmgr_state <= dmgr_state_next;
end if;
end process;
 
-- Process debugging the descriptors memory - for simulation only!
-- process (clk, rst_n)
-- variable L : line;
-- begin -- process
-- if rst_n = '0' then -- asynchronous reset (active low)
-- null;
-- elsif clk'event and clk = '1' then -- rising clock edge
-- if c.desc_we = '1' then
-- write(L, string'("nr="));
-- write(L, c.desc_addr);
-- write(L, string'(" set="));
-- write(L, c.desc_out.set);
-- write(L, string'(" valid="));
-- --write(L,c.desc_out.valid);
-- if c.desc_out.valid = '1' then
-- write(L, string'("1"));
-- else
-- write(L, string'("0"));
-- end if;
-- write(L, string'(" confirmed="));
-- --write(L,c.desc_out.valid);
-- if c.desc_out.confirmed = '1' then
-- write(L, string'("1"));
-- else
-- write(L, string'("0"));
-- end if;
-- write(L, string'(" r.tail="));
-- write(L, r.tail_ptr);
-- write(L, string'(" r.head="));
-- write(L, r.head_ptr);
-- writeline(output, L);
-- end if;
-- end if;
-- end process;
 
end dmgr_a1;
 
 
 
/trunk/FPGA/sk3e/dcm1.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$9`x7==(`fgn#ub irg\twimmj~x#~e<e^uy+vm4mVodRo}t.qqg*)ckd;%tly>;1684+6>92;?7< <45927+2?38<,dN>70392\4=5>28;"=>?2:066>5592>978>=;764?DTD@^CQ=:5NRVX\KKJ^WJKXOLJFNF]@HN7?3HX\VRAALX]@HNOIWLR_I_@NL078EWQ]WFDGURMCKHL\RDJRM8h0M_YU_NLO]ZBDEVY\EYMGIOE\GIM682KY[WQ@NM[\@ATXK9;;7L\XZ^MMH\YCL[UH=<?4ASUY[JHKQVNO^RMCK048EWQ]WFDGURJKR^DOMU@KGY;>7L\XZ^MMH\YAJVOSXH\AAM31?DTPRVEE@TQFNRV\JPKb3HX\VRAALX]SIFB6=2KY[WQ@NM[\V@UB\VFDKDM>8:CQS_YHFESTZLBFD^FEWZKHLLk0M^]@C^UJPM`<I^PTOAEMUGVZT@76>2K\VRMCKCWEP\VB9VDDIIG[129BS_YDDBUDYY^ZT^VZT@e<I^PTJAAXTXRF<>GPRVZJ^Yj4AVX\W\HS@]ED@95MOUJ7?GSAO=1H@F>7;BNH4ZDRNl1H@F>PBTDD[LHT\11H@F>POTV5?FJL91:=7NBD2626?FJL:Q20OAE=X0:31>EKC0:>7NBDDWa8GIMC^VNBZDJJ5:AOOCD?3JF@JOQFN49@HN@_02IGGKV>81;8GIMAPVH^Jk5LLJD[[GSAOVCE_Ym4CMIE\ZBN^@NNi6MCKGZ\IPJSAYFR56MCKGZ\KPR23JF@EC?>;BNHMKYCA_COIRLV_3`8GIMNFVCIYKI>0:AOOLHXAK_MKRGASUd8GIMNFVCIYKIPOTV;?FJLAGUBBn5LLJKM[UCUAFNn7NBDIO]PVFYSQYO:>6MCKNWW[UNF[LUXDDH[c:AOOZ@BMMHJOF74CNONMQRBL>1H^HO[EE48@FKX[Yh0HNCPSQ]JJVRc3MOXGHYPAEHVWQ753MLXSK\JQTGMG\YJGMOj7IBC_@LG[C^6:2NG@RH]EPWFJF_XEFNN96J\SDL21>BR\PUHUNBJ_BMQV@ESAFD<7IQYAMWF<>C_\LXEMAo4F@AWKW_XBO?0JLB\E89EFZUH][INo6HJEE@BGNYE]O30JD@PUOKWW==AG\^T_Y\n;GMVPZSIA]Yj7KAZT^TBHPC63@?0EO[IG99JJQCUFHF:=6DFTUGQ[LHW]]U_U]Kl;KKWP@TXXB8[Gn5EIUVFVZPFD\O=7AANDDF5?IIDCLNj7AALKDF\KPR43EE\?6CGZ69N[SGK]L=0BHZXOSI7?KIIM81D46AIDEP@T@d<XAKXIR]GIGV:?UOI@HYIY^o4PHLJWBHCMM20\D@XIEVK<>VUAD^R\H??;QPLTZVNF@YJOYGYE49SWFJL>2ZXHB@J4:RPAK><XZCEOIKL3:PPP3=U[]UBBo5\IFG[P@TIIE<0_D@HLDa8WQGU\\ZT[LG[6:QWEQST9;1XU^ZJM^QZJFNUGGE^_>5[OQ68PWSB02_XIRLZFF;8QVCXJ\LL_85YIDU2f>^F_V\N^^G@N0f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFI29[WQ0<PmhTEi??;Yfn[Hgmg{\n~~g`n028\akXE`dd~[k}shmm1>]729W>7V>57\68ewq};2nhao5yesqjkk&6&9>0zejcf:z`7v378l'?jj==0|BCt6b<HIr;6K49:0yP00<?>3236<=<05d`>67>l:qe4?4>;o:0>3=#080<j6s\458;2?>?2898<9hl:23:a0=T=l03:767:01041`d2:;2in5\458;2?>?2898<9hl:23b6==T=l03:767:01041`d2:9i:?5\458;2?>?2898<9hl:21a2f=c0?0;6<4>{R66>=0=010:?>>;fb805<b43^<h7>51;39e~U3=32=656512130ce=;83o?6l89;294?2=ir.m6594$339<<=#:;03m6*=3;:3?!1b2<1i8:4?:0194?6|,?i18;5+1181b>"693=>7)?<:348 42=:?1/=84=a:&22?413-;<6;94$0:930=#90087)?n:778 4d==81/=n4=4:&77?1<,::146*<7;c8 6>=j2.8n7;>;%63><=#<80?j6*;2;46?!2?2>20(9k53:&7=?063->i6;?4$5f93d=#=90=7);=:4c8 02=>;1/9;492:&63?c<,<h1985+628`?!0?281/;;4:1:&4f?1d3-;96i5+2187e>"2l380(8m54:k0e?6=,?h1495+6e84e>=n;80;6)8m:968 3b=?h10e:<50;&5f?>33-<o6:o4;h53>5<#>k0386*9a;5b?>o093:1(;l5859'2d<0i21b:h4?:%4a>=2<,?k1;l54i5a94?"1j32?7)8n:6c8?j41290/:o474:&5`?1f3-;n6?;4$0d916=<g;o1<7*9b;:7?>i5i3:1(;l58598k7d=83.=n76;;:m1b?6=,?h14954o3a94?"1j32?76a=d;29 3d=0=10c>=50;&5f?>33-<o6:o4$0g960=<g:>1<7*9b;:7?>i0?3:1(;l5849'2<<0i21d9k4?:%4a>=2<,?n1;l54o7d94?"1j32?76sm3e83>7<729q/:n4:9:k6<?6=,?h1495+6e84e>=h>?0;6)8m:968 3b=?h10qo<7:181>5<7s-<h6?;4i4:94?"1j32?7)8k:6c8?j01290/:o474:&5`?1f32wi?;4?:383>5}#>j0996g:8;29 3d=0=1/:i48a:9l23<72-<i65:4$7f93d=<uz9h6=4={<64>6g<5:n1:;5+1e80a>{t;;0;6?u246805>;503<=7)?k:3;8yv14290:w0:8:608 22==11v?950;0x911=:?16>54:8:p70<72;q68:4<3:?02?3?3ty=<7>51z?73?3a3-=?6;84}r1e>5<6s49o6864$6691==z{:31<7?t=24923=#?=0=:6s|3d83>5}#?=0=:6s|2883>5}#?=0=:6srn3;94?7|ug8j6=4>{|l1f?6=9rwe>n4?:0y~j7b=83;pqc<j:182xh5n3:1=vsa3183>4}zf:;1<7?t}o11>5<6stwvqMNL{2f9<0d5jmk2qMNM{1CDU}zHI
/trunk/FPGA/sk3e/spartan3e_eth_top.vhd
0,0 → 1,662
-------------------------------------------------------------------------------
-- Title : L3 FADE protocol demo for Spartan-3E Starter Kit board
-- Project :
-------------------------------------------------------------------------------
-- File : spartan3e_eth_top.vhd
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
-- Company :
-- Created : 2007-12-31
-- Last update: 2012-08-29
-- Platform :
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- This file implements a simple entity with JTAG driven internal bus
-- allowing to control LEDs, read buttons, set two registers
-- and to read results of simple arithmetical operations
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-- This is public domain code!!!
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-08-03 1.0 wzab Created
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
 
library unisim;
use unisim.vcomponents.all;
 
entity spart3e_sk_eth is
port(CLK_50MHZ : in std_logic;
RS232_DCE_RXD : in std_logic;
RS232_DCE_TXD : out std_logic;
 
SD_CK_P : out std_logic; --DDR SDRAM clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
 
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
 
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic; --low_data_strobe
 
E_MDC : out std_logic; --Ethernet PHY
E_MDIO : inout std_logic; --management data in/out
E_COL : in std_logic;
E_CRS : in std_logic;
E_RX_CLK : in std_logic; --receive clock
E_RX_ER : in std_logic; --receive error
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0);
E_TX_CLK : in std_logic; --transmit clock
E_TX_EN : out std_logic; --data valid
E_TX_ER : out std_logic; --transmit error
E_TXD : out std_logic_vector(3 downto 0);
 
SF_CE0 : out std_logic; --NOR flash
SF_OE : out std_logic;
SF_WE : out std_logic;
SF_BYTE : out std_logic;
SF_STS : in std_logic; --status
SF_A : out std_logic_vector(24 downto 0);
SF_D : inout std_logic_vector(15 downto 1);
SPI_MISO : inout std_logic;
 
CDC_MCK : out std_logic;
CDC_CSn : out std_logic;
CDC_SDIN : out std_logic;
CDC_SCLK : out std_logic;
CDC_DIN : out std_logic;
CDC_BCLK : out std_logic;
--CDC_CLKOUT : in std_logic;
CDC_DOUT : in std_logic;
CDC_LRC_IN_OUT : out std_logic;
 
VGA_VSYNC : out std_logic; --VGA port
VGA_HSYNC : out std_logic;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
 
PS2_CLK : in std_logic; --Keyboard
PS2_DATA : in std_logic;
 
LED : out std_logic_vector(7 downto 0);
ROT_CENTER : in std_logic;
ROT_A : in std_logic;
ROT_B : in std_logic;
BTN_EAST : in std_logic;
BTN_NORTH : in std_logic;
BTN_SOUTH : in std_logic;
BTN_WEST : in std_logic;
SW : in std_logic_vector(3 downto 0));
 
end spart3e_sk_eth;
 
architecture beh of spart3e_sk_eth is
 
component dp_ram_scl
generic (
DATA_WIDTH : integer;
ADDR_WIDTH : integer);
port (
clk : in std_logic;
we_a : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
we_b : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
 
component ack_fifo
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(pkt_ack_width-1 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(pkt_ack_width-1 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
 
component dcm1
port(
CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic
);
end component;
 
component desc_manager
generic (
N_OF_PKTS : integer);
port (
dta : in std_logic_vector(31 downto 0);
dta_we : in std_logic;
dta_ready : out std_logic;
set_number : out unsigned(15 downto 0);
pkt_number : out unsigned(15 downto 0);
snd_start : out std_logic;
snd_ready : in std_logic;
dmem_addr : out std_logic_vector(13 downto 0);
dmem_dta : out std_logic_vector(31 downto 0);
dmem_we : out std_logic;
ack_fifo_empty : in std_logic;
ack_fifo_rd_en : out std_logic;
ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0);
transmit_data : in std_logic;
transm_delay : out unsigned(31 downto 0);
clk : in std_logic;
rst_n : in std_logic);
end component;
 
component eth_sender
port (
peer_mac : in std_logic_vector(47 downto 0);
my_mac : in std_logic_vector(47 downto 0);
my_ether_type : in std_logic_vector(15 downto 0);
set_number : in unsigned(15 downto 0);
pkt_number : in unsigned(15 downto 0);
retry_number : in unsigned(15 downto 0);
transm_delay : in unsigned(31 downto 0);
clk : in std_logic;
rst_n : in std_logic;
ready : out std_logic;
start : in std_logic;
tx_mem_addr : out std_logic_vector(13 downto 0);
tx_mem_data : in std_logic_vector(31 downto 0);
Tx_mac_wa : in std_logic;
Tx_mac_wr : out std_logic;
Tx_mac_data : out std_logic_vector(31 downto 0);
Tx_mac_BE : out std_logic_vector(1 downto 0);
Tx_mac_sop : out std_logic;
Tx_mac_eop : out std_logic);
end component;
 
component eth_receiver
port (
peer_mac : out std_logic_vector(47 downto 0);
my_mac : in std_logic_vector(47 downto 0);
my_ether_type : in std_logic_vector(15 downto 0);
transmit_data : out std_logic;
restart : out std_logic;
ack_fifo_full : in std_logic;
ack_fifo_wr_en : out std_logic;
ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0);
clk : in std_logic;
rst_n : in std_logic;
Rx_mac_pa : in std_logic;
Rx_mac_ra : in std_logic;
Rx_mac_rd : out std_logic;
Rx_mac_data : in std_logic_vector(31 downto 0);
Rx_mac_BE : in std_logic_vector(1 downto 0);
Rx_mac_sop : in std_logic;
Rx_mac_eop : in std_logic);
end component;
 
component jtag_bus_ctl
generic (
d_width : integer;
a_width : integer);
port (
din : in std_logic_vector((d_width-1) downto 0);
dout : out std_logic_vector((d_width-1) downto 0);
addr : out std_logic_vector((a_width-1) downto 0);
nwr : out std_logic;
nrd : out std_logic);
end component;
 
component MAC_top
port (
--system signals
Reset : in std_logic;
Clk_125M : in std_logic;
Clk_user : in std_logic;
Clk_reg : in std_logic;
Speed : out std_logic_vector(2 downto 0);
--user interface
Rx_mac_ra : out std_logic;
Rx_mac_rd : in std_logic;
Rx_mac_data : out std_logic_vector(31 downto 0);
Rx_mac_BE : out std_logic_vector(1 downto 0);
Rx_mac_pa : out std_logic;
Rx_mac_sop : out std_logic;
Rx_mac_eop : out std_logic;
--user interface
Tx_mac_wa : out std_logic;
Tx_mac_wr : in std_logic;
Tx_mac_data : in std_logic_vector(31 downto 0);
Tx_mac_BE : in std_logic_vector(1 downto 0);
Tx_mac_sop : in std_logic;
Tx_mac_eop : in std_logic;
-- pkg_lgth fifo
Pkg_lgth_fifo_rd : in std_logic;
Pkg_lgth_fifo_ra : out std_logic;
Pkg_lgth_fifo_data : out std_logic_vector(15 downto 0);
--Phy interface
Gtx_clk : out std_logic; -- used only in GMII mode
Rx_clk : in std_logic;
Tx_clk : in std_logic; -- used only in MII mode
Tx_er : out std_logic;
Tx_en : out std_logic;
Txd : out std_logic_vector(7 downto 0);
Rx_er : in std_logic;
Rx_dv : in std_logic;
Rxd : in std_logic_vector(7 downto 0);
Crs : in std_logic;
Col : in std_logic;
-- host interface
CSB : in std_logic;
WRB : in std_logic;
CD_in : in std_logic_vector(15 downto 0);
CD_out : out std_logic_vector(15 downto 0);
CA : in std_logic_vector(7 downto 0);
-- mdx
Mdo : out std_logic; -- MII Management Data Output
MdoEn : out std_logic; -- MII Management Data Output Enable
Mdi : in std_logic;
Mdc : out std_logic -- MII Management Data Clock
);
end component;
 
signal my_mac : std_logic_vector(47 downto 0);
constant my_ether_type : std_logic_vector(15 downto 0) := x"fade";
signal transm_delay : unsigned(31 downto 0);
signal restart : std_logic;
signal dta : std_logic_vector(31 downto 0);
signal dta_we : std_logic := '0';
signal dta_ready : std_logic;
signal snd_start : std_logic;
signal snd_ready : std_logic;
signal dmem_addr : std_logic_vector(13 downto 0);
signal dmem_dta : std_logic_vector(31 downto 0);
signal dmem_we : std_logic;
signal addr_a, addr_b : integer;
signal test_dta : unsigned(31 downto 0);
signal tx_mem_addr : std_logic_vector(13 downto 0);
signal tx_mem_data : std_logic_vector(31 downto 0);
 
signal arg1, arg2, res1 : unsigned(7 downto 0);
signal res2 : unsigned(15 downto 0);
signal sender : std_logic_vector(47 downto 0);
signal peer_mac : std_logic_vector(47 downto 0);
signal inputs, din, dout : std_logic_vector(7 downto 0);
signal addr : std_logic_vector(3 downto 0);
signal leds : std_logic_vector(7 downto 0);
signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic;
signal cpu_reset, not_cpu_reset, rst_del : std_logic;
 
signal set_number : unsigned(15 downto 0);
signal pkt_number : unsigned(15 downto 0);
signal retry_number : unsigned(15 downto 0) := (others => '0');
signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0');
 
 
signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0);
signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic;
signal transmit_data : std_logic := '0';
 
signal read_addr : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal read_done, read_in_progress : std_logic;
 
 
signal led_counter : integer := 0;
signal tx_counter : integer := 10000;
signal Reset : std_logic;
signal s_gtx_clk : std_logic;
signal sysclk : std_logic;
signal Clk_125M : std_logic;
signal Clk_user : std_logic;
signal Clk_reg : std_logic;
signal Speed : std_logic_vector(2 downto 0);
signal Rx_mac_ra : std_logic;
signal Rx_mac_rd : std_logic;
signal Rx_mac_data : std_logic_vector(31 downto 0);
signal Rx_mac_BE : std_logic_vector(1 downto 0);
signal Rx_mac_pa : std_logic;
signal Rx_mac_sop : std_logic;
signal Rx_mac_eop : std_logic;
signal Tx_mac_wa : std_logic;
signal Tx_mac_wr : std_logic;
signal Tx_mac_data : std_logic_vector(31 downto 0);
signal Tx_mac_BE : std_logic_vector(1 downto 0);
signal Tx_mac_sop : std_logic;
signal Tx_mac_eop : std_logic;
signal Pkg_lgth_fifo_rd : std_logic;
signal Pkg_lgth_fifo_ra : std_logic;
signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0);
signal Gtx_clk : std_logic;
signal Rx_clk : std_logic;
signal Tx_clk : std_logic;
signal Tx_er : std_logic;
signal Tx_en : std_logic;
signal s_Txd : std_logic_vector(7 downto 0);
signal Rx_er : std_logic;
signal Rx_dv : std_logic;
signal s_Rxd : std_logic_vector(7 downto 0);
signal Crs : std_logic;
signal Col : std_logic;
signal CSB : std_logic := '1';
signal WRB : std_logic := '1';
signal CD_in : std_logic_vector(15 downto 0) := (others => '0');
signal CD_out : std_logic_vector(15 downto 0) := (others => '0');
signal CA : std_logic_vector(7 downto 0) := (others => '0');
signal s_Mdo : std_logic;
signal s_MdoEn : std_logic;
signal s_Mdi : std_logic;
 
signal s_dta_we : std_logic;
constant zeroes_32 : std_logic_vector(31 downto 0) := (others => '0');
begin -- beh
 
cpu_reset <= not ROT_CENTER;
-- Different not used signals
sysclk <= clk_50mhz;
sd_dq <= (others => 'Z');
sf_oe <= '1';
sf_we <= '1';
sf_d <= (others => 'Z');
 
sd_cs <= '1';
sd_we <= '1';
sd_ras <= '1';
sd_cas <= '1';
 
SD_CK_P <= '0';
SD_CK_N <= '1';
SD_CKE <= '0';
 
SD_BA <= (others => '0');
SD_A <= (others => '0');
 
SD_UDM <= 'Z';
SD_UDQS <= 'Z';
SD_LDM <= 'Z';
SD_LDQS <= 'Z';
 
--E_MDC <= '1';
--E_MDIO <= 'Z';
--E_TX_ER <= '0';
--E_TXD <= (others => '0');
 
SF_CE0 <= '0';
SF_BYTE <= '0';
SF_A <= (others => '0');
SPI_MISO <= 'Z';
 
VGA_VSYNC <= '0';
VGA_HSYNC <= '0';
VGA_RED <= '0';
VGA_GREEN <= '0';
VGA_BLUE <= '0';
 
-- Codec is not connected
CDC_DIN <= '0';
CDC_LRC_IN_OUT <= '0';
CDC_BCLK <= '0';
CDC_MCK <= '0';
CDC_SCLK <= '0';
CDC_SDIN <= '0';
CDC_CSn <= '0';
 
-- LEDs are not used
LED <= LEDs;
 
-- RS not used
RS232_DCE_TXD <= '1';
 
-- Allow selection of MAC with the DIP switch to allow testing
-- with multiple boards!
with SW(1 downto 0) select
my_mac <=
x"de_ad_ba_be_be_ef" when "00",
x"de_ad_ba_be_be_e1" when "01",
x"de_ad_ba_be_be_e2" when "10",
x"de_ad_ba_be_be_e3" when "11",
x"de_ad_ba_be_be_e4" when others;
 
-- iic_sda_main <= 'Z';
-- iic_scl_main <= 'Z';
 
not_cpu_reset <= not cpu_reset;
rst_p <= not rst_n;
 
-- flash_oe_b <= '1';
-- flash_we_b <= '1';
-- flash_ce_b <= '1';
 
MAC_top_1 : MAC_top
port map (
Reset => rst_p,
Clk_125M => Clk_125M,
Clk_user => Clk_user,
Clk_reg => Clk_user, -- was Clk_reg
Speed => Speed,
Rx_mac_ra => Rx_mac_ra,
Rx_mac_rd => Rx_mac_rd,
Rx_mac_data => Rx_mac_data,
Rx_mac_BE => Rx_mac_BE,
Rx_mac_pa => Rx_mac_pa,
Rx_mac_sop => Rx_mac_sop,
Rx_mac_eop => Rx_mac_eop,
Tx_mac_wa => Tx_mac_wa,
Tx_mac_wr => Tx_mac_wr,
Tx_mac_data => Tx_mac_data,
Tx_mac_BE => Tx_mac_BE,
Tx_mac_sop => Tx_mac_sop,
Tx_mac_eop => Tx_mac_eop,
Pkg_lgth_fifo_rd => Pkg_lgth_fifo_rd,
Pkg_lgth_fifo_ra => Pkg_lgth_fifo_ra,
Pkg_lgth_fifo_data => Pkg_lgth_fifo_data,
Gtx_clk => s_gtx_clk, -- not used
Rx_clk => E_RX_CLK,
Tx_clk => E_TX_CLK,
Tx_er => E_TX_ER,
Tx_en => E_TX_EN,
Txd => s_TXD,
Rx_er => E_RX_ER,
Rx_dv => E_RX_DV,
Rxd => s_RXD,
Crs => E_CRS,
Col => E_COL,
-- Host interface
CSB => CSB,
WRB => WRB,
CD_in => CD_in,
CD_out => CD_out,
CA => CA,
-- MDI interface
Mdo => s_Mdo,
MdoEn => s_MdoEn,
Mdi => s_Mdi,
Mdc => E_MDC);
 
s_RXD(3 downto 0) <= E_RXD;
s_RXD(7 downto 4) <= (others => '0');
E_TXD <= s_TXD(3 downto 0);
 
Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra;
 
addr_a <= to_integer(unsigned(dmem_addr));
addr_b <= to_integer(unsigned(tx_mem_addr));
 
dp_ram_scl_1 : dp_ram_scl
generic map (
DATA_WIDTH => 32,
ADDR_WIDTH => 13)
port map (
clk => clk_user,
we_a => dmem_we,
addr_a => dmem_addr(12 downto 0),
data_a => dmem_dta,
q_a => open,
we_b => '0',
addr_b => tx_mem_addr(12 downto 0),
data_b => zeroes_32,
q_b => tx_mem_data);
 
desc_manager_1 : desc_manager
generic map (
N_OF_PKTS => N_OF_PKTS)
port map (
dta => dta,
dta_we => dta_we,
dta_ready => dta_ready,
set_number => set_number,
pkt_number => pkt_number,
snd_start => snd_start,
snd_ready => snd_ready,
dmem_addr => dmem_addr,
dmem_dta => dmem_dta,
dmem_we => dmem_we,
ack_fifo_empty => ack_fifo_empty,
ack_fifo_rd_en => ack_fifo_rd_en,
ack_fifo_dout => ack_fifo_dout,
transmit_data => transmit_data,
transm_delay => transm_delay,
clk => clk_user,
rst_n => rst_n);
 
eth_sender_1 : eth_sender
port map (
peer_mac => peer_mac,
my_mac => my_mac,
my_ether_type => my_ether_type,
transm_delay => transm_delay,
set_number => set_number,
pkt_number => pkt_number,
retry_number => retry_number,
clk => clk_user,
rst_n => rst_n,
ready => snd_ready,
start => snd_start,
tx_mem_addr => tx_mem_addr,
tx_mem_data => tx_mem_data,
Tx_mac_wa => Tx_mac_wa,
Tx_mac_wr => Tx_mac_wr,
Tx_mac_data => Tx_mac_data,
Tx_mac_BE => Tx_mac_BE,
Tx_mac_sop => Tx_mac_sop,
Tx_mac_eop => Tx_mac_eop);
 
eth_receiver_1 : eth_receiver
port map (
peer_mac => peer_mac,
my_mac => my_mac,
my_ether_type => my_ether_type,
restart => restart,
transmit_data => transmit_data,
ack_fifo_full => ack_fifo_full,
ack_fifo_wr_en => ack_fifo_wr_en,
ack_fifo_din => ack_fifo_din,
clk => clk_user,
rst_n => rst_n,
Rx_mac_pa => Rx_mac_pa,
Rx_mac_ra => Rx_mac_ra,
Rx_mac_rd => Rx_mac_rd,
Rx_mac_data => Rx_mac_data,
Rx_mac_BE => Rx_mac_BE,
Rx_mac_sop => Rx_mac_sop,
Rx_mac_eop => Rx_mac_eop);
 
-- We don't use 125MHz clock!
s_gtx_clk <= '0';
dcm1_1 : dcm1
port map (
CLKIN_IN => sysclk,
RST_IN => not_cpu_reset,
CLKFX_OUT => clk_user,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => dcm_locked);
 
process (Clk_user, not_cpu_reset)
begin -- process
if not_cpu_reset = '1' then -- asynchronous reset (active low)
rst_n <= '0';
rst_del <= '0';
elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
if restart = '1' then
rst_n <= '0';
rst_del <= '0';
else
if dcm_locked = '1' then
rst_del <= '1';
rst_n <= rst_del;
end if;
end if;
end if;
end process;
 
-- reset
 
--phy_reset <= rst_n;
 
-- Connection of MDI
s_Mdi <= E_MDIO;
E_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo;
 
ack_fifo_1 : ack_fifo
port map (
clk => Clk_user,
rst => rst_p,
din => ack_fifo_din,
wr_en => ack_fifo_wr_en,
rd_en => ack_fifo_rd_en,
dout => ack_fifo_dout,
full => ack_fifo_full,
empty => ack_fifo_empty);
 
--E_TXD <= s_Txd(3 downto 0);
--s_Rxd <= "0000" & E_RXD;
 
-- signal generator
 
dta <= std_logic_vector(test_dta);
s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0';
dta_we <= s_dta_we;
 
process (Clk_user, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
test_dta <= (others => '0');
elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
if s_dta_we = '1' then
test_dta <= test_dta + 1;
end if;
end if;
end process;
 
-- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2));
LEDs(0) <= snd_ready;
LEDs(1) <= transmit_data;
LEDs(2) <= not_cpu_reset;
LEDs(3) <= Tx_mac_wa;
 
 
end beh;
/trunk/FPGA/sk3e/dcm1.vhd
0,0 → 1,98
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm1.vhd
-- /___/ /\ Timestamp : 08/28/2012 23:23:31
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/xl/ise_projects/sk3e_wz/sk3e_eth_art/src/dcm1.xaw -st dcm1.vhd
--Design Name: dcm1
--Device: xc3s500e-4fg320
--
-- Module dcm1
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.09 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.34 ns
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
 
entity dcm1 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm1;
 
architecture BEHAVIORAL of dcm1 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 32,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
 
 
/trunk/FPGA/sk3e/build.sh
0,0 → 1,5
#!/bin/bash
#coregen -r -b dcm1.xco -p coregen.cgp
coregen -r -b ack_fifo.xco -p coregen.cgp
xtclsh sk3e_eth_art.tcl rebuild_project
 
trunk/FPGA/sk3e/build.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/FPGA/sk3e/ack_fifo.xco =================================================================== --- trunk/FPGA/sk3e/ack_fifo.xco (nonexistent) +++ trunk/FPGA/sk3e/ack_fifo.xco (revision 2) @@ -0,0 +1,219 @@ +############################################################## +# +# Xilinx Core Generator version 13.4 +# Date: Tue Aug 28 21:19:54 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:8.4 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.4 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=ack_fifo +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_handshake_flag_options_axis=false +CSET enable_handshake_flag_options_rach=false +CSET enable_handshake_flag_options_rdch=false +CSET enable_handshake_flag_options_wach=false +CSET enable_handshake_flag_options_wdch=false +CSET enable_handshake_flag_options_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Common_Clock_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1023 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=1022 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=32 +CSET input_depth=1024 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=32 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=Empty +CSET programmable_empty_type_rach=Empty +CSET programmable_empty_type_rdch=Empty +CSET programmable_empty_type_wach=Empty +CSET programmable_empty_type_wdch=Empty +CSET programmable_empty_type_wrch=Empty +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=Full +CSET programmable_full_type_rach=Full +CSET programmable_full_type_rdch=Full +CSET programmable_full_type_wach=Full +CSET programmable_full_type_wdch=Full +CSET programmable_full_type_wrch=Full +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=11 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=11 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-10-22T06:08:52Z +# END Extra information +GENERATE +# CRC: 467ad5a6 Index: trunk/FPGA/sk3e/coregen.cgp =================================================================== --- trunk/FPGA/sk3e/coregen.cgp (nonexistent) +++ trunk/FPGA/sk3e/coregen.cgp (revision 2) @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET package = fg320 +SET speedgrade = -4 +SET verilogsim = false +SET vhdlsim = true Index: trunk/FPGA/sk3e/reg_int.v =================================================================== --- trunk/FPGA/sk3e/reg_int.v (nonexistent) +++ trunk/FPGA/sk3e/reg_int.v (revision 2) @@ -0,0 +1,182 @@ +module Reg_int ( +input Reset , +input Clk_reg , +input CSB , +input WRB , +input [15:0] CD_in , +output reg [15:0] CD_out , +input [7:0] CA , + //Tx host interface +output [4:0] Tx_Hwmark , +output [4:0] Tx_Lwmark , +output pause_frame_send_en , +output [15:0] pause_quanta_set , +output MAC_tx_add_en , +output FullDuplex , +output [3:0] MaxRetry , +output [5:0] IFGset , +output [7:0] MAC_tx_add_prom_data , +output [2:0] MAC_tx_add_prom_add , +output MAC_tx_add_prom_wr , +output tx_pause_en , +output xoff_cpu , +output xon_cpu , + //Rx host interface +output MAC_rx_add_chk_en , +output [7:0] MAC_rx_add_prom_data , +output [2:0] MAC_rx_add_prom_add , +output MAC_rx_add_prom_wr , +output broadcast_filter_en , +output [15:0] broadcast_bucket_depth , +output [15:0] broadcast_bucket_interval , +output RX_APPEND_CRC , +output [4:0] Rx_Hwmark , +output [4:0] Rx_Lwmark , +output CRC_chk_en , +output [5:0] RX_IFG_SET , +output [15:0] RX_MAX_LENGTH ,// 1518 +output [6:0] RX_MIN_LENGTH ,// 64 + //RMON host interface +output [5:0] CPU_rd_addr , +output CPU_rd_apply , +input CPU_rd_grant , +input [31:0] CPU_rd_dout , + //Phy int host interface +output Line_loop_en , +output [2:0] Speed , + //MII to CPU +output [7:0] Divider ,// Divider for the host clock +output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +output [4:0] Rgad ,// Register Address (within the PHY) +output [4:0] Fiad ,// PHY Address +output NoPre ,// No Preamble (no 32-bit preamble) +output WCtrlData ,// Write Control Data operation +output RStat ,// Read Status operation +output ScanStat ,// Scan Status operation +input Busy ,// Busy Signal +input LinkFail ,// Link Integrity Signal +input Nvalid ,// Invalid Status (qualifier for the valid scan result) +input [15:0] Prsd ,// Read Status Data (data read from the PHY) +input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + +// RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +//Line below for 1Gb Ethernet +// RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +//Line below for 100Mb Ethernet + RegCPUData U_0_034(Speed ,7'd034,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + +always @ (posedge Clk_reg or posedge Reset) + if (Reset) + CD_out <=0; + else if (!CSB&&WRB) + case (CA[7:1]) + 7'd00: CD_out<=Tx_Hwmark ; + 7'd01: CD_out<=Tx_Lwmark ; + 7'd02: CD_out<=pause_frame_send_en ; + 7'd03: CD_out<=pause_quanta_set ; + 7'd04: CD_out<=IFGset ; + 7'd05: CD_out<=FullDuplex ; + 7'd06: CD_out<=MaxRetry ; + 7'd07: CD_out<=MAC_tx_add_en ; + 7'd08: CD_out<=MAC_tx_add_prom_data ; + 7'd09: CD_out<=MAC_tx_add_prom_add ; + 7'd10: CD_out<=MAC_tx_add_prom_wr ; + 7'd11: CD_out<=tx_pause_en ; + 7'd12: CD_out<=xoff_cpu ; + 7'd13: CD_out<=xon_cpu ; + 7'd14: CD_out<=MAC_rx_add_chk_en ; + 7'd15: CD_out<=MAC_rx_add_prom_data ; + 7'd16: CD_out<=MAC_rx_add_prom_add ; + 7'd17: CD_out<=MAC_rx_add_prom_wr ; + 7'd18: CD_out<=broadcast_filter_en ; + 7'd19: CD_out<=broadcast_bucket_depth ; + 7'd20: CD_out<=broadcast_bucket_interval ; + 7'd21: CD_out<=RX_APPEND_CRC ; + 7'd22: CD_out<=Rx_Hwmark ; + 7'd23: CD_out<=Rx_Lwmark ; + 7'd24: CD_out<=CRC_chk_en ; + 7'd25: CD_out<=RX_IFG_SET ; + 7'd26: CD_out<=RX_MAX_LENGTH ; + 7'd27: CD_out<=RX_MIN_LENGTH ; + 7'd28: CD_out<=CPU_rd_addr ; + 7'd29: CD_out<=CPU_rd_apply ; + 7'd30: CD_out<=CPU_rd_grant ; + 7'd31: CD_out<=CPU_rd_dout[15:0] ; + 7'd32: CD_out<=CPU_rd_dout[31:16] ; + 7'd33: CD_out<=Line_loop_en ; + 7'd34: CD_out<=Speed ; + default: CD_out<=0 ; + endcase + + +endmodule + +module RegCPUData( +RegOut, +CA_reg_set, +RegInit, + +Reset, +Clk, +CWR_pulse, +CCSB, +CA_reg, +CD_in_reg +); +output[15:0] RegOut; +input[6:0] CA_reg_set; +input[15:0] RegInit; +// +input Reset; +input Clk; +input CWR_pulse; +input CCSB; +input[7:0] CA_reg; +input[15:0] CD_in_reg; +// +reg[15:0] RegOut; + +always @(posedge Reset or posedge Clk) + if(Reset) + RegOut <=RegInit; + else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0]) + RegOut <=CD_in_reg; + +endmodule \ No newline at end of file Index: trunk/FPGA/sk3e/sk3e_eth_art.tcl =================================================================== --- trunk/FPGA/sk3e/sk3e_eth_art.tcl (nonexistent) +++ trunk/FPGA/sk3e/sk3e_eth_art.tcl (revision 2) @@ -0,0 +1,524 @@ +# +# Project automation script for sk3e_eth_art +# +# Created for ISE version 13.4 +# +# This file contains several Tcl procedures (procs) that you can use to automate +# your project by running from xtclsh or the Project Navigator Tcl console. +# If you load this file (using the Tcl command: source sk3e_eth_art.tcl), then you can +# run any of the procs included here. +# +# This script is generated assuming your project has HDL sources. +# Several of the defined procs won't apply to an EDIF or NGC based project. +# If that is the case, simply remove them from this script. +# +# You may also edit any of these procs to customize them. See comments in each +# proc for more instructions. +# +# This file contains the following procedures: +# +# Top Level procs (meant to be called directly by the user): +# run_process: you can use this top-level procedure to run any processes +# that you choose to by adding and removing comments, or by +# adding new entries. +# rebuild_project: you can alternatively use this top-level procedure +# to recreate your entire project, and the run selected processes. +# +# Lower Level (helper) procs (called under in various cases by the top level procs): +# show_help: print some basic information describing how this script works +# add_source_files: adds the listed source files to your project. +# set_project_props: sets the project properties that were in effect when this +# script was generated. +# create_libraries: creates and adds file to VHDL libraries that were defined when +# this script was generated. +# set_process_props: set the process properties as they were set for your project +# when this script was generated. +# + +set myProject "sk3e_eth_art" +set myScript "sk3e_eth_art.tcl" + +# +# Main (top-level) routines +# +# run_process +# This procedure is used to run processes on an existing project. You may comment or +# uncomment lines to control which processes are run. This routine is set up to run +# the Implement Design and Generate Programming File processes by default. This proc +# also sets process properties as specified in the "set_process_props" proc. Only +# those properties which have values different from their current settings in the project +# file will be modified in the project. +# +proc run_process {} { + + global myScript + global myProject + + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: running ($myProject)...\n" + + if { ! [ open_project ] } { + return false + } + + set_process_props + # + # Remove the comment characters (#'s) to enable the following commands + # process run "Synthesize" + # process run "Translate" + # process run "Map" + # process run "Place & Route" + # + set task "Implement Design" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + set task "Generate Programming File" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + puts "Run completed (successfully)." + project close + +} + +# +# rebuild_project +# +# This procedure renames the project file (if it exists) and recreates the project. +# It then sets project properties and adds project sources as specified by the +# set_project_props and add_source_files support procs. It recreates VHDL Libraries +# as they existed at the time this script was generated. +# +# It then calls run_process to set process properties and run selected processes. +# +proc rebuild_project {} { + + global myScript + global myProject + + project close + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: Rebuilding ($myProject)...\n" + + set proj_exts [ list ise xise gise ] + foreach ext $proj_exts { + set proj_name "${myProject}.$ext" + if { [ file exists $proj_name ] } { + file delete $proj_name + } + } + + project new $myProject + set_project_props + add_source_files + create_libraries + puts "$myScript: project rebuild completed." + + run_process + +} + +# +# Support Routines +# + +# +proc run_task { task } { + + # helper proc for run_process + + puts "Running '$task'" + set result [ process run "$task" ] + # + # check process status (and result) + set status [ process get $task status ] + if { ( ( $status != "up_to_date" ) && \ + ( $status != "warnings" ) ) || \ + ! $result } { + return false + } + return true +} + +# +# show_help: print information to help users understand the options available when +# running this script. +# +proc show_help {} { + + global myScript + + puts "" + puts "usage: xtclsh $myScript " + puts " or you can run xtclsh and then enter 'source $myScript'." + puts "" + puts "options:" + puts " run_process - set properties and run processes." + puts " rebuild_project - rebuild the project from scratch and run processes." + puts " set_project_props - set project properties (device, speed, etc.)" + puts " add_source_files - add source files" + puts " create_libraries - create vhdl libraries" + puts " set_process_props - set process property values" + puts " show_help - print this message" + puts "" +} + +proc open_project {} { + + global myScript + global myProject + + if { ! [ file exists ${myProject}.xise ] } { + ## project file isn't there, rebuild it. + puts "Project $myProject not found. Use project_rebuild to recreate it." + return false + } + + project open $myProject + + return true + +} +# +# set_project_props +# +# This procedure sets the project properties as they were set in the project +# at the time this script was generated. +# +proc set_project_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Setting project properties..." + + project set family "Spartan3E" + project set device "xc3s500e" + project set package "fg320" + project set speed "-4" + project set top_level_module_type "HDL" + project set synthesis_tool "XST (VHDL/Verilog)" + project set simulator "ISim (VHDL/Verilog)" + project set "Preferred Language" "VHDL" + project set "Enable Message Filtering" "false" + +} + + +# +# add_source_files +# +# This procedure add the source files that were known to the project at the +# time this script was generated. +# +proc add_source_files {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Adding sources to project..." + + xfile add "./ack_fifo.xco" + xfile add "../src/ack_fifo/pkt_ack_pkg.vhd" + xfile add "./dcm1.vhd" + xfile add "../src/common/desc_manager_simple.vhd" + xfile add "../src/common/dpram_inf.vhd" + xfile add "../src/eth/Clk_ctrl.v" + xfile add "../src/eth/MAC_rx.v" + xfile add "../src/eth/MAC_rx/Broadcast_filter.v" + xfile add "../src/eth/MAC_rx/CRC_chk.v" + xfile add "../src/eth/MAC_rx/MAC_rx_FF.v" + xfile add "../src/eth/MAC_rx/MAC_rx_add_chk.v" + xfile add "../src/eth/MAC_rx/MAC_rx_ctrl.v" + xfile add "../src/eth/MAC_top.v" + xfile add "../src/eth/MAC_tx.v" + xfile add "../src/eth/MAC_tx/CRC_gen.v" + xfile add "../src/eth/MAC_tx/MAC_tx_Ctrl.v" + xfile add "../src/eth/MAC_tx/MAC_tx_FF.v" + xfile add "../src/eth/MAC_tx/MAC_tx_addr_add.v" + xfile add "../src/eth/MAC_tx/Ramdon_gen.v" + xfile add "../src/eth/MAC_tx/flow_ctrl.v" + xfile add "../src/eth/Phy_int.v" + xfile add "../src/eth/RMON.v" + xfile add "../src/eth/RMON/RMON_addr_gen.v" + xfile add "../src/eth/RMON/RMON_ctrl.v" + xfile add "../src/eth/RMON/RMON_dpram.v" + xfile add "../src/eth/TECH/xilinx/CLK_DIV2.v" + xfile add "../src/eth/TECH/xilinx/CLK_SWITCH.v" + xfile add "../src/eth/TECH/xilinx/duram.v" + xfile add "../src/eth/afifo.v" + xfile add "../src/eth/eth_miim.v" + xfile add "../src/eth/miim/eth_clockgen.v" + xfile add "../src/eth/miim/eth_outputcontrol.v" + xfile add "../src/eth/miim/eth_shiftreg.v" + xfile add "../src/eth/miim/timescale.v" + xfile add "./reg_int.v" + xfile add "../src/common/eth_receiver.vhd" + xfile add "../src/common/eth_sender.vhd" + xfile add "./spartan3e.ucf" + xfile add "./spartan3e_eth_top.vhd" + puts "" + puts "WARNING: project contains IP cores, synthesis will fail if any of the cores require regenerating." + puts "" + + # Set the Top Module as well... + project set top "beh" "spart3e_sk_eth" + + puts "$myScript: project sources reloaded." + +} ; # end add_source_files + +# +# create_libraries +# +# This procedure defines VHDL libraries and associates files with those libraries. +# It is expected to be used when recreating the project. Any libraries defined +# when this script was generated are recreated by this procedure. +# +proc create_libraries {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Creating libraries..." + + + # must close the project or library definitions aren't saved. + project save + +} ; # end create_libraries + +# +# set_process_props +# +# This procedure sets properties as requested during script generation (either +# all of the properties, or only those modified from their defaults). +# +proc set_process_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: setting process properties..." + + project set "Compiled Library Directory" "\$XILINX//" + project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core" + project set "Filter Files From Compile Order" "true" + project set "Last Applied Goal" "Balanced" + project set "Last Applied Strategy" "Xilinx Default (unlocked)" + project set "Last Unlock Status" "false" + project set "Manual Compile Order" "false" + project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing" + project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing" + project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing" + project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing" + project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing" + project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing" + project set "Project Description" "" + project set "Property Specification in Project File" "Store all values" + project set "Case Implementation Style" "None" -process "Synthesize - XST" + project set "Decoder Extraction" "true" -process "Synthesize - XST" + project set "Priority Encoder Extraction" "Yes" -process "Synthesize - XST" + project set "Mux Extraction" "Yes" -process "Synthesize - XST" + project set "RAM Extraction" "true" -process "Synthesize - XST" + project set "ROM Extraction" "true" -process "Synthesize - XST" + project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" + project set "Logical Shifter Extraction" "true" -process "Synthesize - XST" + project set "Optimization Goal" "Speed" -process "Synthesize - XST" + project set "Optimization Effort" "High" -process "Synthesize - XST" + project set "Resource Sharing" "true" -process "Synthesize - XST" + project set "Shift Register Extraction" "true" -process "Synthesize - XST" + project set "XOR Collapsing" "true" -process "Synthesize - XST" + project set "User Browsed Strategy Files" "" + project set "VHDL Source Analysis Standard" "VHDL-93" + project set "Input TCL Command Script" "" -process "Generate Text Power Report" + project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report" + project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Simulation File" "Default" -process "Generate Text Power Report" + project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Setting File" "" -process "Generate Text Power Report" + project set "Setting Output File" "" -process "Generate Text Power Report" + project set "Produce Verbose Report" "false" -process "Generate Text Power Report" + project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report" + project set "Other Bitgen Command Line Options" "" -process "Generate Programming File" + project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model" + project set "Show All Models" "false" -process "Generate IBIS Model" + project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream" + project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream" + project set "Target UCF File Name" "" -process "Back-annotate Pin Locations" + project set "Ignore User Timing Constraints" "false" -process "Map" + project set "Use RLOC Constraints" "Yes" -process "Map" + project set "Other Map Command Line Options" "" -process "Map" + project set "Use LOC Constraints" "true" -process "Translate" + project set "Other Ngdbuild Command Line Options" "" -process "Translate" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis" + project set "Ignore User Timing Constraints" "false" -process "Place & Route" + project set "Other Place & Route Command Line Options" "" -process "Place & Route" + project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" + project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" + project set "Create ASCII Configuration File" "false" -process "Generate Programming File" + project set "Create Bit File" "true" -process "Generate Programming File" + project set "Enable BitStream Compression" "false" -process "Generate Programming File" + project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File" + project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" + project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File" + project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" + project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File" + project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" + project set "Drive Done Pin High" "false" -process "Generate Programming File" + project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" + project set "Wait for DLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File" + project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" + project set "Enable Internal Done Pipe" "true" -process "Generate Programming File" + project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map" + project set "Optimization Strategy (Cover Mode)" "Area" -process "Map" + project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map" + project set "Generate Detailed MAP Report" "false" -process "Map" + project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map" + project set "Perform Timing-Driven Packing and Placement" "false" -process "Map" + project set "Trim Unconnected Signals" "true" -process "Map" + project set "Create I/O Pads from Ports" "false" -process "Translate" + project set "Macro Search Path" "" -process "Translate" + project set "Netlist Translation Type" "Timestamp" -process "Translate" + project set "User Rules File for Netlister Launcher" "" -process "Translate" + project set "Allow Unexpanded Blocks" "false" -process "Translate" + project set "Allow Unmatched LOC Constraints" "false" -process "Translate" + project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate" + project set "Placer Effort Level (Overrides Overall Level)" "None" -process "Place & Route" + project set "Router Effort Level (Overrides Overall Level)" "None" -process "Place & Route" + project set "Place And Route Mode" "Normal Place and Route" -process "Place & Route" + project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing" + project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing" + project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing" + project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing" + project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing" + project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing" + project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing" + project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing" + project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing" + project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing" + project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing" + project set "Add I/O Buffers" "true" -process "Synthesize - XST" + project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" + project set "Keep Hierarchy" "No" -process "Synthesize - XST" + project set "Register Balancing" "Yes" -process "Synthesize - XST" + project set "Register Duplication" "true" -process "Synthesize - XST" + project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST" + project set "Automatic BRAM Packing" "false" -process "Synthesize - XST" + project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" + project set "Bus Delimiter" "<>" -process "Synthesize - XST" + project set "Case" "Maintain" -process "Synthesize - XST" + project set "Cross Clock Analysis" "false" -process "Synthesize - XST" + project set "Equivalent Register Removal" "true" -process "Synthesize - XST" + project set "FSM Style" "LUT" -process "Synthesize - XST" + project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" + project set "Generics, Parameters" "" -process "Synthesize - XST" + project set "Hierarchy Separator" "/" -process "Synthesize - XST" + project set "HDL INI File" "" -process "Synthesize - XST" + project set "Library Search Order" "" -process "Synthesize - XST" + project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" + project set "Optimize Instantiated Primitives" "true" -process "Synthesize - XST" + project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" + project set "Read Cores" "true" -process "Synthesize - XST" + project set "Slice Packing" "true" -process "Synthesize - XST" + project set "Slice Utilization Ratio" "100" -process "Synthesize - XST" + project set "Use Clock Enable" "Yes" -process "Synthesize - XST" + project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST" + project set "Use Synchronous Set" "Yes" -process "Synthesize - XST" + project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST" + project set "Verilog Include Directories" "" -process "Synthesize - XST" + project set "Verilog 2001" "true" -process "Synthesize - XST" + project set "Verilog Macros" "" -process "Synthesize - XST" + project set "Work Directory" "./xst" -process "Synthesize - XST" + project set "Write Timing Constraints" "true" -process "Synthesize - XST" + project set "Other XST Command Line Options" "" -process "Synthesize - XST" + project set "Auto Implementation Compile Order" "true" + project set "Starting Placer Cost Table (1-100)" "1" -process "Map" + project set "Power Reduction" "false" -process "Map" + project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing" + project set "Synthesis Constraints File" "" -process "Synthesize - XST" + project set "Mux Style" "Auto" -process "Synthesize - XST" + project set "RAM Style" "Auto" -process "Synthesize - XST" + project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report" + project set "Output File Name" "spart3e_sk_eth" -process "Generate IBIS Model" + project set "Timing Mode" "Non Timing Driven" -process "Map" + project set "Generate Asynchronous Delay Report" "false" -process "Place & Route" + project set "Generate Clock Region Report" "false" -process "Place & Route" + project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route" + project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route" + project set "Power Reduction" "false" -process "Place & Route" + project set "Timing Mode" "Performance Evaluation" -process "Place & Route" + project set "Create Binary Configuration File" "false" -process "Generate Programming File" + project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File" + project set "CLB Pack Factor Percentage" "100" -process "Map" + project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route" + project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing" + project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST" + project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST" + project set "ROM Style" "Auto" -process "Synthesize - XST" + project set "Safe Implementation" "No" -process "Synthesize - XST" + project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route" + project set "Starting Placer Cost Table (1-100)" "1" -process "Place & Route" + project set "Functional Model Target Language" "VHDL" -process "View HDL Source" + project set "Change Device Speed To" "-4" -process "Generate Post-Place & Route Static Timing" + project set "Change Device Speed To" "-4" -process "Generate Post-Map Static Timing" + + puts "$myScript: project property values set." + +} ; # end set_process_props + +proc main {} { + + if { [llength $::argv] == 0 } { + show_help + return true + } + + foreach option $::argv { + switch $option { + "show_help" { show_help } + "run_process" { run_process } + "rebuild_project" { rebuild_project } + "set_project_props" { set_project_props } + "add_source_files" { add_source_files } + "create_libraries" { create_libraries } + "set_process_props" { set_process_props } + default { puts "unrecognized option: $option"; show_help } + } + } +} + +if { $tcl_interactive } { + show_help +} else { + if {[catch {main} result]} { + puts "$myScript failed: $result." + } +} + Index: trunk/FPGA/sk3e/spartan3e.ucf =================================================================== --- trunk/FPGA/sk3e/spartan3e.ucf (nonexistent) +++ trunk/FPGA/sk3e/spartan3e.ucf (revision 2) @@ -0,0 +1,322 @@ +##################################################### +### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE +##################################################### +# ==== Analog-to-Digital Converter (ADC) ==== +# some connections shared with SPI Flash, DAC, ADC, and AMP +#NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +# ==== Programmable Gain Amplifier (AMP) ==== +# some connections shared with SPI Flash, DAC, ADC, and AMP +#NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +#NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ; +#NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +# ==== Pushbuttons (BTN) ==== +NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; +NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; +NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; +NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; +# ==== Clock inputs (CLK) ==== +NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; +# Define clock period for 50 MHz oscillator (40%/60% duty-cycle) +#NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %; +NET "CLK_50MHZ" PERIOD = 20 ns HIGH 50 %; +#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ; +#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ; +# ==== Digital-to-Analog Converter (DAC) ==== +# some connections shared with SPI Flash, DAC, ADC, and AMP +#NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +# ==== 1-Wire Secure EEPROM (DS) +#NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +# ==== Ethernet PHY (E) ==== +NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ; +NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ; +NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ; +NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ; +NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ; +NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; +NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ; +NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ; +NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ; +NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ; +NET "E_TX_CLK" PERIOD = 30 ns HIGH 50 %; +NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ==== +#NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; +#NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; +#NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ; +# ==== FX2 Connector (FX2) ==== +#NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ; +#NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +# These four connections are shared with the J1 6-pin accessory header +#NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +# These four connections are shared with the J2 6-pin accessory header +#NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +# These four connections are shared with the J4 6-pin accessory header +#NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +# The discrete LEDs are shared with the following 8 FX2 connections +#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; +#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; + +NET "CDC_MCK" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_CSn" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_SDIN" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_SCLK" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_DIN" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_BCLK" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_DOUT" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; +NET "CDC_LRC_IN_OUT" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; + +# ==== 6-pin header J1 ==== +# These are shared connections with the FX2 connector +#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +# ==== 6-pin header J2 ==== +# These are shared connections with the FX2 connector +#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +# ==== 6-pin header J4 ==== +# These are shared connections with the FX2 connector +#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; +# ==== Character LCD (LCD) ==== +#NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +#NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +#NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +# LCD data connections are shared with StrataFlash connections SF_D<11:8> +#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +# ==== Discrete LEDs (LED) ==== +# These are shared connections with the FX2 connector +NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +# ==== PS/2 Mouse/Keyboard Port (PS2) ==== +NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 ; +NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ; +# ==== Rotary Pushbutton Switch (ROT) ==== +NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ; +NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ; +NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ; +# ==== RS-232 Serial Ports (RS232) ==== +NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ; +NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; +#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ; +#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; +# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V) +NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ; +NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ; +NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ; +NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ; +NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ; +NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ; +NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ; +NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ; +NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ; +NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ; +NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ; +NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ; +NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ; +NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ; +NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ; +NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ; +NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; +NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; +NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ; +NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ; +NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ; +NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ; +NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ; +NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ; +NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ; +NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ; +NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ; +# Path to allow connection to top DCM connection +#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ; +# Prohibit VREF pins +CONFIG PROHIBIT = D2; +CONFIG PROHIBIT = G4; +CONFIG PROHIBIT = J6; +CONFIG PROHIBIT = L5; +CONFIG PROHIBIT = R4; +# ==== Intel StrataFlash Parallel NOR Flash (SF) ==== +NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ; +NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +# ==== STMicro SPI serial Flash (SPI) ==== +# some connections shared with SPI Flash, DAC, ADC, and AMP +NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; +#NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +#NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +#NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +#NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; +# ==== Slide Switches (SW) ==== +NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; +NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; +NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; +NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; +# ==== VGA Port (VGA) ==== +NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; +# ==== Xilinx CPLD (XC) ==== +#NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; +#NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; +#NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ; +#NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; +#NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; +#NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; +#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ; +#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "CLK_50MHZ" TNM_NET = "CLK_50MHZ"; +#NET "clk_reg1" TNM_NET = "clk_reg1"; +#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %; +NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +TIMEGRP "E_TX_OUTS" OFFSET=OUT 20 ns BEFORE E_TX_CLK; +INST "E_TXD<0>" TNM="E_TX_OUTS"; +INST "E_TXD<1>" TNM="E_TX_OUTS"; +INST "E_TXD<2>" TNM="E_TX_OUTS"; +INST "E_TXD<3>" TNM="E_TX_OUTS"; +INST "E_TX_EN" TNM="E_TX_OUTS"; + +TIMEGRP "CDC_INS" OFFSET=IN 5 ns BEFORE "clk_50MHz"; +INST "CDC_DOUT" TNM="CDC_INS"; + +TIMEGRP "CDC_SPI" OFFSET= OUT 10 ns BEFORE "clk_50MHz"; +INST "CDC_CSn" TNM="CDC_SPI"; +INST "CDC_SDIN" TNM="CDC_SPI"; +INST "CDC_SCLK" TNM="CDC_SPI"; + +TIMEGRP "CDC_CLK" OFFSET= OUT 10 ns BEFORE "clk_50MHz"; +INST "CDC_BCLK" TNM="CDC_CLK"; +INST "CDC_MCK" TNM="CDC_CLK"; + +TIMEGRP "CDC_OUTS" OFFSET= OUT 10 ns BEFORE "clk_50MHz"; +#TIMEGRP "CDC_OUTS" OFFSET= OUT 0 ns BEFORE "clk_50MHz"; +INST "CDC_DIN" TNM="CDC_OUTS"; +INST "CDC_LRC_IN_OUT" TNM="CDC_OUTS"; + +NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "CLK_50MHZ" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "dcm2_1/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "dcm1_1/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; Index: trunk/FPGA/src/eth/eth_miim.v =================================================================== --- trunk/FPGA/src/eth/eth_miim.v (nonexistent) +++ trunk/FPGA/src/eth/eth_miim.v (revision 2) @@ -0,0 +1,479 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_miim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +// Revision 1.4 2005/08/16 12:07:57 Administrator +// no message +// +// Revision 1.3 2005/05/19 07:04:29 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2003/05/16 10:08:27 mohor +// Busy was set 2 cycles too late. Reported by Dennis Scott. +// +// Revision 1.4 2002/08/14 18:32:10 mohor +// - Busy signal was not set on time when scan status operation was performed +// and clock was divided with more than 2. +// - Nvalid remains valid two more clocks (was previously cleared too soon). +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + + +module eth_miim +( + Clk, + Reset, + Divider, + NoPre, + CtrlData, + Rgad, + Fiad, + WCtrlData, + RStat, + ScanStat, + Mdo, + MdoEn, + Mdi, + Mdc, + Busy, + Prsd, + LinkFail, + Nvalid, + WCtrlDataStart, + RStatStart, + UpdateMIIRX_DATAReg +); + + + +input Clk; // Host Clock +input Reset; // General Reset +input [7:0] Divider; // Divider for the host clock +input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) +input [4:0] Rgad; // Register Address (within the PHY) +input [4:0] Fiad; // PHY Address +input NoPre; // No Preamble (no 32-bit preamble) +input WCtrlData; // Write Control Data operation +input RStat; // Read Status operation +input ScanStat; // Scan Status operation +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable +input Mdi; + +output Mdc; // MII Management Data Clock + +output Busy; // Busy Signal +output LinkFail; // Link Integrity Signal +output Nvalid; // Invalid Status (qualifier for the valid scan result) + +output [15:0] Prsd; // Read Status Data (data read from the PHY) + +output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register +output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register +output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +parameter Tp = 1; + + +reg Nvalid; +reg EndBusy_d; // Pre-end Busy signal +reg EndBusy; // End Busy signal (stops the operation in progress) + +reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle +reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles +reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles +reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) +reg WCtrlDataStart_q; +reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle +reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles + +reg RStat_q1; // Read Status operation delayed 1 Clk cycle +reg RStat_q2; // Read Status operation delayed 2 Clk cycles +reg RStat_q3; // Read Status operation delayed 3 Clk cycles +reg RStatStart; // Start Read Status Command (positive edge detected) +reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle +reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles + +reg ScanStat_q1; // Scan Status operation delayed 1 cycle +reg ScanStat_q2; // Scan Status operation delayed 2 cycles +reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn + +wire WriteDataOp; // Write Data Operation (positive edge detected) +wire ReadStatusOp; // Read Status Operation (positive edge detected) +wire ScanStatusOp; // Scan Status Operation (positive edge detected) +wire StartOp; // Start Operation (start of any of the preceding operations) +wire EndOp; // End of Operation + +reg InProgress; // Operation in progress +reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle +reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles +reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles + +reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +reg [6:0] BitCounter; // Bit Counter + + +wire MdcFrame; // Frame window for limiting the Mdc +wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. +wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. +wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal + + +wire LatchByte1_d2; +wire LatchByte0_d2; +reg LatchByte1_d; +reg LatchByte0_d; +reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register + +reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + + + +/* +assign Mdi=Mdio; +assign Mdio=MdoEn?Mdo:1'bz; +*/ + + + +// Generation of the EndBusy signal. It is used for ending the MII Management operation. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + EndBusy_d <= #Tp 1'b0; + EndBusy <= #Tp 1'b0; + end + else + begin + EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3; + EndBusy <= #Tp EndBusy_d; + end +end + + +// Update MII RX_DATA register +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + UpdateMIIRX_DATAReg <= #Tp 0; + else + if(EndBusy & ~WCtrlDataStart_q) + UpdateMIIRX_DATAReg <= #Tp 1; + else + UpdateMIIRX_DATAReg <= #Tp 0; +end + + + +// Generation of the delayed signals used for positive edge triggering. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlData_q1 <= #Tp 1'b0; + WCtrlData_q2 <= #Tp 1'b0; + WCtrlData_q3 <= #Tp 1'b0; + + RStat_q1 <= #Tp 1'b0; + RStat_q2 <= #Tp 1'b0; + RStat_q3 <= #Tp 1'b0; + + ScanStat_q1 <= #Tp 1'b0; + ScanStat_q2 <= #Tp 1'b0; + SyncStatMdcEn <= #Tp 1'b0; + end + else + begin + WCtrlData_q1 <= #Tp WCtrlData; + WCtrlData_q2 <= #Tp WCtrlData_q1; + WCtrlData_q3 <= #Tp WCtrlData_q2; + + RStat_q1 <= #Tp RStat; + RStat_q2 <= #Tp RStat_q1; + RStat_q3 <= #Tp RStat_q2; + + ScanStat_q1 <= #Tp ScanStat; + ScanStat_q2 <= #Tp ScanStat_q1; + if(MdcEn) + SyncStatMdcEn <= #Tp ScanStat_q2; + end +end + + +// Generation of the Start Commands (Write Control Data or Read Status) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart <= #Tp 1'b0; + WCtrlDataStart_q <= #Tp 1'b0; + RStatStart <= #Tp 1'b0; + end + else + begin + if(EndBusy) + begin + WCtrlDataStart <= #Tp 1'b0; + RStatStart <= #Tp 1'b0; + end + else + begin + if(WCtrlData_q2 & ~WCtrlData_q3) + WCtrlDataStart <= #Tp 1'b1; + if(RStat_q2 & ~RStat_q3) + RStatStart <= #Tp 1'b1; + WCtrlDataStart_q <= #Tp WCtrlDataStart; + end + end +end + + +// Generation of the Nvalid signal (indicates when the status is invalid) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Nvalid <= #Tp 1'b0; + else + begin + if(~InProgress_q2 & InProgress_q3) + begin + Nvalid <= #Tp 1'b0; + end + else + begin + if(ScanStat_q2 & ~SyncStatMdcEn) + Nvalid <= #Tp 1'b1; + end + end +end + +// Signals used for the generation of the Operation signals (positive edge) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart_q1 <= #Tp 1'b0; + WCtrlDataStart_q2 <= #Tp 1'b0; + + RStatStart_q1 <= #Tp 1'b0; + RStatStart_q2 <= #Tp 1'b0; + + InProgress_q1 <= #Tp 1'b0; + InProgress_q2 <= #Tp 1'b0; + InProgress_q3 <= #Tp 1'b0; + + LatchByte0_d <= #Tp 1'b0; + LatchByte1_d <= #Tp 1'b0; + + LatchByte <= #Tp 2'b00; + end + else + begin + if(MdcEn) + begin + WCtrlDataStart_q1 <= #Tp WCtrlDataStart; + WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1; + + RStatStart_q1 <= #Tp RStatStart; + RStatStart_q2 <= #Tp RStatStart_q1; + + LatchByte[0] <= #Tp LatchByte0_d; + LatchByte[1] <= #Tp LatchByte1_d; + + LatchByte0_d <= #Tp LatchByte0_d2; + LatchByte1_d <= #Tp LatchByte1_d2; + + InProgress_q1 <= #Tp InProgress; + InProgress_q2 <= #Tp InProgress_q1; + InProgress_q3 <= #Tp InProgress_q2; + end + end +end + + +// Generation of the Operation signals +assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; +assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; +assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; +assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; + +// Busy +reg Busy; +always @ (posedge Clk or posedge Reset) + if (Reset) + Busy <=0; + else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid) + Busy <=1; + else + Busy <=0; + +//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; + + +// Generation of the InProgress signal (indicates when an operation is in progress) +// Generation of the WriteOp signal (indicates when a write is in progress) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + InProgress <= #Tp 1'b0; + WriteOp <= #Tp 1'b0; + end + else + begin + if(MdcEn) + begin + if(StartOp) + begin + if(~InProgress) + WriteOp <= #Tp WriteDataOp; + InProgress <= #Tp 1'b1; + end + else + begin + if(EndOp) + begin + InProgress <= #Tp 1'b0; + WriteOp <= #Tp 1'b0; + end + end + end + end +end + + + +// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + BitCounter[6:0] <= #Tp 7'h0; + else + begin + if(MdcEn) + begin + if(InProgress) + begin + if(NoPre & ( BitCounter == 7'h0 )) + BitCounter[6:0] <= #Tp 7'h21; + else + BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1; + end + else + BitCounter[6:0] <= #Tp 7'h0; + end + end +end + + +// Operation ends when the Bit Counter reaches 63 +assign EndOp = BitCounter==63; + +assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); +assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); +assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); +assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); + + +// Latch Byte selects which part of Read Status Data is updated from the shift register +assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; +assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; + + +// Connecting the Clock Generator Module +eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) + ); + +// Connecting the Shift Register Module +eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), + .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), + .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) + ); + +// Connecting the Output Control Module +eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), + .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), + .Mdo(Mdo), .MdoEn(MdoEn) + ); + +endmodule Index: trunk/FPGA/src/eth/RMON.v =================================================================== --- trunk/FPGA/src/eth/RMON.v (nonexistent) +++ trunk/FPGA/src/eth/RMON.v (revision 2) @@ -0,0 +1,180 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module RMON ( +Clk , +Reset , +//Tx_RMON +Tx_pkt_type_rmon , +Tx_pkt_length_rmon , +Tx_apply_rmon , +Tx_pkt_err_type_rmon, +//Tx_RMON +Rx_pkt_type_rmon , +Rx_pkt_length_rmon , +Rx_apply_rmon , +Rx_pkt_err_type_rmon, +//CPU +CPU_rd_addr , +CPU_rd_apply , +CPU_rd_grant , +CPU_rd_dout + +); +input Clk ; +input Reset ; + //Tx_RMON +input [2:0] Tx_pkt_type_rmon ; +input [15:0] Tx_pkt_length_rmon ; +input Tx_apply_rmon ; +input [2:0] Tx_pkt_err_type_rmon; + //Tx_RMON +input [2:0] Rx_pkt_type_rmon ; +input [15:0] Rx_pkt_length_rmon ; +input Rx_apply_rmon ; +input [2:0] Rx_pkt_err_type_rmon; + //CPU +input [5:0] CPU_rd_addr ; +input CPU_rd_apply ; +output CPU_rd_grant ; +output [31:0] CPU_rd_dout ; + +//****************************************************************************** +//interface signals +//****************************************************************************** +wire Reg_apply_0 ; +wire [4:0] Reg_addr_0 ; +wire [15:0] Reg_data_0 ; +wire Reg_next_0 ; +wire Reg_apply_1 ; +wire [4:0] Reg_addr_1 ; +wire [15:0] Reg_data_1 ; +wire Reg_next_1 ; +wire [5:0] Addra ; +wire [31:0] Dina ; +wire [31:0] Douta ; +wire Wea ; + +//****************************************************************************** + +assign RxAddrb=0; +assign TxAddrb=0; + +RMON_addr_gen U_0_Rx_RMON_addr_gen( +.Clk (Clk ), +.Reset (Reset ), + //RMON (//RMON ), +.Pkt_type_rmon (Rx_pkt_type_rmon ), +.Pkt_length_rmon (Rx_pkt_length_rmon ), +.Apply_rmon (Rx_apply_rmon ), +.Pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //Rmon_ctrl (//Rron_ctrl ), +.Reg_apply (Reg_apply_0 ), +.Reg_addr (Reg_addr_0 ), +.Reg_data (Reg_data_0 ), +.Reg_next (Reg_next_0 ), + //CPU (//CPU ), +.Reg_drop_apply ( )); + +RMON_addr_gen U_0_Tx_RMON_addr_gen( +.Clk (Clk ), +.Reset (Reset ), + //RMON (//RMON ), +.Pkt_type_rmon (Tx_pkt_type_rmon ), +.Pkt_length_rmon (Tx_pkt_length_rmon ), +.Apply_rmon (Tx_apply_rmon ), +.Pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //Rmon_ctrl (//Rron_ctrl ), +.Reg_apply (Reg_apply_1 ), +.Reg_addr (Reg_addr_1 ), +.Reg_data (Reg_data_1 ), +.Reg_next (Reg_next_1 ), + //CPU (//CPU ), +.Reg_drop_apply ( )); + +RMON_CTRL U_RMON_CTRL( +.Clk (Clk ), +.Reset (Reset ), + //RMON_CTRL (//RMON_CTRL ), +.Reg_apply_0 (Reg_apply_0 ), +.Reg_addr_0 (Reg_addr_0 ), +.Reg_data_0 (Reg_data_0 ), +.Reg_next_0 (Reg_next_0 ), +.Reg_apply_1 (Reg_apply_1 ), +.Reg_addr_1 (Reg_addr_1 ), +.Reg_data_1 (Reg_data_1 ), +.Reg_next_1 (Reg_next_1 ), + //dual-port ram (//dual-port ram ), +.Addra (Addra ), +.Dina (Dina ), +.Douta (Douta ), +.Wea (Wea ), + //CPU (//CPU ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ) +); + +RMON_dpram U_Rx_RMON_dpram( +.Reset (Reset ), +.Clk (Clk ), +//port-a for Rmon (//port-a for Rmon ), +.Addra (Addra ), +.Dina (Dina ), +.Douta ( ), +.Wea (Wea ), +//port-b for CPU (//port-b for CPU ), +.Addrb (Addra ), +.Doutb (Douta )); + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_tx.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx.v (revision 2) @@ -0,0 +1,264 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +module MAC_tx( +input Reset , +input Clk , +input Clk_user , + //PHY interface +output [7:0] TxD , +output TxEn , +input CRS , + //RMON +output [2:0] Tx_pkt_type_rmon , +output [15:0] Tx_pkt_length_rmon , +output Tx_apply_rmon , +output [2:0] Tx_pkt_err_type_rmon, + //user interface +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , + //host interface +input [4:0] Tx_Hwmark , +input [4:0] Tx_Lwmark , +input pause_frame_send_en , +input [15:0] pause_quanta_set , +input MAC_tx_add_en , +input FullDuplex , +input [3:0] MaxRetry , +input [5:0] IFGset , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , +input tx_pause_en , +input xoff_cpu , +input xon_cpu , + //MAC_rx_flow , +input [15:0] pause_quanta , +input pause_quanta_val +); +`include "header.v" +//****************************************************************************** +//internal signals +//****************************************************************************** + //CRC_gen Interface +wire CRC_init ; +wire[7:0] Frame_data ; +wire Data_en ; +wire CRC_rd ; +wire CRC_end ; +wire[7:0] CRC_out ; + //Ramdon_gen interface +wire Random_init ; +wire[3:0] RetryCnt ; +wire Random_time_meet ;//levle hight indicate random time passed away + //flow control +wire pause_apply ; +wire pause_quanta_sub ; +wire xoff_gen ; +wire xoff_gen_complete ; +wire xon_gen ; +wire xon_gen_complete ; + //MAC_rx_FF +wire[7:0] Fifo_data ; +wire Fifo_rd ; +wire Fifo_eop ; +wire Fifo_da ; +wire Fifo_rd_finish ; +wire Fifo_rd_retry ; +wire Fifo_ra ; +wire Fifo_data_err_empty ; +wire Fifo_data_err_full ; + //MAC_tx_addr_add +wire MAC_tx_addr_init ; +wire MAC_tx_addr_rd ; +wire[7:0] MAC_tx_addr_data ; + +//****************************************************************************** +//instantiation +//****************************************************************************** +MAC_tx_ctrl U_MAC_tx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //CRC_gen Interface (//CRC_gen Interface ), +.CRC_init (CRC_init ), +.Frame_data (Frame_data ), +.Data_en (Data_en ), +.CRC_rd (CRC_rd ), +.CRC_end (CRC_end ), +.CRC_out (CRC_out ), + //Ramdon_gen interfac (//Ramdon_gen interfac ), +.Random_init (Random_init ), +.RetryCnt (RetryCnt ), +.Random_time_meet (Random_time_meet ), + //flow control (//flow control ), +.pause_apply (pause_apply ), +.pause_quanta_sub (pause_quanta_sub ), +.xoff_gen (xoff_gen ), +.xoff_gen_complete (xoff_gen_complete ), +.xon_gen (xon_gen ), +.xon_gen_complete (xon_gen_complete ), + //MAC_tx_FF (//MAC_tx_FF ), +.Fifo_data (Fifo_data ), +.Fifo_rd (Fifo_rd ), +.Fifo_eop (Fifo_eop ), +.Fifo_da (Fifo_da ), +.Fifo_rd_finish (Fifo_rd_finish ), +.Fifo_rd_retry (Fifo_rd_retry ), +.Fifo_ra (Fifo_ra ), +.Fifo_data_err_empty (Fifo_data_err_empty ), +.Fifo_data_err_full (Fifo_data_err_full ), + //RMII (//RMII ), +.TxD (TxD ), +.TxEn (TxEn ), +.CRS (CRS ), + //MAC_tx_addr_add (//MAC_tx_addr_add ), +.MAC_tx_addr_rd (MAC_tx_addr_rd ), +.MAC_tx_addr_data (MAC_tx_addr_data ), +.MAC_tx_addr_init (MAC_tx_addr_init ), + //RMON (//RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //CPU (//CPU ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ) +); + +CRC_gen U_CRC_gen( +.Reset (Reset ), +.Clk (Clk ), +.Init (CRC_init ), +.Frame_data (Frame_data ), +.Data_en (Data_en ), +.CRC_rd (CRC_rd ), +.CRC_out (CRC_out ), +.CRC_end (CRC_end ) +); + +flow_ctrl U_flow_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //host processor (//host processor ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //MAC_rx_flow (//MAC_rx_flow ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //MAC_tx_ctrl (//MAC_tx_ctrl ), +.pause_apply (pause_apply ), +.pause_quanta_sub (pause_quanta_sub ), +.xoff_gen (xoff_gen ), +.xoff_gen_complete (xoff_gen_complete ), +.xon_gen (xon_gen ), +.xon_gen_complete (xon_gen_complete ) +); + +`ifdef MAC_SOURCE_REPLACE_EN +MAC_tx_addr_add U_MAC_tx_addr_add( +.Reset (Reset ), +.Clk (Clk ), +.MAC_tx_addr_rd (MAC_tx_addr_rd ), +.MAC_tx_addr_init (MAC_tx_addr_init ), +.MAC_tx_addr_data (MAC_tx_addr_data ), + //CPU (//CPU ), +.MAC_add_prom_data (MAC_add_prom_data ), +.MAC_add_prom_add (MAC_add_prom_add ), +.MAC_add_prom_wr (MAC_add_prom_wr ) +); +`else +assign MAC_tx_addr_data=0; +`endif +MAC_tx_FF U_MAC_tx_FF( +.Reset (Reset ), +.Clk_MAC (Clk ), +.Clk_SYS (Clk_user ), + //MAC_rx_ctrl interf (//MAC_rx_ctrl interf ), +.Fifo_data (Fifo_data ), +.Fifo_rd (Fifo_rd ), +.Fifo_rd_finish (Fifo_rd_finish ), +.Fifo_rd_retry (Fifo_rd_retry ), +.Fifo_eop (Fifo_eop ), +.Fifo_da (Fifo_da ), +.Fifo_ra (Fifo_ra ), +.Fifo_data_err_empty (Fifo_data_err_empty ), +.Fifo_data_err_full (Fifo_data_err_full ), + //user interface (//user interface ), +.Tx_mac_wa (Tx_mac_wa ), +.Tx_mac_wr (Tx_mac_wr ), +.Tx_mac_data (Tx_mac_data ), +.Tx_mac_BE (Tx_mac_BE ), +.Tx_mac_sop (Tx_mac_sop ), +.Tx_mac_eop (Tx_mac_eop ), + //host interface (//host interface ), +.FullDuplex (FullDuplex ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ) +); + +Ramdon_gen U_Ramdon_gen( +.Reset (Reset ), +.Clk (Clk ), +.Init (Random_init ), +.RetryCnt (RetryCnt ), +.Random_time_meet (Random_time_meet ) +); + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/Clk_ctrl.v =================================================================== --- trunk/FPGA/src/eth/Clk_ctrl.v (nonexistent) +++ trunk/FPGA/src/eth/Clk_ctrl.v (revision 2) @@ -0,0 +1,124 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clk_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Clk_ctrl( +Reset , +Clk_125M , +//host interface, +Speed , +//Phy interface , +Gtx_clk , +Rx_clk , +Tx_clk , +//interface clk , +MAC_tx_clk , +MAC_rx_clk , +MAC_tx_clk_div , +MAC_rx_clk_div +); +input Reset ; +input Clk_125M ; + //host interface +input [2:0] Speed ; + //Phy interface +output Gtx_clk ;//used only in GMII mode +input Rx_clk ; +input Tx_clk ;//used only in MII mode + //interface clk signals +output MAC_tx_clk ; +output MAC_rx_clk ; +output MAC_tx_clk_div ; +output MAC_rx_clk_div ; + + +//****************************************************************************** +//internal signals +//****************************************************************************** +wire Rx_clk_div2 ; +wire Tx_clk_div2 ; +//****************************************************************************** +// +//****************************************************************************** +assign Gtx_clk =Clk_125M ; +assign MAC_rx_clk =Rx_clk ; + +CLK_DIV2 U_0_CLK_DIV2( +.Reset (Reset ), +.IN (Rx_clk ), +.OUT (Rx_clk_div2 ) +); + +CLK_DIV2 U_1_CLK_DIV2( +.Reset (Reset ), +.IN (Tx_clk ), +.OUT (Tx_clk_div2 ) +); + +CLK_SWITCH U_0_CLK_SWITCH( +.IN_0 (Rx_clk_div2 ), +.IN_1 (Rx_clk ), +.SW (Speed[2] ), +.OUT (MAC_rx_clk_div ) +); + +CLK_SWITCH U_1_CLK_SWITCH( +.IN_0 (Tx_clk ), +.IN_1 (Clk_125M ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk ) +); + + +CLK_SWITCH U_2_CLK_SWITCH( +.IN_0 (Tx_clk_div2 ), +.IN_1 (Clk_125M ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk_div ) +); +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/TECH/CLK_DIV2.v =================================================================== --- trunk/FPGA/src/eth/TECH/CLK_DIV2.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/CLK_DIV2.v (revision 2) @@ -0,0 +1,68 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/TECH/altera/CLK_DIV2.v =================================================================== --- trunk/FPGA/src/eth/TECH/altera/CLK_DIV2.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/altera/CLK_DIV2.v (revision 2) @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:41 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/TECH/altera/duram.v =================================================================== --- trunk/FPGA/src/eth/TECH/altera/duram.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/altera/duram.v (revision 2) @@ -0,0 +1,87 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); //synthesis syn_black_box + +parameter DATA_WIDTH = 32; +parameter ADDR_WIDTH = 5; +parameter BLK_RAM_TYPE = "AUTO"; +parameter DURAM_MODE = "BIDIR_DUAL_PORT"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + + + +altsyncram U_altsyncram ( +.wren_a (wren_a), +.wren_b (wren_b), +.data_a (data_a), +.data_b (data_b), +.address_a (address_a), +.address_b (address_b), +.clock0 (clock_a), +.clock1 (clock_b), +.q_a (q_a), +.q_b (q_b), +// synopsys translate_off +.aclr0 (), +.aclr1 (), +.addressstall_a (), +.addressstall_b (), +.byteena_a (), +.byteena_b (), +.clocken0 (), +.clocken1 (), +.rden_b () +// synopsys translate_on +); + defparam + U_altsyncram.intended_device_family = "Stratix", + U_altsyncram.ram_block_type = BLK_RAM_TYPE, + U_altsyncram.operation_mode = DURAM_MODE, + U_altsyncram.width_a = DATA_WIDTH, + U_altsyncram.widthad_a = ADDR_WIDTH, +// U_altsyncram.numwords_a = 256, + U_altsyncram.width_b = DATA_WIDTH, + U_altsyncram.widthad_b = ADDR_WIDTH, +// U_altsyncram.numwords_b = 256, + U_altsyncram.lpm_type = "altsyncram", + U_altsyncram.width_byteena_a = 1, + U_altsyncram.width_byteena_b = 1, + U_altsyncram.outdata_reg_a = "UNREGISTERED", + U_altsyncram.outdata_aclr_a = "NONE", + U_altsyncram.outdata_reg_b = "UNREGISTERED", + U_altsyncram.indata_aclr_a = "NONE", + U_altsyncram.wrcontrol_aclr_a = "NONE", + U_altsyncram.address_aclr_a = "NONE", + U_altsyncram.indata_reg_b = "CLOCK1", + U_altsyncram.address_reg_b = "CLOCK1", + U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1", + U_altsyncram.indata_aclr_b = "NONE", + U_altsyncram.wrcontrol_aclr_b = "NONE", + U_altsyncram.address_aclr_b = "NONE", + U_altsyncram.outdata_aclr_b = "NONE", + U_altsyncram.power_up_uninitialized = "FALSE"; + +endmodule + + Index: trunk/FPGA/src/eth/TECH/altera/CLK_SWITCH.v =================================================================== --- trunk/FPGA/src/eth/TECH/altera/CLK_SWITCH.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/altera/CLK_SWITCH.v (revision 2) @@ -0,0 +1,68 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:41 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/TECH/xilinx/_xmsgs/cg.xmsgs =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/_xmsgs/cg.xmsgs (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/_xmsgs/cg.xmsgs (revision 2) @@ -0,0 +1,12 @@ + + + +Generating IP... + + + + Index: trunk/FPGA/src/eth/TECH/xilinx/tmp/_cg/_dbg/xil_546.in =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/tmp/_cg/_dbg/xil_546.in (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/tmp/_cg/_dbg/xil_546.in (revision 2) @@ -0,0 +1,41 @@ +SET_FLAG DEBUG FALSE +SET_FLAG MODE INTERACTIVE +SET_FLAG STANDALONE_MODE FALSE +SET_PREFERENCE devicefamily spartan6 +SET_PREFERENCE device xc6slx16 +SET_PREFERENCE speedgrade -2 +SET_PREFERENCE package csg324 +SET_PREFERENCE verilogsim false +SET_PREFERENCE vhdlsim true +SET_PREFERENCE simulationfiles Behavioral +SET_PREFERENCE busformat BusFormatAngleBracketNotRipped +SET_PREFERENCE outputdirectory /home/xl/ise_projects/Spartan6/sp601_eth_art/src/eth/TECH/xilinx/ +SET_PREFERENCE workingdirectory /home/xl/ise_projects/Spartan6/sp601_eth_art/src/eth/TECH/xilinx/tmp/ +SET_PREFERENCE subworkingdirectory /home/xl/ise_projects/Spartan6/sp601_eth_art/src/eth/TECH/xilinx/tmp/_cg/ +SET_PREFERENCE transientdirectory /home/xl/ise_projects/Spartan6/sp601_eth_art/src/eth/TECH/xilinx/tmp/_cg/_dbg/ +SET_PREFERENCE designentry VHDL +SET_PREFERENCE flowvendor Other +SET_PREFERENCE addpads false +SET_PREFERENCE projectname coregen +SET_PREFERENCE formalverification false +SET_PREFERENCE asysymbol false +SET_PREFERENCE implementationfiletype Ngc +SET_PREFERENCE foundationsym false +SET_PREFERENCE createndf false +SET_PREFERENCE removerpms false +SET_PARAMETER Component_Name clkdiv2 +SET_SIM_PARAMETER c_component_name clkdiv2 +SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)" +SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase" +SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +SET_CORE_NAME Clocking Wizard +SET_CORE_VERSION 3.3 +SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.3 +SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_3.clk_wiz_v3_3 +SET_CORE_PATH /home/xl/Xilinx/13.4/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_3 +SET_CORE_GUIPATH /home/xl/Xilinx/13.4/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_3/gui/clk_wiz_v3_3.tcl +SET_CORE_DATASHEET /home/xl/Xilinx/13.4/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_3/doc/clk_wiz_ds709.pdf +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT Index: trunk/FPGA/src/eth/TECH/xilinx/tmp/_cg/_dbg/xil_546.out =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/tmp/_cg/_dbg/xil_546.out (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/tmp/_cg/_dbg/xil_546.out (revision 2) @@ -0,0 +1,4 @@ +SET_PARAMETER component_name clkdiv2 +SET_ERROR_CODE 2 +SET_ERROR_MSG CANCEL: Customization cancelled. +SET_ERROR_TEXT Finished initializing IP model. Index: trunk/FPGA/src/eth/TECH/xilinx/CLK_DIV2.v =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/CLK_DIV2.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/CLK_DIV2.v (revision 2) @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:42 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/TECH/xilinx/coregen.log =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/coregen.log (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/coregen.log (revision 2) @@ -0,0 +1,3 @@ +INFO:sim:172 - Generating IP... +Cancelled executing Tcl generator. +Wrote CGP file for project 'clkdiv2'. Index: trunk/FPGA/src/eth/TECH/xilinx/create_clkdiv2.tcl =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/create_clkdiv2.tcl (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/create_clkdiv2.tcl (revision 2) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.3" "clkdiv2" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.3) generated by Project Navigator" xc6slx16-2csg324 VHDL ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result Index: trunk/FPGA/src/eth/TECH/xilinx/duram.v.old =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/duram.v.old (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/duram.v.old (revision 2) @@ -0,0 +1,60 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); + +parameter DATA_WIDTH = 36; +parameter ADDR_WIDTH = 9; +parameter BLK_RAM_TYPE = "AUTO"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + +wire [35:0] do_b; +wire [35:0] din_a; + +assign din_a =data_a; +assign q_b =do_b; + + +RAMB16_S36_S36 U_RAMB16_S36_S36 ( +.DOA ( ), +.DOB (do_b[31:0] ), +.DOPA ( ), +.DOPB (do_b[35:32] ), +.ADDRA (address_a ), +.ADDRB (address_b ), +.CLKA (clock_a ), +.CLKB (clock_b ), +.DIA (din_a[31:0] ), +.DIB ( ), +.DIPA (din_a[35:32] ), +.DIPB ( ), +.ENA (1'b1 ), +.ENB (1'b1 ), +.SSRA (1'b0 ), +.SSRB (1'b0 ), +.WEA (wren_a ), +.WEB (1'b0 )); + +endmodule + + Index: trunk/FPGA/src/eth/TECH/xilinx/duram.v =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/duram.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/duram.v (revision 2) @@ -0,0 +1,50 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); + +parameter DATA_WIDTH = 36; +parameter ADDR_WIDTH = 10; +parameter dummy = "dummy"; +parameter dummy2 = "dummy2"; + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output reg [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output reg [DATA_WIDTH -1:0] q_b; + + // Shared memory + reg [DATA_WIDTH-1:0] mem [(2**ADDR_WIDTH)-1:0]; + + // Port A + always @(posedge clock_a) begin + q_a <= mem[address_a]; + if(wren_a) begin + q_a <= data_a; + mem[address_a] <= data_a; + end + end + + // Port B + always @(posedge clock_b) begin + q_b <= mem[address_b]; + if(wren_b) begin + q_b <= data_b; + mem[address_b] <= data_b; + end + end + +endmodule Index: trunk/FPGA/src/eth/TECH/xilinx/CLK_SWITCH.v =================================================================== --- trunk/FPGA/src/eth/TECH/xilinx/CLK_SWITCH.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/xilinx/CLK_SWITCH.v (revision 2) @@ -0,0 +1,74 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2006/06/22 09:01:42 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +BUFGMUX U_BUFGMUX ( +.O (OUT ), +.I0 (IN_0 ), +.I1 (IN_1 ), +.S (SW )); + +//assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/TECH/duram.v =================================================================== --- trunk/FPGA/src/eth/TECH/duram.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/duram.v (revision 2) @@ -0,0 +1,87 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); //synthesis syn_black_box + +parameter DATA_WIDTH = 32; +parameter ADDR_WIDTH = 5; +parameter BLK_RAM_TYPE = "AUTO"; +parameter DURAM_MODE = "BIDIR_DUAL_PORT"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + + + +altsyncram U_altsyncram ( +.wren_a (wren_a), +.wren_b (wren_b), +.data_a (data_a), +.data_b (data_b), +.address_a (address_a), +.address_b (address_b), +.clock0 (clock_a), +.clock1 (clock_b), +.q_a (q_a), +.q_b (q_b), +// synopsys translate_off +.aclr0 (), +.aclr1 (), +.addressstall_a (), +.addressstall_b (), +.byteena_a (), +.byteena_b (), +.clocken0 (), +.clocken1 (), +.rden_b () +// synopsys translate_on +); + defparam + U_altsyncram.intended_device_family = "Stratix", + U_altsyncram.ram_block_type = BLK_RAM_TYPE, + U_altsyncram.operation_mode = DURAM_MODE, + U_altsyncram.width_a = DATA_WIDTH, + U_altsyncram.widthad_a = ADDR_WIDTH, +// U_altsyncram.numwords_a = 256, + U_altsyncram.width_b = DATA_WIDTH, + U_altsyncram.widthad_b = ADDR_WIDTH, +// U_altsyncram.numwords_b = 256, + U_altsyncram.lpm_type = "altsyncram", + U_altsyncram.width_byteena_a = 1, + U_altsyncram.width_byteena_b = 1, + U_altsyncram.outdata_reg_a = "UNREGISTERED", + U_altsyncram.outdata_aclr_a = "NONE", + U_altsyncram.outdata_reg_b = "UNREGISTERED", + U_altsyncram.indata_aclr_a = "NONE", + U_altsyncram.wrcontrol_aclr_a = "NONE", + U_altsyncram.address_aclr_a = "NONE", + U_altsyncram.indata_reg_b = "CLOCK1", + U_altsyncram.address_reg_b = "CLOCK1", + U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1", + U_altsyncram.indata_aclr_b = "NONE", + U_altsyncram.wrcontrol_aclr_b = "NONE", + U_altsyncram.address_aclr_b = "NONE", + U_altsyncram.outdata_aclr_b = "NONE", + U_altsyncram.power_up_uninitialized = "FALSE"; + +endmodule + + Index: trunk/FPGA/src/eth/TECH/CLK_SWITCH.v =================================================================== --- trunk/FPGA/src/eth/TECH/CLK_SWITCH.v (nonexistent) +++ trunk/FPGA/src/eth/TECH/CLK_SWITCH.v (revision 2) @@ -0,0 +1,65 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_top.v =================================================================== --- trunk/FPGA/src/eth/MAC_top.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_top.v (revision 2) @@ -0,0 +1,485 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_top.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module MAC_top( + //system signals +input Reset , +input Clk_125M , +input Clk_user , +input Clk_reg , +output [2:0] Speed , + //user interface +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , + //user interface +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , + //pkg_lgth fifo +input Pkg_lgth_fifo_rd , +output Pkg_lgth_fifo_ra , +output [15:0] Pkg_lgth_fifo_data , + //Phy interface + //Phy interface +output Gtx_clk ,//used only in GMII mode +input Rx_clk , +input Tx_clk ,//used only in MII mode +output Tx_er , +output Tx_en , +output [7:0] Txd , +input Rx_er , +input Rx_dv , +input [7:0] Rxd , +input Crs , +input Col , + //host interface +input CSB , +input WRB , +input [15:0] CD_in , +output [15:0] CD_out , +input [7:0] CA , + //mdx +output Mdo, // MII Management Data Output +output MdoEn, // MII Management Data Output Enable +input Mdi, +output Mdc // MII Management Data Clock + +); +`include "header.v" +//****************************************************************************** +//internal signals +//****************************************************************************** + //RMON interface +wire [15:0] Rx_pkt_length_rmon ; +wire Rx_apply_rmon ; +wire [2:0] Rx_pkt_err_type_rmon ; +wire [2:0] Rx_pkt_type_rmon ; +wire [2:0] Tx_pkt_type_rmon ; +wire [15:0] Tx_pkt_length_rmon ; +wire Tx_apply_rmon ; +wire [2:0] Tx_pkt_err_type_rmon ; + //PHY interface +wire MCrs_dv ; +wire [7:0] MRxD ; +wire MRxErr ; + //flow_control signals +wire [15:0] pause_quanta ; +wire pause_quanta_val ; + //PHY interface +wire [7:0] MTxD ; +wire MTxEn ; +wire MCRS ; + //interface clk signals +wire MAC_tx_clk ; +wire MAC_rx_clk ; +wire MAC_tx_clk_div ; +wire MAC_rx_clk_div ; + //reg signals +wire [4:0] Tx_Hwmark ; +wire [4:0] Tx_Lwmark ; +wire pause_frame_send_en ; +wire [15:0] pause_quanta_set ; +wire MAC_tx_add_en ; +wire FullDuplex ; +wire [3:0] MaxRetry ; +wire [5:0] IFGset ; +wire [7:0] MAC_tx_add_prom_data ; +wire [2:0] MAC_tx_add_prom_add ; +wire MAC_tx_add_prom_wr ; +wire tx_pause_en ; +wire xoff_cpu ; +wire xon_cpu ; + //Rx host interface +wire MAC_rx_add_chk_en ; +wire [7:0] MAC_rx_add_prom_data ; +wire [2:0] MAC_rx_add_prom_add ; +wire MAC_rx_add_prom_wr ; +wire broadcast_filter_en ; +wire [15:0] broadcast_MAX ; +wire RX_APPEND_CRC ; +wire [4:0] Rx_Hwmark ; +wire [4:0] Rx_Lwmark ; +wire CRC_chk_en ; +wire [5:0] RX_IFG_SET ; +wire [15:0] RX_MAX_LENGTH ; +wire [6:0] RX_MIN_LENGTH ; + //RMON host interface +wire [5:0] CPU_rd_addr ; +wire CPU_rd_apply ; +wire CPU_rd_grant ; +wire [31:0] CPU_rd_dout ; + //Phy int host interface +wire Line_loop_en ; + //MII to CPU +wire [7:0] Divider ; +wire [15:0] CtrlData ; +wire [4:0] Rgad ; +wire [4:0] Fiad ; +wire NoPre ; +wire WCtrlData ; +wire RStat ; +wire ScanStat ; +wire Busy ; +wire LinkFail ; +wire Nvalid ; +wire [15:0] Prsd ; +wire WCtrlDataStart ; +wire RStatStart ; +wire UpdateMIIRX_DATAReg ; +wire [15:0] broadcast_bucket_depth ; +wire [15:0] broadcast_bucket_interval ; +wire Pkg_lgth_fifo_empty; + +reg rx_pkg_lgth_fifo_wr_tmp; +reg rx_pkg_lgth_fifo_wr_tmp_pl1; +reg rx_pkg_lgth_fifo_wr; + +//****************************************************************************** +//internal signals +//****************************************************************************** +MAC_rx U_MAC_rx( +.Reset (Reset ), +.Clk_user (Clk_user ), +.Clk (MAC_rx_clk_div ), + //RMII interface (//PHY interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //user interface (//user interface ), +.Rx_mac_ra (Rx_mac_ra ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_pa (Rx_mac_pa ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_eop (Rx_mac_eop ), + //CPU (//CPU ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_add_prom_data (MAC_rx_add_prom_data ), +.MAC_add_prom_add (MAC_rx_add_prom_add ), +.MAC_add_prom_wr (MAC_rx_add_prom_wr ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ), +.RX_APPEND_CRC (RX_APPEND_CRC ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.CRC_chk_en (CRC_chk_en ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ), + //RMON interface (//RMON interface ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ) +); + +MAC_tx U_MAC_tx( +.Reset (Reset ), +.Clk (MAC_tx_clk_div ), +.Clk_user (Clk_user ), + //PHY interface (//PHY interface ), +.TxD (MTxD ), +.TxEn (MTxEn ), +.CRS (MCRS ), + //RMON (//RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //user interface (//user interface ), +.Tx_mac_wa (Tx_mac_wa ), +.Tx_mac_wr (Tx_mac_wr ), +.Tx_mac_data (Tx_mac_data ), +.Tx_mac_BE (Tx_mac_BE ), +.Tx_mac_sop (Tx_mac_sop ), +.Tx_mac_eop (Tx_mac_eop ), + //host interface (//host interface ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ), +.MAC_add_prom_data (MAC_tx_add_prom_data ), +.MAC_add_prom_add (MAC_tx_add_prom_add ), +.MAC_add_prom_wr (MAC_tx_add_prom_wr ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //MAC_rx_flow (//MAC_rx_flow ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ) +); + + +assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty; +always @ (posedge Reset or posedge MAC_rx_clk_div) + if (Reset) + rx_pkg_lgth_fifo_wr_tmp <=0; + else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100) + rx_pkg_lgth_fifo_wr_tmp <=1; + else + rx_pkg_lgth_fifo_wr_tmp <=0; + +always @ (posedge Reset or posedge MAC_rx_clk_div) + if (Reset) + rx_pkg_lgth_fifo_wr_tmp_pl1 <=0; + else + rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp; + +always @ (posedge Reset or posedge MAC_rx_clk_div) + if (Reset) + rx_pkg_lgth_fifo_wr <=0; + else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1) + rx_pkg_lgth_fifo_wr <=1; + else + rx_pkg_lgth_fifo_wr <=0; + +afifo U_rx_pkg_lgth_fifo ( +.din (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4), +.wr_en (rx_pkg_lgth_fifo_wr ), +.wr_clk (MAC_rx_clk_div ), +.rd_en (Pkg_lgth_fifo_rd ), +.rd_clk (Clk_user ), +.ainit (Reset ), +.dout (Pkg_lgth_fifo_data ), +.full ( ), +.almost_full ( ), +.empty (Pkg_lgth_fifo_empty ), +.wr_count ( ), +.rd_count ( ), +.rd_ack ( ), +.wr_ack ( )); + + +RMON U_RMON( +.Clk (Clk_reg ), +.Reset (Reset ), + //Tx_RMON (//Tx_RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //Tx_RMON (//Tx_RMON ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ) +); + +Phy_int U_Phy_int( +.Reset (Reset ), +.MAC_rx_clk (MAC_rx_clk ), +.MAC_tx_clk (MAC_tx_clk ), + //Rx interface (//Rx interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //Tx interface (//Tx interface ), +.MTxD (MTxD ), +.MTxEn (MTxEn ), +.MCRS (MCRS ), + //Phy interface (//Phy interface ), +.Tx_er (Tx_er ), +.Tx_en (Tx_en ), +.Txd (Txd ), +.Rx_er (Rx_er ), +.Rx_dv (Rx_dv ), +.Rxd (Rxd ), +.Crs (Crs ), +.Col (Col ), + //host interface (//host interface ), +.Line_loop_en (Line_loop_en ), +.Speed (Speed ) +); + +Clk_ctrl U_Clk_ctrl( +.Reset (Reset ), +.Clk_125M (Clk_125M ), + //host interface (//host interface ), +.Speed (Speed ), + //Phy interface (//Phy interface ), +.Gtx_clk (Gtx_clk ), +.Rx_clk (Rx_clk ), +.Tx_clk (Tx_clk ), + //interface clk (//interface clk ), +.MAC_tx_clk (MAC_tx_clk ), +.MAC_rx_clk (MAC_rx_clk ), +.MAC_tx_clk_div (MAC_tx_clk_div ), +.MAC_rx_clk_div (MAC_rx_clk_div ) +); + +eth_miim U_eth_miim( +.Clk (Clk_reg ), +.Reset (Reset ), +.Divider (Divider ), +.NoPre (NoPre ), +.CtrlData (CtrlData ), +.Rgad (Rgad ), +.Fiad (Fiad ), +.WCtrlData (WCtrlData ), +.RStat (RStat ), +.ScanStat (ScanStat ), +.Mdo (Mdo ), +.MdoEn (MdoEn ), +.Mdi (Mdi ), +.Mdc (Mdc ), +.Busy (Busy ), +.Prsd (Prsd ), +.LinkFail (LinkFail ), +.Nvalid (Nvalid ), +.WCtrlDataStart (WCtrlDataStart ), +.RStatStart (RStatStart ), +.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )); + +Reg_int U_Reg_int( +.Reset (Reset ), +.Clk_reg (Clk_reg ), +.CSB (CSB ), +.WRB (WRB ), +.CD_in (CD_in ), +.CD_out (CD_out ), +.CA (CA ), + //Tx host interface (//Tx host interface ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ), +.MAC_tx_add_prom_data (MAC_tx_add_prom_data ), +.MAC_tx_add_prom_add (MAC_tx_add_prom_add ), +.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //Rx host interface (//Rx host interface ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_rx_add_prom_data (MAC_rx_add_prom_data ), +.MAC_rx_add_prom_add (MAC_rx_add_prom_add ), +.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ), +.RX_APPEND_CRC (RX_APPEND_CRC ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.CRC_chk_en (CRC_chk_en ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ), + //RMON host interface (//RMON host interface ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ), + //Phy int host interface (//Phy int host interface ), +.Line_loop_en (Line_loop_en ), +.Speed (Speed ), + //MII to CPU (//MII to CPU ), +.Divider (Divider ), +.CtrlData (CtrlData ), +.Rgad (Rgad ), +.Fiad (Fiad ), +.NoPre (NoPre ), +.WCtrlData (WCtrlData ), +.RStat (RStat ), +.ScanStat (ScanStat ), +.Busy (Busy ), +.LinkFail (LinkFail ), +.Nvalid (Nvalid ), +.Prsd (Prsd ), +.WCtrlDataStart (WCtrlDataStart ), +.RStatStart (RStatStart ), +.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ) +); + +endmodule + + + + + + + + + + + + + + + + + Index: trunk/FPGA/src/eth/afifo.v =================================================================== --- trunk/FPGA/src/eth/afifo.v (nonexistent) +++ trunk/FPGA/src/eth/afifo.v (revision 2) @@ -0,0 +1,285 @@ +module afifo( +din, +wr_en, +wr_clk, +rd_en, +rd_clk, +ainit, +dout, +full, +almost_full, +empty, +wr_count, +rd_count, +rd_ack, +wr_ack); + +////////////////////////////////////////////////////// +parameter DATA_WIDTH =16; +parameter ADDR_WIDTH =8; +parameter COUNT_DATA_WIDTH =8; +parameter ALMOST_FULL_DEPTH =8; +////////////////////////////////////////////////////// +input [DATA_WIDTH-1:0] din; +input wr_en; +input wr_clk; +input rd_en; +input rd_clk; +input ainit; +output [DATA_WIDTH-1:0] dout; +output full; +output almost_full; +output empty; +output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */; +output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */; +output rd_ack; +output wr_ack; +////////////////////////////////////////////////////// +//local signals +////////////////////////////////////////////////////// +reg [ADDR_WIDTH-1:0] Add_wr; +reg [ADDR_WIDTH-1:0] Add_wr_ungray; +reg [ADDR_WIDTH-1:0] Add_wr_gray; +reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1; + +reg [ADDR_WIDTH-1:0] Add_rd; +wire [ADDR_WIDTH-1:0] Add_rd_pluse; +reg [ADDR_WIDTH-1:0] Add_rd_gray; +reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1; +reg [ADDR_WIDTH-1:0] Add_rd_ungray; +wire [ADDR_WIDTH-1:0] Add_wr_pluse; +integer i; +reg full /* synthesis syn_keep=1 */; +reg empty; +wire [ADDR_WIDTH-1:0] ff_used_wr; +wire [ADDR_WIDTH-1:0] ff_used_rd; +reg rd_ack; +reg rd_ack_tmp; +reg almost_full; +wire [DATA_WIDTH-1:0] dout_tmp; + +////////////////////////////////////////////////////// +//Write clock domain +////////////////////////////////////////////////////// +assign wr_ack =0; +assign ff_used_wr =Add_wr-Add_rd_ungray; + +assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH]; + + + + +always @ (posedge ainit or posedge wr_clk) + if (ainit) + Add_wr_gray <=0; + else + begin + Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +//¶ÁµØÖ·½øÐз´gray±àÂë. + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + Add_rd_ungray =0; + else + begin + Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end + +assign Add_wr_pluse=Add_wr+1; + + +/* +always @ (Add_wr_pluse or Add_rd_ungray) + if (Add_wr_pluse==Add_rd_ungray) + full =1; + else + full =0; + +*/ +always @ (posedge wr_clk or posedge ainit) + if (ainit) + full <=0; + else if(Add_wr_pluse==Add_rd_ungray&&wr_en) + full <=1; + else if(Add_wr!=Add_rd_ungray) + full <=0; + + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + almost_full <=0; + else if (wr_count>=ALMOST_FULL_DEPTH) + almost_full <=1; + else + almost_full <=0; + +always @ (posedge wr_clk or posedge ainit) + if (ainit) + Add_wr <=0; + else if (wr_en&&!full) + Add_wr <=Add_wr +1; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//****************************************************************************** +//read clock domain +//****************************************************************************** +always @ (posedge rd_clk or posedge ainit) + if (ainit) + rd_ack <=0; + else if (rd_en&&!empty) + rd_ack <=1; + else + rd_ack <=0; + + + +assign ff_used_rd =Add_wr_ungray-Add_rd; +assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH]; +assign Add_rd_pluse =Add_rd+1; + + +always @ (posedge rd_clk or posedge ainit) + if (ainit) + Add_rd <=0; + else if (rd_en&&!empty) //³öEOPºó¾Í²»¶ÁÁË¡£ + Add_rd <=Add_rd + 1; + +//¶ÁµØÖ·½øÐÐgrayÂë±ä»». +always @ (posedge ainit or posedge rd_clk) + if (ainit) + Add_rd_gray <=0; + else + begin + Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +/* Add_rd_gray <={ Add_rd[8], + Add_rd[8]^Add_rd[7], + Add_rd[7]^Add_rd[6], + Add_rd[6]^Add_rd[5], + Add_rd[5]^Add_rd[4], + Add_rd[4]^Add_rd[3], + Add_rd[3]^Add_rd[2], + Add_rd[2]^Add_rd[1], + Add_rd[1]^Add_rd[0]}; +*/ +//дµØÖ·½øÐз´gray±àÂë. + +always @ (posedge rd_clk or posedge ainit) + if (ainit) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge rd_clk or posedge ainit) + if (ainit) + Add_wr_ungray =0; + else + begin + Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1]; + for (i=ADDR_WIDTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end + +/* Add_wr_ungray <={ + Add_wr_gray_dl1[8], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1], + Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] }; +*/ +//emptyÐźŲúÉú +/* +always @ (Add_rd or Add_wr_ungray) + if (Add_rd==Add_wr_ungray) + empty =1; + else + empty =0; +*/ +always @ (posedge rd_clk or posedge ainit) + if (ainit) + empty <=1; + else if (Add_rd_pluse==Add_wr_ungray&&rd_en) + empty <=1; + else if (Add_rd!=Add_wr_ungray) + empty <=0; + + + +////////////////////////////////////////////////////// +//instant need change for your own dpram +////////////////////////////////////////////////////// +duram #( +DATA_WIDTH, +ADDR_WIDTH +) +U_duram ( +.data_a (din ), +.wren_a (wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (wr_clk ), +.clock_b (rd_clk ), +.q_b (dout )); + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_rx/CRC_chk.v =================================================================== --- trunk/FPGA/src/eth/MAC_rx/CRC_chk.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_rx/CRC_chk.v (revision 2) @@ -0,0 +1,126 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_chk( +Reset , +Clk , +CRC_data , +CRC_init , +CRC_en , +//From CPU +CRC_chk_en , +CRC_err +); +input Reset ; +input Clk ; +input[7:0] CRC_data ; +input CRC_init ; +input CRC_en ; + //From CPU +input CRC_chk_en ; +output CRC_err ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [31:0] CRC_reg; +wire[31:0] Next_CRC; +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction + +always @ (posedge Clk or posedge Reset) + if (Reset) + CRC_reg <=32'hffffffff; + else if (CRC_init) + CRC_reg <=32'hffffffff; + else if (CRC_en) + CRC_reg <=NextCRC(CRC_data,CRC_reg); + +assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b); + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_rx/MAC_rx_ctrl.v =================================================================== --- trunk/FPGA/src/eth/MAC_rx/MAC_rx_ctrl.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_rx/MAC_rx_ctrl.v (revision 2) @@ -0,0 +1,533 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_ctrl ( +Reset , +Clk , +//RMII interface +MCrs_dv , // +MRxD , // +MRxErr , // +//CRC_chk interface +CRC_en , +CRC_init , +CRC_err , +//MAC_rx_add_chk interface +MAC_add_en , +MAC_rx_add_chk_err , +//broadcast_filter +broadcast_ptr , +broadcast_drop , +//flow_control signals +pause_quanta , +pause_quanta_val , +//MAC_rx_FF interface +Fifo_data , +Fifo_data_en , +Fifo_data_err , +Fifo_data_end , +Fifo_full , +//RMON interface +Rx_pkt_type_rmon , +Rx_pkt_length_rmon , +Rx_apply_rmon , +Rx_pkt_err_type_rmon , +//CPU +RX_IFG_SET , +RX_MAX_LENGTH, +RX_MIN_LENGTH +); + +input Reset ; +input Clk ; + //RMII interface +input MCrs_dv ; +input [7:0] MRxD ; +input MRxErr ; + //CRC_chk interface +output CRC_en ; +output CRC_init; +input CRC_err ; + //MAC_rx_add_chk interface +output MAC_add_en ; +input MAC_rx_add_chk_err ; + //broadcast_filter +output broadcast_ptr ; +input broadcast_drop ; + //flow_control signals +output [15:0] pause_quanta ; +output pause_quanta_val ; + //MAC_rx_FF interface +output [7:0] Fifo_data ; +output Fifo_data_en ; +output Fifo_data_err ; +output Fifo_data_end ; +input Fifo_full; + //RMON interface +output [15:0] Rx_pkt_length_rmon ; +output Rx_apply_rmon ; +output [2:0] Rx_pkt_err_type_rmon ; +output [2:0] Rx_pkt_type_rmon ; + //CPU +input [5:0] RX_IFG_SET ; +input [15:0] RX_MAX_LENGTH ;// 1518 +input [6:0] RX_MIN_LENGTH ;// 64 + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_idle =4'd00; +parameter State_preamble =4'd01; +parameter State_SFD =4'd02; +parameter State_data =4'd03; +parameter State_checkCRC =4'd04; +parameter State_OkEnd =4'd07; +parameter State_drop =4'd08; +parameter State_ErrEnd =4'd09; +parameter State_CRCErrEnd =4'd10; +parameter State_FFFullDrop =4'd11; +parameter State_FFFullErrEnd =4'd12; +parameter State_IFG =4'd13; + +parameter Pause_idle =4'd0; +parameter Pause_pre_syn =4'd1; +parameter Pause_quanta_hi =4'd2; +parameter Pause_quanta_lo =4'd3; +parameter Pause_syn =4'd4; + +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [3:0] Pause_current /* synthesis syn_keep=1 */; +reg [3:0] Pause_next; +reg [5:0] IFG_counter; +reg Crs_dv ; +reg [7:0] RxD ; +reg [7:0] RxD_dl1 ; +reg RxErr ; +reg [15:0] Frame_length_counter; +reg Too_long; +reg Too_short; +reg Fifo_data_en; +reg Fifo_data_end; +reg Fifo_data_err; +reg CRC_en; +reg CRC_init; +reg Rx_apply_rmon; +reg Rx_apply_rmon_tmp; +reg Rx_apply_rmon_tmp_pl1; +reg [2:0] Rx_pkt_err_type_rmon; +reg MAC_add_en; +reg [2:0] Rx_pkt_type_rmon; +reg [7:0] pause_quanta_h ; +reg [15:0] pause_quanta ; +reg pause_quanta_val ; +reg pause_quanta_val_tmp; +reg pause_frame_ptr ; +reg broadcast_ptr ; +//****************************************************************************** +//delay signals +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + begin + Crs_dv <=0; + RxD <=0; + RxErr <=0; + end + else + begin + Crs_dv <=MCrs_dv ; + RxD <=MRxD ; + RxErr <=MRxErr ; + end + +always @ (posedge Reset or posedge Clk) + if (Reset) + RxD_dl1 <=0; + else + RxD_dl1 <=RxD; + +//****************************************************************************** +//State_machine +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + State_idle: + if (Crs_dv&&RxD==8'h55) + Next_state =State_preamble; + else + Next_state =Current_state; + State_preamble: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else if (RxD==8'hd5) + Next_state =State_SFD; + else if (RxD==8'h55) + Next_state =Current_state; + else + Next_state =State_drop; + State_SFD: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else + Next_state =State_data; + State_data: + if (!Crs_dv&&!Too_short&&!Too_long) + Next_state =State_checkCRC; + else if (!Crs_dv&&(Too_short||Too_long)) + Next_state =State_ErrEnd; + else if (Fifo_full) + Next_state =State_FFFullErrEnd; + else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop) + Next_state =State_drop; + else + Next_state =State_data; + State_checkCRC: + if (CRC_err) + Next_state =State_CRCErrEnd; + else + Next_state =State_OkEnd; + State_drop: + if (!Crs_dv) + Next_state =State_ErrEnd; + else + Next_state =Current_state; + State_OkEnd: + Next_state =State_IFG; + State_ErrEnd: + Next_state =State_IFG; + + State_CRCErrEnd: + Next_state =State_IFG; + State_FFFullDrop: + if (!Crs_dv) + Next_state =State_IFG; + else + Next_state =Current_state; + State_FFFullErrEnd: + Next_state =State_FFFullDrop; + State_IFG: + if (IFG_counter==RX_IFG_SET-4) //remove some additional time + Next_state =State_idle; + else + Next_state =Current_state; + + default: + Next_state =State_idle; + endcase + + +always @ (posedge Reset or posedge Clk) + if (Reset) + IFG_counter <=0; + else if (Current_state!=State_IFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; +//****************************************************************************** +//gen fifo interface signals +//****************************************************************************** + +assign Fifo_data =RxD_dl1; + +always @(Current_state) + if (Current_state==State_data) + Fifo_data_en =1; + else + Fifo_data_en =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_OkEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_end =1; + else + Fifo_data_end =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_err =1; + else + Fifo_data_err =0; + +//****************************************************************************** +//CRC_chk interface +//****************************************************************************** + +always @(Current_state) + if (Current_state==State_data) + CRC_en =1; + else + CRC_en =0; + +always @(Current_state) + if (Current_state==State_SFD) + CRC_init =1; + else + CRC_init =0; + +//****************************************************************************** +//gen rmon signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Frame_length_counter <=0; + else if (Current_state==State_SFD) + Frame_length_counter <=1; + else if (Current_state==State_data) + Frame_length_counter <=Frame_length_counter+ 1'b1; + +always @ (Frame_length_counter or RX_MIN_LENGTH) + if (Frame_length_counterRX_MAX_LENGTH) + Too_long =1; + else + Too_long =0; + +assign Rx_pkt_length_rmon=Frame_length_counter-1'b1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon_tmp <=1; + else + Rx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp_pl1 <=0; + else + Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon <=1; + else if (Rx_apply_rmon_tmp_pl1) + Rx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_err_type_rmon <=0; + else if (Current_state==State_CRCErrEnd) + Rx_pkt_err_type_rmon <=3'b001 ;// + else if (Current_state==State_FFFullErrEnd) + Rx_pkt_err_type_rmon <=3'b010 ;// + else if (Current_state==State_ErrEnd) + Rx_pkt_err_type_rmon <=3'b011 ;// + else if(Current_state==State_OkEnd) + Rx_pkt_err_type_rmon <=3'b100 ; + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_type_rmon <=0; + else if (Current_state==State_OkEnd&&pause_frame_ptr) + Rx_pkt_type_rmon <=3'b100 ;// + else if(Current_state==State_SFD&&Next_state==State_data) + Rx_pkt_type_rmon <={1'b0,MRxD[7:6]}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_ptr <=0; + else if(Current_state==State_IFG) + broadcast_ptr <=0; + else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11) + broadcast_ptr <=1; + + + +//****************************************************************************** +//MAC add checker signals +//****************************************************************************** +always @ (Frame_length_counter or Fifo_data_en) + if(Frame_length_counter>=1&&Frame_length_counter<=6) + MAC_add_en <=Fifo_data_en; + else + MAC_add_en <=0; + +//****************************************************************************** +//flow control signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Pause_current <=Pause_idle; + else + Pause_current <=Pause_next; + +always @ (*) + case (Pause_current) + Pause_idle : + if(Current_state==State_SFD) + Pause_next =Pause_pre_syn; + else + Pause_next =Pause_current; + Pause_pre_syn: + case (Frame_length_counter) + 16'd1: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd2: if (RxD_dl1==8'h80) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd3: if (RxD_dl1==8'hc2) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd4: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd5: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd6: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd13: if (RxD_dl1==8'h88) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd14: if (RxD_dl1==8'h08) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd15: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd16: if (RxD_dl1==8'h01) + Pause_next =Pause_quanta_hi; + else + Pause_next =Pause_idle; + default: Pause_next =Pause_current; + endcase + Pause_quanta_hi : + Pause_next =Pause_quanta_lo; + Pause_quanta_lo : + Pause_next =Pause_syn; + Pause_syn : + if (Current_state==State_IFG) + Pause_next =Pause_idle; + else + Pause_next =Pause_current; + default + Pause_next =Pause_idle; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_h <=0; + else if(Pause_current==Pause_quanta_hi) + pause_quanta_h <=RxD_dl1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta <=0; + else if(Pause_current==Pause_quanta_lo) + pause_quanta <={pause_quanta_h,RxD_dl1}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val_tmp <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn) + pause_quanta_val_tmp <=1; + else + pause_quanta_val_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp) + pause_quanta_val <=1; + else + pause_quanta_val <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_frame_ptr <=0; + else if(Pause_current==Pause_syn) + pause_frame_ptr <=1; + else + pause_frame_ptr <=0; + +endmodule + + \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_rx/MAC_rx_FF.v =================================================================== --- trunk/FPGA/src/eth/MAC_rx/MAC_rx_FF.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_rx/MAC_rx_FF.v (revision 2) @@ -0,0 +1,735 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2008/08/17 11:41:30 maverickist +// no message +// +// Revision 1.5 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.4 2006/05/28 05:09:20 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_FF ( +Reset , +Clk_MAC , +Clk_SYS , +//MAC_rx_ctrl interface +Fifo_data , +Fifo_data_en , +Fifo_full , +Fifo_data_err , +Fifo_data_end , +//CPU +Rx_Hwmark, +Rx_Lwmark, +RX_APPEND_CRC, +//user interface +Rx_mac_ra , +Rx_mac_rd , +Rx_mac_data , +Rx_mac_BE , +Rx_mac_sop , +Rx_mac_pa, +Rx_mac_eop +); +`include "../header.v" +input Reset ; +input Clk_MAC ; +input Clk_SYS ; + //MAC_rx_ctrl interface +input [7:0] Fifo_data ; +input Fifo_data_en ; +output Fifo_full ; +input Fifo_data_err ; +input Fifo_data_end ; + //CPU +input RX_APPEND_CRC ; +input [4:0] Rx_Hwmark ; +input [4:0] Rx_Lwmark ; + //user interface +output Rx_mac_ra ;// +input Rx_mac_rd ; +output [31:0] Rx_mac_data ; +output [1:0] Rx_mac_BE ; +output Rx_mac_pa ; +output Rx_mac_sop ; +output Rx_mac_eop ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_byte3 =4'd0; +parameter State_byte2 =4'd1; +parameter State_byte1 =4'd2; +parameter State_byte0 =4'd3; +parameter State_be0 =4'd4; +parameter State_be3 =4'd5; +parameter State_be2 =4'd6; +parameter State_be1 =4'd7; +parameter State_err_end =4'd8; +parameter State_idle =4'd9; + +parameter SYS_read =3'd0; +parameter SYS_pause =3'd1; +parameter SYS_wait_end =3'd2; +parameter SYS_idle =3'd3; +parameter FF_emtpy_err =3'd4; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray; +reg [35:0] Din; +reg [35:0] Din_tmp; +reg [35:0] Din_tmp_reg; +wire[35:0] Dout; +reg Wr_en; +reg Wr_en_tmp; +reg Wr_en_ptr; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2; +reg Full; +reg Almost_full; +reg Empty /* synthesis syn_keep=1 */; +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [7:0] Fifo_data_byte0; +reg [7:0] Fifo_data_byte1; +reg [7:0] Fifo_data_byte2; +reg [7:0] Fifo_data_byte3; +reg Fifo_data_en_dl1; +reg [7:0] Fifo_data_dl1; +reg Rx_mac_sop_tmp ; +reg Rx_mac_sop ; +reg Rx_mac_ra ; +reg Rx_mac_pa ; + + + +reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */; +reg [2:0] Next_state_SYS ; +reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */; +reg Packet_number_sub ; +wire Packet_number_add_edge; +reg Packet_number_add_dl1; +reg Packet_number_add_dl2; +reg Packet_number_add ; +reg Packet_number_add_tmp ; +reg Packet_number_add_tmp_dl1; +reg Packet_number_add_tmp_dl2; + +reg Rx_mac_sop_tmp_dl1; +reg [35:0] Dout_dl1; +reg [4:0] Fifo_data_count; +reg Rx_mac_pa_tmp ; +reg Add_wr_jump_tmp ; +reg Add_wr_jump_tmp_pl1 ; +reg Add_wr_jump ; +reg Add_wr_jump_rd_pl1 ; +reg [4:0] Rx_Hwmark_pl ; +reg [4:0] Rx_Lwmark_pl ; +reg Addr_freshed_ptr ; +integer i ; +//****************************************************************************** +//domain Clk_MAC,write data to dprom.a-port for write +//****************************************************************************** +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end) + case (Current_state) + State_idle: + if (Fifo_data_en) + Next_state =State_byte3; + else + Next_state =Current_state; + State_byte3: + if (Fifo_data_en) + Next_state =State_byte2; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be1; + else + Next_state =Current_state; + State_byte2: + if (Fifo_data_en) + Next_state =State_byte1; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be2; + else + Next_state =Current_state; + State_byte1: + if (Fifo_data_en) + Next_state =State_byte0; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be3; + else + Next_state =Current_state; + State_byte0: + if (Fifo_data_en) + Next_state =State_byte3; + else if (Fifo_data_err) + Next_state =State_err_end; + else if (Fifo_data_end) + Next_state =State_be0; + else + Next_state =Current_state; + State_be1: + Next_state =State_idle; + State_be2: + Next_state =State_idle; + State_be3: + Next_state =State_idle; + State_be0: + Next_state =State_idle; + State_err_end: + Next_state =State_idle; + default: + Next_state =State_idle; + endcase + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_reg <=0; + else if (Current_state==State_idle) + Add_wr_reg <=Add_wr; + +// + + +always @ (posedge Reset or posedge Clk_MAC) + if (Reset) + Add_wr_gray <=0; + else + begin + Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +// + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else + begin + Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end +assign Add_wr_pluse=Add_wr+1; +assign Add_wr_pluse4=Add_wr+4; +assign Add_wr_pluse3=Add_wr+3; +assign Add_wr_pluse2=Add_wr+2; + + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Full <=0; + else if (Add_wr_pluse==Add_rd_ungray) + Full <=1; + else + Full <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Almost_full <=0; + else if (Add_wr_pluse4==Add_rd_ungray|| + Add_wr_pluse3==Add_rd_ungray|| + Add_wr_pluse2==Add_rd_ungray|| + Add_wr_pluse==Add_rd_ungray + ) + Almost_full <=1; + else + Almost_full <=0; + +assign Fifo_full =Almost_full; + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr <=0; + else if (Current_state==State_err_end) + Add_wr <=Add_wr_reg; + else if (Wr_en&&!Full) + Add_wr <=Add_wr +1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp <=0; + else if (Current_state==State_err_end) + Add_wr_jump_tmp <=1; + else + Add_wr_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp_pl1 <=0; + else + Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump <=0; + else if (Current_state==State_err_end) + Add_wr_jump <=1; + else if (Add_wr_jump_tmp_pl1) + Add_wr_jump <=0; + +// +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_en_dl1 <=0; + else + Fifo_data_en_dl1 <=Fifo_data_en; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_dl1 <=0; + else + Fifo_data_dl1 <=Fifo_data; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte3 <=0; + else if (Current_state==State_byte3&&Fifo_data_en_dl1) + Fifo_data_byte3 <=Fifo_data_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte2 <=0; + else if (Current_state==State_byte2&&Fifo_data_en_dl1) + Fifo_data_byte2 <=Fifo_data_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte1 <=0; + else if (Current_state==State_byte1&&Fifo_data_en_dl1) + Fifo_data_byte1 <=Fifo_data_dl1; + +always @ (* ) + case (Current_state) + State_be0: + Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + State_be1: + Din_tmp ={4'b1001,Fifo_data_byte3,24'h0}; + State_be2: + Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0}; + State_be3: + Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0}; + default: + Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + endcase + +always @ (*) + if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3|| + (Current_state==State_byte0&&Fifo_data_en)) + Wr_en_tmp =1; + else + Wr_en_tmp =0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Din_tmp_reg <=0; + else if(Wr_en_tmp) + Din_tmp_reg <=Din_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Wr_en_ptr <=0; + else if(Current_state==State_idle) + Wr_en_ptr <=0; + else if(Wr_en_tmp) + Wr_en_ptr <=1; + +//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Wr_en <=0; + Din <=0; + end + else if(RX_APPEND_CRC) + begin + Wr_en <=Wr_en_tmp; + Din <=Din_tmp; + end + else + begin + Wr_en <=Wr_en_tmp&&Wr_en_ptr; + Din <={Din_tmp[35:32],Din_tmp_reg[31:0]}; + end + +//this signal for read side to handle the packet number in fifo +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add_tmp <=0; + else if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3) + Packet_number_add_tmp <=1; + else + Packet_number_add_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Packet_number_add_tmp_dl1 <=0; + Packet_number_add_tmp_dl2 <=0; + end + else + begin + Packet_number_add_tmp_dl1 <=Packet_number_add_tmp; + Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1; + end + +//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram. +//expand to two cycles long almost=16 ns +//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2) + Packet_number_add <=1; + else + Packet_number_add <=0; + + + + + + + + + + + + + + + + + + + + + + + + +//****************************************************************************** +//domain Clk_SYS,read data from dprom.b-port for read +//****************************************************************************** + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + +always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty) + case (Current_state_SYS) + SYS_idle: + if (Rx_mac_rd&&Rx_mac_ra&&!Empty) + Next_state_SYS =SYS_read; + else if(Rx_mac_rd&&Rx_mac_ra&&Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_read: + if (Dout[35]) + Next_state_SYS =SYS_wait_end; + else if (!Rx_mac_rd) + Next_state_SYS =SYS_pause; + else if (Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_pause: + if (Rx_mac_rd) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + FF_emtpy_err: + if (!Empty) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + SYS_wait_end: + if (!Rx_mac_rd) + Next_state_SYS =SYS_idle; + else + Next_state_SYS =Current_state_SYS; + default: + Next_state_SYS =SYS_idle; + endcase + + +//gen Rx_mac_ra +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_add_dl1 <=0; + Packet_number_add_dl2 <=0; + end + else + begin + Packet_number_add_dl1 <=Packet_number_add; + Packet_number_add_dl2 <=Packet_number_add_dl1; + end +assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2; + +always @ (Current_state_SYS or Next_state_SYS) + if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end) + Packet_number_sub =1; + else + Packet_number_sub =0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add_edge&&!Packet_number_sub) + Packet_number_inFF <=Packet_number_inFF + 1; + else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0) + Packet_number_inFF <=Packet_number_inFF - 1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else + Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_Hwmark_pl <=0; + Rx_Lwmark_pl <=0; + end + else + begin + Rx_Hwmark_pl <=Rx_Hwmark; + Rx_Lwmark_pl <=Rx_Lwmark; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_ra <=0; + else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl) + Rx_mac_ra <=0; + else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl) + Rx_mac_ra <=1; + + +//control Add_rd signal; +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr)) + Add_rd <=Add_rd + 1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_pl1 <=0; + else + Add_rd_pl1 <=Add_rd; + +always @ (*) + if (Add_rd_pl1==Add_rd) + Addr_freshed_ptr =0; + else + Addr_freshed_ptr =1; + +// +always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_rd_gray <=0; + else + begin + Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +// + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_jump_rd_pl1 <=0; + else + Add_wr_jump_rd_pl1 <=Add_wr_jump; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else if (!Add_wr_jump_rd_pl1) + begin + Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end +//empty signal gen +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Dout_dl1 <=0; + else + Dout_dl1 <=Dout; + +assign Rx_mac_data =Dout_dl1[31:0]; +assign Rx_mac_BE =Dout_dl1[33:32]; +assign Rx_mac_eop =Dout_dl1[35]; + +//aligned to Addr_rd +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa_tmp <=0; + else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr)) + Rx_mac_pa_tmp <=1; + else + Rx_mac_pa_tmp <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa <=0; + else + Rx_mac_pa <=Rx_mac_pa_tmp; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_sop_tmp <=0; + else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read) + Rx_mac_sop_tmp <=1; + else + Rx_mac_sop_tmp <=0; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_mac_sop_tmp_dl1 <=0; + Rx_mac_sop <=0; + end + else + begin + Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp; + Rx_mac_sop <=Rx_mac_sop_tmp_dl1; + end + + + +//****************************************************************************** + +duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram( +.data_a (Din ), +.wren_a (Wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (Clk_MAC ), +.clock_b (Clk_SYS ), +.q_b (Dout )); + +endmodule + + + + + Index: trunk/FPGA/src/eth/MAC_rx/MAC_rx_add_chk.v =================================================================== --- trunk/FPGA/src/eth/MAC_rx/MAC_rx_add_chk.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_rx/MAC_rx_add_chk.v (revision 2) @@ -0,0 +1,153 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_add_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_add_chk ( +Reset , +Clk , +Init , +data , +MAC_add_en , +MAC_rx_add_chk_err , +//From CPU +MAC_rx_add_chk_en , +MAC_add_prom_data , +MAC_add_prom_add , +MAC_add_prom_wr + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] data ; +input MAC_add_en ; +output MAC_rx_add_chk_err ; + //From CPU +input MAC_rx_add_chk_en ; +input [7:0] MAC_add_prom_data ; +input [2:0] MAC_add_prom_add ; +input MAC_add_prom_wr ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [2:0] addr_rd; +wire[2:0] addr_wr; +wire[7:0] din; +wire[7:0] dout; +wire wr_en; + +reg MAC_rx_add_chk_err; +reg MAC_add_prom_wr_dl1; +reg MAC_add_prom_wr_dl2; +reg [7:0] data_dl1 ; +reg MAC_add_en_dl1 ; +//****************************************************************************** +//write data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + data_dl1 <=0; + MAC_add_en_dl1 <=0; + end + else + begin + data_dl1 <=data; + MAC_add_en_dl1 <=MAC_add_en; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end + +assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; +assign addr_wr =MAC_add_prom_add; +assign din =MAC_add_prom_data; + +//****************************************************************************** +//mac add verify +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + addr_rd <=0; + else if (Init) + addr_rd <=0; + else if (MAC_add_en) + addr_rd <=addr_rd + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_rx_add_chk_err <=0; + else if (Init) + MAC_rx_add_chk_err <=0; + else if (MAC_rx_add_chk_en&&MAC_add_en_dl1&&dout!=data_dl1) + MAC_rx_add_chk_err <=1; + + +//****************************************************************************** +//a port for read ,b port for write . +//****************************************************************************** +duram #(8,3,"M512","DUAL_PORT") U_duram( +.data_a (din ), +.wren_a (wr_en ), +.address_a (addr_wr ), +.address_b (addr_rd ), +.clock_a (Clk ), +.clock_b (Clk ), +.q_b (dout )); + +endmodule Index: trunk/FPGA/src/eth/MAC_rx/Broadcast_filter.v =================================================================== --- trunk/FPGA/src/eth/MAC_rx/Broadcast_filter.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_rx/Broadcast_filter.v (revision 2) @@ -0,0 +1,104 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Broadcast_filter.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module Broadcast_filter ( +Reset , +Clk , +//MAC_rx_ctrl , +broadcast_ptr , +broadcast_drop , +//FromCPU , +broadcast_filter_en , +broadcast_bucket_depth , +broadcast_bucket_interval +); +input Reset ; +input Clk ; + //MAC_rx_ctrl +input broadcast_ptr ; +output broadcast_drop ; + //FromCPU ; +input broadcast_filter_en ; +input [15:0] broadcast_bucket_depth ; +input [15:0] broadcast_bucket_interval ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [15:0] time_counter ; +reg [15:0] broadcast_counter ; +reg broadcast_drop ; +//****************************************************************************** +// +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + time_counter <=0; + else if (time_counter==broadcast_bucket_interval) + time_counter <=0; + else + time_counter <=time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_counter <=0; + else if (time_counter==broadcast_bucket_interval) + broadcast_counter <=0; + else if (broadcast_ptr&&broadcast_counter!=broadcast_bucket_depth) + broadcast_counter <=broadcast_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_drop <=0; + else if(broadcast_filter_en&&broadcast_counter==broadcast_bucket_depth) + broadcast_drop <=1; + else + broadcast_drop <=0; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_tx/flow_ctrl.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx/flow_ctrl.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/flow_ctrl.v (revision 2) @@ -0,0 +1,200 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// flow_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module flow_ctrl +( +Reset , +Clk , +//host processor , +tx_pause_en , +xoff_cpu , +xon_cpu , +//MAC_rx_flow , +pause_quanta , +pause_quanta_val , +//MAC_tx_ctrl , +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete + +); + +input Reset ; +input Clk ; + //host processor ; +input tx_pause_en ; +input xoff_cpu ; +input xon_cpu ; + //MAC_rx_flow ; +input [15:0] pause_quanta ; +input pause_quanta_val ; + //MAC_tx_ctrl ; +output pause_apply ; +input pause_quanta_sub ; +output xoff_gen ; +input xoff_gen_complete ; +output xon_gen ; +input xon_gen_complete ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg xoff_cpu_dl1 ; +reg xoff_cpu_dl2 ; +reg xon_cpu_dl1 ; +reg xon_cpu_dl2 ; +reg [15:0] pause_quanta_dl1 ; +reg pause_quanta_val_dl1 ; +reg pause_quanta_val_dl2 ; +reg pause_apply ; +reg xoff_gen ; +reg xon_gen ; +reg [15:0] pause_quanta_counter ; +reg tx_pause_en_dl1 ; +reg tx_pause_en_dl2 ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + xoff_cpu_dl1 <=0; + xoff_cpu_dl2 <=0; + end + else + begin + xoff_cpu_dl1 <=xoff_cpu; + xoff_cpu_dl2 <=xoff_cpu_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + xon_cpu_dl1 <=0; + xon_cpu_dl2 <=0; + end + else + begin + xon_cpu_dl1 <=xon_cpu; + xon_cpu_dl2 <=xon_cpu_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_dl1 <=0; + end + else + begin + pause_quanta_dl1 <=pause_quanta; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_val_dl1 <=0; + pause_quanta_val_dl2 <=0; + end + else + begin + pause_quanta_val_dl1 <=pause_quanta_val; + pause_quanta_val_dl2 <=pause_quanta_val_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + tx_pause_en_dl1 <=0; + tx_pause_en_dl2 <=0; + end + else + begin + tx_pause_en_dl1 <=tx_pause_en; + tx_pause_en_dl2 <=tx_pause_en_dl1; + end + +//****************************************************************************** +//gen output signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen <=0; + else if (xoff_gen_complete) + xoff_gen <=0; + else if (xoff_cpu_dl1&&!xoff_cpu_dl2) + xoff_gen <=1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen <=0; + else if (xon_gen_complete) + xon_gen <=0; + else if (xon_cpu_dl1&&!xon_cpu_dl2) + xon_gen <=1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_counter <=0; + else if(pause_quanta_val_dl1&&!pause_quanta_val_dl2) + pause_quanta_counter <=pause_quanta_dl1; + else if(pause_quanta_sub&&pause_quanta_counter!=0) + pause_quanta_counter <=pause_quanta_counter-1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_apply <=0; + else if(pause_quanta_counter==0) + pause_apply <=0; + else if (tx_pause_en_dl2) + pause_apply <=1; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_tx/MAC_tx_addr_add.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx/MAC_tx_addr_add.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/MAC_tx_addr_add.v (revision 2) @@ -0,0 +1,125 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_addr_add.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:18 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_addr_add ( +Reset , +Clk , +MAC_tx_addr_init , +MAC_tx_addr_rd , +MAC_tx_addr_data , +//CPU , +MAC_add_prom_data , +MAC_add_prom_add , +MAC_add_prom_wr +); + +input Reset ; +input Clk ; +input MAC_tx_addr_rd ; +input MAC_tx_addr_init ; +output [7:0] MAC_tx_addr_data ; + //CPU ; +input [7:0] MAC_add_prom_data ; +input [2:0] MAC_add_prom_add ; +input MAC_add_prom_wr ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [2:0] add_rd; +wire[2:0] add_wr; +wire[7:0] din; +wire[7:0] dout; +wire wr_en; +reg MAC_add_prom_wr_dl1; +reg MAC_add_prom_wr_dl2; +//****************************************************************************** +//write data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end +assign # 2 wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; +assign # 2 add_wr =MAC_add_prom_add; +assign # 2 din =MAC_add_prom_data; + +//****************************************************************************** +//read data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + add_rd <=0; + else if (MAC_tx_addr_init) + add_rd <=0; + else if (MAC_tx_addr_rd) + add_rd <=add_rd + 1; +assign MAC_tx_addr_data=dout; +//****************************************************************************** +//b port for read ,a port for write . +//****************************************************************************** +duram #(8,3,"M512","DUAL_PORT") U_duram( +.data_a (din ), +.wren_a (wr_en ), +.address_a (add_wr ), +.address_b (add_rd ), +.clock_a (Clk ), +.clock_b (Clk ), +.q_b (dout )); + + +endmodule + Index: trunk/FPGA/src/eth/MAC_tx/MAC_tx_Ctrl.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx/MAC_tx_Ctrl.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/MAC_tx_Ctrl.v (revision 2) @@ -0,0 +1,649 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:38 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_ctrl ( +Reset , +Clk , +//CRC_gen Interface +CRC_init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out , +//Ramdon_gen interfac +Random_init , +RetryCnt , +Random_time_meet , +//flow control +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete , +//MAC_tx_FF +Fifo_data , +Fifo_rd , +Fifo_eop , +Fifo_da , +Fifo_rd_finish , +Fifo_rd_retry , +Fifo_ra , +Fifo_data_err_empty , +Fifo_data_err_full , +//RMII +TxD , +TxEn , +CRS , +//MAC_tx_addr_add +MAC_tx_addr_rd , +MAC_tx_addr_data , +MAC_tx_addr_init , +//RMON +Tx_pkt_type_rmon , +Tx_pkt_length_rmon , +Tx_apply_rmon , +Tx_pkt_err_type_rmon, +//CPU +pause_frame_send_en , +pause_quanta_set , +MAC_tx_add_en , +FullDuplex , +MaxRetry , +IFGset +); + +input Reset ; +input Clk ; + //CRC_gen Interface +output CRC_init ; +output [7:0] Frame_data ; +output Data_en ; +output CRC_rd ; +input CRC_end ; +input [7:0] CRC_out ; + //Ramdon_gen interface +output Random_init ; +output [3:0] RetryCnt ; +input Random_time_meet ;//levle hight indicate random time passed away + //flow control +input pause_apply ; +output pause_quanta_sub ; +input xoff_gen ; +output xoff_gen_complete ; +input xon_gen ; +output xon_gen_complete ; + //MAC_rx_FF +input [7:0] Fifo_data ; +output Fifo_rd ; +input Fifo_eop ; +input Fifo_da ; +output Fifo_rd_finish ; +output Fifo_rd_retry ; +input Fifo_ra ; +input Fifo_data_err_empty ; +input Fifo_data_err_full ; + //RMII +output [7:0] TxD ; +output TxEn ; +input CRS ; + //MAC_tx_addr_add +output MAC_tx_addr_init ; +output MAC_tx_addr_rd ; +input [7:0] MAC_tx_addr_data ; + //RMON +output [2:0] Tx_pkt_type_rmon ; +output [15:0] Tx_pkt_length_rmon ; +output Tx_apply_rmon ; +output [2:0] Tx_pkt_err_type_rmon; + //CPU +input pause_frame_send_en ; +input [15:0] pause_quanta_set ; +input MAC_tx_add_en ; +input FullDuplex ; +input [3:0] MaxRetry ; +input [5:0] IFGset ; +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =5'd00; +parameter StatePreamble =5'd01; +parameter StateSFD =5'd02; +parameter StateData =5'd03; +parameter StatePause =5'd04; +parameter StatePAD =5'd05; +parameter StateFCS =5'd06; +parameter StateIFG =5'd07; +parameter StateJam =5'd08; +parameter StateBackOff =5'd09; +parameter StateJamDrop =5'd10; +parameter StateFFEmptyDrop =5'd11; +parameter StateSwitchNext =5'd12; +parameter StateDefer =5'd13; +parameter StateSendPauseFrame =5'd14; +parameter StateIdle2 =5'd15; +parameter StateIdle3 =5'd16; + +reg [4:0] Current_state /*synthesis syn_keep=1 */; +reg [4:0] Next_state; +reg [5:0] IFG_counter; +reg [4:0] Preamble_counter;// +reg [7:0] TxD_tmp ; +reg TxEn_tmp ; +reg [15:0] Tx_pkt_length_rmon ; +reg Tx_apply_rmon ; +reg Tx_apply_rmon_tmp ; +reg Tx_apply_rmon_tmp_pl1; +reg [2:0] Tx_pkt_err_type_rmon; +reg [3:0] RetryCnt ; +reg Random_init ; +reg Fifo_rd_finish ; +reg Fifo_rd_retry ; +reg [7:0] TxD ; +reg TxEn ; +reg CRC_init ; +reg Data_en ; +reg CRC_rd ; +reg Fifo_rd ; +reg MAC_tx_addr_rd ; +reg MAC_header_slot ; +reg MAC_header_slot_tmp ; +reg [2:0] Tx_pkt_type_rmon ; +wire Collision ; +reg MAC_tx_addr_init ; +reg Src_MAC_ptr ; +reg [7:0] IPLengthCounter ;//for pad append +reg [1:0] PADCounter ; +reg [7:0] JamCounter ; +reg PktDrpEvenPtr ; +reg [7:0] pause_counter ; +reg pause_quanta_sub ; +reg pause_frame_send_en_dl1 ; +reg [15:0] pause_quanta_set_dl1 ; +reg xoff_gen_complete ; +reg xon_gen_complete ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + begin + pause_frame_send_en_dl1 <=0; + pause_quanta_set_dl1 <=0; + end + else + begin + pause_frame_send_en_dl1 <=pause_frame_send_en ; + pause_quanta_set_dl1 <=pause_quanta_set ; + end +//****************************************************************************** +//state machine +//****************************************************************************** +assign Collision=TxEn&CRS; + +always @(posedge Clk or posedge Reset) + if (Reset) + pause_counter <=0; + else if (Current_state!=StatePause) + pause_counter <=0; + else + pause_counter <=pause_counter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + IPLengthCounter <=0; + else if (Current_state==StateDefer) + IPLengthCounter <=0; + else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)) + IPLengthCounter <=IPLengthCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + PADCounter <=0; + else if (Current_state!=StatePAD) + PADCounter <=0; + else + PADCounter <=PADCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + Current_state <=StateDefer; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + StateDefer: + if ((FullDuplex)||(!FullDuplex&&!CRS)) + Next_state=StateIFG; + else + Next_state=Current_state; + StateIFG: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time + Next_state=StateIdle; + else + Next_state=Current_state; + StateIdle: + Next_state=StateIdle2; + StateIdle2: + Next_state=StateIdle3; + StateIdle3: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if (pause_apply) + Next_state=StatePause; + else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))) + Next_state=StatePreamble; + else + Next_state=Current_state; + StatePause: + if (pause_counter==512/8) + Next_state=StateDefer; + else + Next_state=Current_state; + StatePreamble: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6)) + Next_state=StateSFD; + else + Next_state=Current_state; + StateSFD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) + Next_state=StateSendPauseFrame; + else + Next_state=StateData; + StateSendPauseFrame: + if (IPLengthCounter==17) + Next_state=StatePAD; + else + Next_state=Current_state; + StateData: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (Fifo_data_err_empty) + Next_state=StateFFEmptyDrop; + else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0 + Next_state=StateFCS; + else if (Fifo_eop) + Next_state=StatePAD; + else + Next_state=StateData; + StatePAD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (IPLengthCounter>=59) + Next_state=StateFCS; + else + Next_state=Current_state; + StateJam: + if (RetryCnt<=MaxRetry&&JamCounter==16) + Next_state=StateBackOff; + else if (RetryCnt>MaxRetry) + Next_state=StateJamDrop; + else + Next_state=Current_state; + StateBackOff: + if (Random_time_meet) + Next_state =StateDefer; + else + Next_state =Current_state; + StateFCS: + if (!FullDuplex&&Collision) + Next_state =StateJam; + else if (CRC_end) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateFFEmptyDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateJamDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateSwitchNext: + Next_state =StateDefer; + default: + Next_state =StateDefer; + endcase + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + JamCounter <=0; + else if (Current_state!=StateJam) + JamCounter <=0; + else if (Current_state==StateJam) + JamCounter <=JamCounter+1; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + RetryCnt <=0; + else if (Current_state==StateSwitchNext) + RetryCnt <=0; + else if (Current_state==StateJam&&Next_state==StateBackOff) + RetryCnt <=RetryCnt + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + IFG_counter <=0; + else if (Current_state!=StateIFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Preamble_counter <=0; + else if (Current_state!=StatePreamble) + Preamble_counter <=0; + else + Preamble_counter <=Preamble_counter+ 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + PktDrpEvenPtr <=0; + else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop) + PktDrpEvenPtr <=~PktDrpEvenPtr; +//****************************************************************************** +//generate output signals +//****************************************************************************** +//CRC related +always @(Current_state) + if (Current_state==StateSFD) + CRC_init =1; + else + CRC_init =0; + +assign Frame_data=TxD_tmp; + +always @(Current_state) + if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD) + Data_en =1; + else + Data_en =0; + +always @(Current_state) + if (Current_state==StateFCS) + CRC_rd =1; + else + CRC_rd =0; + +//Ramdon_gen interface +always @(Current_state or Next_state) + if (Current_state==StateJam&&Next_state==StateBackOff) + Random_init =1; + else + Random_init =0; + +//MAC_rx_FF +//data have one cycle delay after fifo read signals +always @ (*) + if (Current_state==StateData || + Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) || + Current_state==StateJamDrop&&PktDrpEvenPtr|| + Current_state==StateFFEmptyDrop&&PktDrpEvenPtr ) + Fifo_rd =1; + else + Fifo_rd =0; + +always @ (Current_state) + if (Current_state==StateSwitchNext) + Fifo_rd_finish =1; + else + Fifo_rd_finish =0; + +always @ (Current_state) + if (Current_state==StateJam) + Fifo_rd_retry =1; + else + Fifo_rd_retry =0; +//RMII +always @(Current_state) + if (Current_state==StatePreamble||Current_state==StateSFD|| + Current_state==StateData||Current_state==StateSendPauseFrame|| + Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam) + TxEn_tmp =1; + else + TxEn_tmp =0; + +//gen txd data +always @(*) + case (Current_state) + StatePreamble: + TxD_tmp =8'h55; + StateSFD: + TxD_tmp =8'hd5; + StateData: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + TxD_tmp =Fifo_data; + StateSendPauseFrame: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + case (IPLengthCounter) + 7'd0: TxD_tmp =8'h01; + 7'd1: TxD_tmp =8'h80; + 7'd2: TxD_tmp =8'hc2; + 7'd3: TxD_tmp =8'h00; + 7'd4: TxD_tmp =8'h00; + 7'd5: TxD_tmp =8'h01; + 7'd12: TxD_tmp =8'h88;//type + 7'd13: TxD_tmp =8'h08;// + 7'd14: TxD_tmp =8'h00;//opcode + 7'd15: TxD_tmp =8'h01; + 7'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8]; + 7'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0]; +// 7'd60: TxD_tmp =8'h26; +// 7'd61: TxD_tmp =8'h6b; +// 7'd62: TxD_tmp =8'hae; +// 7'd63: TxD_tmp =8'h0a; + default:TxD_tmp =0; + endcase + + StatePAD: + TxD_tmp =8'h00; + StateJam: + TxD_tmp =8'h01; //jam sequence + StateFCS: + TxD_tmp =CRC_out; + default: + TxD_tmp =2'b0; + endcase +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + TxD <=0; + TxEn <=0; + end + else + begin + TxD <=TxD_tmp; + TxEn <=TxEn_tmp; + end +//RMON + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateSFD) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS) + Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon_tmp <=1; + else + Tx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp_pl1 <=0; + else + Tx_apply_rmon_tmp_pl1 <=Tx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon <=1; + else if (Tx_apply_rmon_tmp_pl1) + Tx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_err_type_rmon <=0; + else if(Fifo_eop&&Current_state==StateJamDrop) + Tx_pkt_err_type_rmon <=3'b001;// + else if(Fifo_eop&&Current_state==StateFFEmptyDrop) + Tx_pkt_err_type_rmon <=3'b010;//underflow + else if(Fifo_eop&&Fifo_data_err_full) + Tx_pkt_err_type_rmon <=3'b011;//overflow + else if(CRC_end) + Tx_pkt_err_type_rmon <=3'b100;//normal + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot_tmp <=0; + else if(Current_state==StateSFD&&Next_state==StateData) + MAC_header_slot_tmp <=1; + else + MAC_header_slot_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot <=0; + else + MAC_header_slot <=MAC_header_slot_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_type_rmon <=0; + else if (Current_state==StateSendPauseFrame) + Tx_pkt_type_rmon <=3'b100; + else if(MAC_header_slot) + Tx_pkt_type_rmon <={1'b0,TxD[7:6]}; + + +always @(Tx_pkt_length_rmon) + if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11) + Src_MAC_ptr =1; + else + Src_MAC_ptr =0; + +//MAC_tx_addr_add +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_tx_addr_rd <=0; + else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame)) + MAC_tx_addr_rd <=1; + else + MAC_tx_addr_rd <=0; + +always @ (Tx_pkt_length_rmon or Fifo_rd) + if ((Tx_pkt_length_rmon==3)&&Fifo_rd) + MAC_tx_addr_init=1; + else + MAC_tx_addr_init=0; + +//flow control +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_sub <=0; + else if(pause_counter==512/8) + pause_quanta_sub <=1; + else + pause_quanta_sub <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen_complete <=0; + else if(Current_state==StateDefer&&xoff_gen) + xoff_gen_complete <=1; + else + xoff_gen_complete <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen_complete <=0; + else if(Current_state==StateDefer&&xon_gen) + xon_gen_complete <=1; + else + xon_gen_complete <=0; + +endmodule Index: trunk/FPGA/src/eth/MAC_tx/CRC_gen.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx/CRC_gen.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/CRC_gen.v (revision 2) @@ -0,0 +1,165 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_gen ( +Reset , +Clk , +Init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] Frame_data ; +input Data_en ; +input CRC_rd ; +output [7:0] CRC_out ; +output CRC_end ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] CRC_out ; +reg [31:0] CRC_reg; +reg CRC_end; +reg [3:0] Counter; +//****************************************************************************** +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction +//****************************************************************************** + +always @ (posedge Clk or posedge Reset) + if (Reset) + CRC_reg <=32'hffffffff; + else if (Init) + CRC_reg <=32'hffffffff; + else if (Data_en) + CRC_reg <=NextCRC(Frame_data,CRC_reg); + else if (CRC_rd) + CRC_reg <={CRC_reg[23:0],8'hff}; + +always @ (CRC_rd or CRC_reg) + if (CRC_rd) + CRC_out <=~{ + CRC_reg[24], + CRC_reg[25], + CRC_reg[26], + CRC_reg[27], + CRC_reg[28], + CRC_reg[29], + CRC_reg[30], + CRC_reg[31] + }; + else + CRC_out <=0; + +//caculate CRC out length ,4 cycles +//CRC_end aligned to last CRC checksum data +always @(posedge Clk or posedge Reset) + if (Reset) + Counter <=0; + else if (!CRC_rd) + Counter <=0; + else + Counter <=Counter + 1; + +always @ (Counter) + if (Counter==3) + CRC_end=1; + else + CRC_end=0; + +endmodule + + Index: trunk/FPGA/src/eth/MAC_tx/MAC_tx_FF.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx/MAC_tx_FF.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/MAC_tx_FF.v (revision 2) @@ -0,0 +1,791 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2006/05/28 05:09:20 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:18 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:39 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_FF ( +Reset , +Clk_MAC , +Clk_SYS , +//MAC_rx_ctrl interface +Fifo_data , +Fifo_rd , +Fifo_rd_finish , +Fifo_rd_retry , +Fifo_eop , +Fifo_da , +Fifo_ra , +Fifo_data_err_empty , +Fifo_data_err_full , +//user interface +Tx_mac_wa , +Tx_mac_wr , +Tx_mac_data , +Tx_mac_BE , +Tx_mac_sop , +Tx_mac_eop , +//host interface +FullDuplex , +Tx_Hwmark , +Tx_Lwmark + +); +`include "../header.v" +input Reset ; +input Clk_MAC ; +input Clk_SYS ; + //MAC_tx_ctrl +output [7:0] Fifo_data ; +input Fifo_rd ; +input Fifo_rd_finish ; +input Fifo_rd_retry ; +output Fifo_eop ; +output Fifo_da ; +output Fifo_ra ; +output Fifo_data_err_empty ; +output Fifo_data_err_full ; + //user interface +output Tx_mac_wa ; +input Tx_mac_wr ; +input [31:0] Tx_mac_data ; +input [1:0] Tx_mac_BE ;//big endian +input Tx_mac_sop ; +input Tx_mac_eop ; + //host interface +input FullDuplex ; +input [4:0] Tx_Hwmark ; +input [4:0] Tx_Lwmark ; +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter MAC_byte3 =4'd00; +parameter MAC_byte2 =4'd01; +parameter MAC_byte1 =4'd02; +parameter MAC_byte0 =4'd03; +parameter MAC_wait_finish =4'd04; +parameter MAC_retry =4'd08; +parameter MAC_idle =4'd09; +parameter MAC_FFEmpty =4'd10; +parameter MAC_FFEmpty_drop =4'd11; +parameter MAC_pkt_sub =4'd12; +parameter MAC_FF_Err =4'd13; + + +reg [3:0] Current_state_MAC /* synthesis syn_preserve =1 */ ; +reg [3:0] Current_state_MAC_reg /* synthesis syn_preserve =1 */ ; +reg [3:0] Next_state_MAC ; + + +parameter SYS_idle =4'd0; +parameter SYS_WaitSop =4'd1; +parameter SYS_SOP =4'd2; +parameter SYS_MOP =4'd3; +parameter SYS_DROP =4'd4; +parameter SYS_EOP_ok =4'd5; +parameter SYS_FFEmpty =4'd6; +parameter SYS_EOP_err =4'd7; +parameter SYS_SOP_err =4'd8; + +reg [3:0] Current_state_SYS /* synthesis syn_preserve =1 */; +reg [3:0] Next_state_SYS; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1 ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_tmp ; + +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_reg ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1 ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_tmp ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray ; +wire[35:0] Din ; +wire[35:0] Dout ; +reg Wr_en ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse ; +wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse_pluse; +wire[`MAC_RX_FF_DEPTH-1:0] Add_rd_pluse ; +reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_reg_dl1 ; +reg Full /* synthesis syn_keep=1 */; +reg AlmostFull /* synthesis syn_keep=1 */; +reg Empty /* synthesis syn_keep=1 */; + +reg Tx_mac_wa ; +reg Tx_mac_wr_dl1 ; +reg [31:0] Tx_mac_data_dl1 ; +reg [1:0] Tx_mac_BE_dl1 ; +reg Tx_mac_sop_dl1 ; +reg Tx_mac_eop_dl1 ; +reg FF_FullErr ; +wire[1:0] Dout_BE ; +wire Dout_eop ; +wire Dout_err ; +wire[31:0] Dout_data ; +reg [35:0] Dout_reg /* synthesis syn_preserve=1 */; +reg Packet_number_sub_dl1 ; +reg Packet_number_sub_dl2 ; +reg Packet_number_sub_edge /* synthesis syn_preserve=1 */; +reg Packet_number_add /* synthesis syn_preserve=1 */; +reg [4:0] Fifo_data_count /* synthesis syn_keep=1 */; +reg Fifo_ra /* synthesis syn_keep=1 */; +reg [7:0] Fifo_data ; +reg Fifo_da ; +reg Fifo_data_err_empty /* synthesis syn_preserve=1 */; +reg Fifo_eop ; +reg Fifo_rd_dl1 ; +reg Fifo_ra_tmp ; +reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */; +reg [5:0] Packet_number_inFF_reg /* synthesis syn_preserve=1 */; +reg Pkt_sub_apply_tmp ; +reg Pkt_sub_apply ; +reg Add_rd_reg_rdy_tmp ; +reg Add_rd_reg_rdy ; +reg Add_rd_reg_rdy_dl1 ; +reg Add_rd_reg_rdy_dl2 ; +reg [4:0] Tx_Hwmark_pl ; +reg [4:0] Tx_Lwmark_pl ; +reg Add_rd_jump_tmp ; +reg Add_rd_jump_tmp_pl1 ; +reg Add_rd_jump ; +reg Add_rd_jump_wr_pl1 ; + +integer i ; +//****************************************************************************** +//write data to from FF . +//domain Clk_SYS +//****************************************************************************** +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + +always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull + or Tx_mac_eop ) + case (Current_state_SYS) + SYS_idle: + if (Tx_mac_wr&&Tx_mac_sop&&!Full) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =Current_state_SYS ; + SYS_SOP: + Next_state_SYS =SYS_MOP; + SYS_MOP: + if (AlmostFull) + Next_state_SYS =SYS_DROP; + else if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP_err; + else if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_ok; + else + Next_state_SYS =Current_state_SYS ; + SYS_EOP_ok: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_EOP_err: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_SOP_err: + Next_state_SYS =SYS_DROP; + SYS_DROP: //FIFO overflow + if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_err; + else + Next_state_SYS =Current_state_SYS ; + default: + Next_state_SYS =SYS_idle; + endcase + +//delay signals +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_mac_wr_dl1 <=0; + Tx_mac_data_dl1 <=0; + Tx_mac_BE_dl1 <=0; + Tx_mac_sop_dl1 <=0; + Tx_mac_eop_dl1 <=0; + end + else + begin + Tx_mac_wr_dl1 <=Tx_mac_wr ; + Tx_mac_data_dl1 <=Tx_mac_data ; + Tx_mac_BE_dl1 <=Tx_mac_BE ; + Tx_mac_sop_dl1 <=Tx_mac_sop ; + Tx_mac_eop_dl1 <=Tx_mac_eop ; + end + +always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err) + FF_FullErr =1; + else + FF_FullErr =0; + +reg Tx_mac_eop_gen; + +always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok) + Tx_mac_eop_gen =1; + else + Tx_mac_eop_gen =0; + +assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1}; + +always @(Current_state_SYS or Tx_mac_wr_dl1) + if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok|| + Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1) + Wr_en = 1; + else + Wr_en = 0; + + +// + + +always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_wr_gray <=0; + else + begin + Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +// + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_jump_wr_pl1 <=0; + else + Add_rd_jump_wr_pl1 <=Add_rd_jump; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else if (!Add_rd_jump_wr_pl1) + begin + Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end +assign Add_wr_pluse =Add_wr+1; +assign Add_wr_pluse_pluse =Add_wr+4; + +always @ (Add_wr_pluse or Add_rd_ungray) + if (Add_wr_pluse==Add_rd_ungray) + Full =1; + else + Full =0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + AlmostFull <=0; + else if (Add_wr_pluse_pluse==Add_rd_ungray) + AlmostFull <=1; + else + AlmostFull <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr <= 0; + else if (Wr_en&&!Full) + Add_wr <= Add_wr +1; + + +// +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_sub_dl1 <=0; + Packet_number_sub_dl2 <=0; + end + else + begin + Packet_number_sub_dl1 <=Pkt_sub_apply; + Packet_number_sub_dl2 <=Packet_number_sub_dl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_sub_edge <=0; + else if (Packet_number_sub_dl1&!Packet_number_sub_dl2) + Packet_number_sub_edge <=1; + else + Packet_number_sub_edge <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err) + Packet_number_add <=1; + else + Packet_number_add <=0; + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add&&!Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF + 1'b1; + else if (!Packet_number_add&&Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF - 1'b1; + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF_reg <=0; + else + Packet_number_inFF_reg <=Packet_number_inFF; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Add_rd_reg_rdy_dl1 <=0; + Add_rd_reg_rdy_dl2 <=0; + end + else + begin + Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy; + Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_reg_dl1 <=0; + else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2) + Add_rd_reg_dl1 <=Add_rd_reg; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else if (FullDuplex) + Fifo_data_count <=Add_wr[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; + else + Fifo_data_count <=Add_wr[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd_reg_dl1[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; //for half duplex backoff requirement + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_ra_tmp <=0; + else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark) + Fifo_ra_tmp <=1; + else + Fifo_ra_tmp <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_Hwmark_pl <=0; + Tx_Lwmark_pl <=0; + end + else + begin + Tx_Hwmark_pl <=Tx_Hwmark; + Tx_Lwmark_pl <=Tx_Lwmark; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Tx_mac_wa <=0; + else if (Fifo_data_count>=Tx_Hwmark_pl) + Tx_mac_wa <=0; + else if (Fifo_data_count=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end +// + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else + begin + Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1]; + for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end +//empty +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + +//ra +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_ra <=0; + else + Fifo_ra <=Fifo_ra_tmp; + + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply_tmp <=0; + else if (Current_state_MAC==MAC_pkt_sub) + Pkt_sub_apply_tmp <=1; + else + Pkt_sub_apply_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply <=0; + else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp) + Pkt_sub_apply <=1; + else + Pkt_sub_apply <=0; + +//reg Add_rd for collison retry +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg <=0; + else if (Fifo_rd_finish) + Add_rd_reg <=Add_rd; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy_tmp <=0; + else if (Fifo_rd_finish) + Add_rd_reg_rdy_tmp <=1; + else + Add_rd_reg_rdy_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy <=0; + else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp) + Add_rd_reg_rdy <=1; + else + Add_rd_reg_rdy <=0; + +reg Add_rd_add /* synthesis syn_keep=1 */; + +always @ (Current_state_MAC or Next_state_MAC) + if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3) + Add_rd_add =1; + else + Add_rd_add =0; + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd <= Add_rd_reg; + else if (Add_rd_add) + Add_rd <= Add_rd + 1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump_tmp <=1; + else + Add_rd_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp_pl1 <=0; + else + Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump <=1; + else if (Add_rd_jump_tmp_pl1) + Add_rd_jump <=0; + +//gen Fifo_data + + +always @ (Dout_data or Current_state_MAC) + case (Current_state_MAC) + MAC_byte3: + Fifo_data =Dout_data[31:24]; + MAC_byte2: + Fifo_data =Dout_data[23:16]; + MAC_byte1: + Fifo_data =Dout_data[15:8]; + MAC_byte0: + Fifo_data =Dout_data[7:0]; + default: + Fifo_data =0; + endcase +//gen Fifo_da +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_rd_dl1 <=0; + else + Fifo_rd_dl1 <=Fifo_rd; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_da <=0; + else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1|| + Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop) + Fifo_da <=1; + else + Fifo_da <=0; + +//gen Fifo_data_err_empty +assign Fifo_data_err_full=Dout_err; +//gen Fifo_data_err_empty +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state_MAC_reg <=0; + else + Current_state_MAC_reg <=Current_state_MAC; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_err_empty <=0; + else if (Current_state_MAC_reg==MAC_FFEmpty) + Fifo_data_err_empty <=1; + else + Fifo_data_err_empty <=0; + +//always @ (posedge Clk_MAC) +// if (Current_state_MAC_reg==MAC_FF_Err) +// begin + //$finish(2); + //$display("mac_tx_FF meet error status at time :%t",$time); +// end + +//gen Fifo_eop aligned to last valid data byte +always @ (Current_state_MAC or Dout_eop) + if (((Current_state_MAC==MAC_byte0&&Dout_BE==2'b00|| + Current_state_MAC==MAC_byte1&&Dout_BE==2'b11|| + Current_state_MAC==MAC_byte2&&Dout_BE==2'b10|| + Current_state_MAC==MAC_byte3&&Dout_BE==2'b01)&&Dout_eop)) + Fifo_eop =1; + else + Fifo_eop =0; +//****************************************************************************** +//****************************************************************************** + +duram #(36,`MAC_TX_FF_DEPTH,"M4K") U_duram( +.data_a (Din ), +.wren_a (Wr_en ), +.address_a (Add_wr ), +.address_b (Add_rd ), +.clock_a (Clk_SYS ), +.clock_b (Clk_MAC ), +.q_b (Dout )); + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/MAC_tx/MAC_tx_Ctrl.patch =================================================================== --- trunk/FPGA/src/eth/MAC_tx/MAC_tx_Ctrl.patch (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/MAC_tx_Ctrl.patch (revision 2) @@ -0,0 +1,23 @@ +*** /tmp/MAC_tx_Ctrl.v 2006-06-25 06:59:00.000000000 +0200 +--- MAC_tx_Ctrl.v 2011-10-09 11:43:32.544538167 +0200 +*************** +*** 174,179 **** +--- 174,180 ---- + parameter StateSwitchNext =4'd12; + parameter StateDefer =4'd13; + parameter StateSendPauseFrame =4'd14; ++ parameter StateIdle2 =4'd15; + + reg [3:0] Current_state /*synthesis syn_keep=1 */; + reg [3:0] Next_state; +*************** +*** 277,282 **** +--- 278,285 ---- + else + Next_state=Current_state; + StateIdle: ++ Next_state=StateIdle2; ++ StateIdle2: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if (pause_apply) Index: trunk/FPGA/src/eth/MAC_tx/Ramdon_gen.v =================================================================== --- trunk/FPGA/src/eth/MAC_tx/Ramdon_gen.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_tx/Ramdon_gen.v (revision 2) @@ -0,0 +1,120 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Ramdon_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module Ramdon_gen( +Reset , +Clk , +Init , +RetryCnt , +Random_time_meet +); +input Reset ; +input Clk ; +input Init ; +input [3:0] RetryCnt ; +output Random_time_meet; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [9:0] Random_sequence ; +reg [9:0] Ramdom ; +reg [9:0] Ramdom_counter ; +reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time +reg Random_time_meet; + +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_sequence <=0; + else + Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])}; + +always @ (RetryCnt or Random_sequence) + case (RetryCnt) + 4'h0 : Ramdom={9'b0,Random_sequence[0]}; + 4'h1 : Ramdom={8'b0,Random_sequence[1:0]}; + 4'h2 : Ramdom={7'b0,Random_sequence[2:0]}; + 4'h3 : Ramdom={6'b0,Random_sequence[3:0]}; + 4'h4 : Ramdom={5'b0,Random_sequence[4:0]}; + 4'h5 : Ramdom={4'b0,Random_sequence[5:0]}; + 4'h6 : Ramdom={3'b0,Random_sequence[6:0]}; + 4'h7 : Ramdom={2'b0,Random_sequence[7:0]}; + 4'h8 : Ramdom={1'b0,Random_sequence[8:0]}; + 4'h9 : Ramdom={ Random_sequence[9:0]}; + default : Ramdom={ Random_sequence[9:0]}; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + Slot_time_counter <=0; + else if(Init) + Slot_time_counter <=0; + else if(!Random_time_meet) + Slot_time_counter <=Slot_time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Ramdom_counter <=0; + else if (Init) + Ramdom_counter <=Ramdom; + else if (Ramdom_counter!=0&&Slot_time_counter==255) + Ramdom_counter <=Ramdom_counter -1 ; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_time_meet <=1; + else if (Init) + Random_time_meet <=0; + else if (Ramdom_counter==0) + Random_time_meet <=1; + +endmodule + + Index: trunk/FPGA/src/eth/RMON/RMON_addr_gen.v =================================================================== --- trunk/FPGA/src/eth/RMON/RMON_addr_gen.v (nonexistent) +++ trunk/FPGA/src/eth/RMON/RMON_addr_gen.v (revision 2) @@ -0,0 +1,292 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_addr_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_addr_gen( +Clk , +Reset , +//RMON +Pkt_type_rmon , +Pkt_length_rmon , +Apply_rmon ,//pluse signal looks like eop +Pkt_err_type_rmon , +// +Reg_apply , +Reg_addr , +Reg_data , +Reg_next , +//CPU +Reg_drop_apply +); +input Clk ; +input Reset ; + //RMON +input [2:0] Pkt_type_rmon ; +input [15:0] Pkt_length_rmon ; +input Apply_rmon ;//pluse signal looks like eop +input [2:0] Pkt_err_type_rmon ; + //RMON_ctrl +output Reg_apply ; +output [4:0] Reg_addr ; +output [15:0] Reg_data ; +input Reg_next ; + //CPU +output Reg_drop_apply ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd0; +parameter StatePktLength =4'd1; +parameter StatePktNumber =4'd2; +parameter StatePktType =4'd3; +parameter StatePktRange =4'd4; + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; + +reg [2:0] PktTypeReg ; +reg [15:0] PktLengthReg ; +reg [2:0] PktErrTypeReg ; + +reg Reg_apply ; +reg [4:0] Reg_addr ; +reg [15:0] Reg_data ; +reg Reg_drop_apply ; +//****************************************************************************** +//register boundery signals + +//****************************************************************************** +reg Apply_rmon_dl1; +reg Apply_rmon_dl2; +reg Apply_rmon_pulse; +reg [2:0] Pkt_type_rmon_dl1 ; +reg [15:0] Pkt_length_rmon_dl1 ; +reg [2:0] Pkt_err_type_rmon_dl1 ; + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Pkt_type_rmon_dl1 <=0; + Pkt_length_rmon_dl1 <=0; + Pkt_err_type_rmon_dl1 <=0; + end + else + begin + Pkt_type_rmon_dl1 <=Pkt_type_rmon ; + Pkt_length_rmon_dl1 <=Pkt_length_rmon ; + Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ; + end + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Apply_rmon_dl1 <=0; + Apply_rmon_dl2 <=0; + end + else + begin + Apply_rmon_dl1 <=Apply_rmon; + Apply_rmon_dl2 <=Apply_rmon_dl1; + end + +always @(Apply_rmon_dl1 or Apply_rmon_dl2) + if (Apply_rmon_dl1&!Apply_rmon_dl2) + Apply_rmon_pulse =1; + else + Apply_rmon_pulse =0; + + + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + PktTypeReg <=0; + PktLengthReg <=0; + PktErrTypeReg <=0; + end + else if (Apply_rmon_pulse&&CurrentState==StateIdle) + begin + PktTypeReg <=Pkt_type_rmon_dl1 ; + PktLengthReg <=Pkt_length_rmon_dl1 ; + PktErrTypeReg <=Pkt_err_type_rmon_dl1 ; + end + + +//****************************************************************************** +//State Machine +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateIdle; + else + CurrentState <=NextState; + +always @(CurrentState or Apply_rmon_pulse or Reg_next) + case (CurrentState) + StateIdle: + if (Apply_rmon_pulse) + NextState =StatePktLength; + else + NextState =StateIdle; + StatePktLength: + if (Reg_next) + NextState =StatePktNumber; + else + NextState =CurrentState; + StatePktNumber: + if (Reg_next) + NextState =StatePktType; + else + NextState =CurrentState; + StatePktType: + if (Reg_next) + NextState =StatePktRange; + else + NextState =CurrentState; + StatePktRange: + if (Reg_next) + NextState =StateIdle; + else + NextState =CurrentState; + default: + NextState =StateIdle; + endcase + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Reg_apply +always @ (CurrentState) + if (CurrentState==StatePktLength||CurrentState==StatePktNumber|| + CurrentState==StatePktType||CurrentState==StatePktRange) + Reg_apply =1; + else + Reg_apply =0; + +//Reg_addr +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_addr <=0; + else case (CurrentState) + StatePktLength: + Reg_addr <=5'd00; + StatePktNumber: + Reg_addr <=5'd01; + StatePktType: + case(PktTypeReg) + 3'b011: + Reg_addr <=5'd02; //broadcast + 3'b001: + Reg_addr <=5'd03; //multicast + 3'b100: + Reg_addr <=5'd16; //pause frame + default: + Reg_addr <=5'd04; //unicast + endcase + StatePktRange: + case(PktErrTypeReg) + 3'b001: + Reg_addr <=5'd05; + 3'b010: + Reg_addr <=5'd06; + 3'b011: + Reg_addr <=5'd07; + 3'b100: + if (PktLengthReg<64) + Reg_addr <=5'd08; + else if (PktLengthReg==64) + Reg_addr <=5'd09; + else if (PktLengthReg<128) + Reg_addr <=5'd10; + else if (PktLengthReg<256) + Reg_addr <=5'd11; + else if (PktLengthReg<512) + Reg_addr <=5'd12; + else if (PktLengthReg<1024) + Reg_addr <=5'd13; + else if (PktLengthReg<1519) + Reg_addr <=5'd14; + else + Reg_addr <=5'd15; + default: + Reg_addr <=5'd05; + endcase + default: + Reg_addr <=5'd05; + endcase + +//Reg_data +always @ (CurrentState or PktLengthReg) + case (CurrentState) + StatePktLength: + Reg_data =PktLengthReg; + StatePktNumber: + Reg_data =1; + StatePktType: + Reg_data =1; + StatePktRange: + Reg_data =1; + default: + Reg_data =0; + endcase + +//Reg_drop_apply +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_drop_apply <=0; + else if (CurrentState!=StateIdle&&Apply_rmon_pulse) + Reg_drop_apply <=1; + else + Reg_drop_apply <=0; + + +endmodule + Index: trunk/FPGA/src/eth/RMON/RMON_dpram.v =================================================================== --- trunk/FPGA/src/eth/RMON/RMON_dpram.v (nonexistent) +++ trunk/FPGA/src/eth/RMON/RMON_dpram.v (revision 2) @@ -0,0 +1,46 @@ +module RMON_dpram( +Reset , +Clk , +//port-a for Rmon +Addra, +Dina, +Douta, +Wea, +//port-b for CPU +Addrb, +Doutb +); + +input Reset ; +input Clk ; + //port-a for Rmon +input [5:0] Addra; +input [31:0] Dina; +output [31:0] Douta; +input Wea; + //port-b for CPU +input [5:0] Addrb; +output [31:0] Doutb; +//****************************************************************************** +//internal signals +//****************************************************************************** + +wire Clka; +wire Clkb; +assign Clka=Clk; +assign #2 Clkb=Clk; +//****************************************************************************** + +duram #(32,6,"M4K") U_duram( +.data_a (Dina ), +.data_b (32'b0 ), +.wren_a (Wea ), +.wren_b (1'b0 ), +.address_a (Addra ), +.address_b (Addrb ), +.clock_a (Clka ), +.clock_b (Clkb ), +.q_a (Douta ), +.q_b (Doutb )); + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/RMON/RMON_ctrl.v =================================================================== --- trunk/FPGA/src/eth/RMON/RMON_ctrl.v (nonexistent) +++ trunk/FPGA/src/eth/RMON/RMON_ctrl.v (revision 2) @@ -0,0 +1,287 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_CTRL.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_CTRL ( +Clk , +Reset , +//RMON_CTRL +Reg_apply_0 , +Reg_addr_0 , +Reg_data_0 , +Reg_next_0 , +Reg_apply_1 , +Reg_addr_1 , +Reg_data_1 , +Reg_next_1 , +//dual-port ram +Addra , +Dina , +Douta , +Wea , +//CPU +CPU_rd_addr , +CPU_rd_apply , +CPU_rd_grant , +CPU_rd_dout + +); +input Clk ; +input Reset ; + //RMON_CTRL +input Reg_apply_0 ; +input [4:0] Reg_addr_0 ; +input [15:0] Reg_data_0 ; +output Reg_next_0 ; +input Reg_apply_1 ; +input [4:0] Reg_addr_1 ; +input [15:0] Reg_data_1 ; +output Reg_next_1 ; + //dual-port ram + //port-a for Rmon +output [5:0] Addra ; +output [31:0] Dina ; +input [31:0] Douta ; +output Wea ; + //CPU +input [5:0] CPU_rd_addr ; +input CPU_rd_apply ; +output CPU_rd_grant ; +output [31:0] CPU_rd_dout ; + + + + +//****************************************************************************** +//internal signals +//****************************************************************************** + +parameter StateCPU =4'd00; +parameter StateMAC0 =4'd01; +parameter StateMAC1 =4'd02; + + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; +reg [3:0] CurrentState_reg; + +reg [4:0] StepCounter; +reg [31:0] DoutaReg; +reg [5:0] Addra ; +reg [31:0] Dina; +reg Reg_next_0 ; +reg Reg_next_1 ; +reg Write; +reg Read; +reg Pipeline; +reg [31:0] CPU_rd_dout ; +reg CPU_rd_apply_reg ; +//****************************************************************************** +//State Machine +//****************************************************************************** + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateMAC0; + else + CurrentState <=NextState; + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState_reg <=StateMAC0; + else if(CurrentState!=StateCPU) + CurrentState_reg <=CurrentState; + +always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg + or Reg_apply_1 + or StepCounter + ) + case(CurrentState) + StateMAC0: + if(!Reg_apply_0&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_0) + NextState =StateMAC1; + else + NextState =CurrentState; + StateMAC1: + if(!Reg_apply_1&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_1) + NextState =StateMAC0; + else + NextState =CurrentState; + StateCPU: + if (StepCounter==3) + case (CurrentState_reg) + StateMAC0 :NextState =StateMAC0 ; + StateMAC1 :NextState =StateMAC1 ; + default :NextState =StateMAC0; + endcase + else + NextState =CurrentState; + + default: + NextState =StateMAC0; + endcase + + + +always @(posedge Clk or posedge Reset) + if (Reset) + StepCounter <=0; + else if(NextState!=CurrentState) + StepCounter <=0; + else if (StepCounter!=4'hf) + StepCounter <=StepCounter + 1; + +//****************************************************************************** +//temp signals +//****************************************************************************** +always @(StepCounter) + if( StepCounter==1||StepCounter==4|| + StepCounter==7||StepCounter==10) + Read =1; + else + Read =0; + +always @(StepCounter or CurrentState) + if( StepCounter==2||StepCounter==5|| + StepCounter==8||StepCounter==11) + Pipeline =1; + else + Pipeline =0; + +always @(StepCounter or CurrentState) + if( StepCounter==3||StepCounter==6|| + StepCounter==9||StepCounter==12) + Write =1; + else + Write =0; + +always @(posedge Clk or posedge Reset) + if (Reset) + DoutaReg <=0; + else if (Read) + DoutaReg <=Douta; + + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Addra +always @(*) + case(CurrentState) + StateMAC0 : Addra={1'd0 ,Reg_addr_0 }; + StateMAC1 : Addra={1'd1 ,Reg_addr_1 }; + StateCPU: Addra=CPU_rd_addr; + default: Addra=0; + endcase + +//Dina +always @(posedge Clk or posedge Reset) + if (Reset) + Dina <=0; + else + case(CurrentState) + StateMAC0 : Dina<=Douta+Reg_data_0 ; + StateMAC1 : Dina<=Douta+Reg_data_1 ; + StateCPU: Dina<=0; + default: Dina<=0; + endcase + +assign Wea =Write; +//Reg_next +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC0) + Reg_next_0 =Pipeline; + else + Reg_next_0 =0; + +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC1) + Reg_next_1 =Pipeline; + else + Reg_next_1 =0; + + +//CPU_rd_grant +reg CPU_rd_apply_dl1; +reg CPU_rd_apply_dl2; +//rising edge +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + CPU_rd_apply_dl1 <=0; + CPU_rd_apply_dl2 <=0; + end + else + begin + CPU_rd_apply_dl1 <=CPU_rd_apply; + CPU_rd_apply_dl2 <=CPU_rd_apply_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_apply_reg <=0; + else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2) + CPU_rd_apply_reg <=1; + else if (CurrentState==StateCPU&&Write) + CPU_rd_apply_reg <=0; + +assign CPU_rd_grant =!CPU_rd_apply_reg; + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_dout <=0; + else if (Pipeline&&CurrentState==StateCPU) + CPU_rd_dout <=Douta; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/miim/eth_shiftreg.v =================================================================== --- trunk/FPGA/src/eth/miim/eth_shiftreg.v (nonexistent) +++ trunk/FPGA/src/eth/miim/eth_shiftreg.v (revision 2) @@ -0,0 +1,161 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_shiftreg.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:47 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2002/08/14 18:16:59 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.4 2002/03/02 21:06:01 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + + +module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, + LatchByte, ShiftedBit, Prsd, LinkFail); + + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. +input Mdi; // MII input data +input [4:0] Fiad; // PHY address +input [4:0] Rgad; // Register address (within the selected PHY) +input [15:0]CtrlData; // Control data (data to be written to the PHY) +input WriteOp; // The current operation is a PHY register write operation +input [3:0] ByteSelect; // Byte select +input [1:0] LatchByte; // Byte select for latching (read operation) + +output ShiftedBit; // Bit shifted out of the shift register +output[15:0]Prsd; // Read Status Data (data read from the PHY) +output LinkFail; // Link Integrity Signal + +reg [7:0] ShiftReg; // Shift register for shifting the data in and out +reg [15:0]Prsd; +reg LinkFail; + + + + +// ShiftReg[7:0] :: Shift Register Data +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + ShiftReg[7:0] <= #Tp 8'h0; + Prsd[15:0] <= #Tp 16'h0; + LinkFail <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + if(|ByteSelect) + begin + case (ByteSelect[3:0]) + 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; + 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; + 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; + 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; + default : ShiftReg[7:0] <= #Tp 8'h0; + endcase + end + else + begin + ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(LatchByte[0]) + begin + Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(Rgad == 5'h01) + LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet + end + else + begin + if(LatchByte[1]) + Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; + end + end + end + end +end + + +assign ShiftedBit = ShiftReg[7]; + + +endmodule Index: trunk/FPGA/src/eth/miim/eth_outputcontrol.v =================================================================== --- trunk/FPGA/src/eth/miim/eth_outputcontrol.v (nonexistent) +++ trunk/FPGA/src/eth/miim/eth_outputcontrol.v (revision 2) @@ -0,0 +1,159 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_outputcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.4 2002/07/09 20:11:59 mohor +// Comment removed. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + +module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); + +parameter Tp = 1; + +input Clk; // Host Clock +input Reset; // General Reset +input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +input NoPre; // No Preamble (no 32-bit preamble) +input InProgress; // Operation in progress +input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +input [6:0] BitCounter; // Bit Counter +input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. + +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable + +wire SerialEn; + +reg MdoEn_2d; +reg MdoEn_d; +reg MdoEn; + +reg Mdo_2d; +reg Mdo_d; +reg Mdo; // MII Management Data Output + + + +// Generation of the Serial Enable signal (enables the serialization of the data) +assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) + | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); + + +// Generation of the MdoEn signal +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + MdoEn_2d <= #Tp 1'b0; + MdoEn_d <= #Tp 1'b0; + MdoEn <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32; + MdoEn_d <= #Tp MdoEn_2d; + MdoEn <= #Tp MdoEn_d; + end + end +end + + +// Generation of the Mdo signal. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + Mdo_2d <= #Tp 1'b0; + Mdo_d <= #Tp 1'b0; + Mdo <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + Mdo_2d <= #Tp ~SerialEn & BitCounter<32; + Mdo_d <= #Tp ShiftedBit | Mdo_2d; + Mdo <= #Tp Mdo_d; + end + end +end + + + +endmodule Index: trunk/FPGA/src/eth/miim/eth_clockgen.v =================================================================== --- trunk/FPGA/src/eth/miim/eth_clockgen.v (nonexistent) +++ trunk/FPGA/src/eth/miim/eth_clockgen.v (revision 2) @@ -0,0 +1,140 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clockgen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:55 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + +module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) + +output Mdc; // Output clock +output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. +output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. + +reg Mdc; +reg [7:0] Counter; + +wire CountEq0; +wire [7:0] CounterPreset; +wire [7:0] TempDivider; + + +assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 +assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period + + +// Counter counts half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Counter[7:0] <= #Tp 8'h1; + else + begin + if(CountEq0) + begin + Counter[7:0] <= #Tp CounterPreset[7:0]; + end + else + Counter[7:0] <= #Tp Counter - 8'h1; + end +end + + +// Mdc is asserted every other half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Mdc <= #Tp 1'b0; + else + begin + if(CountEq0) + Mdc <= #Tp ~Mdc; + end +end + + +assign CountEq0 = Counter == 8'h0; +assign MdcEn = CountEq0 & ~Mdc; +assign MdcEn_n = CountEq0 & Mdc; + +endmodule + + Index: trunk/FPGA/src/eth/miim/timescale.v =================================================================== --- trunk/FPGA/src/eth/miim/timescale.v (nonexistent) +++ trunk/FPGA/src/eth/miim/timescale.v (revision 2) @@ -0,0 +1,59 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 11:36:31 mohor +// Log file added. +// +// +// + +`timescale 1ns / 1ns Index: trunk/FPGA/src/eth/header.v =================================================================== --- trunk/FPGA/src/eth/header.v (nonexistent) +++ trunk/FPGA/src/eth/header.v (revision 2) @@ -0,0 +1,5 @@ +// `define MAC_SOURCE_REPLACE_EN 1 +// `define MAC_TARGET_CHECK_EN 1 +// `define MAC_BROADCAST_FILTER_EN 1 + `define MAC_TX_FF_DEPTH 9 + `define MAC_RX_FF_DEPTH 9 Index: trunk/FPGA/src/eth/MAC_rx.v =================================================================== --- trunk/FPGA/src/eth/MAC_rx.v (nonexistent) +++ trunk/FPGA/src/eth/MAC_rx.v (revision 2) @@ -0,0 +1,228 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +module MAC_rx ( +input Reset , +input Clk_user, +input Clk , + //RMII interface +input MCrs_dv , +input [7:0] MRxD , +input MRxErr , + //flow_control signals +output [15:0] pause_quanta , +output pause_quanta_val , + //user interface +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , + //CPU +input MAC_rx_add_chk_en , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , +input broadcast_filter_en , +input [15:0] broadcast_bucket_depth , +input [15:0] broadcast_bucket_interval , +input RX_APPEND_CRC, +input [4:0] Rx_Hwmark , +input [4:0] Rx_Lwmark , +input CRC_chk_en , +input [5:0] RX_IFG_SET , +input [15:0] RX_MAX_LENGTH ,// 1518 +input [6:0] RX_MIN_LENGTH ,// 64 + //RMON interface +output [15:0] Rx_pkt_length_rmon , +output Rx_apply_rmon , +output [2:0] Rx_pkt_err_type_rmon , +output [2:0] Rx_pkt_type_rmon +); +`include "header.v" +//****************************************************************************** +//internal signals +//****************************************************************************** + //CRC_chk interface +wire CRC_en ; +wire CRC_init; +wire CRC_err ; + //MAC_rx_add_chk interface +wire MAC_add_en ; +wire MAC_rx_add_chk_err ; + //broadcast_filter +wire broadcast_ptr ; +wire broadcast_drop ; + //flow_control signals +//wire [15:0] pause_quanta ; +//wire pause_quanta_val ; + //MAC_rx_ctrl interface +wire [7:0] Fifo_data ; +wire Fifo_data_en ; +wire Fifo_full ; +wire Fifo_data_err ; +wire Fifo_data_end ; +//****************************************************************************** +//instantiation +//****************************************************************************** + + +MAC_rx_ctrl U_MAC_rx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //RMII interface ( //RMII interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //CRC_chk interface (//CRC_chk interface ), +.CRC_en (CRC_en ), +.CRC_init (CRC_init ), +.CRC_err (CRC_err ), + //MAC_rx_add_chk interface (//MAC_rx_add_chk interface), +.MAC_add_en (MAC_add_en ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //broadcast_filter (//broadcast_filter ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //MAC_rx_FF interface (//MAC_rx_FF interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_end (Fifo_data_end ), +.Fifo_full (Fifo_full ), + //RMON interface (//RMON interface ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ) +); + +MAC_rx_FF U_MAC_rx_FF ( +.Reset (Reset ), +.Clk_MAC (Clk ), +.Clk_SYS (Clk_user ), + //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_full (Fifo_full ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_end (Fifo_data_end ), + //CPU (//CPU ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.RX_APPEND_CRC (RX_APPEND_CRC ), + //user interface (//user interface ), +.Rx_mac_ra (Rx_mac_ra ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_pa (Rx_mac_pa ), +.Rx_mac_eop (Rx_mac_eop ) +); + +`ifdef MAC_BROADCAST_FILTER_EN +Broadcast_filter U_Broadcast_filter( +.Reset (Reset ), +.Clk (Clk ), + //MAC_rx_ctrl (//MAC_rx_ctrl ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //FromCPU (//FromCPU ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ) +); +`else +assign broadcast_drop=0; +`endif + +CRC_chk U_CRC_chk( +.Reset (Reset ), +.Clk (Clk ), +.CRC_data (Fifo_data ), +.CRC_init (CRC_init ), +.CRC_en (CRC_en ), + //From CPU (//From CPU ), +.CRC_chk_en (CRC_chk_en ), +.CRC_err (CRC_err ) +); + +`ifdef MAC_TARGET_CHECK_EN +MAC_rx_add_chk U_MAC_rx_add_chk( +.Reset (Reset ), +.Clk (Clk ), +.Init (CRC_init ), +.data (Fifo_data ), +.MAC_add_en (MAC_add_en ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //From CPU (//From CPU ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_add_prom_data (MAC_add_prom_data ), +.MAC_add_prom_add (MAC_add_prom_add ), +.MAC_add_prom_wr (MAC_add_prom_wr ) +); +`else +assign MAC_rx_add_chk_err=0; +`endif + + + +endmodule \ No newline at end of file Index: trunk/FPGA/src/eth/Phy_int.v =================================================================== --- trunk/FPGA/src/eth/Phy_int.v (nonexistent) +++ trunk/FPGA/src/eth/Phy_int.v (revision 2) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_int.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:36 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Phy_int ( +Reset , +MAC_rx_clk , +MAC_tx_clk , +//Rx interface , +MCrs_dv , +MRxD , +MRxErr , +//Tx interface , +MTxD , +MTxEn , +MCRS , +//Phy interface , +Tx_er , +Tx_en , +Txd , +Rx_er , +Rx_dv , +Rxd , +Crs , +Col , +//host interface , +Line_loop_en , +Speed + +); +input Reset ; +input MAC_rx_clk ; +input MAC_tx_clk ; + //Rx interface +output MCrs_dv ; +output [7:0] MRxD ; +output MRxErr ; + //Tx interface +input [7:0] MTxD ; +input MTxEn ; +output MCRS ; + //Phy interface +output Tx_er ; +output Tx_en ; +output [7:0] Txd ; +input Rx_er ; +input Rx_dv ; +input [7:0] Rxd ; +input Crs ; +input Col ; + //host interface +input Line_loop_en ; +input [2:0] Speed ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] MTxD_dl1 ; +reg MTxEn_dl1 ; +reg Tx_odd_data_ptr ; +reg Rx_odd_data_ptr ; +reg Tx_en ; +reg [7:0] Txd ; +reg MCrs_dv ; +reg [7:0] MRxD ; +reg Rx_er_dl1 ; +reg Rx_dv_dl1 ; +reg Rx_dv_dl2 ; +reg [7:0] Rxd_dl1 ; +reg [7:0] Rxd_dl2 ; +reg Crs_dl1 ; +reg Col_dl1 ; +//****************************************************************************** +//Tx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + begin + MTxD_dl1 <=0; + MTxEn_dl1 <=0; + end + else + begin + MTxD_dl1 <=MTxD ; + MTxEn_dl1 <=MTxEn ; + end + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_odd_data_ptr <=0; + else if (!MTxD_dl1) + Tx_odd_data_ptr <=0; + else + Tx_odd_data_ptr <=!Tx_odd_data_ptr; + + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Txd <=0; + else if(Speed[2]&&MTxEn_dl1) + Txd <=MTxD_dl1; + else if(MTxEn_dl1&&!Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[3:0]}; + else if(MTxEn_dl1&&Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[7:4]}; + else + Txd <=0; + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_en <=0; + else if(MTxEn_dl1) + Tx_en <=1; + else + Tx_en <=0; + +assign Tx_er=0; + +//****************************************************************************** +//Rx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + begin + Rx_er_dl1 <=0; + Rx_dv_dl1 <=0; + Rx_dv_dl2 <=0 ; + Rxd_dl1 <=0; + Rxd_dl2 <=0; + Crs_dl1 <=0; + Col_dl1 <=0; + end + else + begin + Rx_er_dl1 <=Rx_er ; + Rx_dv_dl1 <=Rx_dv ; + Rx_dv_dl2 <=Rx_dv_dl1 ; + Rxd_dl1 <=Rxd ; + Rxd_dl2 <=Rxd_dl1 ; + Crs_dl1 <=Crs ; + Col_dl1 <=Col ; + end + +assign MRxErr =Rx_er_dl1 ; +assign MCRS =Crs_dl1 ; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MCrs_dv <=0; + else if(Line_loop_en) + MCrs_dv <=Tx_en; + else if(Rx_dv_dl2) + MCrs_dv <=1; + else + MCrs_dv <=0; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + Rx_odd_data_ptr <=0; + else if (!Rx_dv_dl1) + Rx_odd_data_ptr <=0; + else + Rx_odd_data_ptr <=!Rx_odd_data_ptr; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MRxD <=0; + else if(Line_loop_en) + MRxD <=Txd; + else if(Speed[2]&&Rx_dv_dl2) + MRxD <=Rxd_dl2; + else if(Rx_dv_dl1&&Rx_odd_data_ptr) + MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]}; + +endmodule \ No newline at end of file Index: trunk/FPGA/src/ack_fifo/rec_to_pkg.py =================================================================== --- trunk/FPGA/src/ack_fifo/rec_to_pkg.py (nonexistent) +++ trunk/FPGA/src/ack_fifo/rec_to_pkg.py (revision 2) @@ -0,0 +1,124 @@ +#!/usr/bin/python +# The script below is written by Wojciech M. Zabolotny +# wzabise.pw.edu.pl 19.03.2012 +# it is published as PUBLIC DOMAIN +import sys +class field: + last_bit = 0; + def __init__(self,field_desc): + fd = field_desc.split(",") + self.fname = fd[0] + if not fd[1] in ["signed","unsigned","std_logic_vector"]: + raise Exception("Wrong field type") + self.ftype = fd[1] + if len(fd)==3: + self.b1=int(fd[2])-1 + self.b2=0 + elif len(fd)==4: + self.b1=int(fd[2]) + self.b2=int(fd[3]) + else: + raise Exception("Syntax error in line: "+field_desc) + #Assign vector bits + self.v1=field.last_bit + self.v2=field.last_bit+abs(self.b2-self.b1) + field.last_bit = self.v2+1 + +if len(sys.argv) != 2: + print """ +The rec_to_pkg scripts creates VHDL package for conversion +between the VHDL records containing "signed" and "unsigned" +fields and std_logic_vectors. +It should be called as: rec_to_pkg.py description_file +where the description file should have the following syntax: + +#Optional comment line +record record_name +#optional comment lines +#[...] +field_name,signed_or_unsigned,width +#or +field_name,signed_or_unsigned,left_bit_nr,right_bit_nr +end + +The generated package is written to the record_name_pkg.vhd file +""" + exit(0) +fin=open(sys.argv[1]) +#Read the full description of the type +type_desc=[l.strip() for l in fin.readlines() if len(l) > 0 and l[0] != "#" ] +#The first line should contain the record name +l=type_desc[0].split(" ") +if l[0] != "record": + raise Exception("Syntax error! The first line should have form \"record name_of_type\"") +type_name=l[1] +pkg_name=type_name+"_pkg" +#Prepare for analysis of fields +msb=0 +fields=[] +end_found = False +#Find the field definitions +for l in type_desc[1:]: + if l=="end": + end_found=True + break + fields.append(field(l)) +if not end_found: + raise Exception("Syntax error: no \"end\" found") +#If we got here, probably the syntax was correct +#Lets generate the package +p="""\ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +""" +p+="package "+pkg_name+" is\n\n" +p+="type "+type_name+" is record\n" +for f in fields: + s=" "+f.fname+" : "+f.ftype+"(" + if f.b1 > f.b2: + s=s+str(f.b1)+" downto "+str(f.b2)+");\n" + else: + s=s+str(f.b1)+" to "+str(f.b2)+");\n" + p+=s +p+="end record;\n\n" +#Write width of our type +p+="constant "+type_name+"_width : integer := "+str(field.last_bit)+";\n\n" +#Write headers of conversion functions +p+="function "+type_name+"_to_stlv(\n" +p+=" constant din : "+type_name+")\n" +p+=" return std_logic_vector;\n\n" +p+="function stlv_to_"+type_name+"(\n" +p+=" constant din : std_logic_vector)\n" +p+=" return "+type_name+";\n\n" +p+="end "+pkg_name+";\n\n" +#Now the body of the package - the conversion functions +p+="package body "+pkg_name+" is\n\n" +# +p+="function "+type_name+"_to_stlv(\n" +p+=" constant din : "+type_name+")\n" +p+=" return std_logic_vector is\n" +p+=" variable res : std_logic_vector("+str(field.last_bit-1)+" downto 0);\n" +p+="begin\n" +for f in fields: + p+=" res("+str(f.v2)+" downto "+str(f.v1)+ ") := std_logic_vector(din."+f.fname+");\n" +p+=" return res;\n" +p+="end "+type_name+"_to_stlv;\n\n" +# +p+="function stlv_to_"+type_name+"(\n" +p+=" constant din : std_logic_vector)\n" +p+=" return "+type_name+" is\n" +p+=" variable res : "+type_name+";\n" +p+="begin\n" +for f in fields: + p+=" res."+f.fname+":="+f.ftype+"(din("+str(f.v2)+" downto "+str(f.v1)+"));\n" +p+=" return res;\n" +p+="end stlv_to_"+type_name+";\n\n" +p+="end "+pkg_name+";\n" + +#The output file name +fout_name=type_name+"_pkg.vhd" +fout=open(fout_name,"w") +fout.write(p) +fout.close() +
trunk/FPGA/src/ack_fifo/rec_to_pkg.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/FPGA/src/ack_fifo/ack.rec =================================================================== --- trunk/FPGA/src/ack_fifo/ack.rec (nonexistent) +++ trunk/FPGA/src/ack_fifo/ack.rec (revision 2) @@ -0,0 +1,12 @@ +# This is a test record - packet acknowledgment +record pkt_ack +# Below are fields definitions +# First two pointers fo linked list +# pkt - number of the packet +pkt,unsigned,8 +# set - number of the set +set,unsigned,16 +# cmd - command - 1 for ACK +cmd,unsigned,8 +end + Index: trunk/FPGA/src/ack_fifo/pkt_ack_pkg.vhd =================================================================== --- trunk/FPGA/src/ack_fifo/pkt_ack_pkg.vhd (nonexistent) +++ trunk/FPGA/src/ack_fifo/pkt_ack_pkg.vhd (revision 2) @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +package pkt_ack_pkg is + +type pkt_ack is record + pkt : unsigned(7 downto 0); + set : unsigned(15 downto 0); + cmd : unsigned(7 downto 0); +end record; + +constant pkt_ack_width : integer := 32; + +function pkt_ack_to_stlv( + constant din : pkt_ack) + return std_logic_vector; + +function stlv_to_pkt_ack( + constant din : std_logic_vector) + return pkt_ack; + +end pkt_ack_pkg; + +package body pkt_ack_pkg is + +function pkt_ack_to_stlv( + constant din : pkt_ack) + return std_logic_vector is + variable res : std_logic_vector(31 downto 0); +begin + res(7 downto 0) := std_logic_vector(din.pkt); + res(23 downto 8) := std_logic_vector(din.set); + res(31 downto 24) := std_logic_vector(din.cmd); + return res; +end pkt_ack_to_stlv; + +function stlv_to_pkt_ack( + constant din : std_logic_vector) + return pkt_ack is + variable res : pkt_ack; +begin + res.pkt:=unsigned(din(7 downto 0)); + res.set:=unsigned(din(23 downto 8)); + res.cmd:=unsigned(din(31 downto 24)); + return res; +end stlv_to_pkt_ack; + +end pkt_ack_pkg; Index: trunk/FPGA/src/common/dpram_inf.vhd =================================================================== --- trunk/FPGA/src/common/dpram_inf.vhd (nonexistent) +++ trunk/FPGA/src/common/dpram_inf.vhd (revision 2) @@ -0,0 +1,61 @@ +-- A parameterized, inferable, true dual-port, common-clock block RAM in VHDL. +-- Original file was taken from: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ +-- No license information were provided by the original author. +-- Minimal modifications were introduced by me to make it suitable for my FPGA +-- interface. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity dp_ram_scl is + generic ( + DATA_WIDTH : integer := 72; + ADDR_WIDTH : integer := 10 + ); + port ( +-- common clock + clk : in std_logic; + -- Port A + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + + -- Port B + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0) + ); +end dp_ram_scl; + +architecture rtl of dp_ram_scl is + -- Shared memory + type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); + shared variable mem : mem_type; +begin + +-- Port A + process(clk) + begin + if(clk'event and clk = '1') then + if(we_a = '1') then + mem(conv_integer(addr_a)) := data_a; + end if; + q_a <= mem(conv_integer(addr_a)); + end if; + end process; + +-- Port B + process(clk) + begin + if(clk'event and clk = '1') then + if(we_b = '1') then + mem(conv_integer(addr_b)) := data_b; + end if; + q_b <= mem(conv_integer(addr_b)); + end if; + end process; + +end rtl; Index: trunk/FPGA/src/common/eth_sender.vhd =================================================================== --- trunk/FPGA/src/common/eth_sender.vhd (nonexistent) +++ trunk/FPGA/src/common/eth_sender.vhd (revision 2) @@ -0,0 +1,201 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block sending packets via Ethernet MAC +-- Project : +------------------------------------------------------------------------------- +-- File : desc_manager.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2012-05-03 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity eth_sender is + + port ( + -- Configuration + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + set_number : in unsigned(15 downto 0); + pkt_number : in unsigned(15 downto 0); + retry_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + -- Control interface + ready : out std_logic; + start : in std_logic; + -- Data memory interface + tx_mem_addr : out std_logic_vector(13 downto 0); + tx_mem_data : in std_logic_vector(31 downto 0); + -- MAC inerface + Tx_mac_wa : in std_logic; + Tx_mac_wr : out std_logic; + Tx_mac_data : out std_logic_vector(31 downto 0); + Tx_mac_BE : out std_logic_vector(1 downto 0); + Tx_mac_sop : out std_logic; + Tx_mac_eop : out std_logic + ); + +end eth_sender; + + +architecture beh1 of eth_sender is + + type T_ETH_SENDER_STATE is (WST_IDLE, WST_SEND_1, WST_SEND_1a, WST_SEND_1b, + WST_SEND_2, WST_SEND_3, WST_SEND_4, WST_SEND_5); + + type T_ETH_SENDER_REGS is record + state : T_ETH_SENDER_STATE; + ready : std_logic; + tx_mem_addr : unsigned (7 downto 0); + end record; + + constant ETH_SENDER_REGS_INI : T_ETH_SENDER_REGS := ( + tx_mem_addr => (others => '0'), + state => WST_IDLE, + ready => '1' + ) ; + + signal r, r_i : T_ETH_SENDER_REGS := ETH_SENDER_REGS_INI; + + type T_ETH_SENDER_COMB is record + Tx_mac_wr : std_logic; + Tx_mac_sop : std_logic; + Tx_mac_eop : std_logic; + Tx_mac_data : std_logic_vector(31 downto 0); + tx_mem_addr : unsigned(7 downto 0); + end record; + + constant ETH_SENDER_COMB_DEFAULT : T_ETH_SENDER_COMB := ( + Tx_mac_wr => '0', + Tx_mac_sop => '0', + Tx_mac_eop => '0', + Tx_mac_data => (others => '0'), + tx_mem_addr => (others => '0') + ); + + signal c : T_ETH_SENDER_COMB := ETH_SENDER_COMB_DEFAULT; + +begin -- beh1 + + -- Connection of the signals + Tx_mac_data <= c.Tx_mac_data; + Tx_mac_eop <= c.Tx_mac_eop; + Tx_mac_sop <= c.Tx_mac_sop; + Tx_mac_wr <= C.Tx_mac_wr; + Tx_mac_be <= "00"; + + ready <= r.ready; + + -- The memory address is built from the packet number (6 bits) and word + -- number (8 bits) + tx_mem_addr <= std_logic_vector(pkt_number(5 downto 0)) & std_logic_vector(c.tx_mem_addr); + + -- Main state machine used to send the packet + snd1 : process (clk, rst_n) + begin + if rst_n = '0' then -- asynchronous reset (active low) + r <= ETH_SENDER_REGS_INI; + elsif clk'event and clk = '1' then -- rising clock edge + r <= r_i; + end if; + end process snd1; -- snd1 + + snd2 : process (Tx_mac_wa, my_ether_type, my_mac, peer_mac, pkt_number, r, + retry_number, set_number, start, transm_delay, + tx_mem_data) + begin -- process snd1 + -- default values + c <= ETH_SENDER_COMB_DEFAULT; + r_i <= r; + case r.state is + when WST_IDLE => + if start = '1' then + r_i.ready <= '0'; + r_i.state <= WST_SEND_1; + end if; + when WST_SEND_1 => + if Tx_mac_wa = '1' then + c.tx_mac_data <= peer_mac(47 downto 16); + c.Tx_mac_sop <= '1'; + c.tx_mac_wr <= '1'; + r_i.state <= WST_SEND_1a; + end if; + when WST_SEND_1a => + if Tx_mac_wa = '1' then + c.tx_mac_data <= peer_mac(15 downto 0) & my_mac(47 downto 32); + c.tx_mac_wr <= '1'; + r_i.state <= WST_SEND_1b; + end if; + when WST_SEND_1b => + if Tx_mac_wa = '1' then + c.tx_mac_data <= my_mac(31 downto 0); + c.tx_mac_wr <= '1'; + r_i.state <= WST_SEND_2; + end if; + when WST_SEND_2 => + if Tx_mac_wa = '1' then + c.tx_mac_data <= my_ether_type & x"a5a5"; + c.tx_mac_wr <= '1'; + r_i.state <= WST_SEND_3; + end if; + when WST_SEND_3 => + -- Now we send the set & packet number & retry_number + if Tx_mac_wa = '1' then + c.tx_mac_data <= std_logic_vector(set_number(15 downto 0)) & std_logic_vector(pkt_number(5 downto 0)) & std_logic_vector(retry_number(9 downto 0)); + c.tx_mac_wr <= '1'; + r_i.tx_mem_addr <= (others => '0'); + r_i.state <= WST_SEND_4; + end if; + when WST_SEND_4 => + -- Now we send the set & packet number & retry_number + if Tx_mac_wa = '1' then + c.tx_mac_data <= std_logic_vector(transm_delay); + c.tx_mac_wr <= '1'; + r_i.tx_mem_addr <= (others => '0'); + r_i.state <= WST_SEND_5; + end if; + when WST_SEND_5 => + -- Now we send the packet data + -- If the address is not incremented, + -- we still send the last address to the memory... + c.tx_mem_addr <= r.tx_mem_addr; + if Tx_mac_wa = '1' then + c.tx_mac_data <= tx_mem_data; + c.tx_mac_wr <= '1'; + if r.tx_mem_addr < 255 then + -- Still some data should be sent + -- We increase the address, so the data are available + -- in the next cycle + r_i.tx_mem_addr <= r.tx_mem_addr + 1; + c.tx_mem_addr <= r.tx_mem_addr + 1; + r_i.state <= WST_SEND_5; -- we remain in the same state + else + -- All data sent + -- set the "end_of_packet" flag + c.Tx_mac_eop <= '1'; + r_i.state <= WST_IDLE; + r_i.ready <= '1'; + end if; + end if; + end case; + end process snd2; + +end beh1; Index: trunk/FPGA/src/common/desc_manager_simple.vhd =================================================================== --- trunk/FPGA/src/common/desc_manager_simple.vhd (nonexistent) +++ trunk/FPGA/src/common/desc_manager_simple.vhd (revision 2) @@ -0,0 +1,585 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - descriptor manager +-- Project : +------------------------------------------------------------------------------- +-- File : desc_manager.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2012-08-30 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +use ieee.std_logic_textio.all; +library work; +use work.pkt_ack_pkg.all; + +package desc_mgr_pkg is + + constant N_OF_PKTS : integer := 32; + constant N_OF_SETS : integer := 65536; + + type T_PKT_DESC is record + set : integer range 0 to N_OF_SETS-1; -- number of sets + confirmed : std_logic; + valid : std_logic; + sent : std_logic; + end record; + +end desc_mgr_pkg; + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +-- The below implementation of the descriptor memory is awfull, +-- but seemed to be necessary to force XST to infer it as an +-- single port BRAM. +-- I simply provide vector long enough to accomodate my T_PKT_DESC +-- type, and hope that the synthesis tool (XST) will optimize out +-- unused bits.should be inferred as block memory (so be carefull +-- when modifying the below process)! + +entity desc_memory is + + port ( + clk : in std_logic; + desc_we : in std_logic; + desc_addr : in integer range 0 to N_OF_PKTS-1; + desc_out : in T_PKT_DESC; + desc_in : out T_PKT_DESC); + +end desc_memory; + +architecture beh1 of desc_memory is + + type T_PKT_DESC_MEM is array (0 to N_OF_PKTS-1) of unsigned(22 downto 0); + signal desc_mem : T_PKT_DESC_MEM := (others => (others => '0')); + signal din : unsigned(22 downto 0) := (others => '0'); + signal dout : unsigned(22 downto 0) := (others => '0'); + signal rdaddr : integer range 0 to N_OF_PKTS-1; + +begin -- beh1 + + process (desc_out, dout) + begin -- process + din <= (others => '0'); + din(22) <= desc_out.valid; + din(21) <= desc_out.confirmed; + din(20) <= desc_out.sent; + din(19 downto 0) <= to_unsigned(desc_out.set, 20); + desc_in.valid <= dout(22); + desc_in.confirmed <= dout(21); + desc_in.sent <= dout(20); + desc_in.set <= to_integer(dout(19 downto 0)); + end process; + + process (clk) + begin -- process + if (clk'event and clk = '1') then -- rising clock edge + if (desc_we = '1') then + desc_mem(desc_addr) <= din; + end if; + rdaddr <= desc_addr; + end if; + end process; + dout <= desc_mem(rdaddr); + +end beh1; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +entity desc_manager is + + generic ( + N_OF_PKTS : integer := 64); -- Number of packet_logi buffers + + port ( + -- Data input interface + dta : in std_logic_vector(31 downto 0); + dta_we : in std_logic; + dta_ready : out std_logic; + -- ETH Sender interface + set_number : out unsigned(15 downto 0); + pkt_number : out unsigned(15 downto 0); + snd_start : out std_logic; + snd_ready : in std_logic; + + -- Data memory interface + dmem_addr : out std_logic_vector(13 downto 0); + dmem_dta : out std_logic_vector(31 downto 0); + dmem_we : out std_logic; + -- Interface to the ACK FIFO + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + + -- + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + + -- + clk : in std_logic; + rst_n : in std_logic); + +end desc_manager; + +architecture dmgr_a1 of desc_manager is + + constant PKT_CNT_MAX : integer := 10000; + + -- To simplify description of state machines, all registers are grouped + -- in a record: + + type T_DESC_MGR_REGS is record + set : integer range 0 to N_OF_SETS-1; + cur_set : integer range 0 to N_OF_SETS-1; + all_pkt_count : integer range 0 to PKT_CNT_MAX; + retr_pkt_count : integer range 0 to PKT_CNT_MAX; + retr_delay : unsigned(31 downto 0); + transm_delay : unsigned(31 downto 0); + nxt : integer range 0 to N_OF_PKTS-1; + tail_ptr : integer range 0 to N_OF_PKTS-1; + head_ptr : integer range 0 to N_OF_PKTS-1; + retr_ptr : integer range 0 to N_OF_PKTS-1; -- buffer, which is retransmitted + -- when equal to head_ptr - + -- retransmission is finished + retr_nxt : integer range 0 to N_OF_PKTS-1; -- buffer, which will be + -- retransmitted next + -- when equal to head_ptr -- no retransmission + -- is performed + end record; + + constant DESC_MGR_REGS_INI : T_DESC_MGR_REGS := ( + retr_delay => (others => '0'), + transm_delay => to_unsigned(10000, 32), + all_pkt_count => 0, + retr_pkt_count => 0, + set => 0, + cur_set => 0, + nxt => 0, + tail_ptr => 0, + head_ptr => 0, + retr_ptr => 0, + retr_nxt => 0 + ); + + -- To simplify setting of outputs of my Mealy state machine, all combinatorial + -- outputs are grouped in a record + type T_DESC_MGR_COMB is record + dta_buf_free : std_logic; + desc_addr : integer range 0 to N_OF_PKTS-1; + desc_we : std_logic; + ack_rd : std_logic; + snd_start : std_logic; + desc_out : T_PKT_DESC; + end record; + + constant DESC_MGR_COMB_DEFAULT : T_DESC_MGR_COMB := ( + dta_buf_free => '0', + desc_addr => 0, + desc_we => '0', + ack_rd => '0', + snd_start => '0', + desc_out => (confirmed => '0', valid => '0', sent => '0', set => 0) + ); + + type T_DESC_MGR_STATE is (ST_DMGR_IDLE, ST_DMGR_START, ST_DMGR_RST, ST_DMGR_RST1, + ST_DMGR_ACK1, ST_DMGR_INS1, ST_DMGR_INS2, ST_DMGR_ACK_TAIL, + ST_DMGR_ACK_TAIL_1, + ST_DMGR_RETR, ST_DMGR_RETR_2); + + signal desc_in : T_PKT_DESC; + + signal r, r_i : T_DESC_MGR_REGS := DESC_MGR_REGS_INI; + signal c : T_DESC_MGR_COMB; + signal dmgr_state, dmgr_state_next : T_DESC_MGR_STATE := ST_DMGR_RST; + attribute keep : string; + attribute keep of dmgr_state : signal is "true"; + + signal dta_buf_full : std_logic := '0'; + + signal ack_pkt_in : pkt_ack; + + signal wrd_addr : integer range 0 to 255; + + component desc_memory + port ( + clk : in std_logic; + desc_we : in std_logic; + desc_addr : in integer range 0 to N_OF_PKTS-1; + desc_out : in T_PKT_DESC; + desc_in : out T_PKT_DESC); + end component; + + +begin -- dmgr_a1 + + transm_delay <= r.transm_delay; + set_number <= to_unsigned(r.set, 16); + pkt_number <= to_unsigned(r.retr_ptr, 16); + dta_ready <= not dta_buf_full; + snd_start <= c.snd_start; + ack_fifo_rd_en <= c.ack_rd; + + ack_pkt_in <= stlv_to_pkt_ack(ack_fifo_dout); + + + -- Packet descriptors are stored in the desc_memory + + desc_memory_1 : desc_memory + port map ( + clk => clk, + desc_we => c.desc_we, + desc_addr => c.desc_addr, + desc_out => c.desc_out, + desc_in => desc_in); + + -- Process used to fill the buffer memory with the data to be transmitted + -- We simply write words to the memory buffer pointed by r.head_ptr + -- When we write the last (0xff-th) word, we signal that the buffer + -- is full. Only after reception of + dta_rcv : process (clk, rst_n) + begin -- process dta_rcv + if rst_n = '0' then -- asynchronous reset (active low) + wrd_addr <= 0; + dta_buf_full <= '0'; + dmem_we <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + dmem_we <= '0'; + -- if we signalled "data full", we are only waiting for + -- dta_buf_free; + if dta_buf_full = '1' then + if c.dta_buf_free = '1' then + dta_buf_full <= '0'; + wrd_addr <= 0; + end if; + else + -- if data write requested - write it + if dta_we = '1' then + dmem_addr <= std_logic_vector(to_unsigned(r.head_ptr, 6)) & + std_logic_vector(to_unsigned(wrd_addr, 8)); + dmem_we <= '1'; + dmem_dta <= dta; + if wrd_addr < 255 then + wrd_addr <= wrd_addr + 1; + else + dta_buf_full <= '1'; + end if; + end if; + end if; + end if; + end process dta_rcv; + + + c1 : process (ack_fifo_empty, ack_pkt_in, desc_in, dmgr_state, dta_buf_full, + r, snd_ready) + begin -- process c1 + c <= DESC_MGR_COMB_DEFAULT; -- set defaults + r_i <= r; -- avoid latches + + if r.retr_delay /= to_unsigned(0, r.retr_delay'length) then + r_i.retr_delay <= r.retr_delay-1; + end if; + dmgr_state_next <= dmgr_state; + -- State machine + case dmgr_state is + when ST_DMGR_RST => + dmgr_state_next <= ST_DMGR_RST1; + when ST_DMGR_RST1 => + -- We should initialize the 0th position of list descriptors + c.desc_addr <= r.head_ptr; + c.desc_out <= desc_in; + c.desc_out.confirmed <= '0'; + c.desc_out.valid <= '0'; + c.desc_out.sent <= '0'; + c.desc_out.set <= 0; + c.desc_we <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + when ST_DMGR_IDLE => + -- First we check, if there are any packets to acknowledge + if ack_fifo_empty = '0' then + -- Read the description of the acknowledged packet + c.desc_addr <= to_integer(ack_pkt_in.pkt); + dmgr_state_next <= ST_DMGR_ACK1; + elsif dta_buf_full = '1' then + -- We should handle reception of data. + -- If the previously filled buffer is full, pass it for transmission, + -- and allocate the next one. + -- + -- Calculate the number of the packet, which shoud be the next "head" + -- packet. + if r.head_ptr = N_OF_PKTS-1 then + r_i.nxt <= 0; + else + r_i.nxt <= r.head_ptr + 1; + end if; + -- Prepare for reading of the current "head" descriptor + c.desc_addr <= r.head_ptr; + dmgr_state_next <= ST_DMGR_INS1; + elsif (r.tail_ptr /= r.head_ptr) and (r.retr_delay = to_unsigned(0, r.retr_delay'length)) then + -- We need to (re)transmit some buffers + -- prepare reading of the descriptor, which should be transmitted + c.desc_addr <= r.retr_nxt; + dmgr_state_next <= ST_DMGR_RETR; + end if; + when ST_DMGR_INS1 => + -- First we check, if there is free space, r.nxt is the number of the + -- future head packet. + if (r.nxt = r.tail_ptr) then + -- No free place! The packet, which we would like to fill is still + -- occupied. + -- Return to idle, waiting until something is freed. + -- In this case we should also force retransmission + if r.retr_delay = 0 then + c.desc_addr <= r.retr_nxt; + dmgr_state_next <= ST_DMGR_RETR; + else + dmgr_state_next <= ST_DMGR_IDLE; + end if; + else + -- We can fill the next buffer + -- First we mark the previous head packet + -- as valid and not confirmed + c.desc_addr <= r.head_ptr; + c.desc_out <= desc_in; + c.desc_out.confirmed <= '0'; + c.desc_out.valid <= '1'; + c.desc_we <= '1'; + -- Now we move the "head" pointer + r_i.head_ptr <= r.nxt; + -- Increase the set number if we wrapped around + if r.nxt = 0 then + if r.cur_set = N_OF_SETS-1 then + r_i.cur_set <= 0; + else + r_i.cur_set <= r.cur_set + 1; + end if; + end if; + dmgr_state_next <= ST_DMGR_INS2; + end if; + when ST_DMGR_INS2 => + -- We fill the new head descriptor + c.desc_addr <= r.head_ptr; + c.desc_out.set <= r.cur_set; + c.desc_out.confirmed <= '0'; + c.desc_out.valid <= '0'; + c.desc_out.sent <= '0'; + c.desc_we <= '1'; + -- Signal, that the buffer is freed + c.dta_buf_free <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + when ST_DMGR_ACK1 => + -- In this state the desc memory should respond with the data of the + -- buffered packet, so we can state, if this packet is really correctly + -- acknowledged (here we also ignore the NACK packets! + if (ack_pkt_in.set = desc_in.set) and + (ack_pkt_in.cmd = to_unsigned(3,ack_pkt_in.cmd'length)) and + (desc_in.valid = '1') then + -- This is really correct, unconfirmed packet + -- Increase the counter of not-repeated ACK packets + -- Write the confirmation + c.desc_addr <= to_integer(ack_pkt_in.pkt); + c.desc_out <= desc_in; + c.desc_out.valid <= '0'; + c.desc_out.confirmed <= '1'; + c.desc_we <= '1'; + -- Here we also handle the case, if the acknowledged packet was + -- the one which is now scheduled for retransmission... + if ack_pkt_in.pkt = r.retr_nxt then + if r.retr_nxt < N_OF_PKTS-1 then + r_i.retr_nxt <= r.retr_nxt + 1; + else + r_i.retr_nxt <= 0; + end if; + end if; + -- Check, if we need to update the "tail" pointer + if r.tail_ptr = ack_pkt_in.pkt then + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_ACK_TAIL; + else + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + end if; + else + -- This packet was already confirmed or it was NACK + -- just flush the ack_fifo + c.ack_rd <= '1'; + dmgr_state_next <= ST_DMGR_IDLE; + end if; + when ST_DMGR_ACK_TAIL => + c.desc_addr <= r.tail_ptr; + dmgr_state_next <= ST_DMGR_ACK_TAIL_1; + when ST_DMGR_ACK_TAIL_1 => + -- In this state we update the "tail" pointer if necessary + if r.tail_ptr /= r.head_ptr then + if desc_in.confirmed = '1' then + if r.tail_ptr < N_OF_PKTS-1 then + r_i.tail_ptr <= r.tail_ptr + 1; + c.desc_addr <= r.tail_ptr + 1; + else + r_i.tail_ptr <= 0; + c.desc_addr <= 0; + end if; + -- We remain in that state, to check the next packet descriptor + else + -- We return to idle + dmgr_state_next <= ST_DMGR_IDLE; + end if; + else + -- Buffer is empty - return to idle + dmgr_state_next <= ST_DMGR_IDLE; + end if; + when ST_DMGR_RETR => + -- Here we handle the transmission of a new packet, + -- retransmission of not confirmed packet + -- We must be sure, that the transmitter is ready + if snd_ready = '0' then + -- transmitter not ready, return to idle + dmgr_state_next <= ST_DMGR_IDLE; + else + -- We will be able to send the next packet, but let's check if + -- this is not the currently filled packet + if r.retr_nxt = r.head_ptr then + -- All packets (re)transmitted, go to the begining of the list + -- and return to idle. + r_i.retr_nxt <= r.tail_ptr; + dmgr_state_next <= ST_DMGR_IDLE; + else + -- before jumping to ST_DMGR_RETR, the address bus + -- was set to the address of r.retr_nxt, so now + -- we can read the descriptor, and check if the packet + -- needs to be retransmitted at all... + r_i.set <= desc_in.set; + r_i.retr_ptr <= r.retr_nxt; + if r.retr_nxt < N_OF_PKTS-1 then + r_i.retr_nxt <= r.retr_nxt + 1; + else + r_i.retr_nxt <= 0; + end if; + if desc_in.valid = '1' and desc_in.confirmed = '0' then + if desc_in.sent = '1' then + -- Increase count of retransmitted packets for + -- adaptive adjustment of delay + if r.retr_pkt_count < PKT_CNT_MAX then + r_i.retr_pkt_count <= r.retr_pkt_count + 1; + end if; + end if; + -- Increase count of all packets for adaptive adjustment + -- of delay + if r.all_pkt_count < PKT_CNT_MAX then + r_i.all_pkt_count <= r.all_pkt_count + 1; + end if; + -- Mark the packet as sent + c.desc_addr <= r.retr_nxt; + c.desc_out <= desc_in; + c.desc_out.sent <= '1'; + c.desc_we <= '1'; + dmgr_state_next <= ST_DMGR_RETR_2; + else + dmgr_state_next <= ST_DMGR_IDLE; + end if; + end if; + end if; + when ST_DMGR_RETR_2 => + -- In this state, we simply trigger the sender! + c.snd_start <= '1'; + r_i.retr_delay <= r.transm_delay; + -- And we update the delay using the packet statistics + -- You may change the constants used in expressions + -- below to change speed of adjustment + if r.all_pkt_count >= PKT_CNT_MAX then + if r.retr_pkt_count < PKT_CNT_MAX/32 then + if r.transm_delay > 32 then + r_i.transm_delay <= r.transm_delay-r.transm_delay/4; + end if; + elsif r.retr_pkt_count > PKT_CNT_MAX/8 then + if r.transm_delay < 1000000 then + r_i.transm_delay <= r.transm_delay+r.transm_delay/4; + end if; + end if; + r_i.all_pkt_count <= 0; + r_i.retr_pkt_count <= 0; + end if; + dmgr_state_next <= ST_DMGR_IDLE; + when others => null; + end case; + end process c1; + +-- Synchronous process + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + r <= DESC_MGR_REGS_INI; + dmgr_state <= ST_DMGR_RST; + elsif clk'event and clk = '1' then -- rising clock edge + r <= r_i; + dmgr_state <= dmgr_state_next; + end if; + end process; + +-- Process debugging the descriptors memory - for simulation only! +-- process (clk, rst_n) +-- variable L : line; +-- begin -- process +-- if rst_n = '0' then -- asynchronous reset (active low) +-- null; +-- elsif clk'event and clk = '1' then -- rising clock edge +-- if c.desc_we = '1' then +-- write(L, string'("nr=")); +-- write(L, c.desc_addr); +-- write(L, string'(" set=")); +-- write(L, c.desc_out.set); +-- write(L, string'(" valid=")); +-- --write(L,c.desc_out.valid); +-- if c.desc_out.valid = '1' then +-- write(L, string'("1")); +-- else +-- write(L, string'("0")); +-- end if; +-- write(L, string'(" confirmed=")); +-- --write(L,c.desc_out.valid); +-- if c.desc_out.confirmed = '1' then +-- write(L, string'("1")); +-- else +-- write(L, string'("0")); +-- end if; +-- write(L, string'(" r.tail=")); +-- write(L, r.tail_ptr); +-- write(L, string'(" r.head=")); +-- write(L, r.head_ptr); +-- writeline(output, L); +-- end if; +-- end if; +-- end process; + +end dmgr_a1; + + + Index: trunk/FPGA/src/common/eth_receiver.vhd =================================================================== --- trunk/FPGA/src/common/eth_receiver.vhd (nonexistent) +++ trunk/FPGA/src/common/eth_receiver.vhd (revision 2) @@ -0,0 +1,251 @@ +------------------------------------------------------------------------------- +-- Title : FPGA Ethernet interface - block receiving packets from Ethernet MAC +-- Project : +------------------------------------------------------------------------------- +-- File : desc_manager.vhd +-- Author : Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) +-- License : BSD License +-- Company : +-- Created : 2012-03-30 +-- Last update: 2012-08-30 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: This file implements the state machine, which manages the +-- table of packet descriptors, used to resend only not confirmed packets +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2012-03-30 1.0 WZab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkt_ack_pkg.all; + +entity eth_receiver is + + port ( + -- Configuration + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + -- ACK FIFO interface + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + -- System interface + clk : in std_logic; + rst_n : in std_logic; + -- MAC inerface + Rx_mac_pa : in std_logic; + Rx_mac_ra : in std_logic; + Rx_mac_rd : out std_logic; + Rx_mac_data : in std_logic_vector(31 downto 0); + Rx_mac_BE : in std_logic_vector(1 downto 0); + Rx_mac_sop : in std_logic; + Rx_mac_eop : in std_logic + ); + +end eth_receiver; + + +architecture beh1 of eth_receiver is + + type T_STATE is (ST_IDLE, ST_ACK_1, ST_NACK_1, ST_SET_DELAY, ST_READ_SRC1, ST_READ_SRC2, ST_READ_OP); + + type T_RCV_REGS is record + state : T_STATE; + sender : std_logic_vector(47 downto 0); + transmit_data : std_logic; + peer_mac : std_logic_vector(47 downto 0); + end record; + + constant RCV_REGS_INI : T_RCV_REGS := ( + state => ST_IDLE, + sender => (others => '0'), + transmit_data => '0', + peer_mac => (others => '0') + ); + + signal r, r_i : T_RCV_REGS := RCV_REGS_INI; + + type T_RCV_COMB is record + ack_fifo_wr_en : std_logic; + Rx_mac_rd : std_logic; + ack_fifo_din : std_logic_vector(pkt_ack_width-1 downto 0); + restart : std_logic; + end record; + + constant RCV_COMB_DEFAULT : T_RCV_COMB := ( + ack_fifo_wr_en => '0', + Rx_mac_rd => '0', + ack_fifo_din => (others => '0'), + restart => '0' + ); + + signal c : T_RCV_COMB := RCV_COMB_DEFAULT; + +begin -- beh1 + + transmit_data <= r.transmit_data; + peer_mac <= r.peer_mac; + ack_fifo_din <= c.ack_fifo_din; + ack_fifo_wr_en <= c.ack_fifo_wr_en; + Rx_mac_rd <= c.Rx_mac_rd; + restart <= c.restart; + + -- Reading of ethernet data + rdp1 : process (clk, rst_n) + begin -- process rdp1 + if rst_n = '0' then -- asynchronous reset (active low) + r <= RCV_REGS_INI; + elsif clk'event and clk = '1' then -- rising clock edge + r <= r_i; + end if; + end process rdp1; + + rdp2 : process (Rx_mac_data, Rx_mac_pa, Rx_mac_ra, Rx_mac_sop, ack_fifo_full, + my_ether_type, my_mac, r, rx_mac_pa) + + variable ack_pkt_in : pkt_ack; + + begin -- process + c <= RCV_COMB_DEFAULT; + r_i <= r; + case r.state is + when ST_IDLE => + if Rx_mac_ra = '1' then + c.Rx_mac_rd <= '1'; + if Rx_mac_pa = '1' then + if Rx_mac_sop = '1' then + if Rx_mac_data(31 downto 0) = my_mac(47 downto 16) then + r_i.state <= ST_READ_SRC1; + else + r_i.state <= ST_IDLE; + end if; + end if; + end if; + end if; + when ST_READ_SRC1 => + if Rx_mac_ra = '1' then + c.Rx_mac_rd <= '1'; + if Rx_mac_pa = '1' then + if Rx_mac_sop = '1' then + -- This shouldn't happen! + r_i.state <= ST_IDLE; + else + if Rx_mac_data(31 downto 16) = my_mac(15 downto 0) then + r_i.sender(47 downto 32) <= Rx_mac_data(15 downto 0); + r_i.state <= ST_READ_SRC2; + else + r_i.state <= ST_IDLE; + end if; + end if; + end if; + end if; + when ST_READ_SRC2 => + if Rx_mac_ra = '1' then + c.Rx_mac_rd <= '1'; + if Rx_mac_pa = '1' then + if Rx_mac_sop = '1' then + -- This shouldn't happen! + r_i.state <= ST_IDLE; + else + r_i.sender(31 downto 0) <= Rx_mac_data; + r_i.state <= ST_READ_OP; + end if; + end if; + end if; + when ST_READ_OP => + if Rx_mac_ra = '1' then + c.Rx_mac_rd <= '1'; + if rx_mac_pa = '1' then + if Rx_mac_sop = '1' then + -- This shouldn't happen! + r_i.state <= ST_IDLE; + -- check the Ethernet type + elsif Rx_mac_data(31 downto 16) /= my_ether_type then + r_i.state <= ST_IDLE; + else + -- This is a packet in our protocol, so we can update + -- the peer address + r_i.peer_mac <= r.sender; + -- check the command + case Rx_mac_data(15 downto 0) is + when x"0001" => + -- Start transmission command + r_i.transmit_data <= '1'; + r_i.state <= ST_IDLE; + when x"0002" => + -- Stop transmission command + r_i.transmit_data <= '0'; + r_i.state <= ST_IDLE; + when x"0003" => + -- Packet ACK command + r_i.state <= ST_ACK_1; + when x"0004" => + -- Packet NACK command (currently not used) + r_i.state <= ST_NACK_1; + when x"0005" => + -- Stop transmission and retransmission + c.restart <= '1'; + r_i.state <= ST_IDLE; + when others => + r_i.state <= ST_IDLE; + end case; + end if; + end if; + end if; + when ST_ACK_1 => + if Rx_mac_ra = '1' then + c.Rx_mac_rd <= '1'; + if Rx_mac_pa = '1' then + if Rx_mac_sop = '1' then + -- This shouldn't happen! + r_i.state <= ST_IDLE; + else + -- put the ACK info int the FIFO queue + -- (if FIFO is full, we simply drop the packet) + if ack_fifo_full = '0' then + ack_pkt_in.cmd := to_unsigned(3, ack_pkt_in.cmd'length); + ack_pkt_in.set := unsigned(Rx_mac_data(31 downto 16)); + ack_pkt_in.pkt := "00" & unsigned(Rx_mac_data(15 downto 10)); + c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); + c.ack_fifo_wr_en <= '1'; + end if; + r_i.state <= ST_IDLE; + end if; + end if; + end if; + when ST_NACK_1 => + if Rx_mac_ra = '1' then + c.Rx_mac_rd <= '1'; + if Rx_mac_pa = '1' then + if Rx_mac_sop = '1' then + -- This shouldn't happen! + r_i.state <= ST_IDLE; + else + if ack_fifo_full = '0' then + -- put the ACK info int the FIFO queue + -- (if FIFO is full, we simply drop the packet) + ack_pkt_in.cmd := to_unsigned(4, ack_pkt_in.cmd'length); + ack_pkt_in.set := unsigned(Rx_mac_data(31 downto 16)); + ack_pkt_in.pkt := "00" & unsigned(Rx_mac_data(15 downto 10)); + c.ack_fifo_din <= pkt_ack_to_stlv(ack_pkt_in); + c.ack_fifo_wr_en <= '1'; + end if; + r_i.state <= ST_IDLE; + end if; + end if; + end if; + when others => null; + end case; + end process rdp2; + +end beh1; Index: trunk/FPGA/sp601/sp601_eth.ucf =================================================================== --- trunk/FPGA/sp601/sp601_eth.ucf (nonexistent) +++ trunk/FPGA/sp601/sp601_eth.ucf (revision 2) @@ -0,0 +1,84 @@ +NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10 +NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10 +NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10 +NET "GPIO_LED<0>" LOC = "E13"; ## 2 on DS11 LED +NET "GPIO_LED<1>" LOC = "C14"; ## 2 on DS12 LED +NET "GPIO_LED<2>" LOC = "C4"; ## 2 on DS13 LED +NET "GPIO_LED<3>" LOC = "A4"; ## 2 on DS14 LED + +NET "SWITCHES<0>" LOC = "D14"; +NET "SWITCHES<1>" LOC = "E12"; +NET "SWITCHES<2>" LOC = "F12"; +NET "SWITCHES<3>" LOC = "V13"; + +## +NET "CPU_RESET" LOC = "N4"; ## 2 on SW9 pushbutton +## +NET "PHY_COL" LOC = "L14"; ## 114 on U3 +NET "PHY_CRS" LOC = "M13"; ## 115 on U3 +NET "PHY_INT" LOC = "J13"; ## 32 on U3 +NET "PHY_MDC" LOC = "N14"; ## 35 on U3 +NET "PHY_MDIO" LOC = "P16"; ## 33 on U3 +NET "PHY_RESET" LOC = "L13"; ## 36 on U3 +NET "PHY_RXCLK" LOC = "L16"; ## 7 on U3 +NET "PHY_RXCTL_RXDV" LOC = "N18"; ## 4 on U3 +NET "PHY_RXD<0>" LOC = "M14"; ## 3 on U3 +NET "PHY_RXD<1>" LOC = "U18"; ## 128 on U3 +NET "PHY_RXD<2>" LOC = "U17"; ## 126 on U3 +NET "PHY_RXD<3>" LOC = "T18"; ## 125 on U3 +NET "PHY_RXD<4>" LOC = "T17"; ## 124 on U3 +NET "PHY_RXD<5>" LOC = "N16"; ## 123 on U3 +NET "PHY_RXD<6>" LOC = "N15"; ## 121 on U3 +NET "PHY_RXD<7>" LOC = "P18"; ## 120 on U3 +NET "PHY_RXER" LOC = "P17"; ## 8 on U3 +NET "PHY_TXCLK" LOC = "B9"; ## 10 on U3 +NET "PHY_TXCTL_TXEN" LOC = "B8"; ## 16 on U3 +NET "PHY_TXC_GTXCLK" LOC = "A9"; ## 14 on U3 +NET "PHY_TXD<0>" LOC = "F8"; ## 18 on U3 +NET "PHY_TXD<1>" LOC = "G8"; ## 19 on U3 +NET "PHY_TXD<2>" LOC = "A6"; ## 20 on U3 +NET "PHY_TXD<3>" LOC = "B6"; ## 24 on U3 +NET "PHY_TXD<4>" LOC = "E6"; ## 25 on U3 +NET "PHY_TXD<5>" LOC = "F7"; ## 26 on U3 +NET "PHY_TXD<6>" LOC = "A5"; ## 28 on U3 +NET "PHY_TXD<7>" LOC = "C5"; ## 29 on U3 +NET "PHY_TXER" LOC = "A8"; ## 13 on U3 +## +NET "SYSCLK_N" LOC = "K16"; ## 5 on U5 EG2121CA, 5 of U20 SI500D (DNP) +NET "SYSCLK_P" LOC = "K15"; ## 6 on U5 EG2121CA, 4 of U20 SI500D (DNP) +## +#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1 +#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1 +#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1 +#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1 +#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1 +#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1 +#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1 +#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1 +# +NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm) +NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm) +NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm) +NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm) +NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm) +NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm) +NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm) +NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm) +# +NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16 +NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16 +# +PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; + +#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04 +NET "sysclk_p" TNM_NET = sysclk_p; +TIMESPEC TS_sysclk_p = PERIOD "sysclk_p" 5 ns HIGH 50%; +NET "sysclk_n" TNM_NET = sysclk_n; +TIMESPEC TS_sysclk_n = PERIOD "sysclk_n" 5 ns HIGH 50%; +#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30 +NET "phy_rxclk" TNM_NET = phy_rxclk; +TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%; +NET "phy_txclk" TNM_NET = phy_txclk; +TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 40 ns HIGH 50%; +NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk; +TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%; Index: trunk/FPGA/sp601/build.sh =================================================================== --- trunk/FPGA/sp601/build.sh (nonexistent) +++ trunk/FPGA/sp601/build.sh (revision 2) @@ -0,0 +1,5 @@ +#!/bin/bash +coregen -r -b dcm1.xco -p coregen.cgp +coregen -r -b ack_fifo.xco -p coregen.cgp +xtclsh sp601_eth.tcl rebuild_project +
trunk/FPGA/sp601/build.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/FPGA/sp601/ack_fifo.xco =================================================================== --- trunk/FPGA/sp601/ack_fifo.xco (nonexistent) +++ trunk/FPGA/sp601/ack_fifo.xco (revision 2) @@ -0,0 +1,91 @@ +############################################################## +# +# Xilinx Core Generator version 13.4 +# Date: Mon Apr 16 20:47:28 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx16 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=ack_fifo +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Common_Clock_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=32 +CSET input_depth=1024 +CSET output_data_width=32 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=11 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=11 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-01-07T15:29:19Z +# END Extra information +GENERATE +# CRC: 2e8c307d Index: trunk/FPGA/sp601/coregen.cgp =================================================================== --- trunk/FPGA/sp601/coregen.cgp (nonexistent) +++ trunk/FPGA/sp601/coregen.cgp (revision 2) @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = VHDL +SET device = xc6slx16 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = csg324 +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true Index: trunk/FPGA/sp601/sp601_eth.tcl =================================================================== --- trunk/FPGA/sp601/sp601_eth.tcl (nonexistent) +++ trunk/FPGA/sp601/sp601_eth.tcl (revision 2) @@ -0,0 +1,572 @@ +# +# Project automation script for sp601_eth +# +# Created for ISE version 13.4 +# +# This file contains several Tcl procedures (procs) that you can use to automate +# your project by running from xtclsh or the Project Navigator Tcl console. +# If you load this file (using the Tcl command: source sp601_eth.tcl), then you can +# run any of the procs included here. +# +# This script is generated assuming your project has HDL sources. +# Several of the defined procs won't apply to an EDIF or NGC based project. +# If that is the case, simply remove them from this script. +# +# You may also edit any of these procs to customize them. See comments in each +# proc for more instructions. +# +# This file contains the following procedures: +# +# Top Level procs (meant to be called directly by the user): +# run_process: you can use this top-level procedure to run any processes +# that you choose to by adding and removing comments, or by +# adding new entries. +# rebuild_project: you can alternatively use this top-level procedure +# to recreate your entire project, and the run selected processes. +# +# Lower Level (helper) procs (called under in various cases by the top level procs): +# show_help: print some basic information describing how this script works +# add_source_files: adds the listed source files to your project. +# set_project_props: sets the project properties that were in effect when this +# script was generated. +# create_libraries: creates and adds file to VHDL libraries that were defined when +# this script was generated. +# set_process_props: set the process properties as they were set for your project +# when this script was generated. +# + +set myProject "sp601_eth" +set myScript "sp601_eth.tcl" + +# +# Main (top-level) routines +# +# run_process +# This procedure is used to run processes on an existing project. You may comment or +# uncomment lines to control which processes are run. This routine is set up to run +# the Implement Design and Generate Programming File processes by default. This proc +# also sets process properties as specified in the "set_process_props" proc. Only +# those properties which have values different from their current settings in the project +# file will be modified in the project. +# +proc run_process {} { + + global myScript + global myProject + + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: running ($myProject)...\n" + + if { ! [ open_project ] } { + return false + } + + set_process_props + # + # Remove the comment characters (#'s) to enable the following commands + # process run "Synthesize" + # process run "Translate" + # process run "Map" + # process run "Place & Route" + # + set task "Implement Design" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + set task "Generate Programming File" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + puts "Run completed (successfully)." + project close + +} + +# +# rebuild_project +# +# This procedure renames the project file (if it exists) and recreates the project. +# It then sets project properties and adds project sources as specified by the +# set_project_props and add_source_files support procs. It recreates VHDL Libraries +# as they existed at the time this script was generated. +# +# It then calls run_process to set process properties and run selected processes. +# +proc rebuild_project {} { + + global myScript + global myProject + + project close + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: Rebuilding ($myProject)...\n" + + set proj_exts [ list ise xise gise ] + foreach ext $proj_exts { + set proj_name "${myProject}.$ext" + if { [ file exists $proj_name ] } { + file delete $proj_name + } + } + + project new $myProject + set_project_props + add_source_files + create_libraries + puts "$myScript: project rebuild completed." + + run_process + +} + +# +# Support Routines +# + +# +proc run_task { task } { + + # helper proc for run_process + + puts "Running '$task'" + set result [ process run "$task" ] + # + # check process status (and result) + set status [ process get $task status ] + if { ( ( $status != "up_to_date" ) && \ + ( $status != "warnings" ) ) || \ + ! $result } { + return false + } + return true +} + +# +# show_help: print information to help users understand the options available when +# running this script. +# +proc show_help {} { + + global myScript + + puts "" + puts "usage: xtclsh $myScript " + puts " or you can run xtclsh and then enter 'source $myScript'." + puts "" + puts "options:" + puts " run_process - set properties and run processes." + puts " rebuild_project - rebuild the project from scratch and run processes." + puts " set_project_props - set project properties (device, speed, etc.)" + puts " add_source_files - add source files" + puts " create_libraries - create vhdl libraries" + puts " set_process_props - set process property values" + puts " show_help - print this message" + puts "" +} + +proc open_project {} { + + global myScript + global myProject + + if { ! [ file exists ${myProject}.xise ] } { + ## project file isn't there, rebuild it. + puts "Project $myProject not found. Use project_rebuild to recreate it." + return false + } + + project open $myProject + + return true + +} +# +# set_project_props +# +# This procedure sets the project properties as they were set in the project +# at the time this script was generated. +# +proc set_project_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Setting project properties..." + + project set family "Spartan6" + project set device "xc6slx16" + project set package "csg324" + project set speed "-2" + project set top_level_module_type "HDL" + project set synthesis_tool "XST (VHDL/Verilog)" + project set simulator "ISim (VHDL/Verilog)" + project set "Preferred Language" "VHDL" + project set "Enable Message Filtering" "false" + +} + + +# +# add_source_files +# +# This procedure add the source files that were known to the project at the +# time this script was generated. +# +proc add_source_files {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Adding sources to project..." + + xfile add "./ack_fifo.xco" + xfile add "../src/ack_fifo/pkt_ack_pkg.vhd" + xfile add "./dcm1.xco" + xfile add "../src/common/desc_manager_simple.vhd" + xfile add "../src/common/dpram_inf.vhd" + xfile add "../src/eth/Clk_ctrl.v" + xfile add "../src/eth/MAC_rx.v" + xfile add "../src/eth/MAC_rx/Broadcast_filter.v" + xfile add "../src/eth/MAC_rx/CRC_chk.v" + xfile add "../src/eth/MAC_rx/MAC_rx_FF.v" + xfile add "../src/eth/MAC_rx/MAC_rx_add_chk.v" + xfile add "../src/eth/MAC_rx/MAC_rx_ctrl.v" + xfile add "../src/eth/MAC_top.v" + xfile add "../src/eth/MAC_tx.v" + xfile add "../src/eth/MAC_tx/CRC_gen.v" + xfile add "../src/eth/MAC_tx/MAC_tx_Ctrl.v" + xfile add "../src/eth/MAC_tx/MAC_tx_FF.v" + xfile add "../src/eth/MAC_tx/MAC_tx_addr_add.v" + xfile add "../src/eth/MAC_tx/Ramdon_gen.v" + xfile add "../src/eth/MAC_tx/flow_ctrl.v" + xfile add "../src/eth/Phy_int.v" + xfile add "../src/eth/RMON.v" + xfile add "../src/eth/RMON/RMON_addr_gen.v" + xfile add "../src/eth/RMON/RMON_ctrl.v" + xfile add "../src/eth/RMON/RMON_dpram.v" + xfile add "../src/eth/TECH/xilinx/CLK_DIV2.v" + xfile add "../src/eth/TECH/xilinx/CLK_SWITCH.v" + xfile add "../src/eth/TECH/xilinx/duram.v" + xfile add "../src/eth/afifo.v" + xfile add "../src/eth/eth_miim.v" + xfile add "../src/eth/miim/eth_clockgen.v" + xfile add "../src/eth/miim/eth_outputcontrol.v" + xfile add "../src/eth/miim/eth_shiftreg.v" + xfile add "../src/eth/miim/timescale.v" + xfile add "./reg_int.v" + xfile add "../src/common/eth_receiver.vhd" + xfile add "../src/common/eth_sender.vhd" + xfile add "./sp601_eth.ucf" + xfile add "./sp601_eth_top.vhd" + puts "" + puts "WARNING: project contains IP cores, synthesis will fail if any of the cores require regenerating." + puts "" + + # Set the Top Module as well... + project set top "beh" "sp601_eth" + + puts "$myScript: project sources reloaded." + +} ; # end add_source_files + +# +# create_libraries +# +# This procedure defines VHDL libraries and associates files with those libraries. +# It is expected to be used when recreating the project. Any libraries defined +# when this script was generated are recreated by this procedure. +# +proc create_libraries {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Creating libraries..." + + + # must close the project or library definitions aren't saved. + project save + +} ; # end create_libraries + +# +# set_process_props +# +# This procedure sets properties as requested during script generation (either +# all of the properties, or only those modified from their defaults). +# +proc set_process_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: setting process properties..." + + project set "Compiled Library Directory" "\$XILINX//" + project set "Global Optimization" "Off" -process "Map" + project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map" + project set "Place And Route Mode" "Route Only" -process "Place & Route" + project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core" + project set "Filter Files From Compile Order" "true" + project set "Last Applied Goal" "Balanced" + project set "Last Applied Strategy" "Xilinx Default (unlocked)" + project set "Last Unlock Status" "false" + project set "Manual Compile Order" "false" + project set "Placer Effort Level" "High" -process "Map" + project set "Extra Cost Tables" "0" -process "Map" + project set "LUT Combining" "Off" -process "Map" + project set "Combinatorial Logic Optimization" "true" -process "Map" + project set "Starting Placer Cost Table (1-100)" "1" -process "Map" + project set "Power Reduction" "Off" -process "Map" + project set "Overwrite Existing Symbol" "false" -process "Create Schematic Symbol" + project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing" + project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing" + project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing" + project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing" + project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing" + project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing" + project set "Project Description" "" + project set "Property Specification in Project File" "Store all values" + project set "Reduce Control Sets" "Auto" -process "Synthesize - XST" + project set "Shift Register Minimum Size" "2" -process "Synthesize - XST" + project set "Case Implementation Style" "None" -process "Synthesize - XST" + project set "RAM Extraction" "true" -process "Synthesize - XST" + project set "ROM Extraction" "true" -process "Synthesize - XST" + project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" + project set "Optimization Goal" "Speed" -process "Synthesize - XST" + project set "Optimization Effort" "High" -process "Synthesize - XST" + project set "Resource Sharing" "true" -process "Synthesize - XST" + project set "Shift Register Extraction" "true" -process "Synthesize - XST" + project set "User Browsed Strategy Files" "" + project set "VHDL Source Analysis Standard" "VHDL-93" + project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report" + project set "Input TCL Command Script" "" -process "Generate Text Power Report" + project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report" + project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Simulation File" "Default" -process "Generate Text Power Report" + project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Setting File" "" -process "Generate Text Power Report" + project set "Setting Output File" "" -process "Generate Text Power Report" + project set "Produce Verbose Report" "false" -process "Generate Text Power Report" + project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report" + project set "Essential Bits" "false" -process "Generate Programming File" + project set "Other Bitgen Command Line Options" "" -process "Generate Programming File" + project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model" + project set "Show All Models" "false" -process "Generate IBIS Model" + project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model" + project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model" + project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream" + project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream" + project set "Target UCF File Name" "" -process "Back-annotate Pin Locations" + project set "Ignore User Timing Constraints" "false" -process "Map" + project set "Register Ordering" "4" -process "Map" + project set "Use RLOC Constraints" "Yes" -process "Map" + project set "Other Map Command Line Options" "" -process "Map" + project set "Use LOC Constraints" "true" -process "Translate" + project set "Other Ngdbuild Command Line Options" "" -process "Translate" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis" + project set "Ignore User Timing Constraints" "false" -process "Place & Route" + project set "Other Place & Route Command Line Options" "" -process "Place & Route" + project set "Use DSP Block" "Auto" -process "Synthesize - XST" + project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" + project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" + project set "Enable External Master Clock" "false" -process "Generate Programming File" + project set "Create ASCII Configuration File" "false" -process "Generate Programming File" + project set "Create Bit File" "true" -process "Generate Programming File" + project set "Enable BitStream Compression" "false" -process "Generate Programming File" + project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File" + project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File" + project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File" + project set "Create ReadBack Data Files" "false" -process "Generate Programming File" + project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" + project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File" + project set "Configuration Rate" "2" -process "Generate Programming File" + project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File" + project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" + project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File" + project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File" + project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" + project set "FPGA Start-Up Clock" "JTAG Clock" -process "Generate Programming File" + project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" + project set "Drive Done Pin High" "false" -process "Generate Programming File" + project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" + project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File" + project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" + project set "Enable Internal Done Pipe" "false" -process "Generate Programming File" + project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File" + project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File" + project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File" + project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File" + project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File" + project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File" + project set "Allow Logic Optimization Across Hierarchy" "true" -process "Map" + project set "Maximum Compression" "false" -process "Map" + project set "Generate Detailed MAP Report" "false" -process "Map" + project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map" + project set "Perform Timing-Driven Packing and Placement" "false" + project set "Trim Unconnected Signals" "true" -process "Map" + project set "Create I/O Pads from Ports" "false" -process "Translate" + project set "Macro Search Path" "" -process "Translate" + project set "Netlist Translation Type" "Timestamp" -process "Translate" + project set "User Rules File for Netlister Launcher" "" -process "Translate" + project set "Allow Unexpanded Blocks" "false" -process "Translate" + project set "Allow Unmatched LOC Constraints" "false" -process "Translate" + project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate" + project set "Perform Advanced Analysis" "true" -process "Generate Post-Place & Route Static Timing" + project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing" + project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing" + project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing" + project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing" + project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing" + project set "Perform Advanced Analysis" "true" -process "Generate Post-Map Static Timing" + project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing" + project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing" + project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing" + project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing" + project set "Number of Clock Buffers" "4" -process "Synthesize - XST" + project set "Add I/O Buffers" "true" -process "Synthesize - XST" + project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" + project set "Keep Hierarchy" "Yes" -process "Synthesize - XST" + project set "Max Fanout" "100000" -process "Synthesize - XST" + project set "Register Balancing" "Yes" -process "Synthesize - XST" + project set "Register Duplication" "true" -process "Synthesize - XST" + project set "Library for Verilog Sources" "" -process "Synthesize - XST" + project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report" + project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST" + project set "Automatic BRAM Packing" "false" -process "Synthesize - XST" + project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" + project set "Bus Delimiter" "<>" -process "Synthesize - XST" + project set "Case" "Maintain" -process "Synthesize - XST" + project set "Cores Search Directories" "" -process "Synthesize - XST" + project set "Cross Clock Analysis" "false" -process "Synthesize - XST" + project set "DSP Utilization Ratio" "100" -process "Synthesize - XST" + project set "Equivalent Register Removal" "true" -process "Synthesize - XST" + project set "FSM Style" "LUT" -process "Synthesize - XST" + project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" + project set "Generics, Parameters" "" -process "Synthesize - XST" + project set "Hierarchy Separator" "/" -process "Synthesize - XST" + project set "HDL INI File" "" -process "Synthesize - XST" + project set "LUT Combining" "Auto" -process "Synthesize - XST" + project set "Library Search Order" "" -process "Synthesize - XST" + project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" + project set "Optimize Instantiated Primitives" "true" -process "Synthesize - XST" + project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" + project set "Power Reduction" "false" -process "Synthesize - XST" + project set "Read Cores" "true" -process "Synthesize - XST" + project set "Use Clock Enable" "Auto" -process "Synthesize - XST" + project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST" + project set "Use Synchronous Set" "Auto" -process "Synthesize - XST" + project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST" + project set "Verilog Include Directories" "" -process "Synthesize - XST" + project set "Verilog Macros" "" -process "Synthesize - XST" + project set "Work Directory" "./xst" -process "Synthesize - XST" + project set "Write Timing Constraints" "false" -process "Synthesize - XST" + project set "Other XST Command Line Options" "" -process "Synthesize - XST" + project set "Timing Mode" "Performance Evaluation" -process "Map" + project set "Generate Asynchronous Delay Report" "false" -process "Place & Route" + project set "Generate Clock Region Report" "false" -process "Place & Route" + project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route" + project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route" + project set "Power Reduction" "false" -process "Place & Route" + project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route" + project set "Auto Implementation Compile Order" "true" + project set "Equivalent Register Removal" "true" -process "Map" + project set "Placer Extra Effort" "None" -process "Map" + project set "Power Activity File" "" -process "Map" + project set "Register Duplication" "On" -process "Map" + project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing" + project set "Synthesis Constraints File" "" -process "Synthesize - XST" + project set "RAM Style" "Auto" -process "Synthesize - XST" + project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report" + project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File" + project set "Output File Name" "sp601_eth" -process "Generate IBIS Model" + project set "Timing Mode" "Performance Evaluation" -process "Place & Route" + project set "Create Binary Configuration File" "false" -process "Generate Programming File" + project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File" + project set "Create Logic Allocation File" "false" -process "Generate Programming File" + project set "Create Mask File" "false" -process "Generate Programming File" + project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File" + project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File" + project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File" + project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File" + project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File" + project set "Setup External Master Clock Division" "1" -process "Generate Programming File" + project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File" + project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File" + project set "Enable Multi-Threading" "2" -process "Map" + project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing" + project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST" + project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST" + project set "ROM Style" "Auto" -process "Synthesize - XST" + project set "Safe Implementation" "No" -process "Synthesize - XST" + project set "Power Activity File" "" -process "Place & Route" + project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route" + project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File" + project set "Encrypt Bitstream" "false" -process "Generate Programming File" + project set "Enable Multi-Threading" "Off" -process "Place & Route" + project set "AES Initial Vector" "" -process "Generate Programming File" + project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File" + project set "AES Key (Hex String)" "" -process "Generate Programming File" + project set "Input Encryption Key File" "" -process "Generate Programming File" + project set "Functional Model Target Language" "VHDL" -process "View HDL Source" + project set "Change Device Speed To" "-2" -process "Generate Post-Place & Route Static Timing" + project set "Change Device Speed To" "-2" -process "Generate Post-Map Static Timing" + + puts "$myScript: project property values set." + +} ; # end set_process_props + +proc main {} { + + if { [llength $::argv] == 0 } { + show_help + return true + } + + foreach option $::argv { + switch $option { + "show_help" { show_help } + "run_process" { run_process } + "rebuild_project" { rebuild_project } + "set_project_props" { set_project_props } + "add_source_files" { add_source_files } + "create_libraries" { create_libraries } + "set_process_props" { set_process_props } + default { puts "unrecognized option: $option"; show_help } + } + } +} + +if { $tcl_interactive } { + show_help +} else { + if {[catch {main} result]} { + puts "$myScript failed: $result." + } +} + Index: trunk/FPGA/sp601/sp601_eth_top.vhd =================================================================== --- trunk/FPGA/sp601/sp601_eth_top.vhd (nonexistent) +++ trunk/FPGA/sp601/sp601_eth_top.vhd (revision 2) @@ -0,0 +1,610 @@ +------------------------------------------------------------------------------- +-- Title : L3 FADE protocol demo for SP601 board +-- Project : +------------------------------------------------------------------------------- +-- File : sp601_eth_top.vhd +-- Author : Wojciech M. Zabolotny +-- License : BSD License +-- Company : +-- Created : 2010-08-03 +-- Last update: 2012-05-03 +-- Platform : +-- Standard : VHDL +------------------------------------------------------------------------------- +-- Description: +-- This file implements the top entity, integrating all component +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +-- This is public domain code!!! +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2010-08-03 1.0 wzab Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +entity sp601_eth is + + port ( + cpu_reset : in std_logic; +-- -- DDR2 interface +-- ddr2_a : out std_logic_vector(12 downto 0); +-- ddr2_ba : out std_logic_vector(2 downto 0); +-- ddr2_cas_b : out std_logic; +-- ddr2_cke : out std_logic; +-- ddr2_clk_n : out std_logic; +-- ddr2_clk_p : out std_logic; +-- ddr2_dq : inout std_logic_vector(15 downto 0); +-- ddr2_ldm : out std_logic; +-- ddr2_ldqs_n : out std_logic; +-- ddr2_ldqs_p : out std_logic; +-- ddr2_odt : out std_logic; +-- ddr2_ras_b : out std_logic; +-- ddr2_udm : out std_logic; +-- ddr2_udqs_n : out std_logic; +-- ddr2_udqs_p : out std_logic; +-- ddr2_we_b : out std_logic; +-- -- FLASH interface +-- flash_a : out std_logic_vector(24 downto 0); + flash_ce_b : out std_logic; +-- flash_d : inout std_logic_vector(7 downto 0); + flash_oe_b : out std_logic; + flash_we_b : out std_logic; +-- -- FMC interface +-- fmc_la28_n : out std_logic; +-- fmc_la28_p : out std_logic; +-- fmc_la29_n : out std_logic; +-- fmc_la29_p : out std_logic; +-- fmc_la30_n : out std_logic; +-- fmc_la30_p : out std_logic; +-- fmc_la31_n : out std_logic; +-- fmc_la31_p : out std_logic; + iic_scl_main : out std_logic; + iic_sda_main : out std_logic; + + gpio_hdr0 : in std_logic; + gpio_hdr1 : in std_logic; + gpio_hdr2 : in std_logic; + gpio_hdr3 : in std_logic; + gpio_hdr4 : in std_logic; + gpio_hdr5 : in std_logic; + gpio_hdr6 : in std_logic; + gpio_hdr7 : in std_logic; + +-- fmc_clk0_m2c_n : out std_logic; +-- fmc_clk0_m2c_p : out std_logic; +-- fmc_clk1_m2c_n : out std_logic; +-- fmc_clk1_m2c_p : out std_logic; +-- fmc_la00_cc_n : out std_logic; +-- fmc_la00_cc_p : out std_logic; +-- fmc_la01_cc_n : out std_logic; +-- fmc_la01_cc_p : out std_logic; +-- fmc_la02_n : out std_logic; +-- fmc_la02_p : out std_logic; +-- fmc_la03_n : out std_logic; +-- fmc_la03_p : out std_logic; +-- fmc_la04_n : out std_logic; +-- fmc_la04_p : out std_logic; +-- led : out std_logic_vector(3 downto 0); + switches : in std_logic_vector(3 downto 0); +-- flash_oen : out std_logic; +-- flash_wen : out std_logic; +-- flash_cen : out std_logic; + gpio_led : out std_logic_vector(3 downto 0); + -- PHY interface + phy_col : in std_logic; + phy_crs : in std_logic; + phy_int : in std_logic; + phy_mdc : out std_logic; + phy_mdio : inout std_logic; + phy_reset : out std_logic; + phy_rxclk : in std_logic; + phy_rxctl_rxdv : in std_logic; + phy_rxd : in std_logic_vector(7 downto 0); + phy_rxer : in std_logic; + phy_txclk : in std_logic; + phy_txctl_txen : out std_logic; + phy_txc_gtxclk : out std_logic; + phy_txd : out std_logic_vector(7 downto 0); + phy_txer : out std_logic; + sysclk_n : in std_logic; + sysclk_p : in std_logic + ); + +end sp601_eth; + +architecture beh of sp601_eth is + + component dp_ram_scl + generic ( + DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + clk : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); + end component; + + component ack_fifo + port ( + clk : in std_logic; + rst : in std_logic; + din : in std_logic_vector(pkt_ack_width-1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(pkt_ack_width-1 downto 0); + full : out std_logic; + empty : out std_logic); + end component; + + component dcm1 + port + ( -- Clock in ports + CLK_IN1_P : in std_logic; + CLK_IN1_N : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + CLK_OUT3 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); + end component; + + component desc_manager + generic ( + N_OF_PKTS : integer); + port ( + dta : in std_logic_vector(31 downto 0); + dta_we : in std_logic; + dta_ready : out std_logic; + set_number : out unsigned(15 downto 0); + pkt_number : out unsigned(15 downto 0); + snd_start : out std_logic; + snd_ready : in std_logic; + dmem_addr : out std_logic_vector(13 downto 0); + dmem_dta : out std_logic_vector(31 downto 0); + dmem_we : out std_logic; + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic); + end component; + + component eth_sender + port ( + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + set_number : in unsigned(15 downto 0); + pkt_number : in unsigned(15 downto 0); + retry_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic; + ready : out std_logic; + start : in std_logic; + tx_mem_addr : out std_logic_vector(13 downto 0); + tx_mem_data : in std_logic_vector(31 downto 0); + Tx_mac_wa : in std_logic; + Tx_mac_wr : out std_logic; + Tx_mac_data : out std_logic_vector(31 downto 0); + Tx_mac_BE : out std_logic_vector(1 downto 0); + Tx_mac_sop : out std_logic; + Tx_mac_eop : out std_logic); + end component; + + component eth_receiver + port ( + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + clk : in std_logic; + rst_n : in std_logic; + Rx_mac_pa : in std_logic; + Rx_mac_ra : in std_logic; + Rx_mac_rd : out std_logic; + Rx_mac_data : in std_logic_vector(31 downto 0); + Rx_mac_BE : in std_logic_vector(1 downto 0); + Rx_mac_sop : in std_logic; + Rx_mac_eop : in std_logic); + end component; + + component jtag_bus_ctl + generic ( + d_width : integer; + a_width : integer); + port ( + din : in std_logic_vector((d_width-1) downto 0); + dout : out std_logic_vector((d_width-1) downto 0); + addr : out std_logic_vector((a_width-1) downto 0); + nwr : out std_logic; + nrd : out std_logic); + end component; + + component MAC_top + port ( + --system signals + Reset : in std_logic; + Clk_125M : in std_logic; + Clk_user : in std_logic; + Clk_reg : in std_logic; + Speed : out std_logic_vector(2 downto 0); + --user interface + Rx_mac_ra : out std_logic; + Rx_mac_rd : in std_logic; + Rx_mac_data : out std_logic_vector(31 downto 0); + Rx_mac_BE : out std_logic_vector(1 downto 0); + Rx_mac_pa : out std_logic; + Rx_mac_sop : out std_logic; + Rx_mac_eop : out std_logic; + --user interface + Tx_mac_wa : out std_logic; + Tx_mac_wr : in std_logic; + Tx_mac_data : in std_logic_vector(31 downto 0); + Tx_mac_BE : in std_logic_vector(1 downto 0); + Tx_mac_sop : in std_logic; + Tx_mac_eop : in std_logic; + -- pkg_lgth fifo + Pkg_lgth_fifo_rd : in std_logic; + Pkg_lgth_fifo_ra : out std_logic; + Pkg_lgth_fifo_data : out std_logic_vector(15 downto 0); + --Phy interface + Gtx_clk : out std_logic; -- used only in GMII mode + Rx_clk : in std_logic; + Tx_clk : in std_logic; -- used only in MII mode + Tx_er : out std_logic; + Tx_en : out std_logic; + Txd : out std_logic_vector(7 downto 0); + Rx_er : in std_logic; + Rx_dv : in std_logic; + Rxd : in std_logic_vector(7 downto 0); + Crs : in std_logic; + Col : in std_logic; + -- host interface + CSB : in std_logic; + WRB : in std_logic; + CD_in : in std_logic_vector(15 downto 0); + CD_out : out std_logic_vector(15 downto 0); + CA : in std_logic_vector(7 downto 0); + -- mdx + Mdo : out std_logic; -- MII Management Data Output + MdoEn : out std_logic; -- MII Management Data Output Enable + Mdi : in std_logic; + Mdc : out std_logic -- MII Management Data Clock + ); + end component; + + signal my_mac : std_logic_vector(47 downto 0); + constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; + signal transm_delay : unsigned(31 downto 0); + signal restart : std_logic; + signal dta : std_logic_vector(31 downto 0); + signal dta_we : std_logic := '0'; + signal dta_ready : std_logic; + signal snd_start : std_logic; + signal snd_ready : std_logic; + signal dmem_addr : std_logic_vector(13 downto 0); + signal dmem_dta : std_logic_vector(31 downto 0); + signal dmem_we : std_logic; + signal addr_a, addr_b : integer; + signal test_dta : unsigned(31 downto 0); + signal tx_mem_addr : std_logic_vector(13 downto 0); + signal tx_mem_data : std_logic_vector(31 downto 0); + + signal arg1, arg2, res1 : unsigned(7 downto 0); + signal res2 : unsigned(15 downto 0); + signal sender : std_logic_vector(47 downto 0); + signal peer_mac : std_logic_vector(47 downto 0); + signal inputs, din, dout : std_logic_vector(7 downto 0); + signal addr, leds : std_logic_vector(3 downto 0); + signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic; + signal not_cpu_reset, rst_del : std_logic; + + signal set_number : unsigned(15 downto 0); + signal pkt_number : unsigned(15 downto 0); + signal retry_number : unsigned(15 downto 0) := (others => '0'); + signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); + + + signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); + signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; + signal transmit_data : std_logic := '0'; + + signal read_addr : std_logic_vector(15 downto 0); + signal read_data : std_logic_vector(15 downto 0); + signal read_done, read_in_progress : std_logic; + + + signal led_counter : integer := 0; + signal tx_counter : integer := 10000; + signal sysclk : std_logic; + signal Reset : std_logic; + signal Clk_125M : std_logic; + signal Clk_user : std_logic; + signal Clk_reg : std_logic; + signal Speed : std_logic_vector(2 downto 0); + signal Rx_mac_ra : std_logic; + signal Rx_mac_rd : std_logic; + signal Rx_mac_data : std_logic_vector(31 downto 0); + signal Rx_mac_BE : std_logic_vector(1 downto 0); + signal Rx_mac_pa : std_logic; + signal Rx_mac_sop : std_logic; + signal Rx_mac_eop : std_logic; + signal Tx_mac_wa : std_logic; + signal Tx_mac_wr : std_logic; + signal Tx_mac_data : std_logic_vector(31 downto 0); + signal Tx_mac_BE : std_logic_vector(1 downto 0); + signal Tx_mac_sop : std_logic; + signal Tx_mac_eop : std_logic; + signal Pkg_lgth_fifo_rd : std_logic; + signal Pkg_lgth_fifo_ra : std_logic; + signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0); + signal Gtx_clk : std_logic; + signal Rx_clk : std_logic; + signal Tx_clk : std_logic; + signal Tx_er : std_logic; + signal Tx_en : std_logic; + signal Txd : std_logic_vector(7 downto 0); + signal Rx_er : std_logic; + signal Rx_dv : std_logic; + signal Rxd : std_logic_vector(7 downto 0); + signal Crs : std_logic; + signal Col : std_logic; + signal CSB : std_logic := '1'; + signal WRB : std_logic := '1'; + signal CD_in : std_logic_vector(15 downto 0) := (others => '0'); + signal CD_out : std_logic_vector(15 downto 0) := (others => '0'); + signal CA : std_logic_vector(7 downto 0) := (others => '0'); + signal s_Mdo : std_logic; + signal s_MdoEn : std_logic; + signal s_Mdi : std_logic; + + signal s_dta_we : std_logic; + +begin -- beh + + -- Allow selection of MAC with the DIP switch to allow testing + -- with multiple boards! + with switches(1 downto 0) select + my_mac <= + x"de_ad_ba_be_be_ef" when "00", + x"de_ad_ba_be_be_e1" when "01", + x"de_ad_ba_be_be_e2" when "10", + x"de_ad_ba_be_be_e3" when "11"; + + + iic_sda_main <= 'Z'; + iic_scl_main <= 'Z'; + + not_cpu_reset <= not cpu_reset; + rst_p <= not rst_n; + + flash_oe_b <= '1'; + flash_we_b <= '1'; + flash_ce_b <= '1'; + + MAC_top_1 : MAC_top + port map ( + Reset => rst_p, + Clk_125M => Clk_125M, + Clk_user => Clk_user, + Clk_reg => Clk_user, -- was Clk_reg + Speed => Speed, + Rx_mac_ra => Rx_mac_ra, + Rx_mac_rd => Rx_mac_rd, + Rx_mac_data => Rx_mac_data, + Rx_mac_BE => Rx_mac_BE, + Rx_mac_pa => Rx_mac_pa, + Rx_mac_sop => Rx_mac_sop, + Rx_mac_eop => Rx_mac_eop, + Tx_mac_wa => Tx_mac_wa, + Tx_mac_wr => Tx_mac_wr, + Tx_mac_data => Tx_mac_data, + Tx_mac_BE => Tx_mac_BE, + Tx_mac_sop => Tx_mac_sop, + Tx_mac_eop => Tx_mac_eop, + Pkg_lgth_fifo_rd => Pkg_lgth_fifo_rd, + Pkg_lgth_fifo_ra => Pkg_lgth_fifo_ra, + Pkg_lgth_fifo_data => Pkg_lgth_fifo_data, + Gtx_clk => PHY_TXC_Gtxclk, + Rx_clk => PHY_Rxclk, + Tx_clk => PHY_Txclk, + Tx_er => PHY_Txer, + Tx_en => PHY_TXCTL_Txen, + Txd => PHY_Txd, + Rx_er => PHY_Rxer, + Rx_dv => PHY_RXCTL_Rxdv, + Rxd => PHY_Rxd, + Crs => PHY_Crs, + Col => PHY_Col, + -- Host interface + CSB => CSB, + WRB => WRB, + CD_in => CD_in, + CD_out => CD_out, + CA => CA, + -- MDI interface + Mdo => s_Mdo, + MdoEn => s_MdoEn, + Mdi => s_Mdi, + Mdc => PHY_Mdc); + + Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra; + + addr_a <= to_integer(unsigned(dmem_addr)); + addr_b <= to_integer(unsigned(tx_mem_addr)); + + dp_ram_scl_1 : dp_ram_scl + generic map ( + DATA_WIDTH => 32, + ADDR_WIDTH => 13) + port map ( + clk => clk_user, + we_a => dmem_we, + addr_a => dmem_addr(12 downto 0), + data_a => dmem_dta, + q_a => open, + we_b => '0', + addr_b => tx_mem_addr(12 downto 0), + data_b => (others => '0'), + q_b => tx_mem_data); + + desc_manager_1 : desc_manager + generic map ( + N_OF_PKTS => N_OF_PKTS) + port map ( + dta => dta, + dta_we => dta_we, + dta_ready => dta_ready, + set_number => set_number, + pkt_number => pkt_number, + snd_start => snd_start, + snd_ready => snd_ready, + dmem_addr => dmem_addr, + dmem_dta => dmem_dta, + dmem_we => dmem_we, + ack_fifo_empty => ack_fifo_empty, + ack_fifo_rd_en => ack_fifo_rd_en, + ack_fifo_dout => ack_fifo_dout, + transmit_data => transmit_data, + transm_delay => transm_delay, + clk => clk_user, + rst_n => rst_n); + + eth_sender_1 : eth_sender + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + transm_delay => transm_delay, + set_number => set_number, + pkt_number => pkt_number, + retry_number => retry_number, + clk => clk_user, + rst_n => rst_n, + ready => snd_ready, + start => snd_start, + tx_mem_addr => tx_mem_addr, + tx_mem_data => tx_mem_data, + Tx_mac_wa => Tx_mac_wa, + Tx_mac_wr => Tx_mac_wr, + Tx_mac_data => Tx_mac_data, + Tx_mac_BE => Tx_mac_BE, + Tx_mac_sop => Tx_mac_sop, + Tx_mac_eop => Tx_mac_eop); + + eth_receiver_1 : eth_receiver + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + restart => restart, + transmit_data => transmit_data, + ack_fifo_full => ack_fifo_full, + ack_fifo_wr_en => ack_fifo_wr_en, + ack_fifo_din => ack_fifo_din, + clk => clk_user, + rst_n => rst_n, + Rx_mac_pa => Rx_mac_pa, + Rx_mac_ra => Rx_mac_ra, + Rx_mac_rd => Rx_mac_rd, + Rx_mac_data => Rx_mac_data, + Rx_mac_BE => Rx_mac_BE, + Rx_mac_sop => Rx_mac_sop, + Rx_mac_eop => Rx_mac_eop); + + dcm1_1 : dcm1 + port map ( + CLK_IN1_P => sysclk_P, + CLK_IN1_N => sysclk_N, + CLK_OUT1 => Clk_125M, + CLK_OUT2 => Clk_user, + CLK_OUT3 => Clk_reg, + RESET => cpu_reset, + LOCKED => dcm_locked); + + process (Clk_user, cpu_reset) + begin -- process + if cpu_reset = '1' then -- asynchronous reset (active low) + rst_n <= '0'; + rst_del <= '0'; + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if restart = '1' then + rst_n <= '0'; + rst_del <= '0'; + else + if dcm_locked = '1' then + rst_del <= '1'; + rst_n <= rst_del; + end if; + end if; + end if; + end process; + + -- reset + + phy_reset <= rst_n; + + -- Connection of MDI + s_Mdi <= PHY_MDIO; + PHY_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo; + ack_fifo_1 : ack_fifo + port map ( + clk => Clk_user, + rst => rst_p, + din => ack_fifo_din, + wr_en => ack_fifo_wr_en, + rd_en => ack_fifo_rd_en, + dout => ack_fifo_dout, + full => ack_fifo_full, + empty => ack_fifo_empty); + + --E_TXD <= s_Txd(3 downto 0); + --s_Rxd <= "0000" & E_RXD; + + -- signal generator + + dta <= std_logic_vector(test_dta); + s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; + dta_we <= s_dta_we; + + process (Clk_user, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + test_dta <= (others => '0'); + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if s_dta_we = '1' then + test_dta <= test_dta + 1; + end if; + end if; + end process; + + -- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2)); + gpio_led(0) <= snd_ready; + gpio_led(1) <= transmit_data; + gpio_led(2) <= cpu_reset; + gpio_led(3) <= Tx_mac_wa; +end beh; Index: trunk/FPGA/sp601/reg_int.v =================================================================== --- trunk/FPGA/sp601/reg_int.v (nonexistent) +++ trunk/FPGA/sp601/reg_int.v (revision 2) @@ -0,0 +1,182 @@ +module Reg_int ( +input Reset , +input Clk_reg , +input CSB , +input WRB , +input [15:0] CD_in , +output reg [15:0] CD_out , +input [7:0] CA , + //Tx host interface +output [4:0] Tx_Hwmark , +output [4:0] Tx_Lwmark , +output pause_frame_send_en , +output [15:0] pause_quanta_set , +output MAC_tx_add_en , +output FullDuplex , +output [3:0] MaxRetry , +output [5:0] IFGset , +output [7:0] MAC_tx_add_prom_data , +output [2:0] MAC_tx_add_prom_add , +output MAC_tx_add_prom_wr , +output tx_pause_en , +output xoff_cpu , +output xon_cpu , + //Rx host interface +output MAC_rx_add_chk_en , +output [7:0] MAC_rx_add_prom_data , +output [2:0] MAC_rx_add_prom_add , +output MAC_rx_add_prom_wr , +output broadcast_filter_en , +output [15:0] broadcast_bucket_depth , +output [15:0] broadcast_bucket_interval , +output RX_APPEND_CRC , +output [4:0] Rx_Hwmark , +output [4:0] Rx_Lwmark , +output CRC_chk_en , +output [5:0] RX_IFG_SET , +output [15:0] RX_MAX_LENGTH ,// 1518 +output [6:0] RX_MIN_LENGTH ,// 64 + //RMON host interface +output [5:0] CPU_rd_addr , +output CPU_rd_apply , +input CPU_rd_grant , +input [31:0] CPU_rd_dout , + //Phy int host interface +output Line_loop_en , +output [2:0] Speed , + //MII to CPU +output [7:0] Divider ,// Divider for the host clock +output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +output [4:0] Rgad ,// Register Address (within the PHY) +output [4:0] Fiad ,// PHY Address +output NoPre ,// No Preamble (no 32-bit preamble) +output WCtrlData ,// Write Control Data operation +output RStat ,// Read Status operation +output ScanStat ,// Scan Status operation +input Busy ,// Busy Signal +input LinkFail ,// Link Integrity Signal +input Nvalid ,// Invalid Status (qualifier for the valid scan result) +input [15:0] Prsd ,// Read Status Data (data read from the PHY) +input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + +// RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +//Line below for 1Gb Ethernet + RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +//Line below for 100Mb Ethernet +// RegCPUData U_0_034(Speed ,7'd034,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + +always @ (posedge Clk_reg or posedge Reset) + if (Reset) + CD_out <=0; + else if (!CSB&&WRB) + case (CA[7:1]) + 7'd00: CD_out<=Tx_Hwmark ; + 7'd01: CD_out<=Tx_Lwmark ; + 7'd02: CD_out<=pause_frame_send_en ; + 7'd03: CD_out<=pause_quanta_set ; + 7'd04: CD_out<=IFGset ; + 7'd05: CD_out<=FullDuplex ; + 7'd06: CD_out<=MaxRetry ; + 7'd07: CD_out<=MAC_tx_add_en ; + 7'd08: CD_out<=MAC_tx_add_prom_data ; + 7'd09: CD_out<=MAC_tx_add_prom_add ; + 7'd10: CD_out<=MAC_tx_add_prom_wr ; + 7'd11: CD_out<=tx_pause_en ; + 7'd12: CD_out<=xoff_cpu ; + 7'd13: CD_out<=xon_cpu ; + 7'd14: CD_out<=MAC_rx_add_chk_en ; + 7'd15: CD_out<=MAC_rx_add_prom_data ; + 7'd16: CD_out<=MAC_rx_add_prom_add ; + 7'd17: CD_out<=MAC_rx_add_prom_wr ; + 7'd18: CD_out<=broadcast_filter_en ; + 7'd19: CD_out<=broadcast_bucket_depth ; + 7'd20: CD_out<=broadcast_bucket_interval ; + 7'd21: CD_out<=RX_APPEND_CRC ; + 7'd22: CD_out<=Rx_Hwmark ; + 7'd23: CD_out<=Rx_Lwmark ; + 7'd24: CD_out<=CRC_chk_en ; + 7'd25: CD_out<=RX_IFG_SET ; + 7'd26: CD_out<=RX_MAX_LENGTH ; + 7'd27: CD_out<=RX_MIN_LENGTH ; + 7'd28: CD_out<=CPU_rd_addr ; + 7'd29: CD_out<=CPU_rd_apply ; + 7'd30: CD_out<=CPU_rd_grant ; + 7'd31: CD_out<=CPU_rd_dout[15:0] ; + 7'd32: CD_out<=CPU_rd_dout[31:16] ; + 7'd33: CD_out<=Line_loop_en ; + 7'd34: CD_out<=Speed ; + default: CD_out<=0 ; + endcase + + +endmodule + +module RegCPUData( +RegOut, +CA_reg_set, +RegInit, + +Reset, +Clk, +CWR_pulse, +CCSB, +CA_reg, +CD_in_reg +); +output[15:0] RegOut; +input[6:0] CA_reg_set; +input[15:0] RegInit; +// +input Reset; +input Clk; +input CWR_pulse; +input CCSB; +input[7:0] CA_reg; +input[15:0] CD_in_reg; +// +reg[15:0] RegOut; + +always @(posedge Reset or posedge Clk) + if(Reset) + RegOut <=RegInit; + else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0]) + RegOut <=CD_in_reg; + +endmodule \ No newline at end of file Index: trunk/FPGA/sp601/dcm1.xco =================================================================== --- trunk/FPGA/sp601/dcm1.xco (nonexistent) +++ trunk/FPGA/sp601/dcm1.xco (revision 2) @@ -0,0 +1,266 @@ +############################################################## +# +# Xilinx Core Generator version 13.4 +# Date: Wed Aug 29 21:33:33 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx16 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.3 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=50.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=125.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=64.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=64.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=dcm1 +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLKDV +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=8 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=5.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=5 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=5.000 +CSET pll_clkout0_divide=4 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=8 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=8 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=2 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=200.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Differential_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-09T17:33:40Z +# END Extra information +GENERATE +# CRC: aacd51df Index: trunk/FPGA/atlys/atlys_eth_art.tcl =================================================================== --- trunk/FPGA/atlys/atlys_eth_art.tcl (nonexistent) +++ trunk/FPGA/atlys/atlys_eth_art.tcl (revision 2) @@ -0,0 +1,570 @@ +# +# Project automation script for atlys_eth_art +# +# Created for ISE version 13.4 +# +# This file contains several Tcl procedures (procs) that you can use to automate +# your project by running from xtclsh or the Project Navigator Tcl console. +# If you load this file (using the Tcl command: source atlys_eth_art.tcl), then you can +# run any of the procs included here. +# +# This script is generated assuming your project has HDL sources. +# Several of the defined procs won't apply to an EDIF or NGC based project. +# If that is the case, simply remove them from this script. +# +# You may also edit any of these procs to customize them. See comments in each +# proc for more instructions. +# +# This file contains the following procedures: +# +# Top Level procs (meant to be called directly by the user): +# run_process: you can use this top-level procedure to run any processes +# that you choose to by adding and removing comments, or by +# adding new entries. +# rebuild_project: you can alternatively use this top-level procedure +# to recreate your entire project, and the run selected processes. +# +# Lower Level (helper) procs (called under in various cases by the top level procs): +# show_help: print some basic information describing how this script works +# add_source_files: adds the listed source files to your project. +# set_project_props: sets the project properties that were in effect when this +# script was generated. +# create_libraries: creates and adds file to VHDL libraries that were defined when +# this script was generated. +# set_process_props: set the process properties as they were set for your project +# when this script was generated. +# + +set myProject "atlys_eth_art" +set myScript "atlys_eth_art.tcl" + +# +# Main (top-level) routines +# +# run_process +# This procedure is used to run processes on an existing project. You may comment or +# uncomment lines to control which processes are run. This routine is set up to run +# the Implement Design and Generate Programming File processes by default. This proc +# also sets process properties as specified in the "set_process_props" proc. Only +# those properties which have values different from their current settings in the project +# file will be modified in the project. +# +proc run_process {} { + + global myScript + global myProject + + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: running ($myProject)...\n" + + if { ! [ open_project ] } { + return false + } + + set_process_props + # + # Remove the comment characters (#'s) to enable the following commands + # process run "Synthesize" + # process run "Translate" + # process run "Map" + # process run "Place & Route" + # + set task "Implement Design" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + set task "Generate Programming File" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + puts "Run completed (successfully)." + project close + +} + +# +# rebuild_project +# +# This procedure renames the project file (if it exists) and recreates the project. +# It then sets project properties and adds project sources as specified by the +# set_project_props and add_source_files support procs. It recreates VHDL Libraries +# as they existed at the time this script was generated. +# +# It then calls run_process to set process properties and run selected processes. +# +proc rebuild_project {} { + + global myScript + global myProject + + project close + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: Rebuilding ($myProject)...\n" + + set proj_exts [ list ise xise gise ] + foreach ext $proj_exts { + set proj_name "${myProject}.$ext" + if { [ file exists $proj_name ] } { + file delete $proj_name + } + } + + project new $myProject + set_project_props + add_source_files + create_libraries + puts "$myScript: project rebuild completed." + + run_process + +} + +# +# Support Routines +# + +# +proc run_task { task } { + + # helper proc for run_process + + puts "Running '$task'" + set result [ process run "$task" ] + # + # check process status (and result) + set status [ process get $task status ] + if { ( ( $status != "up_to_date" ) && \ + ( $status != "warnings" ) ) || \ + ! $result } { + return false + } + return true +} + +# +# show_help: print information to help users understand the options available when +# running this script. +# +proc show_help {} { + + global myScript + + puts "" + puts "usage: xtclsh $myScript " + puts " or you can run xtclsh and then enter 'source $myScript'." + puts "" + puts "options:" + puts " run_process - set properties and run processes." + puts " rebuild_project - rebuild the project from scratch and run processes." + puts " set_project_props - set project properties (device, speed, etc.)" + puts " add_source_files - add source files" + puts " create_libraries - create vhdl libraries" + puts " set_process_props - set process property values" + puts " show_help - print this message" + puts "" +} + +proc open_project {} { + + global myScript + global myProject + + if { ! [ file exists ${myProject}.xise ] } { + ## project file isn't there, rebuild it. + puts "Project $myProject not found. Use project_rebuild to recreate it." + return false + } + + project open $myProject + + return true + +} +# +# set_project_props +# +# This procedure sets the project properties as they were set in the project +# at the time this script was generated. +# +proc set_project_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Setting project properties..." + + project set family "Spartan6" + project set device "xc6slx45" + project set package "csg324" + project set speed "-2" + project set top_level_module_type "HDL" + project set synthesis_tool "XST (VHDL/Verilog)" + project set simulator "ISim (VHDL/Verilog)" + project set "Preferred Language" "VHDL" + project set "Enable Message Filtering" "false" + +} + + +# +# add_source_files +# +# This procedure add the source files that were known to the project at the +# time this script was generated. +# +proc add_source_files {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Adding sources to project..." + + xfile add "./ack_fifo.xco" + xfile add "../src/ack_fifo/pkt_ack_pkg.vhd" + xfile add "./atlys_eth.ucf" + xfile add "./atlys_eth_top.vhd" + xfile add "./dcm1.xco" + xfile add "../src/common/desc_manager_simple.vhd" + xfile add "../src/common/dpram_inf.vhd" + xfile add "../src/eth/Clk_ctrl.v" + xfile add "../src/eth/MAC_rx.v" + xfile add "../src/eth/MAC_rx/Broadcast_filter.v" + xfile add "../src/eth/MAC_rx/CRC_chk.v" + xfile add "../src/eth/MAC_rx/MAC_rx_FF.v" + xfile add "../src/eth/MAC_rx/MAC_rx_add_chk.v" + xfile add "../src/eth/MAC_rx/MAC_rx_ctrl.v" + xfile add "../src/eth/MAC_top.v" + xfile add "../src/eth/MAC_tx.v" + xfile add "../src/eth/MAC_tx/CRC_gen.v" + xfile add "../src/eth/MAC_tx/MAC_tx_Ctrl.v" + xfile add "../src/eth/MAC_tx/MAC_tx_FF.v" + xfile add "../src/eth/MAC_tx/MAC_tx_addr_add.v" + xfile add "../src/eth/MAC_tx/Ramdon_gen.v" + xfile add "../src/eth/MAC_tx/flow_ctrl.v" + xfile add "../src/eth/Phy_int.v" + xfile add "../src/eth/RMON.v" + xfile add "../src/eth/RMON/RMON_addr_gen.v" + xfile add "../src/eth/RMON/RMON_ctrl.v" + xfile add "../src/eth/RMON/RMON_dpram.v" + xfile add "../src/eth/TECH/xilinx/CLK_DIV2.v" + xfile add "../src/eth/TECH/xilinx/CLK_SWITCH.v" + xfile add "../src/eth/TECH/xilinx/duram.v" + xfile add "../src/eth/afifo.v" + xfile add "../src/eth/eth_miim.v" + xfile add "../src/eth/miim/eth_clockgen.v" + xfile add "../src/eth/miim/eth_outputcontrol.v" + xfile add "../src/eth/miim/eth_shiftreg.v" + xfile add "./reg_int.v" + xfile add "../src/common/eth_receiver.vhd" + xfile add "../src/common/eth_sender.vhd" + puts "" + puts "WARNING: project contains IP cores, synthesis will fail if any of the cores require regenerating." + puts "" + + # Set the Top Module as well... + project set top "beh" "atlys_eth" + + puts "$myScript: project sources reloaded." + +} ; # end add_source_files + +# +# create_libraries +# +# This procedure defines VHDL libraries and associates files with those libraries. +# It is expected to be used when recreating the project. Any libraries defined +# when this script was generated are recreated by this procedure. +# +proc create_libraries {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Creating libraries..." + + + # must close the project or library definitions aren't saved. + project save + +} ; # end create_libraries + +# +# set_process_props +# +# This procedure sets properties as requested during script generation (either +# all of the properties, or only those modified from their defaults). +# +proc set_process_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: setting process properties..." + + project set "Compiled Library Directory" "\$XILINX//" + project set "Global Optimization" "Off" -process "Map" + project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map" + project set "Place And Route Mode" "Route Only" -process "Place & Route" + project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core" + project set "Filter Files From Compile Order" "true" + project set "Last Applied Goal" "Balanced" + project set "Last Applied Strategy" "Xilinx Default (unlocked)" + project set "Last Unlock Status" "false" + project set "Manual Compile Order" "false" + project set "Placer Effort Level" "High" -process "Map" + project set "Extra Cost Tables" "0" -process "Map" + project set "LUT Combining" "Off" -process "Map" + project set "Combinatorial Logic Optimization" "true" -process "Map" + project set "Starting Placer Cost Table (1-100)" "1" -process "Map" + project set "Power Reduction" "Off" -process "Map" + project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing" + project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing" + project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing" + project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing" + project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing" + project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing" + project set "Project Description" "" + project set "Property Specification in Project File" "Store all values" + project set "Reduce Control Sets" "Auto" -process "Synthesize - XST" + project set "Shift Register Minimum Size" "2" -process "Synthesize - XST" + project set "Case Implementation Style" "None" -process "Synthesize - XST" + project set "RAM Extraction" "true" -process "Synthesize - XST" + project set "ROM Extraction" "true" -process "Synthesize - XST" + project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" + project set "Optimization Goal" "Speed" -process "Synthesize - XST" + project set "Optimization Effort" "High" -process "Synthesize - XST" + project set "Resource Sharing" "true" -process "Synthesize - XST" + project set "Shift Register Extraction" "true" -process "Synthesize - XST" + project set "User Browsed Strategy Files" "" + project set "VHDL Source Analysis Standard" "VHDL-93" + project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report" + project set "Input TCL Command Script" "" -process "Generate Text Power Report" + project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report" + project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Simulation File" "Default" -process "Generate Text Power Report" + project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)" + project set "Load Setting File" "" -process "Generate Text Power Report" + project set "Setting Output File" "" -process "Generate Text Power Report" + project set "Produce Verbose Report" "false" -process "Generate Text Power Report" + project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report" + project set "Essential Bits" "false" -process "Generate Programming File" + project set "Other Bitgen Command Line Options" "" -process "Generate Programming File" + project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model" + project set "Show All Models" "false" -process "Generate IBIS Model" + project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model" + project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model" + project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream" + project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream" + project set "Target UCF File Name" "" -process "Back-annotate Pin Locations" + project set "Ignore User Timing Constraints" "false" -process "Map" + project set "Register Ordering" "4" -process "Map" + project set "Use RLOC Constraints" "Yes" -process "Map" + project set "Other Map Command Line Options" "" -process "Map" + project set "Use LOC Constraints" "true" -process "Translate" + project set "Other Ngdbuild Command Line Options" "" -process "Translate" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis" + project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis" + project set "Ignore User Timing Constraints" "false" -process "Place & Route" + project set "Other Place & Route Command Line Options" "" -process "Place & Route" + project set "Use DSP Block" "Auto" -process "Synthesize - XST" + project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" + project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" + project set "Enable External Master Clock" "false" -process "Generate Programming File" + project set "Create ASCII Configuration File" "false" -process "Generate Programming File" + project set "Create Bit File" "true" -process "Generate Programming File" + project set "Enable BitStream Compression" "false" -process "Generate Programming File" + project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File" + project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File" + project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File" + project set "Create ReadBack Data Files" "false" -process "Generate Programming File" + project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" + project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File" + project set "Configuration Rate" "2" -process "Generate Programming File" + project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File" + project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" + project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" + project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File" + project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File" + project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" + project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File" + project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" + project set "Drive Done Pin High" "false" -process "Generate Programming File" + project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" + project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File" + project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" + project set "Enable Internal Done Pipe" "true" -process "Generate Programming File" + project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File" + project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File" + project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File" + project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File" + project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File" + project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File" + project set "Allow Logic Optimization Across Hierarchy" "true" -process "Map" + project set "Maximum Compression" "false" -process "Map" + project set "Generate Detailed MAP Report" "false" -process "Map" + project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map" + project set "Perform Timing-Driven Packing and Placement" "false" + project set "Trim Unconnected Signals" "true" -process "Map" + project set "Create I/O Pads from Ports" "false" -process "Translate" + project set "Macro Search Path" "" -process "Translate" + project set "Netlist Translation Type" "Timestamp" -process "Translate" + project set "User Rules File for Netlister Launcher" "" -process "Translate" + project set "Allow Unexpanded Blocks" "false" -process "Translate" + project set "Allow Unmatched LOC Constraints" "false" -process "Translate" + project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate" + project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing" + project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing" + project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing" + project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing" + project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing" + project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing" + project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing" + project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing" + project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing" + project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing" + project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing" + project set "Number of Clock Buffers" "16" -process "Synthesize - XST" + project set "Add I/O Buffers" "true" -process "Synthesize - XST" + project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" + project set "Keep Hierarchy" "Yes" -process "Synthesize - XST" + project set "Max Fanout" "100000" -process "Synthesize - XST" + project set "Register Balancing" "Yes" -process "Synthesize - XST" + project set "Register Duplication" "true" -process "Synthesize - XST" + project set "Library for Verilog Sources" "" -process "Synthesize - XST" + project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report" + project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST" + project set "Automatic BRAM Packing" "false" -process "Synthesize - XST" + project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" + project set "Bus Delimiter" "<>" -process "Synthesize - XST" + project set "Case" "Maintain" -process "Synthesize - XST" + project set "Cores Search Directories" "" -process "Synthesize - XST" + project set "Cross Clock Analysis" "false" -process "Synthesize - XST" + project set "DSP Utilization Ratio" "100" -process "Synthesize - XST" + project set "Equivalent Register Removal" "true" -process "Synthesize - XST" + project set "FSM Style" "LUT" -process "Synthesize - XST" + project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" + project set "Generics, Parameters" "" -process "Synthesize - XST" + project set "Hierarchy Separator" "/" -process "Synthesize - XST" + project set "HDL INI File" "" -process "Synthesize - XST" + project set "LUT Combining" "Auto" -process "Synthesize - XST" + project set "Library Search Order" "" -process "Synthesize - XST" + project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" + project set "Optimize Instantiated Primitives" "true" -process "Synthesize - XST" + project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" + project set "Power Reduction" "false" -process "Synthesize - XST" + project set "Read Cores" "true" -process "Synthesize - XST" + project set "Use Clock Enable" "Auto" -process "Synthesize - XST" + project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST" + project set "Use Synchronous Set" "Auto" -process "Synthesize - XST" + project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST" + project set "Verilog Include Directories" "" -process "Synthesize - XST" + project set "Verilog Macros" "" -process "Synthesize - XST" + project set "Work Directory" "./xst" -process "Synthesize - XST" + project set "Write Timing Constraints" "false" -process "Synthesize - XST" + project set "Other XST Command Line Options" "" -process "Synthesize - XST" + project set "Timing Mode" "Performance Evaluation" -process "Map" + project set "Generate Asynchronous Delay Report" "false" -process "Place & Route" + project set "Generate Clock Region Report" "false" -process "Place & Route" + project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route" + project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route" + project set "Power Reduction" "false" -process "Place & Route" + project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route" + project set "Auto Implementation Compile Order" "true" + project set "Equivalent Register Removal" "true" -process "Map" + project set "Placer Extra Effort" "None" -process "Map" + project set "Power Activity File" "" -process "Map" + project set "Register Duplication" "On" -process "Map" + project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing" + project set "Synthesis Constraints File" "" -process "Synthesize - XST" + project set "RAM Style" "Auto" -process "Synthesize - XST" + project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report" + project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File" + project set "Output File Name" "sp601_eth" -process "Generate IBIS Model" + project set "Timing Mode" "Performance Evaluation" -process "Place & Route" + project set "Create Binary Configuration File" "false" -process "Generate Programming File" + project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File" + project set "Create Logic Allocation File" "false" -process "Generate Programming File" + project set "Create Mask File" "false" -process "Generate Programming File" + project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File" + project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File" + project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File" + project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File" + project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File" + project set "Setup External Master Clock Division" "1" -process "Generate Programming File" + project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File" + project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File" + project set "Enable Multi-Threading" "2" -process "Map" + project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing" + project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST" + project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST" + project set "ROM Style" "Auto" -process "Synthesize - XST" + project set "Safe Implementation" "No" -process "Synthesize - XST" + project set "Power Activity File" "" -process "Place & Route" + project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route" + project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File" + project set "Encrypt Bitstream" "false" -process "Generate Programming File" + project set "Enable Multi-Threading" "Off" -process "Place & Route" + project set "AES Initial Vector" "" -process "Generate Programming File" + project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File" + project set "AES Key (Hex String)" "" -process "Generate Programming File" + project set "Input Encryption Key File" "" -process "Generate Programming File" + project set "Functional Model Target Language" "VHDL" -process "View HDL Source" + project set "Change Device Speed To" "-2" -process "Generate Post-Place & Route Static Timing" + project set "Change Device Speed To" "-2" -process "Generate Post-Map Static Timing" + + puts "$myScript: project property values set." + +} ; # end set_process_props + +proc main {} { + + if { [llength $::argv] == 0 } { + show_help + return true + } + + foreach option $::argv { + switch $option { + "show_help" { show_help } + "run_process" { run_process } + "rebuild_project" { rebuild_project } + "set_project_props" { set_project_props } + "add_source_files" { add_source_files } + "create_libraries" { create_libraries } + "set_process_props" { set_process_props } + default { puts "unrecognized option: $option"; show_help } + } + } +} + +if { $tcl_interactive } { + show_help +} else { + if {[catch {main} result]} { + puts "$myScript failed: $result." + } +} + Index: trunk/FPGA/atlys/build.sh =================================================================== --- trunk/FPGA/atlys/build.sh (nonexistent) +++ trunk/FPGA/atlys/build.sh (revision 2) @@ -0,0 +1,4 @@ +#!/bin/bash +coregen -r -b dcm1.xco -p coregen.cgp +coregen -r -b ack_fifo.xco -p coregen.cgp +xtclsh atlys_eth_art.tcl rebuild_project
trunk/FPGA/atlys/build.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/FPGA/atlys/atlys_eth.ucf =================================================================== --- trunk/FPGA/atlys/atlys_eth.ucf (nonexistent) +++ trunk/FPGA/atlys/atlys_eth.ucf (revision 2) @@ -0,0 +1,90 @@ +#@ NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10 +#@ NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10 +#@ NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10 +NET "GPIO_LED<0>" LOC = "U18"; ## 2 on DS11 LED +NET "GPIO_LED<1>" LOC = "M14"; ## 2 on DS12 LED +NET "GPIO_LED<2>" LOC = "N14"; ## 2 on DS13 LED +NET "GPIO_LED<3>" LOC = "L14"; ## 2 on DS14 LED +NET "GPIO_LED<4>" LOC = "M13"; ## 2 on DS11 LED +NET "GPIO_LED<5>" LOC = "D4"; ## 2 on DS12 LED +NET "GPIO_LED<6>" LOC = "P16"; ## 2 on DS13 LED +NET "GPIO_LED<7>" LOC = "N12"; ## 2 on DS14 LED + +NET "SWITCHES<0>" LOC = "A10"; +NET "SWITCHES<1>" LOC = "D14"; +NET "SWITCHES<2>" LOC = "C14"; +NET "SWITCHES<3>" LOC = "P15"; +NET "SWITCHES<4>" LOC = "P12"; +NET "SWITCHES<5>" LOC = "R5"; +NET "SWITCHES<6>" LOC = "T5"; +NET "SWITCHES<7>" LOC = "E4"; + +## +NET "CPU_RESET" LOC = "T15"; ## 2 on SW9 pushbutton +## +NET "PHY_COL" LOC = "C17"; ## 114 on U3 +NET "PHY_CRS" LOC = "C18"; ## 115 on U3 +NET "PHY_INT" LOC = "L16"; ## 32 on U3 +NET "PHY_MDC" LOC = "F16"; ## 35 on U3 +NET "PHY_MDIO" LOC = "N17"; ## 33 on U3 +NET "PHY_RESET" LOC = "G13"; ## 36 on U3 +NET "PHY_RXCLK" LOC = "K15"; ## 7 on U3 +NET "PHY_RXCTL_RXDV" LOC = "F17"; ## 4 on U3 +NET "PHY_RXD<0>" LOC = "G16"; ## 3 on U3 +NET "PHY_RXD<1>" LOC = "H14"; ## 128 on U3 +NET "PHY_RXD<2>" LOC = "E16"; ## 126 on U3 +NET "PHY_RXD<3>" LOC = "F15"; ## 125 on U3 +NET "PHY_RXD<4>" LOC = "F14"; ## 124 on U3 +NET "PHY_RXD<5>" LOC = "E18"; ## 123 on U3 +NET "PHY_RXD<6>" LOC = "D18"; ## 121 on U3 +NET "PHY_RXD<7>" LOC = "D17"; ## 120 on U3 +NET "PHY_RXER" LOC = "F18"; ## 8 on U3 +NET "PHY_TXCLK" LOC = "K16"; ## 10 on U3 +NET "PHY_TXCTL_TXEN" LOC = "H15"; ## 16 on U3 +NET "PHY_TXC_GTXCLK" LOC = "L12"; ## 14 on U3 +NET "PHY_TXD<0>" LOC = "H16"; ## 18 on U3 +NET "PHY_TXD<1>" LOC = "H13"; ## 19 on U3 +NET "PHY_TXD<2>" LOC = "K14"; ## 20 on U3 +NET "PHY_TXD<3>" LOC = "K13"; ## 24 on U3 +NET "PHY_TXD<4>" LOC = "J13"; ## 25 on U3 +NET "PHY_TXD<5>" LOC = "G14"; ## 26 on U3 +NET "PHY_TXD<6>" LOC = "H12"; ## 28 on U3 +NET "PHY_TXD<7>" LOC = "K12"; ## 29 on U3 +NET "PHY_TXER" LOC = "G18"; ## 13 on U3 +## +NET "SYSCLK" LOC = "L15"; +## +#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1 +#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1 +#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1 +#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1 +#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1 +#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1 +#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1 +#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1 +# +#@ NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm) +#@ NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm) +#@ NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm) +#@ NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm) +#@ NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm) +#@ NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm) +#@ NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm) +#@ NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm) +# +#@ NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16 +#@ NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16 +# +#@ PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; + +#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04 +NET "sysclk" TNM_NET = sysclk; +TIMESPEC TS_sysclk = PERIOD "sysclk" 10 ns HIGH 50%; +#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30 +NET "phy_rxclk" TNM_NET = phy_rxclk; +TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%; +NET "phy_txclk" TNM_NET = phy_txclk; +TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 40 ns HIGH 50%; +NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk; +TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%; Index: trunk/FPGA/atlys/ack_fifo.xco =================================================================== --- trunk/FPGA/atlys/ack_fifo.xco (nonexistent) +++ trunk/FPGA/atlys/ack_fifo.xco (revision 2) @@ -0,0 +1,91 @@ +############################################################## +# +# Xilinx Core Generator version 13.4 +# Date: Mon Aug 27 20:35:07 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=ack_fifo +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Common_Clock_Block_RAM +CSET full_flags_reset_value=0 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=32 +CSET input_depth=1024 +CSET output_data_width=32 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=11 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=11 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-01-07T15:29:19Z +# END Extra information +GENERATE +# CRC: 7cdf8a25 Index: trunk/FPGA/atlys/coregen.cgp =================================================================== --- trunk/FPGA/atlys/coregen.cgp (nonexistent) +++ trunk/FPGA/atlys/coregen.cgp (revision 2) @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = csg324 +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true Index: trunk/FPGA/atlys/reg_int.v =================================================================== --- trunk/FPGA/atlys/reg_int.v (nonexistent) +++ trunk/FPGA/atlys/reg_int.v (revision 2) @@ -0,0 +1,182 @@ +module Reg_int ( +input Reset , +input Clk_reg , +input CSB , +input WRB , +input [15:0] CD_in , +output reg [15:0] CD_out , +input [7:0] CA , + //Tx host interface +output [4:0] Tx_Hwmark , +output [4:0] Tx_Lwmark , +output pause_frame_send_en , +output [15:0] pause_quanta_set , +output MAC_tx_add_en , +output FullDuplex , +output [3:0] MaxRetry , +output [5:0] IFGset , +output [7:0] MAC_tx_add_prom_data , +output [2:0] MAC_tx_add_prom_add , +output MAC_tx_add_prom_wr , +output tx_pause_en , +output xoff_cpu , +output xon_cpu , + //Rx host interface +output MAC_rx_add_chk_en , +output [7:0] MAC_rx_add_prom_data , +output [2:0] MAC_rx_add_prom_add , +output MAC_rx_add_prom_wr , +output broadcast_filter_en , +output [15:0] broadcast_bucket_depth , +output [15:0] broadcast_bucket_interval , +output RX_APPEND_CRC , +output [4:0] Rx_Hwmark , +output [4:0] Rx_Lwmark , +output CRC_chk_en , +output [5:0] RX_IFG_SET , +output [15:0] RX_MAX_LENGTH ,// 1518 +output [6:0] RX_MIN_LENGTH ,// 64 + //RMON host interface +output [5:0] CPU_rd_addr , +output CPU_rd_apply , +input CPU_rd_grant , +input [31:0] CPU_rd_dout , + //Phy int host interface +output Line_loop_en , +output [2:0] Speed , + //MII to CPU +output [7:0] Divider ,// Divider for the host clock +output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +output [4:0] Rgad ,// Register Address (within the PHY) +output [4:0] Fiad ,// PHY Address +output NoPre ,// No Preamble (no 32-bit preamble) +output WCtrlData ,// Write Control Data operation +output RStat ,// Read Status operation +output ScanStat ,// Scan Status operation +input Busy ,// Busy Signal +input LinkFail ,// Link Integrity Signal +input Nvalid ,// Invalid Status (qualifier for the valid scan result) +input [15:0] Prsd ,// Read Status Data (data read from the PHY) +input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + +// RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +//Line below for 1Gb Ethernet + RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +//Line below for 100Mb Ethernet +// RegCPUData U_0_034(Speed ,7'd034,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + +always @ (posedge Clk_reg or posedge Reset) + if (Reset) + CD_out <=0; + else if (!CSB&&WRB) + case (CA[7:1]) + 7'd00: CD_out<=Tx_Hwmark ; + 7'd01: CD_out<=Tx_Lwmark ; + 7'd02: CD_out<=pause_frame_send_en ; + 7'd03: CD_out<=pause_quanta_set ; + 7'd04: CD_out<=IFGset ; + 7'd05: CD_out<=FullDuplex ; + 7'd06: CD_out<=MaxRetry ; + 7'd07: CD_out<=MAC_tx_add_en ; + 7'd08: CD_out<=MAC_tx_add_prom_data ; + 7'd09: CD_out<=MAC_tx_add_prom_add ; + 7'd10: CD_out<=MAC_tx_add_prom_wr ; + 7'd11: CD_out<=tx_pause_en ; + 7'd12: CD_out<=xoff_cpu ; + 7'd13: CD_out<=xon_cpu ; + 7'd14: CD_out<=MAC_rx_add_chk_en ; + 7'd15: CD_out<=MAC_rx_add_prom_data ; + 7'd16: CD_out<=MAC_rx_add_prom_add ; + 7'd17: CD_out<=MAC_rx_add_prom_wr ; + 7'd18: CD_out<=broadcast_filter_en ; + 7'd19: CD_out<=broadcast_bucket_depth ; + 7'd20: CD_out<=broadcast_bucket_interval ; + 7'd21: CD_out<=RX_APPEND_CRC ; + 7'd22: CD_out<=Rx_Hwmark ; + 7'd23: CD_out<=Rx_Lwmark ; + 7'd24: CD_out<=CRC_chk_en ; + 7'd25: CD_out<=RX_IFG_SET ; + 7'd26: CD_out<=RX_MAX_LENGTH ; + 7'd27: CD_out<=RX_MIN_LENGTH ; + 7'd28: CD_out<=CPU_rd_addr ; + 7'd29: CD_out<=CPU_rd_apply ; + 7'd30: CD_out<=CPU_rd_grant ; + 7'd31: CD_out<=CPU_rd_dout[15:0] ; + 7'd32: CD_out<=CPU_rd_dout[31:16] ; + 7'd33: CD_out<=Line_loop_en ; + 7'd34: CD_out<=Speed ; + default: CD_out<=0 ; + endcase + + +endmodule + +module RegCPUData( +RegOut, +CA_reg_set, +RegInit, + +Reset, +Clk, +CWR_pulse, +CCSB, +CA_reg, +CD_in_reg +); +output[15:0] RegOut; +input[6:0] CA_reg_set; +input[15:0] RegInit; +// +input Reset; +input Clk; +input CWR_pulse; +input CCSB; +input[7:0] CA_reg; +input[15:0] CD_in_reg; +// +reg[15:0] RegOut; + +always @(posedge Reset or posedge Clk) + if(Reset) + RegOut <=RegInit; + else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0]) + RegOut <=CD_in_reg; + +endmodule \ No newline at end of file Index: trunk/FPGA/atlys/dcm1.xco =================================================================== --- trunk/FPGA/atlys/dcm1.xco (nonexistent) +++ trunk/FPGA/atlys/dcm1.xco (revision 2) @@ -0,0 +1,266 @@ +############################################################## +# +# Xilinx Core Generator version 13.4 +# Date: Mon Aug 27 21:36:38 2012 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.3 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=100.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=125.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=64.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=64.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=dcm1 +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=4 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=10.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=5 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=10.000 +CSET pll_clkout0_divide=4 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=8 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=8 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=100.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-09T17:33:40Z +# END Extra information +GENERATE +# CRC: 89867365 Index: trunk/FPGA/atlys/atlys_eth_top.vhd =================================================================== --- trunk/FPGA/atlys/atlys_eth_top.vhd (nonexistent) +++ trunk/FPGA/atlys/atlys_eth_top.vhd (revision 2) @@ -0,0 +1,596 @@ +------------------------------------------------------------------------------- +-- Title : L3 FADE protocol demo for Digilent Atlys board +-- Project : +------------------------------------------------------------------------------- +-- File : atlys_eth_top.vhd +-- Author : Wojciech M. Zabolotny +-- License : BSD License +-- Company : +-- Created : 2010-08-03 +-- Last update: 2012-08-22 +-- Platform : +-- Standard : VHDL +------------------------------------------------------------------------------- +-- Description: +-- This file implements the top entity, integrating all component +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +-- This is public domain code!!! +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2010-08-03 1.0 wzab Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; + +entity atlys_eth is + + port ( + cpu_reset : in std_logic; +-- -- DDR2 interface +-- ddr2_a : out std_logic_vector(12 downto 0); +-- ddr2_ba : out std_logic_vector(2 downto 0); +-- ddr2_cas_b : out std_logic; +-- ddr2_cke : out std_logic; +-- ddr2_clk_n : out std_logic; +-- ddr2_clk_p : out std_logic; +-- ddr2_dq : inout std_logic_vector(15 downto 0); +-- ddr2_ldm : out std_logic; +-- ddr2_ldqs_n : out std_logic; +-- ddr2_ldqs_p : out std_logic; +-- ddr2_odt : out std_logic; +-- ddr2_ras_b : out std_logic; +-- ddr2_udm : out std_logic; +-- ddr2_udqs_n : out std_logic; +-- ddr2_udqs_p : out std_logic; +-- ddr2_we_b : out std_logic; +-- -- FLASH interface +-- flash_a : out std_logic_vector(24 downto 0); +-- flash_ce_b : out std_logic; +-- flash_d : inout std_logic_vector(7 downto 0); +-- flash_oe_b : out std_logic; +-- flash_we_b : out std_logic; +-- -- FMC interface +-- fmc_la28_n : out std_logic; +-- fmc_la28_p : out std_logic; +-- fmc_la29_n : out std_logic; +-- fmc_la29_p : out std_logic; +-- fmc_la30_n : out std_logic; +-- fmc_la30_p : out std_logic; +-- fmc_la31_n : out std_logic; +-- fmc_la31_p : out std_logic; +-- iic_scl_main : out std_logic; +-- iic_sda_main : out std_logic; + + --gpio_hdr : in std_logic_vector(7 downto 0); + +-- fmc_clk0_m2c_n : out std_logic; +-- fmc_clk0_m2c_p : out std_logic; +-- fmc_clk1_m2c_n : out std_logic; +-- fmc_clk1_m2c_p : out std_logic; +-- fmc_la00_cc_n : out std_logic; +-- fmc_la00_cc_p : out std_logic; +-- fmc_la01_cc_n : out std_logic; +-- fmc_la01_cc_p : out std_logic; +-- fmc_la02_n : out std_logic; +-- fmc_la02_p : out std_logic; +-- fmc_la03_n : out std_logic; +-- fmc_la03_p : out std_logic; +-- fmc_la04_n : out std_logic; +-- fmc_la04_p : out std_logic; +-- led : out std_logic_vector(3 downto 0); + switches : in std_logic_vector(7 downto 0); +-- flash_oen : out std_logic; +-- flash_wen : out std_logic; +-- flash_cen : out std_logic; + gpio_led : out std_logic_vector(7 downto 0); + -- PHY interface + phy_col : in std_logic; + phy_crs : in std_logic; + phy_int : in std_logic; + phy_mdc : out std_logic; + phy_mdio : inout std_logic; + phy_reset : out std_logic; + phy_rxclk : in std_logic; + phy_rxctl_rxdv : in std_logic; + phy_rxd : in std_logic_vector(7 downto 0); + phy_rxer : in std_logic; + phy_txclk : in std_logic; + phy_txctl_txen : out std_logic; + phy_txc_gtxclk : out std_logic; + phy_txd : out std_logic_vector(7 downto 0); + phy_txer : out std_logic; + sysclk : in std_logic + ); + +end atlys_eth; + +architecture beh of atlys_eth is + + component dp_ram_scl + generic ( + DATA_WIDTH : integer; + ADDR_WIDTH : integer); + port ( + clk : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + we_b : in std_logic; + addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)); + end component; + + component ack_fifo + port ( + clk : in std_logic; + rst : in std_logic; + din : in std_logic_vector(pkt_ack_width-1 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(pkt_ack_width-1 downto 0); + full : out std_logic; + empty : out std_logic); + end component; + + component dcm1 + port ( + CLK_IN1 : in std_logic; + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + CLK_OUT3 : out std_logic; + RESET : in std_logic; + LOCKED : out std_logic); + end component; + + + component desc_manager + generic ( + N_OF_PKTS : integer); + port ( + dta : in std_logic_vector(31 downto 0); + dta_we : in std_logic; + dta_ready : out std_logic; + set_number : out unsigned(15 downto 0); + pkt_number : out unsigned(15 downto 0); + snd_start : out std_logic; + snd_ready : in std_logic; + dmem_addr : out std_logic_vector(13 downto 0); + dmem_dta : out std_logic_vector(31 downto 0); + dmem_we : out std_logic; + ack_fifo_empty : in std_logic; + ack_fifo_rd_en : out std_logic; + ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0); + transmit_data : in std_logic; + transm_delay : out unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic); + end component; + + component eth_sender + port ( + peer_mac : in std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + set_number : in unsigned(15 downto 0); + pkt_number : in unsigned(15 downto 0); + retry_number : in unsigned(15 downto 0); + transm_delay : in unsigned(31 downto 0); + clk : in std_logic; + rst_n : in std_logic; + ready : out std_logic; + start : in std_logic; + tx_mem_addr : out std_logic_vector(13 downto 0); + tx_mem_data : in std_logic_vector(31 downto 0); + Tx_mac_wa : in std_logic; + Tx_mac_wr : out std_logic; + Tx_mac_data : out std_logic_vector(31 downto 0); + Tx_mac_BE : out std_logic_vector(1 downto 0); + Tx_mac_sop : out std_logic; + Tx_mac_eop : out std_logic); + end component; + + component eth_receiver + port ( + peer_mac : out std_logic_vector(47 downto 0); + my_mac : in std_logic_vector(47 downto 0); + my_ether_type : in std_logic_vector(15 downto 0); + transmit_data : out std_logic; + restart : out std_logic; + ack_fifo_full : in std_logic; + ack_fifo_wr_en : out std_logic; + ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0); + clk : in std_logic; + rst_n : in std_logic; + Rx_mac_pa : in std_logic; + Rx_mac_ra : in std_logic; + Rx_mac_rd : out std_logic; + Rx_mac_data : in std_logic_vector(31 downto 0); + Rx_mac_BE : in std_logic_vector(1 downto 0); + Rx_mac_sop : in std_logic; + Rx_mac_eop : in std_logic); + end component; + + component jtag_bus_ctl + generic ( + d_width : integer; + a_width : integer); + port ( + din : in std_logic_vector((d_width-1) downto 0); + dout : out std_logic_vector((d_width-1) downto 0); + addr : out std_logic_vector((a_width-1) downto 0); + nwr : out std_logic; + nrd : out std_logic); + end component; + + component MAC_top + port ( + --system signals + Reset : in std_logic; + Clk_125M : in std_logic; + Clk_user : in std_logic; + Clk_reg : in std_logic; + Speed : out std_logic_vector(2 downto 0); + --user interface + Rx_mac_ra : out std_logic; + Rx_mac_rd : in std_logic; + Rx_mac_data : out std_logic_vector(31 downto 0); + Rx_mac_BE : out std_logic_vector(1 downto 0); + Rx_mac_pa : out std_logic; + Rx_mac_sop : out std_logic; + Rx_mac_eop : out std_logic; + --user interface + Tx_mac_wa : out std_logic; + Tx_mac_wr : in std_logic; + Tx_mac_data : in std_logic_vector(31 downto 0); + Tx_mac_BE : in std_logic_vector(1 downto 0); + Tx_mac_sop : in std_logic; + Tx_mac_eop : in std_logic; + -- pkg_lgth fifo + Pkg_lgth_fifo_rd : in std_logic; + Pkg_lgth_fifo_ra : out std_logic; + Pkg_lgth_fifo_data : out std_logic_vector(15 downto 0); + --Phy interface + Gtx_clk : out std_logic; -- used only in GMII mode + Rx_clk : in std_logic; + Tx_clk : in std_logic; -- used only in MII mode + Tx_er : out std_logic; + Tx_en : out std_logic; + Txd : out std_logic_vector(7 downto 0); + Rx_er : in std_logic; + Rx_dv : in std_logic; + Rxd : in std_logic_vector(7 downto 0); + Crs : in std_logic; + Col : in std_logic; + -- host interface + CSB : in std_logic; + WRB : in std_logic; + CD_in : in std_logic_vector(15 downto 0); + CD_out : out std_logic_vector(15 downto 0); + CA : in std_logic_vector(7 downto 0); + -- mdx + Mdo : out std_logic; -- MII Management Data Output + MdoEn : out std_logic; -- MII Management Data Output Enable + Mdi : in std_logic; + Mdc : out std_logic -- MII Management Data Clock + ); + end component; + + signal my_mac : std_logic_vector(47 downto 0); + constant my_ether_type : std_logic_vector(15 downto 0) := x"fade"; + signal transm_delay : unsigned(31 downto 0); + signal restart : std_logic; + signal dta : std_logic_vector(31 downto 0); + signal dta_we : std_logic := '0'; + signal dta_ready : std_logic; + signal snd_start : std_logic; + signal snd_ready : std_logic; + signal dmem_addr : std_logic_vector(13 downto 0); + signal dmem_dta : std_logic_vector(31 downto 0); + signal dmem_we : std_logic; + signal addr_a, addr_b : integer; + signal test_dta : unsigned(31 downto 0); + signal tx_mem_addr : std_logic_vector(13 downto 0); + signal tx_mem_data : std_logic_vector(31 downto 0); + + signal arg1, arg2, res1 : unsigned(7 downto 0); + signal res2 : unsigned(15 downto 0); + signal sender : std_logic_vector(47 downto 0); + signal peer_mac : std_logic_vector(47 downto 0); + signal inputs, din, dout : std_logic_vector(7 downto 0); + signal addr, leds : std_logic_vector(3 downto 0); + signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic; + signal not_cpu_reset, rst_del : std_logic; + + signal set_number : unsigned(15 downto 0); + signal pkt_number : unsigned(15 downto 0); + signal retry_number : unsigned(15 downto 0) := (others => '0'); + signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0'); + + + signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0); + signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic; + signal transmit_data : std_logic := '0'; + + signal read_addr : std_logic_vector(15 downto 0); + signal read_data : std_logic_vector(15 downto 0); + signal read_done, read_in_progress : std_logic; + + + signal led_counter : integer := 0; + signal tx_counter : integer := 10000; + signal Reset : std_logic; + signal Clk_125M : std_logic; + signal Clk_user : std_logic; + signal Clk_reg : std_logic; + signal Speed : std_logic_vector(2 downto 0); + signal Rx_mac_ra : std_logic; + signal Rx_mac_rd : std_logic; + signal Rx_mac_data : std_logic_vector(31 downto 0); + signal Rx_mac_BE : std_logic_vector(1 downto 0); + signal Rx_mac_pa : std_logic; + signal Rx_mac_sop : std_logic; + signal Rx_mac_eop : std_logic; + signal Tx_mac_wa : std_logic; + signal Tx_mac_wr : std_logic; + signal Tx_mac_data : std_logic_vector(31 downto 0); + signal Tx_mac_BE : std_logic_vector(1 downto 0); + signal Tx_mac_sop : std_logic; + signal Tx_mac_eop : std_logic; + signal Pkg_lgth_fifo_rd : std_logic; + signal Pkg_lgth_fifo_ra : std_logic; + signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0); + signal Gtx_clk : std_logic; + signal Rx_clk : std_logic; + signal Tx_clk : std_logic; + signal Tx_er : std_logic; + signal Tx_en : std_logic; + signal Txd : std_logic_vector(7 downto 0); + signal Rx_er : std_logic; + signal Rx_dv : std_logic; + signal Rxd : std_logic_vector(7 downto 0); + signal Crs : std_logic; + signal Col : std_logic; + signal CSB : std_logic := '1'; + signal WRB : std_logic := '1'; + signal CD_in : std_logic_vector(15 downto 0) := (others => '0'); + signal CD_out : std_logic_vector(15 downto 0) := (others => '0'); + signal CA : std_logic_vector(7 downto 0) := (others => '0'); + signal s_Mdo : std_logic; + signal s_MdoEn : std_logic; + signal s_Mdi : std_logic; + + signal s_dta_we : std_logic; + +begin -- beh + + -- Allow selection of MAC with the DIP switch to allow testing + -- with multiple boards! + with switches(1 downto 0) select + my_mac <= + x"de_ad_ba_be_be_ef" when "00", + x"de_ad_ba_be_be_e1" when "01", + x"de_ad_ba_be_be_e2" when "10", + x"de_ad_ba_be_be_e3" when "11"; + + +-- iic_sda_main <= 'Z'; +-- iic_scl_main <= 'Z'; + + not_cpu_reset <= not cpu_reset; + rst_p <= not rst_n; + +-- flash_oe_b <= '1'; +-- flash_we_b <= '1'; +-- flash_ce_b <= '1'; + + MAC_top_1 : MAC_top + port map ( + Reset => rst_p, + Clk_125M => Clk_125M, + Clk_user => Clk_user, + Clk_reg => Clk_user, -- was Clk_reg + Speed => Speed, + Rx_mac_ra => Rx_mac_ra, + Rx_mac_rd => Rx_mac_rd, + Rx_mac_data => Rx_mac_data, + Rx_mac_BE => Rx_mac_BE, + Rx_mac_pa => Rx_mac_pa, + Rx_mac_sop => Rx_mac_sop, + Rx_mac_eop => Rx_mac_eop, + Tx_mac_wa => Tx_mac_wa, + Tx_mac_wr => Tx_mac_wr, + Tx_mac_data => Tx_mac_data, + Tx_mac_BE => Tx_mac_BE, + Tx_mac_sop => Tx_mac_sop, + Tx_mac_eop => Tx_mac_eop, + Pkg_lgth_fifo_rd => Pkg_lgth_fifo_rd, + Pkg_lgth_fifo_ra => Pkg_lgth_fifo_ra, + Pkg_lgth_fifo_data => Pkg_lgth_fifo_data, + Gtx_clk => PHY_TXC_Gtxclk, + Rx_clk => PHY_Rxclk, + Tx_clk => PHY_Txclk, + Tx_er => PHY_Txer, + Tx_en => PHY_TXCTL_Txen, + Txd => PHY_Txd, + Rx_er => PHY_Rxer, + Rx_dv => PHY_RXCTL_Rxdv, + Rxd => PHY_Rxd, + Crs => PHY_Crs, + Col => PHY_Col, + -- Host interface + CSB => CSB, + WRB => WRB, + CD_in => CD_in, + CD_out => CD_out, + CA => CA, + -- MDI interface + Mdo => s_Mdo, + MdoEn => s_MdoEn, + Mdi => s_Mdi, + Mdc => PHY_Mdc); + + Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra; + + addr_a <= to_integer(unsigned(dmem_addr)); + addr_b <= to_integer(unsigned(tx_mem_addr)); + + dp_ram_scl_1 : dp_ram_scl + generic map ( + DATA_WIDTH => 32, + ADDR_WIDTH => 13) + port map ( + clk => clk_user, + we_a => dmem_we, + addr_a => dmem_addr(12 downto 0), + data_a => dmem_dta, + q_a => open, + we_b => '0', + addr_b => tx_mem_addr(12 downto 0), + data_b => (others => '0'), + q_b => tx_mem_data); + + desc_manager_1 : desc_manager + generic map ( + N_OF_PKTS => N_OF_PKTS) + port map ( + dta => dta, + dta_we => dta_we, + dta_ready => dta_ready, + set_number => set_number, + pkt_number => pkt_number, + snd_start => snd_start, + snd_ready => snd_ready, + dmem_addr => dmem_addr, + dmem_dta => dmem_dta, + dmem_we => dmem_we, + ack_fifo_empty => ack_fifo_empty, + ack_fifo_rd_en => ack_fifo_rd_en, + ack_fifo_dout => ack_fifo_dout, + transmit_data => transmit_data, + transm_delay => transm_delay, + clk => clk_user, + rst_n => rst_n); + + eth_sender_1 : eth_sender + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + transm_delay => transm_delay, + set_number => set_number, + pkt_number => pkt_number, + retry_number => retry_number, + clk => clk_user, + rst_n => rst_n, + ready => snd_ready, + start => snd_start, + tx_mem_addr => tx_mem_addr, + tx_mem_data => tx_mem_data, + Tx_mac_wa => Tx_mac_wa, + Tx_mac_wr => Tx_mac_wr, + Tx_mac_data => Tx_mac_data, + Tx_mac_BE => Tx_mac_BE, + Tx_mac_sop => Tx_mac_sop, + Tx_mac_eop => Tx_mac_eop); + + eth_receiver_1 : eth_receiver + port map ( + peer_mac => peer_mac, + my_mac => my_mac, + my_ether_type => my_ether_type, + restart => restart, + transmit_data => transmit_data, + ack_fifo_full => ack_fifo_full, + ack_fifo_wr_en => ack_fifo_wr_en, + ack_fifo_din => ack_fifo_din, + clk => clk_user, + rst_n => rst_n, + Rx_mac_pa => Rx_mac_pa, + Rx_mac_ra => Rx_mac_ra, + Rx_mac_rd => Rx_mac_rd, + Rx_mac_data => Rx_mac_data, + Rx_mac_BE => Rx_mac_BE, + Rx_mac_sop => Rx_mac_sop, + Rx_mac_eop => Rx_mac_eop); + dcm1_1 : dcm1 + port map ( + CLK_IN1 => sysclk, + CLK_OUT1 => Clk_125M, + CLK_OUT2 => Clk_user, + CLK_OUT3 => Clk_reg, + RESET => not_cpu_reset, + LOCKED => dcm_locked); + + process (Clk_user, not_cpu_reset) + begin -- process + if not_cpu_reset = '1' then -- asynchronous reset (active low) + rst_n <= '0'; + rst_del <= '0'; + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if restart = '1' then + rst_n <= '0'; + rst_del <= '0'; + else + if dcm_locked = '1' then + rst_del <= '1'; + rst_n <= rst_del; + end if; + end if; + end if; + end process; + + -- reset + + phy_reset <= rst_n; + + -- Connection of MDI + s_Mdi <= PHY_MDIO; + PHY_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo; + ack_fifo_1 : ack_fifo + port map ( + clk => Clk_user, + rst => rst_p, + din => ack_fifo_din, + wr_en => ack_fifo_wr_en, + rd_en => ack_fifo_rd_en, + dout => ack_fifo_dout, + full => ack_fifo_full, + empty => ack_fifo_empty); + + --E_TXD <= s_Txd(3 downto 0); + --s_Rxd <= "0000" & E_RXD; + + -- signal generator + + dta <= std_logic_vector(test_dta); + s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0'; + dta_we <= s_dta_we; + + process (Clk_user, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + test_dta <= (others => '0'); + elsif Clk_user'event and Clk_user = '1' then -- rising clock edge + if s_dta_we = '1' then + test_dta <= test_dta + 1; + end if; + end if; + end process; + + -- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2)); + gpio_led(0) <= snd_ready; + gpio_led(1) <= transmit_data; + gpio_led(2) <= not_cpu_reset; + gpio_led(3) <= Tx_mac_wa; + gpio_led(7 downto 4) <= (others => '0'); +end beh;

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