URL
https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk
Subversion Repositories fade_ether_protocol
Compare Revisions
- This comparison shows the changes necessary to convert path
/fade_ether_protocol
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/FPGA_no_MAC/sk3e/ack_fifo.xco
1,7 → 1,7
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# Xilinx Core Generator version 13.4 |
# Date: Sun Jun 16 09:55:13 2013 |
# Date: Sun Jun 16 14:33:14 2013 |
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############################################################## |
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/trunk/FPGA_no_MAC/src/common/eth_sender4.vhd
7,7 → 7,7
-- License : BSD License |
-- Company : |
-- Created : 2012-03-30 |
-- Last update: 2013-06-15 |
-- Last update: 2013-06-16 |
-- Platform : |
-- Standard : VHDL'93 |
------------------------------------------------------------------------------- |
287,8 → 287,8
begin -- process |
if rst_n = '0' then -- asynchronous reset (active low) |
ready <= '0'; |
ready_0 <= '0'; |
ready_1 <= '0'; |
ready_0 <= '0'; |
state2 <= ST2_IDLE; |
elsif clk'event and clk = '1' then -- rising clock edge |
ready_1 <= tx_ready; |
322,12 → 322,10
if tx_rst_n = '0' then -- asynchronous reset (active low) |
tx_start <= '0'; |
tx_start_0 <= '0'; |
tx_start_1 <= '0'; |
state1 <= ST1_IDLE; |
tx_ready <= '1'; |
elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge |
tx_start_1 <= start_0; |
tx_start_0 <= tx_start_1; |
tx_start_0 <= start_0; |
tx_start <= tx_start_0; |
case state1 is |
when ST1_IDLE => |
/trunk/FPGA_no_MAC/src/common/eth_sender8.vhd
7,7 → 7,7
-- License : BSD License |
-- Company : |
-- Created : 2012-03-30 |
-- Last update: 2013-06-15 |
-- Last update: 2013-06-16 |
-- Platform : |
-- Standard : VHDL'93 |
------------------------------------------------------------------------------- |
314,12 → 314,10
if tx_rst_n = '0' then -- asynchronous reset (active low) |
tx_start <= '0'; |
tx_start_0 <= '0'; |
tx_start_1 <= '0'; |
state1 <= ST1_IDLE; |
tx_ready <= '1'; |
elsif Tx_Clk'event and Tx_Clk = '1' then -- rising clock edge |
tx_start_1 <= start_0; |
tx_start_0 <= tx_start_1; |
tx_start_0 <= start_0; |
tx_start <= tx_start_0; |
case state1 is |
when ST1_IDLE => |
/trunk/FPGA_no_MAC/atlys/ack_fifo.xco
1,7 → 1,7
############################################################## |
# |
# Xilinx Core Generator version 13.4 |
# Date: Sun Apr 21 20:58:01 2013 |
# Date: Sun Jun 16 14:37:55 2013 |
# |
############################################################## |
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/trunk/FPGA_no_MAC/atlys/dcm1.xco
1,7 → 1,7
############################################################## |
# |
# Xilinx Core Generator version 13.4 |
# Date: Sat Sep 1 00:29:16 2012 |
# Date: Sun Jun 16 14:37:37 2013 |
# |
############################################################## |
# |