URL
https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk
Subversion Repositories fir_wishbone
Compare Revisions
- This comparison shows the changes necessary to convert path
/fir_wishbone
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/design/fir.vhdl
20,7 → 20,7
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@dependencies: |
@designer(s): |
Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com]; |
Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] |
Tan Hooi Jing [hooijingtan@gmail.com] |
@info: |
Revision History: @see Mercurial log for full list of changes. |
32,20 → 32,24
use ieee.numeric_std.all; |
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/* Filter order = number of unit delays. */ |
entity fir is generic(order:positive:=30; width:positive:=16); |
entity fir is generic(order:positive:=30); --; width:positive:=16); |
port( |
reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again. |
clk:in std_ulogic:='0'; |
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/* Filter ports. */ |
u:in signed(width-1 downto 0):=(others=>'0'); |
y:buffer signed(width-1 downto 0) |
--u:in signed(width-1 downto 0):=(others=>'0'); |
--y:buffer signed(width-1 downto 0) |
u:in signed; |
y:buffer signed |
); |
end entity fir; |
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architecture rtl of fir is |
/* Memory I/Os: */ |
signal q:signed(width-1 downto 0):=(others=>'0'); |
-- signal q:signed(width-1 downto 0):=(others=>'0'); |
signal q:signed(u'range); |
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--signal rst: std_ulogic; |
--signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0'); |
--signal trig:std_logic; |
60,9 → 64,13
/* Memories: */ |
/* TODO: Change these arrays to internal process variables instead. */ |
/* Read-only Memory (ROM). */ |
type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. |
type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0); |
-- type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. |
-- type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0); |
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/* 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. */ |
type signed_vector is array(natural range <>) of signed(u'range); |
type signedx2_vector is array(natural range<>) of signed(u'length*2-1 downto 0); |
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/* Filter length = number of taps = number of coefficients = order + 1 */ |
constant b:signed_vector(0 to order):=( |
x"FFEF", |
102,7 → 110,7
-- signal c:natural range b'range; |
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/* Pipes and delay chains. */ |
signal y0:signed(width*2-1 downto 0); |
signal y0:signed(u'length*2-1 downto 0); |
signal u_pipe:signed_vector(b'range):=(others=>(others=>'0')); |
signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0')); |
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144,5 → 152,5
end generate y_dlyChain; |
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y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0'); |
y<=y0(width-1 downto 0); |
y<=y0(y'range); |
end architecture rtl; |