URL
https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk
Subversion Repositories fir_wishbone
Compare Revisions
- This comparison shows the changes necessary to convert path
/fir_wishbone
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/trunk/design/packages/pkg-dsp.vhdl
File deleted
/trunk/design/quartus-synthesis/tb_fir.vhdl
File deleted
trunk/design/quartus-synthesis/tb_fir.vhdl
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/design/quartus-synthesis/fir.vhdl
===================================================================
--- trunk/design/quartus-synthesis/fir.vhdl (revision 16)
+++ trunk/design/quartus-synthesis/fir.vhdl (nonexistent)
@@ -1,148 +0,0 @@
-/* FIR Filter.
-
- Copyright© 2012 Tauhop Solutions. All rights reserved.
- This core is free hardware design; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public
- License as published by the Free Software Foundation; either
- version 2 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
-
- You should have received a copy of the GNU Library General Public
- License along with this library; if not, write to the
- Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA.
-
- License: LGPL.
-
- @dependencies:
- @designer(s):
- Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com];
- Tan Hooi Jing [hooijingtan@gmail.com]
- @info:
- Revision History: @see Mercurial log for full list of changes.
-
- This notice and disclaimer must be retained as part of this text at all times.
-*/
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-/* Filter order = number of unit delays. */
-entity fir is generic(order:positive:=30; width:positive:=16);
- port(
- reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
- clk:in std_ulogic:='0';
-
- /* Filter ports. */
- u:in signed(width-1 downto 0):=(others=>'0');
- y:buffer signed(width-1 downto 0)
- );
-end entity fir;
-
-architecture rtl of fir is
- /* Memory I/Os: */
- signal q:signed(width-1 downto 0):=(others=>'0');
- --signal rst: std_ulogic;
- --signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0');
- --signal trig:std_logic;
-
- --signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits
-
-
- -- debugger
- --signal dbgSignals:std_ulogic_vector(127 downto 0);
-
-
- /* Memories: */
- /* TODO: Change these arrays to internal process variables instead. */
- /* Read-only Memory (ROM). */
- type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned.
- type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0);
-
- /* Filter length = number of taps = number of coefficients = order + 1 */
- constant b:signed_vector(0 to order):=(
- x"FFEF",
- x"FFED",
- x"FFE8",
- x"FFE6",
- x"FFEB",
- x"0000",
- x"002C",
- x"0075",
- x"00DC",
- x"015F",
- x"01F4",
- x"028E",
- x"031F",
- x"0394",
- x"03E1",
- x"03FC",
- x"03E1",
- x"0394",
- x"031F",
- x"028E",
- x"01F4",
- x"015F",
- x"00DC",
- x"0075",
- x"002C",
- x"0000",
- x"FFEB",
- x"FFE6",
- x"FFE8",
- x"FFED",
- x"FFEF"
- );
-
- /*Memory Addressing*/
--- signal c:natural range b'range;
-
- /* Pipes and delay chains. */
- signal y0:signed(width*2-1 downto 0);
- signal u_pipe:signed_vector(b'range):=(others=>(others=>'0'));
- signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0'));
-
-
- /* Counters. */
--- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line.
-
--- /* memory pointers (acts as the read/write address for the synchronous RAM). */
--- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting).
- /* [end]: Memories. */
-
- /* Signal preservations. */
--- attribute keep:boolean;
-
- /* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
- attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera
--- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx
-
-begin
--- /* 1-Dimensional Synchronous ROM. */
--- readCoeffs: process(clk) is begin
--- if rising_edge(clk) then
--- if reset='1' then q<=(others=>'0');
--- else q<=b(c);
--- end if;
--- end if;
--- end process readCoeffs;
-
- u_pipe(0)<=u;
- u_dlyChain: for i in 1 to u_pipe'high generate
- delayChain: process(clk) is begin
- if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if;
- end process delayChain;
- end generate u_dlyChain;
-
- y_pipe(0)<=b(0)*u;
- y_dlyChain: for i in 1 to y_pipe'high generate
- y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1);
- end generate y_dlyChain;
-
- y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0');
- y<=y0(width-1 downto 0);
-end architecture rtl;
trunk/design/quartus-synthesis/fir.vhdl
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/design/fir.vhdl
===================================================================
--- trunk/design/fir.vhdl (revision 16)
+++ trunk/design/fir.vhdl (nonexistent)
@@ -1,156 +0,0 @@
-/* FIR Filter.
-
- Copyright© 2012 Tauhop Solutions. All rights reserved.
- This core is free hardware design; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public
- License as published by the Free Software Foundation; either
- version 2 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
-
- You should have received a copy of the GNU Library General Public
- License along with this library; if not, write to the
- Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA.
-
- License: LGPL.
-
- @dependencies:
- @designer(s):
- Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com]
- Tan Hooi Jing [hooijingtan@gmail.com]
- @info:
- Revision History: @see Mercurial log for full list of changes.
-
- This notice and disclaimer must be retained as part of this text at all times.
-*/
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-/* Filter order = number of unit delays. */
-entity fir is generic(order:positive:=30); --; width:positive:=16);
- port(
- reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
- clk:in std_ulogic:='0';
-
- /* Filter ports. */
- --u:in signed(width-1 downto 0):=(others=>'0');
- --y:buffer signed(width-1 downto 0)
- u:in signed;
- y:buffer signed
- );
-end entity fir;
-
-architecture rtl of fir is
- /* Memory I/Os: */
--- signal q:signed(width-1 downto 0):=(others=>'0');
- signal q:signed(u'range);
-
- --signal rst: std_ulogic;
- --signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0');
- --signal trig:std_logic;
-
- --signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits
-
-
- -- debugger
- --signal dbgSignals:std_ulogic_vector(127 downto 0);
-
-
- /* Memories: */
- /* TODO: Change these arrays to internal process variables instead. */
- /* Read-only Memory (ROM). */
--- type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned.
--- type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0);
-
- /* 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. */
- type signed_vector is array(natural range <>) of signed(u'range);
- type signedx2_vector is array(natural range<>) of signed(u'length*2-1 downto 0);
-
- /* Filter length = number of taps = number of coefficients = order + 1 */
- constant b:signed_vector(0 to order):=(
- x"FFEF",
- x"FFED",
- x"FFE8",
- x"FFE6",
- x"FFEB",
- x"0000",
- x"002C",
- x"0075",
- x"00DC",
- x"015F",
- x"01F4",
- x"028E",
- x"031F",
- x"0394",
- x"03E1",
- x"03FC",
- x"03E1",
- x"0394",
- x"031F",
- x"028E",
- x"01F4",
- x"015F",
- x"00DC",
- x"0075",
- x"002C",
- x"0000",
- x"FFEB",
- x"FFE6",
- x"FFE8",
- x"FFED",
- x"FFEF"
- );
-
- /*Memory Addressing*/
--- signal c:natural range b'range;
-
- /* Pipes and delay chains. */
- signal y0:signed(u'length*2-1 downto 0);
- signal u_pipe:signed_vector(b'range):=(others=>(others=>'0'));
- signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0'));
-
-
- /* Counters. */
--- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line.
-
--- /* memory pointers (acts as the read/write address for the synchronous RAM). */
--- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting).
- /* [end]: Memories. */
-
- /* Signal preservations. */
--- attribute keep:boolean;
-
- /* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
- attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera
--- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx
-
-begin
--- /* 1-Dimensional Synchronous ROM. */
--- readCoeffs: process(clk) is begin
--- if rising_edge(clk) then
--- if reset='1' then q<=(others=>'0');
--- else q<=b(c);
--- end if;
--- end if;
--- end process readCoeffs;
-
- u_pipe(0)<=u;
- u_dlyChain: for i in 1 to u_pipe'high generate
- delayChain: process(clk) is begin
- if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if;
- end process delayChain;
- end generate u_dlyChain;
-
- y_pipe(0)<=b(0)*u;
- y_dlyChain: for i in 1 to y_pipe'high generate
- y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1);
- end generate y_dlyChain;
-
- y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0');
- y<=y0(y'range);
-end architecture rtl;
Index: trunk/hw/packages/pkg-tlm.vhdl
===================================================================
--- trunk/hw/packages/pkg-tlm.vhdl (nonexistent)
+++ trunk/hw/packages/pkg-tlm.vhdl (revision 17)
@@ -0,0 +1,95 @@
+/*
+ This file is part of the AXI4 Transactor and Bus Functional Model
+ (axi4_tlm_bfm) project:
+ http://www.opencores.org/project,axi4_tlm_bfm
+
+ Description
+ This implements a generic interface for transactors, and has a set
+ of reusable procedures to read and write from / to a bus. This
+ interface can be used in many different bus protocols, by means of
+ instantiating this package. An example implementation for the AXI4
+ protocol can be found at
+ pkg-axi-tlm.vhdl
+ under the axi4_tlm_bfm project.
+
+ To Do:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml.
+*/
+/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
+--use std.textio.all;
+
+package tlm is
+ generic(type t_addr; type t_data; type t_cnt);
+
+-- /* TODO remove once generic packages are supported. */
+-- subtype t_addr is u_unsigned(31 downto 0);
+-- subtype t_data is std_ulogic_vector(31 downto 0);
+-- subtype t_cnt is u_unsigned(127 downto 0);
+
+ /* BFM control interface.
+ address is only used for non-stream interfaces.
+ */
+ type t_bfm is record
+ address: t_addr;
+ data: t_data;
+ trigger: std_ulogic;
+ end record t_bfm;
+
+ procedure write(
+ signal request: out t_bfm;
+ address: in t_addr;
+ data: in t_data
+ );
+
+ procedure read(
+ signal request: out t_bfm;
+ address: in t_addr
+ );
+end package tlm;
+
+package body tlm is
+ procedure write(
+ signal request: out t_bfm;
+ address: in t_addr; -- used only for non-stream interfaces.
+ data: in t_data
+ ) is begin
+ request.address <= address;
+ request.data <= data;
+ request.trigger <= not request.trigger;
+ end procedure write;
+
+ procedure read(
+ signal request: out t_bfm;
+ address: in t_addr -- used only for non-stream interfaces.
+ ) is begin
+ request.address <= address;
+ request.trigger <= not request.trigger;
+ --report "request.address: " & to_hstring(request.address);
+ end procedure read;
+end package body tlm;
Index: trunk/hw/packages/pkg-dsp.vhdl
===================================================================
--- trunk/hw/packages/pkg-dsp.vhdl (nonexistent)
+++ trunk/hw/packages/pkg-dsp.vhdl (revision 17)
@@ -0,0 +1,123 @@
+/* Tauhop Digital Signal Processing package.
+
+ Description
+ This implements common functions used in digital signal processing.
+
+ To Do:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright© 2014 Authors and Tauhop Solutions. All rights reserved.
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see high else s;
+ return clamped;
+ end function clamp;
+
+ function clamp(s:unsigned; low,high:natural) return unsigned is begin
+ return clamp(s,to_unsigned(low,s'length),to_unsigned(high,s'length));
+ end function clamp;
+
+ function clamp(s:signed; low,high:signed) return signed is
+ variable clamped:signed(s'range);
+ begin
+ clamped:=low when shigh else s;
+ return clamped;
+ end function clamp;
+
+ function clamp(s:signed; low,high:integer) return signed is begin
+ return clamp(s,to_signed(low,s'length),to_signed(high,s'length));
+ end function clamp;
+
+ function max(l,r:unsigned) return unsigned is begin
+ /* FIXME support this in next standard. */
+ --return r when r>l else l;
+
+ if r>l then return r; end if;
+ return l;
+ end function max;
+
+ function max(l,r:signed) return signed is begin
+ --return r when r>l else l;
+
+ if r>l then return r; end if;
+ return l;
+ end function max;
+
+ function min(l,r:unsigned) return unsigned is begin
+ --return r when r;
+ --function "<"(l,r:T) return boolean is <>;
+ --function ">"(l,r:T) return boolean is <>;
+ --function ">"(l:T;r:natural) return boolean is <>;
+ --function clamp(s,low,high:T) return T is <>;
+ function clamp(s:T; low,high:natural) return T is <>
+ );
+
+ --function clamp generic(type T) parameter(s:T; low:T; high:T) return T;
+end package dsp_generic;
+
+package body dsp_generic is end package body dsp_generic;
Index: trunk/hw/quartus-synthesis/fir.vhdl
===================================================================
--- trunk/hw/quartus-synthesis/fir.vhdl (nonexistent)
+++ trunk/hw/quartus-synthesis/fir.vhdl (revision 17)
@@ -0,0 +1,148 @@
+/* FIR Filter.
+
+ Copyright© 2012 Tauhop Solutions. All rights reserved.
+ This core is free hardware design; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public
+ License along with this library; if not, write to the
+ Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA.
+
+ License: LGPL.
+
+ @dependencies:
+ @designer(s):
+ Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com];
+ Tan Hooi Jing [hooijingtan@gmail.com]
+ @info:
+ Revision History: @see Mercurial log for full list of changes.
+
+ This notice and disclaimer must be retained as part of this text at all times.
+*/
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+/* Filter order = number of unit delays. */
+entity fir is generic(order:positive:=30; width:positive:=16);
+ port(
+ reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
+ clk:in std_ulogic:='0';
+
+ /* Filter ports. */
+ u:in signed(width-1 downto 0):=(others=>'0');
+ y:buffer signed(width-1 downto 0)
+ );
+end entity fir;
+
+architecture rtl of fir is
+ /* Memory I/Os: */
+ signal q:signed(width-1 downto 0):=(others=>'0');
+ --signal rst: std_ulogic;
+ --signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0');
+ --signal trig:std_logic;
+
+ --signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits
+
+
+ -- debugger
+ --signal dbgSignals:std_ulogic_vector(127 downto 0);
+
+
+ /* Memories: */
+ /* TODO: Change these arrays to internal process variables instead. */
+ /* Read-only Memory (ROM). */
+ type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned.
+ type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0);
+
+ /* Filter length = number of taps = number of coefficients = order + 1 */
+ constant b:signed_vector(0 to order):=(
+ x"FFEF",
+ x"FFED",
+ x"FFE8",
+ x"FFE6",
+ x"FFEB",
+ x"0000",
+ x"002C",
+ x"0075",
+ x"00DC",
+ x"015F",
+ x"01F4",
+ x"028E",
+ x"031F",
+ x"0394",
+ x"03E1",
+ x"03FC",
+ x"03E1",
+ x"0394",
+ x"031F",
+ x"028E",
+ x"01F4",
+ x"015F",
+ x"00DC",
+ x"0075",
+ x"002C",
+ x"0000",
+ x"FFEB",
+ x"FFE6",
+ x"FFE8",
+ x"FFED",
+ x"FFEF"
+ );
+
+ /*Memory Addressing*/
+-- signal c:natural range b'range;
+
+ /* Pipes and delay chains. */
+ signal y0:signed(width*2-1 downto 0);
+ signal u_pipe:signed_vector(b'range):=(others=>(others=>'0'));
+ signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0'));
+
+
+ /* Counters. */
+-- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line.
+
+-- /* memory pointers (acts as the read/write address for the synchronous RAM). */
+-- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting).
+ /* [end]: Memories. */
+
+ /* Signal preservations. */
+-- attribute keep:boolean;
+
+ /* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
+ attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera
+-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx
+
+begin
+-- /* 1-Dimensional Synchronous ROM. */
+-- readCoeffs: process(clk) is begin
+-- if rising_edge(clk) then
+-- if reset='1' then q<=(others=>'0');
+-- else q<=b(c);
+-- end if;
+-- end if;
+-- end process readCoeffs;
+
+ u_pipe(0)<=u;
+ u_dlyChain: for i in 1 to u_pipe'high generate
+ delayChain: process(clk) is begin
+ if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if;
+ end process delayChain;
+ end generate u_dlyChain;
+
+ y_pipe(0)<=b(0)*u;
+ y_dlyChain: for i in 1 to y_pipe'high generate
+ y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1);
+ end generate y_dlyChain;
+
+ y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0');
+ y<=y0(width-1 downto 0);
+end architecture rtl;
trunk/hw/quartus-synthesis/fir.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/hw/fir.vhdl
===================================================================
--- trunk/hw/fir.vhdl (nonexistent)
+++ trunk/hw/fir.vhdl (revision 17)
@@ -0,0 +1,156 @@
+/* FIR Filter.
+
+ Copyright© 2012 Tauhop Solutions. All rights reserved.
+ This core is free hardware design; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public
+ License along with this library; if not, write to the
+ Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA.
+
+ License: LGPL.
+
+ @dependencies:
+ @designer(s):
+ Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com]
+ Tan Hooi Jing [hooijingtan@gmail.com]
+ @info:
+ Revision History: @see Mercurial log for full list of changes.
+
+ This notice and disclaimer must be retained as part of this text at all times.
+*/
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+/* Filter order = number of unit delays. */
+entity fir is generic(order:positive:=30); --; width:positive:=16);
+ port(
+ reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
+ clk:in std_ulogic:='0';
+
+ /* Filter ports. */
+ --u:in signed(width-1 downto 0):=(others=>'0');
+ --y:buffer signed(width-1 downto 0)
+ u:in signed;
+ y:buffer signed
+ );
+end entity fir;
+
+architecture rtl of fir is
+ /* Memory I/Os: */
+-- signal q:signed(width-1 downto 0):=(others=>'0');
+ signal q:signed(u'range);
+
+ --signal rst: std_ulogic;
+ --signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0');
+ --signal trig:std_logic;
+
+ --signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits
+
+
+ -- debugger
+ --signal dbgSignals:std_ulogic_vector(127 downto 0);
+
+
+ /* Memories: */
+ /* TODO: Change these arrays to internal process variables instead. */
+ /* Read-only Memory (ROM). */
+-- type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned.
+-- type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0);
+
+ /* 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. */
+ type signed_vector is array(natural range <>) of signed(u'range);
+ type signedx2_vector is array(natural range<>) of signed(u'length*2-1 downto 0);
+
+ /* Filter length = number of taps = number of coefficients = order + 1 */
+ constant b:signed_vector(0 to order):=(
+ x"FFEF",
+ x"FFED",
+ x"FFE8",
+ x"FFE6",
+ x"FFEB",
+ x"0000",
+ x"002C",
+ x"0075",
+ x"00DC",
+ x"015F",
+ x"01F4",
+ x"028E",
+ x"031F",
+ x"0394",
+ x"03E1",
+ x"03FC",
+ x"03E1",
+ x"0394",
+ x"031F",
+ x"028E",
+ x"01F4",
+ x"015F",
+ x"00DC",
+ x"0075",
+ x"002C",
+ x"0000",
+ x"FFEB",
+ x"FFE6",
+ x"FFE8",
+ x"FFED",
+ x"FFEF"
+ );
+
+ /*Memory Addressing*/
+-- signal c:natural range b'range;
+
+ /* Pipes and delay chains. */
+ signal y0:signed(u'length*2-1 downto 0);
+ signal u_pipe:signed_vector(b'range):=(others=>(others=>'0'));
+ signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0'));
+
+
+ /* Counters. */
+-- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line.
+
+-- /* memory pointers (acts as the read/write address for the synchronous RAM). */
+-- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting).
+ /* [end]: Memories. */
+
+ /* Signal preservations. */
+-- attribute keep:boolean;
+
+ /* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
+ attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera
+-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx
+
+begin
+-- /* 1-Dimensional Synchronous ROM. */
+-- readCoeffs: process(clk) is begin
+-- if rising_edge(clk) then
+-- if reset='1' then q<=(others=>'0');
+-- else q<=b(c);
+-- end if;
+-- end if;
+-- end process readCoeffs;
+
+ u_pipe(0)<=u;
+ u_dlyChain: for i in 1 to u_pipe'high generate
+ delayChain: process(clk) is begin
+ if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if;
+ end process delayChain;
+ end generate u_dlyChain;
+
+ y_pipe(0)<=b(0)*u;
+ y_dlyChain: for i in 1 to y_pipe'high generate
+ y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1);
+ end generate y_dlyChain;
+
+ y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0');
+ y<=y0(y'range);
+end architecture rtl;
Index: trunk/workspaces/fir.qpf
===================================================================
--- trunk/workspaces/fir.qpf (revision 16)
+++ trunk/workspaces/fir.qpf (nonexistent)
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 12.1 Build 177 11/07/2012 SJ Full Version
-# Date created = 00:43:37 March 31, 2015
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "12.1"
-DATE = "00:43:37 March 31, 2015"
-
-# Revisions
-
-PROJECT_REVISION = "fir"
Index: trunk/workspaces/Makefile
===================================================================
--- trunk/workspaces/Makefile (revision 16)
+++ trunk/workspaces/Makefile (revision 17)
@@ -35,8 +35,7 @@
ROOT_PATH = $(PWD)
MODEL_SRC_PATH = $(ROOT_PATH)/../model
-#VHDL_SRC_PATH = $(ROOT_PATH)/../hw
-VHDL_SRC_PATH = $(ROOT_PATH)/../design
+VHDL_SRC_PATH = $(ROOT_PATH)/../hw
VHDL_TB_PATH = $(ROOT_PATH)/../tester
#COMMONFILES_PATH = $(SRC_PATH)/common