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URL https://opencores.org/ocsvn/fpga-cf/fpga-cf/trunk

Subversion Repositories fpga-cf

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  • This comparison shows the changes necessary to convert path
    /fpga-cf/trunk/hdl/port_blank
    from Rev 2 to Rev 8
    Reverse comparison

Rev 2 → Rev 8

/channel5_blank.v
0,0 → 1,23
// 32 bit Port Register
 
`timescale 1ns/100ps
 
module channel5(
input clk,
input rst,
input wen,
input ren,
input in_sof,
input in_eof,
input in_src_rdy,
output in_dst_rdy,
input [7:0] in_data,
output reg out_sof,
output reg out_eof,
input out_dst_rdy,
output out_src_rdy,
output reg [7:0] out_data
);
 
endmodule
/channel6_blank.v
0,0 → 1,23
// 32 bit Port Register
 
`timescale 1ns/100ps
 
module channel6(
input clk,
input rst,
input wen,
input ren,
input in_sof,
input in_eof,
input in_src_rdy,
output in_dst_rdy,
input [7:0] in_data,
output reg out_sof,
output reg out_eof,
input out_dst_rdy,
output out_src_rdy,
output reg [7:0] out_data
);
 
endmodule

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