URL
https://opencores.org/ocsvn/fpga-median/fpga-median/trunk
Subversion Repositories fpga-median
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/fpga-median
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/tags/fpga-filter-b1/sim/tb/dut_if.sv
0,0 → 1,39
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : dut_if.sv |
// AUTHOR : Laue Rami Souza Costa de Jesus |
// ----------------------------------------------------------------------------- |
|
interface dut_if (input bit clk); |
|
//input signals task |
|
logic rst_n; |
logic start; |
|
logic [7:0] pixel1; |
logic [7:0] pixel2; |
logic [7:0] pixel3; |
logic [7:0] pixel4; |
|
logic [31:0] word0; |
logic [31:0] word1; |
logic [31:0] word2; |
|
logic [9:0] waddr; |
logic [1:0] window_line_counter; |
|
//output signals task |
|
logic [31:0] ch_word0; |
logic [31:0] ch_word1; |
logic [31:0] ch_word2; |
|
logic end_of_operation; |
|
logic [7:0] result [0:51983]; |
|
endinterface |
tags/fpga-filter-b1/sim/tb/dut_if.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/fpga-filter-b1/sim/tb/driver.sv
===================================================================
--- tags/fpga-filter-b1/sim/tb/driver.sv (nonexistent)
+++ tags/fpga-filter-b1/sim/tb/driver.sv (revision 6)
@@ -0,0 +1,114 @@
+// +----------------------------------------------------------------------------
+// Universidade Federal da Bahia
+//------------------------------------------------------------------------------
+// PROJECT: FPGA Median Filter
+//------------------------------------------------------------------------------
+// FILE NAME : driver.sv
+// AUTHOR : Laue Rami Souza Costa de Jesus
+// -----------------------------------------------------------------------------
+class driver;
+
+// localparam MEMORY_WIDTH = 4331;
+ localparam NUM_PIXELS = (`IMG_WIDTH * `IMG_HEIGHT) - 1;//102400-1;
+
+ int cnt;
+ int addr;
+ int i;
+ logic [31:0] r_data_bram0;
+ logic [31:0] r_data_bram1;
+ logic [31:0] r_data_bram2;
+
+ logic [7:0] image [0:NUM_PIXELS];
+
+ virtual interface dut_if dut_if;
+
+ function new (virtual interface dut_if m_dut_if);
+ begin
+ dut_if = m_dut_if;
+ end
+ endfunction
+
+ task init();
+ begin
+ $display("RESET --------");
+ dut_if.rst_n = 1;
+ dut_if.start = 0;
+ dut_if.ch_word0 = 0;
+ dut_if.ch_word1 = 0;
+ dut_if.ch_word2 = 0;
+ addr = 0;
+ i = 0;
+ dut_if.end_of_operation = 0;
+ repeat(5)@(negedge dut_if.clk);
+ dut_if.rst_n = 0;
+ repeat(5)@(negedge dut_if.clk);
+ dut_if.rst_n = 1;
+ dut_if.start = 1;
+ repeat(3)@(negedge dut_if.clk);
+ end
+ endtask
+
+ task reorganize_lines();
+ begin
+ wait(dut_if.start);
+ @(negedge dut_if.clk);
+ while(!(dut_if.end_of_operation))begin
+ if(dut_if.window_line_counter == 2'b00)begin
+ dut_if.ch_word0 = dut_if.word0;
+ dut_if.ch_word1 = dut_if.word1;
+ dut_if.ch_word2 = dut_if.word2;
+ end
+ else if(dut_if.window_line_counter == 2'b01)begin
+ dut_if.ch_word0 = dut_if.word1;
+ dut_if.ch_word1 = dut_if.word2;
+ dut_if.ch_word2 = dut_if.word0;
+ end
+ else if(dut_if.window_line_counter == 2'b10)begin
+ dut_if.ch_word0 = dut_if.word2;
+ dut_if.ch_word1 = dut_if.word0;
+ dut_if.ch_word2 = dut_if.word1;
+ end
+ //addr = addr+1;
+ //read 4 pixels from all memories
+ @(negedge dut_if.clk);
+ end
+ dut_if.start = 0;
+ end
+ endtask
+
+ task receive_data();
+ fork begin
+ while(i
tags/fpga-filter-b1/sim/tb/driver.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/fpga-filter-b1/sim/tb/median_tb.v
===================================================================
--- tags/fpga-filter-b1/sim/tb/median_tb.v (nonexistent)
+++ tags/fpga-filter-b1/sim/tb/median_tb.v (revision 6)
@@ -0,0 +1,104 @@
+// +----------------------------------------------------------------------------
+// Universidade Federal da Bahia
+//------------------------------------------------------------------------------
+// PROJECT: FPGA Median Filter
+//------------------------------------------------------------------------------
+// FILE NAME : median_tb.v
+// AUTHOR : João Carlos Bittencourt
+// AUTHOR'S E-MAIL : joaocarlos@ieee.org
+// -----------------------------------------------------------------------------
+// RELEASE HISTORY
+// VERSION DATE AUTHOR DESCRIPTION
+// 1.0 2013-08-27 joao.nunes initial version
+// -----------------------------------------------------------------------------
+// KEYWORDS: median, filter, image processing
+// -----------------------------------------------------------------------------
+// PURPOSE: Testbench for Median filter.
+// -----------------------------------------------------------------------------
+module median_tb;
+
+ localparam PERIOD = 10;
+ localparam PIXEL_DATA_WIDTH = 8;
+ localparam LUT_ADDR_WIDTH = 10; // Input LUTs
+ localparam MEM_ADDR_WIDTH = 10; // Output Memory
+
+ reg clk;
+ reg rst_n;
+ always #(PERIOD/2) clk = ~clk;
+
+ reg [(PIXEL_DATA_WIDTH*4)-1:0] word0;
+ reg [(PIXEL_DATA_WIDTH*4)-1:0] word1;
+ reg [(PIXEL_DATA_WIDTH*4)-1:0] word2;
+
+ wire [PIXEL_DATA_WIDTH-1:0] pixel1;
+ wire [PIXEL_DATA_WIDTH-1:0] pixel2;
+ wire [PIXEL_DATA_WIDTH-1:0] pixel3;
+ wire [PIXEL_DATA_WIDTH-1:0] pixel4;
+
+ wire [9:0] raddr_a;
+ wire [9:0] raddr_b;
+ wire [9:0] raddr_c;
+
+ wire [9:0] waddr;
+
+ median
+ #(
+ .MEM_DATA_WIDTH(PIXEL_DATA_WIDTH*4),
+ .PIXEL_DATA_WIDTH(PIXEL_DATA_WIDTH),
+ .LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
+ .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH)
+ ) dut_u0 (
+ .clk(clk), // Clock
+ .rst_n(rst_n), // Asynchronous reset active low
+
+ .word0(word0),
+ .word1(word1),
+ .word2(word2),
+
+ .pixel1(pixel1),
+ .pixel2(pixel2),
+ .pixel3(pixel3),
+ .pixel4(pixel4),
+ .raddr_a(raddr_a),
+ .raddr_b(raddr_b),
+ .raddr_c(raddr_c),
+
+ .waddr(waddr)
+ );
+
+ initial begin
+ clk = 1;
+ rst_n = 0;
+ word0 = 0;
+ word1 = 0;
+ word2 = 0;
+ #(PERIOD*3)
+ rst_n = 1;
+ word0 = {8'd160,8'd171,8'd164,8'd142};
+ word1 = {8'd123,8'd141,8'd149,8'd154};
+ word2 = {8'd163,8'd177,8'd171,8'd136};
+ #PERIOD
+ word0 = {8'd167,8'd193,8'd171,8'd160};
+ word1 = {8'd174,8'd150,8'd123,8'd166};
+ word2 = {8'd142,8'd165,8'd162,8'd171};
+ #PERIOD
+ word0 = {8'd168,8'd179,8'd146,8'd173};
+ word1 = {8'd171,8'd160,8'd152,8'd154};
+ word2 = {8'd156,8'd142,8'd147,8'd167};
+ #PERIOD
+ word0 = {8'd123,8'd141,8'd149,8'd154};
+ word1 = {8'd163,8'd177,8'd171,8'd136};
+ word2 = {8'd204,8'd151,8'd140,8'd140};
+ #PERIOD
+ word0 = {8'd174,8'd150,8'd123,8'd166};
+ word1 = {8'd142,8'd165,8'd162,8'd171};
+ word2 = {8'd142,8'd158,8'd149,8'd128};
+ #PERIOD
+ word0 = {8'd171,8'd160,8'd152,8'd154};
+ word1 = {8'd156,8'd142,8'd147,8'd167};
+ word2 = {8'd159,8'd128,8'd131,8'd160};
+ repeat (100) @(negedge clk);
+ $stop;
+ end
+
+endmodule
\ No newline at end of file
Index: tags/fpga-filter-b1/sim/tb/median_tb_directed.sv
===================================================================
--- tags/fpga-filter-b1/sim/tb/median_tb_directed.sv (nonexistent)
+++ tags/fpga-filter-b1/sim/tb/median_tb_directed.sv (revision 6)
@@ -0,0 +1,151 @@
+// +----------------------------------------------------------------------------
+// Universidade Federal da Bahia
+//------------------------------------------------------------------------------
+// PROJECT: FPGA Median Filter
+//------------------------------------------------------------------------------
+// FILE NAME : median_tb.v
+// AUTHOR : João Carlos Bittencourt
+// AUTHOR'S E-MAIL : joaocarlos@ieee.org
+// -----------------------------------------------------------------------------
+// RELEASE HISTORY
+// VERSION DATE AUTHOR DESCRIPTION
+// 1.0 2013-08-27 joao.nunes initial version
+// 1.1 2013-09-04 laue.rami modified version
+// -----------------------------------------------------------------------------
+// KEYWORDS: median, filter, image processing
+// -----------------------------------------------------------------------------
+// PURPOSE: Testbench for Median filter.
+// -----------------------------------------------------------------------------
+`define IMG_HEIGHT 'd320
+`define IMG_WIDTH 'd320
+module median_tb;
+
+ `include "../tb/driver.sv"
+
+ driver driver_u0;
+
+ localparam PERIOD = 10;
+ localparam PIXEL_DATA_WIDTH = 8;
+ localparam LUT_ADDR_WIDTH = 14; // Input LUTs
+ localparam MEM_ADDR_WIDTH = 14; // Output Memory
+
+ bit clk;
+
+ wire [MEM_ADDR_WIDTH-1:0] raddr_a;
+ wire [MEM_ADDR_WIDTH-1:0] raddr_b;
+ wire [MEM_ADDR_WIDTH-1:0] raddr_c;
+ wire [MEM_ADDR_WIDTH-1:0] waddr_a;
+ wire [MEM_ADDR_WIDTH-1:0] waddr_b;
+ wire [MEM_ADDR_WIDTH-1:0] waddr_c;
+
+
+ wire [MEM_ADDR_WIDTH-1:0] waddr;
+
+ reg [(PIXEL_DATA_WIDTH*4)-1:0] word0;
+ reg [(PIXEL_DATA_WIDTH*4)-1:0] word1;
+ reg [(PIXEL_DATA_WIDTH*4)-1:0] word2;
+
+ wire [31:0] w_data_bram0;
+ wire [31:0] w_data_bram1;
+ wire [31:0] w_data_bram2;
+
+ //dut_if interface
+ dut_if dut_if (clk);
+
+ //driver
+
+ always #(PERIOD/2) clk = ~clk;
+
+ dual_port_ram
+ #(
+ .MEMFILE("./memA.hex"),
+ .DATA_WIDTH('d32),
+ .ADDR_WIDTH('d14)
+ )
+ BRAM0
+ (
+ .clk(clk),
+ .r_ena(1'b1),
+ .w_ena(1'b0),
+ .w_data(w_data_bram0),
+ .w_addr(waddr_a),
+ .r_addr(raddr_a),
+ .r_data(dut_if.word0)
+ );
+
+ dual_port_ram
+ #(
+ .MEMFILE("./memB.hex"),
+ .DATA_WIDTH('d32),
+ .ADDR_WIDTH('d14)
+ )
+ BRAM1
+ (
+ .clk(clk),
+ .r_ena(1'b1),
+ .w_ena(1'b0),
+ .w_data(w_data_bram1),
+ .w_addr(waddr_b),
+ .r_addr(raddr_b),
+ .r_data(dut_if.word1)
+ );
+
+ dual_port_ram
+ #(
+ .MEMFILE("./memC.hex"),
+ .DATA_WIDTH('d32),
+ .ADDR_WIDTH('d14)
+ )
+ BRAM2
+ (
+ .clk(clk),
+ .r_ena(1'b1),
+ .w_ena(1'b0),
+ .w_data(w_data_bram2),
+ .w_addr(waddr_c),
+ .r_addr(raddr_c),
+ .r_data(dut_if.word2)
+ );
+
+ median
+ #(
+ .MEM_DATA_WIDTH(PIXEL_DATA_WIDTH*4),
+ .PIXEL_DATA_WIDTH(PIXEL_DATA_WIDTH),
+ .LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
+ .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
+ .IMG_WIDTH(`IMG_WIDTH),
+ .IMG_HEIGHT(`IMG_HEIGHT)
+ ) dut_u0 (
+ .clk(clk), // Clock
+ .rst_n(dut_if.rst_n), // Asynchronous reset active low
+ .word0(dut_if.ch_word0),
+ .word1(dut_if.ch_word1),
+ .word2(dut_if.ch_word2),
+ .pixel1(dut_if.pixel1),
+ .pixel2(dut_if.pixel2),
+ .pixel3(dut_if.pixel3),
+ .pixel4(dut_if.pixel4),
+ .raddr_a(raddr_a),
+ .raddr_b(raddr_b),
+ .raddr_c(raddr_c),
+ .waddr(dut_if.waddr)
+ );
+
+ always@(*)begin
+ dut_if.window_line_counter = dut_u0.window_contol.window_line_counter;
+ end
+
+ initial begin
+ $display("INICIO -------");
+ driver_u0 = new(dut_if);
+ driver_u0.init();
+ driver_u0.receive_data();
+ driver_u0.reorganize_lines();
+ wait(dut_if.end_of_operation);
+ driver_u0.write_file();
+ #(PERIOD*3)
+ repeat(100)@(negedge clk);
+ $stop;
+ end
+
+endmodule
tags/fpga-filter-b1/sim/tb/median_tb_directed.sv
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property