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URL https://opencores.org/ocsvn/freq_div/freq_div/trunk

Subversion Repositories freq_div

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  • This comparison shows the changes necessary to convert path 
    /freq_div/trunk/rtl
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/even.v
1,7 → 1,7
 
`include "defines.v"
 
module even(clk, out, P, reset, not_zero);
module even(clk, out, P, reset, not_zero, enable);
 
input clk;
output out;
8,6 → 8,7
input [`SIZE-1:0] P;
input reset;
input not_zero;
input enable;
 
reg [`SIZE-1:0] counter;
reg out_counter;
24,7 → 25,7
counter <= 1;
out_counter <= 1;
end
else
else if(enable)
begin
if(counter == 1)
begin
/divider.v
11,12 → 11,17
wire out_odd;
wire out_even;
wire not_zero;
wire enable_even;
wire enable_odd;
 
assign not_zero = | P[`SIZE-1:1];
 
assign out = (out_odd & P[0] & not_zero) | (out_even & !P[0]);
//assign out = out_odd | out_even;
assign enable_odd = P[0] & not_zero;
assign enable_even = !P[0];
 
even even_0(in, out_even, P, reset, not_zero);
odd odd_0(in, out_odd, P, reset);
even even_0(in, out_even, P, reset, not_zero, enable_even);
odd odd_0(in, out_odd, P, reset, enable_odd);
endmodule //divider
/odd.v
1,12 → 1,13
 
`include "defines.v"
 
module odd(clk, out, P, reset);
module odd(clk, out, P, reset, enable);
 
input clk; // slow clock
output out;
input [`SIZE-1:0] P;
input reset;
input enable;
 
reg [`SIZE-1:0] counter;
reg [`SIZE-1:0] counter2;
25,7 → 26,7
counter <= P;
out_counter <= 1;
end
else
else if (enable)
begin
if(counter == 1)
begin
51,7 → 52,7
initial_begin <= interm_3[`SIZE:1];
out_counter2 <= 1;
end
else if(initial_begin <= 1)
else if(initial_begin <= 1 && enable)
begin
if(counter2 == 1)
begin
63,7 → 64,7
counter2 <= counter2-1;
end
end
else
else if(enable)
begin
initial_begin <= initial_begin - 1;
end
75,7 → 76,7
begin
rst_pulse <= 0;
end
else
else if(enable)
begin
if(P != old_P)
begin
89,5 → 90,4
end
end
 
 
endmodule //odd

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