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URL https://opencores.org/ocsvn/ft245r_interface/ft245r_interface/trunk

Subversion Repositories ft245r_interface

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  • This comparison shows the changes necessary to convert path 
    /ft245r_interface
    from Rev 3 to Rev 4
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  •

Rev 3 → Rev 4

/trunk/ft245rl_interface.vhd
92,8 → 92,24
"XXXXXXXX";
in_buff <= data_io;
busy <= '1' when c_state /= IDLE else
'0';
-- Reset the FT245R chip on powerup.
nrst <= '0' when c_state = INIT else
'1';
 
process(clk, reset, nrxf, ntxe, nce)
nrd <= '0' when c_state = READ_BYTE or c_state = READ_BYTE1 or
(c_state = DO_DELAY and (n_state = READ_BYTE1 or n_state = READ_BYTE2)) else
'1';
nwr <= '1' when (c_state = WRITE_BYTE and ntxe = '0') or (c_state = DO_DELAY and n_state = WRITE_BYTE1) else
'0';
 
we <= '1' when (c_state = WRITE_BYTE and ntxe = '0') or c_state = WRITE_BYTE1 or (c_state = DO_DELAY and (n_state = WRITE_BYTE1 or n_state = WRITE_BYTE2)) else
'0';
process(clk, reset, nrxf, ntxe, nce, data_available, fetch_next_byte, do_write)
begin
if(reset = '0')then
c_state <= INIT;
105,12 → 121,9
delay_cnt <= 0;
current_delay <= 0;
c_state <= IDLE;
nrst <= '0'; -- Reset FT245RL on init
-- This is the "main loop"
when IDLE =>
nrst <= '1';
-- If this condition is true, we may safely read another byte from FT245RL's FIFO
if(nrxf = '0' and data_available = '0')then
c_state <= READ_BYTE;
118,7 → 131,7
-- We have to clear 'data_available' when the client module is requesting a new byte
elsif(fetch_next_byte = '1')then
data_available <= '0';
c_state <= IDLE;
c_state <= READ_BYTE;
-- Well, here we simply write a byte to FT245RL's data bus
elsif(do_write = '1')then
128,8 → 141,6
-- Read one byte from the device
when READ_BYTE =>
busy <= '1';
nrd <= '0';
current_delay <= t3_delay;
c_state <= DO_DELAY;
n_state <= READ_BYTE1;
141,7 → 152,6
when READ_BYTE2 =>
data_out <= in_buff;
nrd <= '1';
current_delay <= t5_delay;
c_state <= DO_DELAY;
n_state <= READ_BYTE3;
151,14 → 161,10
c_state <= DO_DELAY;
n_state <= IDLE;
data_available <= '1';
busy <= '0';
-- Write one byte to the device
when WRITE_BYTE =>
busy <= '1';
if(ntxe = '0')then
nwr <= '1';
we <= '1';
current_delay<= t7_delay;
c_state <= DO_DELAY;
n_state <= WRITE_BYTE1;
168,19 → 174,16
end if;
when WRITE_BYTE1 =>
nwr <= '0';
current_delay <= t11_delay;
c_state <= DO_DELAY;
n_state <= WRITE_BYTE2;
when WRITE_BYTE2 =>
we <= '0';
current_delay <= t12_delay;
c_state <=DO_DELAY;
n_state <= WRITE_BYTE3;
when WRITE_BYTE3 =>
busy <= '0';
c_state <= IDLE;
when DO_DELAY =>

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