URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
Subversion Repositories ft816float
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- This comparison shows the changes necessary to convert path
/ft816float/trunk/rtl/verilog
- from Rev 27 to Rev 28
- ↔ Reverse comparison
Rev 27 → Rev 28
/fpSqrt.v
29,11 → 29,16
// |
// ============================================================================ |
|
`include "fpConfig.sv" |
`include "fp_defines.v" |
|
module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg); |
parameter WID = 128; |
parameter FPWID = 32; |
`include "fpSize.sv" |
localparam pShiftAmt = |
FPWID==80 ? 48 : |
FPWID==64 ? 36 : |
FPWID==32 ? 7 : (FMSB+1-16); |
|
input rst; |
input clk; |
85,7 → 90,7
// - calculate fraction |
// ----------------------------------------------------------- |
|
fpDecomp #(WID) u1 |
fpDecomp #(FPWID) u1 |
( |
.i(a), |
.sgn(sa), |
100,7 → 105,7
assign ex1 = xa + 8'd1; |
assign so = 1'b0; // square root of positive numbers only |
assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in. |
assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << 36); |
assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << pShiftAmt); |
assign sqrinf = aInf; |
assign sqrneg = !az & so; |
|
112,7 → 117,7
.clk(clk), |
.ce(ce), |
.ld(ld), |
.a({fracta1,{FMSB+1{1'b0}}}), |
.a({1'b0,fracta1,{FMSB+1{1'b0}}}), |
.o(sqrto), |
.done(done) |
); |
129,7 → 134,7
endmodule |
|
module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg); |
parameter WID=32; |
parameter FPWID=32; |
`include "fpSize.sv" |
|
input rst; |
149,9 → 154,9
wire [MSB+3:0] fpn0; |
wire done1; |
|
fpSqrt #(WID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg); |
fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) ); |
fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) ); |
fpSqrt #(FPWID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg); |
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) ); |
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) ); |
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf)); |
delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done)); |
endmodule |
/isqrt.v
68,8 → 68,6
else if (ce) begin |
if (!cnt_done) |
cnt <= cnt + 8'd1; |
case(state) |
IDLE: |
if (ld) begin |
cnt <= 8'd0; |
state <= CALC; |
77,6 → 75,7
remHi <= {WID{1'b0}}; |
root <= {WID{1'b0}}; |
end |
case(state) |
CALC: |
if (!cnt_done) begin |
// Shift the remainder low |