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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

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  • This comparison shows the changes necessary to convert path 
    /ft816float/trunk/rtl/verilog2
    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/fpAddsub.v
9,7 → 9,7
// - floating point adder/subtracter
// - ten cycle latency
// - can issue every clock cycle
// - parameterized FPWIDth
// - parameterized width
// - IEEE 754 representation
//
//
146,6 → 146,7
reg a_gt_b3;
reg resZero3;
reg [FMSB+1:0] mfs3;
wire aNan3, bNan3;
 
delay1 #(EMSB+1) dxa3(.clk(clk), .ce(ce), .i(xa2), .o(xa3));
delay1 #(EMSB+1) dxb3(.clk(clk), .ce(ce), .i(xb2), .o(xb3));
155,6 → 156,8
delay2 #(1) dsb2(.clk(clk), .ce(ce), .i(sb1), .o(sb3));
delay2 #(1) dop2(.clk(clk), .ce(ce), .i(op1), .o(op3));
delay3 #(3) drm2(.clk(clk), .ce(ce), .i(rm), .o(rm3));
delay2 #(1) dan2(.clk(clk), .ce(ce), .i(aNan1), .o(aNan3));
delay2 #(1) dbn2(.clk(clk), .ce(ce), .i(bNan1), .o(bNan3));
 
always @(posedge clk)
if (ce) a_gt_b3 <= xa_gt_xb2 || var2;
188,23 → 191,27
// Compute output sign
always @(posedge clk)
if (ce)
case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
4'b0000: so4 <= 0; // + + + = +
4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
4'b0011: so4 <= 0; // + - - = +
4'b0100: so4 <= a_gt_b3; // - + + = sign of larger
4'b0101: so4 <= 1; // - + - = -
4'b0110: so4 <= 1; // - - + = -
4'b0111: so4 <= a_gt_b3; // - - - = sign of larger
4'b1000: so4 <= 0; // A + B, sign = +
4'b1001: so4 <= rm3==3'd3; // A + -B, sign = + unless rounding down
4'b1010: so4 <= rm3==3'd3; // A - B, sign = + unless rounding down
4'b1011: so4 <= 0; // +A - -B, sign = +
4'b1100: so4 <= rm3==3'd3; // -A + B, sign = + unless rounding down
4'b1101: so4 <= 1; // -A + -B, sign = -
4'b1110: so4 <= 1; // -A - +B, sign = -
4'b1111: so4 <= rm3==3'd3; // -A - -B, sign = + unless rounding down
casez ({aNan3,bNan3,resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
6'b10????: so4 <= sa3;
6'b01????: so4 <= sb3;
6'b11????: so4 <= a_gt_b3 ? sa3 : sb3;
6'b000000: so4 <= 0; // + + + = +
6'b000001: so4 <= a_gt_b3 ? 1'b0 : 1'b1; // + + - = sign of larger
6'b000010: so4 <= a_gt_b3 ? 1'b0 : 1'b1; // + - + = sign of larger
6'b000011: so4 <= 0; // + - - = +
6'b000100: so4 <= a_gt_b3 ? 1'b1 : 1'b0; // - + + = sign of larger
6'b000101: so4 <= 1; // - + - = -
6'b000110: so4 <= 1; // - - + = -
6'b000111: so4 <= a_gt_b3 ? 1'b1 : 1'b0; // - - - = sign of larger
 
6'b001000: so4 <= 0; // A + B, sign = +
6'b001001: so4 <= rm3==3'd3; // A + -B, sign = + unless rounding down
6'b001010: so4 <= rm3==3'd3; // A - B, sign = + unless rounding down
6'b001011: so4 <= 0; // +A - -B, sign = +
6'b001100: so4 <= rm3==3'd3; // -A + B, sign = + unless rounding down
6'b001101: so4 <= 1; // -A + -B, sign = -
6'b001110: so4 <= 1; // -A - +B, sign = -
6'b001111: so4 <= rm3==3'd3; // -A - -B, sign = + unless rounding down
endcase
 
always @(posedge clk)
226,19 → 233,19
 
generate
begin
if (FPWID+`EXTRA_BITS==128)
if (FPWID==128)
redor128 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==96)
else if (FPWID==96)
redor96 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==84)
else if (FPWID==84)
redor84 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==80)
else if (FPWID==80)
redor80 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==64)
else if (FPWID==64)
redor64 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==40)
else if (FPWID==40)
redor40 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==32)
else if (FPWID==32)
redor32 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
end
endgenerate
323,7 → 330,7
if (ce)
casez({anbInf9,aNan9,bNan9,xinf9})
4'b1???: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
4'b01??: mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}}; // set MSB of Nan to convert to quiet
4'b01??: mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}}; // Set MSB of Nan to convert to quiet
4'b001?: mo <= {1'b1,1'b1,fractb9[FMSB-1:0],{FMSB+1{1'b0}}};
4'b0001: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero
default: mo <= {mab9,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
347,7 → 354,7
wire [MSB+3:0] fpn0;
 
fpAddsub #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
 
endmodule

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