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/positVerilog/positToInt.sv
0,0 → 1,64
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2020 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// positToInt.sv |
// - posit number to integer convertor |
// - can issue every clock cycle |
// - parameterized width |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// ============================================================================ |
|
`include "positConfig.sv" |
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module positToInt(i, o); |
`include "positSize.sv" |
input [PSTWID-1:0] i; |
output reg [PSTWID-1:0] o; |
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localparam N = PSTWID; |
localparam Bs = $clog2(PSTWID-1); |
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wire sgn; |
wire rgs; |
wire [Bs-1:0] rgm; |
wire [es-1:0] exp; |
wire [N-es-1:0] sig; |
wire zer; |
wire inf; |
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positDecompose #(.PSTWID(PSTWID), .es(es)) u1 (.i(i), .sgn(sgn), .rgs(rgs), .rgm(rgm), .exp(exp), .sig(sig), .zer(zer), .inf(inf)); |
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wire [N-1:0] m = {sig,{es{1'b0}}}; |
// If we have a negative regime then the number is a fraction less than one (output a zero). |
wire isZero = zer|~rgs; |
wire [15:0] ex = (rgm << es) + exp; |
wire [N-1:0] mo = m >> (PSTWID-ex-1); |
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always @* |
casez({isZero,inf}) // exponent all ones or exponent overflow? |
// convert to +0.0 zero-in zero-out (the sign will always be plus) |
2'b1?: o = {PSTWID{1'b0}}; |
// Infinity in or exponent overflow in conversion = infinity out |
2'b01: o = {1'b1,{PSTWID-1{1'b0}}}; |
// Other numbers |
default: o = sgn ? -mo : mo; |
endcase |
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endmodule |