URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
Subversion Repositories ft816float
Compare Revisions
- This comparison shows the changes necessary to convert path
/ft816float/trunk/rtl
- from Rev 72 to Rev 73
- ↔ Reverse comparison
Rev 72 → Rev 73
/verilog2/mult128x128.sv
37,7 → 37,7
// |
// ============================================================================ |
|
//`define KARATSUBA 1 |
`define KARATSUBA 1 |
|
`ifdef KARATSUBA |
|
50,7 → 50,8
|
reg [63:0] a2, b2; |
reg [64:0] a1, b1; |
reg [127:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4; |
reg [127:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3; |
reg [128:0] p4; |
reg [128:0] z1; // extra bit for carry |
reg sgn2, sgn10; |
wire sgn9; |
111,7 → 112,7
always @(posedge clk) |
if (ce) z0c <= z0b; |
always @(posedge clk) |
if (ce) z1 <= {{128{sgn10}},p4} + z2c + z0c; |
if (ce) z1 <= {{128{p4[128]}},p4} + z2c + z0c; |
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always @(posedge clk) |
if (ce) z2d <= z2c; |
/verilog2/mult128x128seq.sv
0,0 → 1,36
module mult128x128seq(clk, ld, a, b, o); |
input clk; |
input ld; |
input [127:0] a; |
input [127:0] b; |
output reg [255:0] o; |
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reg [127:0] aa = 'd0, bb ='d0; |
reg [256:0] acc = 'd0; |
wire [255:0] p1 = acc + bb; |
reg [11:0] count = 'd0; |
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always_ff @(posedge clk) |
begin |
if (ld) begin |
aa <= a; |
bb <= b; |
acc <= 'd0; |
count <= 12'd128; |
end |
else begin |
if (count) begin |
count <= count - 2'd1; |
if (aa[127]) |
acc <= {p1,1'b0}; |
else |
acc <= {acc,1'b0}; |
aa <= {aa[126:0],1'b0}; |
end |
else begin |
o <= acc[256:1]; |
end |
end |
end |
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endmodule |
/verilog2/mult32x32.sv
50,7 → 50,8
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reg [15:0] a2, b2; |
reg [16:0] a1, b1; |
reg [31:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4; |
reg [31:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3; |
reg [32:0] p4; |
reg [32:0] z1; // extra bit for carry |
reg sgn2, sgn3, sgn4; |
|
109,7 → 110,7
always @(posedge clk) |
if (ce) z0c <= z0b; |
always @(posedge clk) |
if (ce) z1 <= {{32{sgn4}},p4} + z2c + z0c; |
if (ce) z1 <= {{32{p4[32]}},p4} + z2c + z0c; |
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always @(posedge clk) |
if (ce) z2d <= z2c; |
/verilog2/mult64x64.sv
37,7 → 37,7
// |
// ============================================================================ |
|
//`define KARATSUBA 1 |
`define KARATSUBA 1 |
|
`ifdef KARATSUBA |
|
50,7 → 50,8
|
reg [31:0] a2, b2; |
reg [32:0] a1, b1; |
reg [63:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4; |
reg [63:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3; |
reg [64:0] p4; |
reg [64:0] z1; // extra bit for carry |
reg sgn2, sgn10; |
wire sgn9; |
111,7 → 112,7
always @(posedge clk) |
if (ce) z0c <= z0b; |
always @(posedge clk) |
if (ce) z1 <= {{64{sgn10}},p4} + z2c + z0c; |
if (ce) z1 <= {{64{p4[64]}},p4} + z2c + z0c; |
|
always @(posedge clk) |
if (ce) z2d <= z2c; |