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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

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    /ft816float/trunk/rtl
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Rev 86 → Rev 88

/verilog2/DFP32To96.sv
0,0 → 1,75
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFP32To96.sv
// - decimal floating convert single to triple
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFP32To96(i, o);
input DFP32 i;
output DFP96 o;
 
wire [11:0] bias96 = 12'h5FF;
wire [ 7:0] bias32 = 8'h5F;
 
DFP32U iu;
DFP96U ou;
 
DFPUnpack32 u1 (i, iu);
 
always_comb
ou.sign = iu.sign;
always_comb
if (iu.infinity|iu.nan)
ou.exp = 12'hBFF;
else
ou.exp = bias96 + (iu.exp - bias32);
always_comb
ou.infinity = iu.infinity;
always_comb
ou.nan = iu.nan;
always_comb
ou.qnan = iu.qnan;
always_comb
ou.snan = iu.snan;
always_comb]
ou.sig = {iu.sig,72'd0};
 
DFPPack96 u2 (ou, o);
 
endmodule
/verilog2/DFP64To96.sv
0,0 → 1,75
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFP64To96.sv
// - decimal floating convert double to triple
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFP64To96(i, o);
input DFP64 i;
output DFP96 o;
 
wire [11:0] bias96 = 12'h5FF;
wire [ 9:0] bias64 = 10'h17F;
 
DFP64U iu;
DFP96U ou;
 
DFPUnpack64 u1 (i, iu);
 
always_comb
ou.sign = iu.sign;
always_comb
if (iu.infinity|iu.nan)
ou.exp = 12'hBFF;
else
ou.exp = bias96 + (iu.exp - bias64);
always_comb
ou.infinity = iu.infinity;
always_comb
ou.nan = iu.nan;
always_comb
ou.qnan = iu.qnan;
always_comb
ou.snan = iu.snan;
always_comb
ou.sig = {iu.sig,36'd0};
 
DFPPack96 u2 (ou, o);
 
endmodule
/verilog2/DFPPkg.sv
191,4 → 191,45
logic [127:0] sig; // significand 32 digits
} DFP64UD;
 
typedef struct packed
{
logic sign;
logic [4:0] combo;
logic [5:0] expc; // exponent continuation field
logic [19:0] sigc; // significand continuation field
} DFP32;
 
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [7:0] exp;
logic [27:0] sig; // significand 7 digits
} DFP32U;
 
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [7:0] exp;
logic [31:0] sig; // significand 8 digits
} DFP32UN;
 
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [7:0] exp;
logic [55:0] sig; // significand 14 digits
} DFP32UD;
 
endpackage
/verilog2/DFPTrunc96.sv
0,0 → 1,107
// ============================================================================
// __
// \\__/ o\ (C) 2019-2021 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPTrunc96.sv
// - convert floating point to integer (chop off fractional bits)
// - single cycle latency floating point unit
// - IEEE 754 representation
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFPTrunc96(clk, ce, i, o, overflow);
parameter N=25; // number of sig. digits
input clk;
input ce;
input DFP96 i;
output DFP96 o;
output reg overflow;
 
 
integer n;
DFP96U maxInt;
DFP96U iu, ou;
 
DFPUnpack96 u01 (i, iu);
DFPPack96 u02 (ou, o);
 
assign maxInt.sign = 1'b0;
assign maxInt.exp = 12'hBFE;
assign maxInt.sig = 100'h9999999999999999999999999;// maximum unsigned integer value
wire [11:0] zeroXp = 12'h5FF; // simple constant - value of exp for zero
 
// Decompose fp value
reg sgn; // sign
reg [11:0] exp;
reg [N*4-1:0] man;
reg [N*4-1:0] mask;
 
wire [12:0] shamt = (N - 1) - (exp - zeroXp);
 
genvar g;
generate begin : gMask
for (g = 0; g < N; g = g +1)
always_comb
mask[g*4+3:g*4] = (g > shamt) ? 4'hF : 4'h0;
end
endgenerate
 
always_comb
sgn = iu.sign;
always_comb
exp = iu.exp;
always_comb
if (exp > zeroXp + (N-1))
man = iu.sig;
else
man = iu.sig & mask;
 
always_ff @(posedge clk)
if (ce) begin
if (exp < zeroXp) begin
ou <= 'd0;
ou.sign <= sgn; // retain sign
end
else begin
ou.sign <= sgn;
ou.exp <= exp;
ou.sig <= man;
end
end
 
always_comb
overflow <= 1'b0;
 
endmodule
/verilog2/DFPUnpack.sv
80,3 → 80,18
assign o.sig[63:60] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
 
endmodule
 
module DFPUnpack32(i, o);
input DFP32 i;
output DFP32U o;
 
assign o.sign = i.sign;
assign o.exp = {i.combo[4:3]==2'b11 ? i.combo[2:1] : i.combo[4:3],i.expc};
assign o.nan = i.combo==5'b11111;
assign o.qnan = i.combo==5'b11111 && i.expc[7]==1'b0;
assign o.snan = i.combo==5'b11111 && i.expc[7]==1'b1;
assign o.infinity = i.combo==5'b11110;
DPDDecodeN #(.N(2)) u1 (i.sigc, o.sig[23:0]);
assign o.sig[27:24] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
 
endmodule

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