URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
Subversion Repositories ft816float
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- This comparison shows the changes necessary to convert path
/ft816float/trunk/test_bench
- from Rev 54 to Rev 55
- ↔ Reverse comparison
Rev 54 → Rev 55
/DFPAddsub_tb.v
41,14 → 41,14
reg rst; |
reg clk; |
reg [15:0] adr; |
reg [127:0] a,b; |
wire [127:0] o; |
reg [127:0] ad,bd; |
reg [127:0] od; |
reg [151:0] a,b; |
wire [151:0] o; |
reg [151:0] ad,bd; |
reg [151:0] od; |
reg [3:0] rm; |
|
integer n; |
reg [127:0] a1, b1; |
reg [151:0] a1, b1; |
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}}; |
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}}; |
|
71,7 → 71,7
|
genvar g; |
generate begin : gRand |
for (g = 0; g < 128; g = g + 4) begin |
for (g = 0; g < 152; g = g + 4) begin |
always @(posedge clk) begin |
a1[g+3:g] <= $urandom() % 10; |
b1[g+3:g] <= $urandom() % 10; |
96,25 → 96,25
if (count > 32) |
count <= 1'd1; |
if (count==2) begin |
a[127:0] <= a1; |
b[127:0] <= b1; |
a[127:124] <= 4'h5; |
b[127:124] <= 4'h5; |
a <= a1; |
b <= b1; |
a[151:148] <= 4'h5; |
b[151:148] <= 4'h5; |
rm <= adr[14:12]; |
//ad <= memd[adr][63: 0]; |
//bd <= memd[adr][127:64]; |
end |
if (adr==1 && count==2) begin |
a <= 127'h50000700000000000000000000000000; |
b <= 127'h50000200000000000000000000000000; |
a <= 152'h50000700000000000000000000000000000000; |
b <= 152'h50000200000000000000000000000000000000; |
end |
if (adr==2 && count==2) begin |
a <= 127'h50000900000000000000000000000000; |
b <= 127'h50000200000000000000000000000000; |
a <= 152'h50000900000000000000000000000000000000; |
b <= 152'h50000200000000000000000000000000000000; |
end |
if (adr==3 && count==2) begin |
a <= 127'h50000000000000000000000000000000; |
b <= 127'h50000000000000000000000000000000; |
a <= 152'h50000000000000000000000000000000000000; |
b <= 152'h50000000000000000000000000000000000000; |
end |
if (count==31) begin |
if (adr[11]) begin |
/DFPDivide_tb.v
49,18 → 49,19
// ============================================================================ |
|
module DFPDivide_tb(); |
parameter N=33; |
reg rst; |
reg clk; |
reg [15:0] adr; |
reg [127:0] a,b; |
wire [127:0] o; |
reg [127:0] ad,bd; |
wire [127:0] od; |
reg [N*4+16+4-1:0] a,b; |
wire [N*4+16+4-1:0] o; |
reg [N*4+16+4-1:0] ad,bd; |
wire [N*4+16+4-1:0] od; |
reg [3:0] rm; |
wire done; |
|
integer n; |
reg [127:0] a1, b1; |
reg [N*4+16+4-1:0] a1, b1; |
reg [39:0] sum_cc; |
|
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}}; |
85,7 → 86,7
|
genvar g; |
generate begin : gRand |
for (g = 0; g < 128; g = g + 4) begin |
for (g = 0; g < N*4+16+4; g = g + 4) begin |
always @(posedge clk) begin |
a1[g+3:g] <= $urandom() % 10; |
b1[g+3:g] <= $urandom() % 10; |
109,42 → 110,42
sum_cc = 0; |
end |
count <= count + 1; |
if (count > 700) |
if (count > 750) |
count <= 1'd1; |
if (count==2) begin |
a[127:0] <= a1; |
b[127:0] <= b1; |
a[127:124] <= 4'h5; |
b[127:124] <= 4'h5; |
a[N*4+16+4-1:0] <= a1; |
b[N*4+16+4-1:0] <= b1; |
a[N*4+16+4-1:N*4+16+4-4] <= 4'h5; |
b[N*4+16+4-1:N*4+16+4-4] <= 4'h5; |
rm <= adr[15:13]; |
//ad <= memd[adr][63: 0]; |
//bd <= memd[adr][127:64]; |
end |
if (adr==1 && count==2) begin |
a <= 127'h50000700000000000000000000000000; |
b <= 127'h50000200000000000000000000000000; |
a <= 152'h50000700000000000000000000000000000000; |
b <= 152'h50000200000000000000000000000000000000; |
end |
if (adr==1 && count==2) begin |
a <= 127'h50000100000000000000000000000000; |
b <= 127'h50000300000000000000000000000000; |
a <= 152'h50000100000000000000000000000000000000; |
b <= 152'h50000300000000000000000000000000000000; |
end |
if (adr==2 && count==2) begin |
a <= 127'h50000900000000000000000000000000; |
b <= 127'h50000200000000000000000000000000; |
a <= 152'h50000900000000000000000000000000000000; |
b <= 152'h50000200000000000000000000000000000000; |
end |
if (adr==3 && count==2) begin |
a <= 127'h50000000000000000000000000000000; |
b <= 127'h50000000000000000000000000000000; |
a <= 152'h50000000000000000000000000000000000000; |
b <= 152'h50000000000000000000000000000000000000; |
end |
if (adr==4 && count==2) begin |
a <= 127'h50001100000000000000000000000000; |
b <= 127'h50001100000000000000000000000000; |
a <= 152'h50001100000000000000000000000000000000; |
b <= 152'h50001100000000000000000000000000000000; |
end |
if (adr==4 && count==2) begin |
a <= 127'h50000100000000000000000000000000; |
b <= 127'h50000300000000000000000000000000; |
a <= 152'h50000100000000000000000000000000000000; |
b <= 152'h50000300000000000000000000000000000000; |
end |
if (count > 700) begin |
if (count > 750) begin |
sum_cc = sum_cc + u6.u1.u2.clkcnt; |
$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\t%f\n", rm, a, b, o, u6.u1.u2.clkcnt, $itor(sum_cc) / $itor(adr)); |
adr <= adr + 1; |
152,7 → 153,7
end |
|
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow); |
DFPDividenr u6 ( |
DFPDividenr #(.N(N)) u6 ( |
.rst(rst), |
.clk(clk), |
.ce(1'b1), |
/DFPMultiply_tb.v
35,13 → 35,14
// ============================================================================ |
|
module DFPMultiply_tb(); |
parameter N=33; |
reg rst; |
reg clk; |
reg [15:0] adr; |
reg [127:0] a,b; |
wire [127:0] o; |
reg [127:0] ad,bd; |
wire [127:0] od; |
reg [N*4+16+4-1:0] a,b; |
wire [N*4+16+4-1:0] o; |
reg [N*4+16+4-1:0] ad,bd; |
wire [N*4+16+4-1:0] od; |
reg [3:0] rm; |
|
integer n; |
60,7 → 61,7
a = $urandom(1); |
#20 rst = 1; |
#50 rst = 0; |
#1000000 $fclose(outfile); |
#2000000 $fclose(outfile); |
#10 $finish; |
end |
|
69,7 → 70,7
|
genvar g; |
generate begin : gRand |
for (g = 0; g < 128; g = g + 4) begin |
for (g = 0; g < N*4+16+4; g = g + 4) begin |
always @(posedge clk) begin |
a1[g+3:g] <= $urandom() % 10; |
b1[g+3:g] <= $urandom() % 10; |
92,13 → 93,17
$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Product - - SIM Product -\n"); |
end |
count <= count + 1; |
if (count > 600) |
if (count > 750) |
count <= 1'd1; |
if (count==2) begin |
a[127:0] <= a1; |
b[127:0] <= b1; |
a[127:124] <= 4'h5; |
b[127:124] <= 4'h5; |
a[N*4+16+4-1:0] <= a1; |
b[N*4+16+4-1:0] <= b1; |
a[N*4+16+4-1:N*4+16+4-4] <= 4'h5; |
b[N*4+16+4-1:N*4+16+4-4] <= 4'h5; |
a[N*4+16+4-2] <= adr[7]; |
a[N*4+16+4-3] <= adr[6]; |
b[N*4+16+4-1] <= adr[5]; |
b[N*4+16+4-4] <= adr[4]; |
ld <= 1'b1; |
rm <= adr[15:13]; |
//ad <= memd[adr][63: 0]; |
105,26 → 110,26
//bd <= memd[adr][127:64]; |
end |
if (adr==1 && count==2) begin |
a <= 127'h50000700000000000000000000000000; |
b <= 127'h50000200000000000000000000000000; |
a <= 152'h50000700000000000000000000000000000000; |
b <= 152'h50000200000000000000000000000000000000; |
end |
if (adr==1 && count==2) begin |
a <= 127'h40001333333333333333333333333333; |
b <= 127'h50000300000000000000000000000000; |
a <= 152'h40001333333333333333333333333333333333; |
b <= 152'h50000300000000000000000000000000000000; |
end |
if (adr==2 && count==2) begin |
a <= 127'h50000900000000000000000000000000; |
b <= 127'h50000200000000000000000000000000; |
a <= 152'h50000900000000000000000000000000000000; |
b <= 152'h50000200000000000000000000000000000000; |
end |
if (adr==3 && count==2) begin |
a <= 127'h50000000000000000000000000000000; |
b <= 127'h50000000000000000000000000000000; |
a <= 152'h50000000000000000000000000000000000000; |
b <= 152'h50000000000000000000000000000000000000; |
end |
if (adr==4 && count==2) begin |
a <= 127'h50001100000000000000000000000000; |
b <= 127'h50001100000000000000000000000000; |
a <= 152'h50001100000000000000000000000000000000; |
b <= 152'h50001100000000000000000000000000000000; |
end |
if (count==600) begin |
if (count==750) begin |
$fwrite(outfile, "%h\t%h\t%h\t%h\n", rm, a, b, o); |
adr <= adr + 1; |
end |