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https://opencores.org/ocsvn/ft816float/ft816float/trunk
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Rev 26 → Rev 27
/rtl/verilog/fpFMA.v
44,7 → 44,7
// |
// ============================================================================ |
|
module fpFMA (clk, ce, op, rm, a, b, c, o, inf); |
module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero); |
parameter WID = 32; |
`include "fpSize.sv" |
|
54,7 → 54,10
input [2:0] rm; |
input [WID:1] a, b, c; |
output [EX:0] o; |
output under; |
output over; |
output inf; |
output zero; |
|
// constants |
wire [EMSB:0] infXp = {EMSB+1{1'b1}}; // infinite / NaN - all ones |
78,7 → 81,6
wire az1, bz1, cz1; |
wire aInf1, bInf1, cInf1; |
reg op1; |
wire xcInf1; |
|
fpDecompReg #(WID) u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa1), .exp(xa1), .fract(fracta1), .xz(a_dn1), .vz(az1), .inf(aInf1), .nan(aNan1) ); |
fpDecompReg #(WID) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb1), .exp(xb1), .fract(fractb1), .xz(b_dn1), .vz(bz1), .inf(bInf1), .nan(bNan1) ); |
389,7 → 391,7
// Status |
reg under5; |
reg over5; |
reg [EMSB:0] ex5; |
reg [EMSB+2:0] ex5; |
reg [EMSB:0] xc5; |
wire aInf5, bInf5; |
wire aNan5, bNan5; |
400,7 → 402,7
always @(posedge clk) |
if (ce) over5 <= (&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2]; |
always @(posedge clk) |
if (ce) ex5 <= ex4[EMSB:0]; |
if (ce) ex5 <= ex4; |
always @(posedge clk) |
if (ce) xc5 <= xc4; |
|
423,9 → 425,8
// ----------------------------------------------------------- |
|
reg [FX:0] mo6; |
reg [EMSB:0] ex6; |
reg [EMSB+2:0] ex6; |
reg [EMSB:0] xc6; |
reg exinf6; |
wire [FMSB+1:0] fractc6; |
delay5 #(FMSB+2) u61 (.clk(clk), .ce(ce), .i(fractc1), .o(fractc6) ); |
delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6)); |
452,8 → 453,8
5'b01???: ex6 <= infXp; // 'a' infinite |
5'b001??: ex6 <= infXp; // 'b' infinite |
5'b0001?: ex6 <= infXp; // result overflow |
5'b00001: ex6 <= ex5[EMSB:0];//0; // underflow |
default: ex6 <= ex5[EMSB:0]; // situation normal |
5'b00001: ex6 <= ex5; //0; // underflow |
default: ex6 <= ex5; // situation normal |
endcase |
|
// ----------------------------------------------------------- |
469,9 → 470,9
|
// which has greater magnitude ? Used for sign calc |
always @(posedge clk) |
if (ce) ex_gt_xc7 <= (ex6 > xc6) && !under6; |
if (ce) ex_gt_xc7 <= $signed(ex6) > $signed({2'b0,xc6}); |
always @(posedge clk) |
if (ce) xeq7 <= (ex6==xc6) && !under6; |
if (ce) xeq7 <= (ex6=={2'b0,xc6}); |
always @(posedge clk) |
if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}}; |
always @(posedge clk) |
490,20 → 491,20
reg a_gt_b8; |
reg resZero8; |
reg ex_gt_xc8; |
wire [EMSB:0] ex8; |
wire [EMSB+2:0] ex8; |
wire [EMSB:0] xc8; |
wire xcInf8; |
wire [2:0] rm8; |
wire op8; |
wire sa8, sb8, sc8; |
wire sa8, sc8; |
|
delay2 #(EMSB+1) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8)); |
delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8)); |
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8)); |
vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8)); |
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8)); |
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8)); |
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd7), .d(sa1 ^ sb1), .q(sa8)); |
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(sc1), .q(sc8)); |
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd6), .d(sa1 ^ sb1), .q(sa8)); |
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd6), .d(sc1), .q(sc8)); |
|
always @(posedge clk) |
if (ce) ex_gt_xc8 <= ex_gt_xc7; |
528,8 → 529,8
// ----------------------------------------------------------- |
|
reg so9; |
reg [EMSB:0] ex9; |
reg [EMSB:0] ex9a; |
reg [EMSB+2:0] ex9; |
reg [EMSB+2:0] ex9a; |
reg ex_gt_xc9; |
reg [EMSB:0] xc9; |
reg a_gt_c9; |
553,7 → 554,7
delay2 u96 (.clk(clk), .ce(ce), .i(xeq7), .o(xeq9)); |
|
always @(posedge clk) |
if (ce) ex9 <= resZero8 ? 0 : ex_gt_xc8 ? ex8 : xc8; |
if (ce) ex9 <= resZero8 ? 1'd0 : ex_gt_xc8 ? ex8 : {2'b0,xc8}; |
|
// Compute output sign |
always @(posedge clk) |
585,13 → 586,19
// is the same as an add. The underflow is tracked rather than |
// using extra bits in the exponent. |
// ----------------------------------------------------------- |
reg [EMSB:0] xdiff10; |
reg [EMSB+2:0] xdiff10; |
reg [FX:0] mfs; |
reg ops10; |
|
// If the multiplier exponent was negative (underflowed) then |
// the mantissa needs to be shifted right even more (until |
// the exponent is zero. The total shift would be xc9-0- |
// amount underflows which is xc9 + -ex9a. |
|
always @(posedge clk) |
if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9 |
: (under9 ? xc9 + ex9a : xc9 - ex9a); |
: ex9a[EMSB+2] ? xc9 + (~ex9a+2'd1) |
: xc9 - ex9a; |
|
// Determine which fraction to denormalize (the one with the |
// smaller exponent is denormalized). If the exponents are equal |
684,9 → 691,11
reg [FX+2:0] oaa, obb; |
wire realOp15; |
wire [EMSB:0] ex15; |
|
wire [EMSB:0] ex9c = ex9[EMSB+1] ? infXp : ex9[EMSB:0]; |
wire overflow15; |
vtdl #(1) u151 (.clk(clk), .ce(ce), .a(4'd7), .d(realOp7), .q(realOp15)); |
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9), .q(ex15)); |
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9c), .q(ex15)); |
vtdl #(EMSB+1) u153 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9[EMSB+1]| &ex9[EMSB:0]), .q(overflow15)); |
|
always @(posedge clk) |
if (ce) oaa <= a_gt_b14 ? oa : ob; |
709,7 → 718,7
|
vtdl #(1) u161 (.clk(clk), .ce(ce), .a(4'd10), .d(qNaNOut5|aNan5|bNan5), .q(Nan16)); |
vtdl #(1) u162 (.clk(clk), .ce(ce), .a(4'd14), .d(cNan1), .q(cNan16)); |
vtdl #(1) u163 (.clk(clk), .ce(ce), .a(4'd9), .d(exinf6), .q(aInf16)); |
vtdl #(1) u163 (.clk(clk), .ce(ce), .a(4'd9), .d(&ex6), .q(aInf16)); |
vtdl #(1) u164 (.clk(clk), .ce(ce), .a(4'd14), .d(cInf1), .q(cInf16)); |
vtdl #(1) u165 (.clk(clk), .ce(ce), .a(4'd14), .d(op1), .q(op16)); |
delay3 #(FX+1) u166 (.clk(clk), .ce(ce), .i(mo13), .o(mo16)); |
726,9 → 735,13
wire [EMSB:0] ex17; |
reg [FX:0] mo17; |
wire so17; |
wire exinf17; |
wire overflow17; |
|
vtdl #(1) u171 (.clk(clk), .ce(ce), .a(4'd7), .d(so9), .q(so17)); |
delay2 #(EMSB+1) u172 (.clk(clk), .ce(ce), .i(ex15), .o(ex17)); |
delay1 #(1) u173 (.clk(clk), .ce(ce), .i(exinf16), .o(exinf17)); |
delay2 u174 (.clk(clk), .ce(ce), .i(overflow15), .o(overflow17)); |
|
always @(posedge clk) |
casez({aInf16&cInf16,Nan16,cNan16,exinf16}) |
740,19 → 753,18
endcase |
|
assign o = {so17,ex17,mo17}; |
assign zero = {ex17,mo17}==1'd0; |
assign inf = exinf17; |
assign under = ex17==1'd0; |
assign over = overflow17; |
|
// The following are from the multiplier!!! |
vtdl #(1) u173 (.clk(clk), .ce(ce), .a(4'd11), .d(over5), .q(overflow) ); |
vtdl #(1) u174 (.clk(clk), .ce(ce), .a(4'd11), .d(over5), .q(inf) ); |
vtdl #(1) u175 (.clk(clk), .ce(ce), .a(4'd11), .d(under5), .q(underflow) ); |
|
endmodule |
|
|
// Multiplier with normalization and rounding. |
|
module fpFMAnr(clk, ce, op, rm, a, b, c, o, sign_exe, inf, overflow, underflow); |
parameter WID=32; |
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, overflow, underflow, inexact); |
parameter WID=64; |
`include "fpSize.sv" |
|
input clk; |
761,19 → 773,45
input [2:0] rm; |
input [MSB:0] a, b, c; |
output [MSB:0] o; |
output sign_exe; |
output inf; |
output overflow; |
output underflow; |
output inexact; |
|
wire [EX:0] o1; |
wire [EX:0] fma_o; |
wire fma_underflow; |
wire norm_underflow; |
wire norm_inexact; |
wire sign_exe1, inf1, overflow1, underflow1; |
wire [MSB+3:0] fpn0; |
|
fpFMA #(WID) u1 (clk, ce, op, rm, a, b, c, o1, inf1); |
fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) ); |
fpFMA #(WID) u1 |
( |
.clk(clk), |
.ce(ce), |
.op(op), |
.rm(rm), |
.a(a), |
.b(b), |
.c(c), |
.o(fma_o), |
.under(fma_underflow), |
.inf() |
); |
fpNormalize #(WID) u2 |
( |
.clk(clk), |
.ce(ce), |
.i(fma_o), |
.o(fpn0), |
.under_i(fma_underflow), |
.under_o(norm_underflow), |
.inexact_o(norm_inexact) |
); |
fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) ); |
delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe)); |
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf)); |
fpDecomp #(WID) u4(.i(o), .xz(underflow), .inf(inf)); |
delay1 #(1) u6 (.clk(clk), .ce(ce), .i(norm_inexact), .o(inexact)); |
assign overflow = inf; |
|
endmodule |
|
/rtl/verilog/fpNormalize.v
8,7 → 8,7
// |
// fpNormalize.v |
// - floating point normalization unit |
// - one cycle latency |
// - eight cycle latency |
// - parameterized width |
// - IEEE 754 representation |
// |
40,117 → 40,226
// to be negative. A right shift is needed. |
// ============================================================================ |
|
module fpNormalize(clk, ce, under, i, o); |
parameter WID = 128; |
module fpNormalize(clk, ce, i, o, under_i, under_o, inexact_o); |
parameter WID = 84; |
`include "fpSize.sv" |
|
input clk; |
input ce; |
input under; |
input [EX:0] i; // expanded format input |
output [WID+2:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit |
input under_i; |
output under_o; |
output inexact_o; |
|
// variables |
wire so; |
|
wire so1 = i[EX]; // sign doesn't change |
// ---------------------------------------------------------------------------- |
// No Clock required |
// ---------------------------------------------------------------------------- |
reg [EMSB:0] xo0; |
reg so0; |
|
always @* |
xo0 <= i[EX-1:FX+1]; |
always @* |
so0 <= i[EX]; // sign doesn't change |
|
// ---------------------------------------------------------------------------- |
// Clock #1 |
// - Capture exponent information |
// ---------------------------------------------------------------------------- |
reg xInf1a, xInf1b, xInf1c; |
wire [FX:0] i1; |
delay1 #(FX+1) u11 (.clk(clk), .ce(ce), .i(i), .o(i1)); |
|
always @(posedge clk) |
if (ce) xInf1a <= &xo0 & !under_i; |
always @(posedge clk) |
if (ce) xInf1b <= &xo0[EMSB:1] & !under_i; |
always @(posedge clk) |
if (ce) xInf1c = &xo0; |
|
// ---------------------------------------------------------------------------- |
// Clock #2 |
// - determine exponent increment |
// Since the there are *three* whole digits in the incoming format |
// the number of whole digits needs to be reduced. If the MSB is |
// set, then increment the exponent and no shift is needed. |
wire [EMSB:0] xo; |
wire [EMSB:0] xo1a = i[EX-1:FX+1]; |
wire xInf = &xo1a & !under; |
wire xInf3 = &xo1a[EMSB:1] & !under; |
wire incExp2 = !xInf3 & i[FX]; |
wire incExp1 = !xInf & i[FX-1]; |
wire [EMSB:0] xo1 = xo1a + (incExp2 ? 2'd2 : incExp1 ? 2'd1 : 2'd0); |
// ---------------------------------------------------------------------------- |
wire xInf2c, xInf2b; |
wire [EMSB:0] xo2; |
wire xInf1 = &xo1; |
reg incExpByOne2, incExpByTwo2; |
delay1 u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c)); |
delay1 u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b)); |
delay2 #(EMSB+1) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2)); |
delay2 u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2)); |
|
// If infinity is reached then set the mantissa to zero |
// shift mantissa left by one to reduce to a single whole digit |
// if there is no exponent increment |
wire [FMSB+4:0] mo; |
wire [FMSB+4:0] mo1 = ((xInf1 & (incExp1|incExp2))|(xInf3 & incExp2)) ? 0 : |
incExp2 ? {i[FX:FMSB+1],|i[FMSB:0]} : |
incExp1 ? {i[FX-1:FMSB],|i[FMSB-1:0]} : // reduce mantissa size |
{i[FX-2:FMSB-1],|i[FMSB-2:0]}; // reduce mantissa size |
wire [FMSB+4:0] mo2; |
wire [7:0] leadingZeros2; |
always @(posedge clk) |
if (ce) incExpByTwo2 <= !xInf1b & i1[FX]; |
always @(posedge clk) |
if (ce) incExpByOne2 <= !xInf1a & i1[FX-1]; |
|
// ---------------------------------------------------------------------------- |
// Clock #3 |
// - increment exponent |
// - detect a zero mantissa |
// ---------------------------------------------------------------------------- |
|
wire incExpByTwo3; |
wire incExpByOne3; |
wire [FX:0] i3; |
reg [EMSB:0] xo3; |
reg zeroMan3; |
delay1 u31 (.clk(clk), .ce(ce), .i(incExpByTwo2), .o(incExpByTwo3)); |
delay1 u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3)); |
delay3 #(FX+1) u33 (.clk(clk), .ce(ce), .i(i[FX:0]), .o(i3)); |
wire [EMSB+1:0] xv3a = xo2 + {incExpByTwo2,1'b0}; |
wire [EMSB+1:0] xv3b = xo2 + incExpByOne2; |
|
always @(posedge clk) |
if (ce) xo3 <= xo2 + (incExpByTwo2 ? 2'd2 : incExpByOne2 ? 2'd1 : 2'd0); |
|
always @(posedge clk) |
if(ce) zeroMan3 <= ((xv3b[EMSB+1]|| &xv3b[EMSB:0])||(xv3a[EMSB+1]| &xv3a[EMSB:0])) |
&& !under2 && !xInf2c; |
|
// ---------------------------------------------------------------------------- |
// Clock #4 |
// - Shift mantissa left |
// - If infinity is reached then set the mantissa to zero |
// shift mantissa left to reduce to a single whole digit |
// - create sticky bit |
// ---------------------------------------------------------------------------- |
|
reg [FMSB+4:0] mo4; |
reg inexact4; |
|
always @(posedge clk) |
if(ce) |
casez({zeroMan3,incExpByTwo3,incExpByOne3}) |
3'b1??: mo4 <= 1'd0; |
3'b01?: mo4 <= {i3[FX:FMSB+1],|i3[FMSB:0]}; |
3'b001: mo4 <= {i3[FX-1:FMSB],|i3[FMSB-1:0]}; |
default: mo4 <= {i3[FX-2:FMSB-1],|i3[FMSB-2:0]}; |
endcase |
|
always @(posedge clk) |
if(ce) |
casez({zeroMan3,incExpByTwo3,incExpByOne3}) |
3'b1??: inexact4 <= 1'd0; |
3'b01?: inexact4 <= |i3[FMSB:0]; |
3'b001: inexact4 <= |i3[FMSB-1:0]; |
default: inexact4 <= |i3[FMSB-2:0]; |
endcase |
|
// ---------------------------------------------------------------------------- |
// Clock edge #5 |
// - count leading zeros |
// ---------------------------------------------------------------------------- |
wire [7:0] leadingZeros5; |
wire [EMSB:0] xo5; |
wire xInf5; |
delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5)); |
delay3 #(1) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) ); |
|
generate |
begin |
if (WID <= 32) begin |
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) ); |
assign leadingZeros2[7:6] = 2'b00; |
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) ); |
assign leadingZeros5[7:6] = 2'b00; |
end |
else if (WID<=64) begin |
assign leadingZeros2[7] = 1'b0; |
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) ); |
assign leadingZeros5[7] = 1'b0; |
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) ); |
end |
else if (WID<=80) begin |
assign leadingZeros2[7] = 1'b0; |
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) ); |
assign leadingZeros5[7] = 1'b0; |
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) ); |
end |
else if (WID<=84) begin |
assign leadingZeros2[7] = 1'b0; |
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,24'b0}), .o(leadingZeros2) ); |
assign leadingZeros5[7] = 1'b0; |
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) ); |
end |
else if (WID<=96) begin |
assign leadingZeros2[7] = 1'b0; |
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) ); |
assign leadingZeros5[7] = 1'b0; |
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) ); |
end |
else if (WID<=128) |
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) ); |
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) ); |
end |
endgenerate |
|
// compensate for leadingZeros delay |
wire xInf2; |
delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) ); |
delay1 #(1) d3(.clk(clk), .ce(ce), .i(xInf1), .o(xInf2) ); |
|
|
// ---------------------------------------------------------------------------- |
// Clock edge #6 |
// - Compute how much we want to decrement exponent by |
// - compute amount to shift left and right |
// - at infinity the exponent can't be incremented, so we can't shift right |
// otherwise it was an underflow situation so the exponent was negative |
// shift amount needs to be negated for shift register |
// If the exponent underflowed, then the shift direction must be to the |
// right regardless of mantissa bits; the number is denormalized. |
// Otherwise the shift direction must be to the left. |
wire rightOrLeft2; // 0=left,1=right |
delay1 #(1) d8(.clk(clk), .ce(ce), .i(under), .o(rightOrLeft2) ); |
// ---------------------------------------------------------------------------- |
reg [7:0] lshiftAmt6; |
reg [7:0] rshiftAmt6; |
wire rightOrLeft6; // 0=left,1=right |
wire xInf6; |
wire [EMSB:0] xo6; |
wire [FMSB+4:0] mo6; |
wire zeroMan6; |
vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) ); |
delay1 #(EMSB+1) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6)); |
delay2 #(FMSB+5) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) ); |
delay1 #(1) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) ); |
delay3 u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6)); |
|
// Compute how much we want to decrement by |
wire [7:0] lshiftAmt2 = leadingZeros2 > xo2 ? xo2 : leadingZeros2; |
always @(posedge clk) |
if (ce) lshiftAmt6 <= leadingZeros5 > xo5 ? xo5 : leadingZeros5; |
|
// compute amount to shift right |
// at infinity the exponent can't be incremented, so we can't shift right |
// otherwise it was an underflow situation so the exponent was negative |
// shift amount needs to be negated for shift register |
wire [7:0] rshiftAmt2 = xInf2 ? 0 : $signed(xo2) > 0 ? 0 : ~xo2+1;//FMSB+4+xo2; // xo2 is negative ! |
always @(posedge clk) |
if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1; // xo2 is negative ! |
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// ---------------------------------------------------------------------------- |
// Clock edge #7 |
// - fogure exponent |
// - shift mantissa |
// ---------------------------------------------------------------------------- |
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// sign |
// the output sign is the same as the input sign |
delay1 #(1) d7(.clk(clk), .ce(ce), .i(so1), .o(so) ); |
reg [EMSB:0] xo7; |
wire rightOrLeft7; |
reg [FMSB+4:0] mo7l, mo7r; |
delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .i(rightOrLeft7)); |
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// exponent |
// always @(posedge clk) |
// if (ce) |
assign xo = |
xInf2 ? xo2 : // an infinite exponent is either a NaN or infinity; no need to change |
rightOrLeft2 ? 0 : // on a right shift, the exponent was negative, it's being made to zero |
xo2 - lshiftAmt2; // on a left shift, the exponent can't be decremented below zero |
always @(posedge clk) |
if (ce) |
xo7 <= zeroMan6 ? xo6 : |
xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change |
rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero |
xo6 - lshiftAmt6; // on a left shift, the exponent can't be decremented below zero |
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// mantissa |
delay1 #(FMSB+5) d4(.clk(clk), .ce(ce), .i(mo1), .o(mo2) ); |
always @(posedge clk) |
if (ce) mo7r <= mo6 >> rshiftAmt6; |
always @(posedge clk) |
if (ce) mo7l <= mo6 << lshiftAmt6; |
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wire [FMSB+3:0] mo2a; |
//shiftAndMask #(FMSB+4) u1 (.op({rightOrLeft2,1'b0}), .a(mo2), .b(rightOrLeft2 ? lshiftAmt2 : rshiftAmt2), .mb(6'd0), .me(FMSB+3), .o(mo2a) ); |
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// always @(posedge clk) |
// if (ce) |
assign mo = rightOrLeft2 ? (mo2 >> rshiftAmt2) : (mo2 << lshiftAmt2); |
//always @(posedge clk) |
// $display("%c xo2=%d -xo2=%d rshift=%d >%d %d", rightOrLeft2 ? "r" : "l",xo2, -xo2, rshiftAmt2,($unsigned(-xo2) > $unsigned(FMSB+3)),FMSB+3); |
// ---------------------------------------------------------------------------- |
// Clock edge #8 |
// - select mantissa |
// ---------------------------------------------------------------------------- |
|
wire so; |
wire [EMSB:0] xo; |
reg [FMSB+4:0] mo; |
vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) ); |
delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .i(xo)); |
vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o)); |
delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o)); |
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always @(posedge clk) |
if (ce) mo <= rightOrLeft7 ? mo7r : mo7l; |
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assign o = {so,xo,mo[FMSB+4:1]}; |
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endmodule |