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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

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  • This comparison shows the changes necessary to convert path 
    /ft816float/trunk
    from Rev 69 to Rev 70
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Rev 69 → Rev 70

/rtl/verilog2/BCDAdd8NClk.sv
61,16 → 61,14
//---------------
// 199999999 <- second row result
 
module BCDAdd8NClk(clk, ld, a, b, o, ci, co, done);
module BCDAdd8NClk(clk, a, b, o, ci, co);
parameter N=33;
input clk;
input ld;
input [N*8-1:0] a;
input [N*8-1:0] b;
output reg [N*8-1:0] o;
input ci;
output reg co;
output reg done;
 
reg [N-1:0] c [0:2];
wire [N*8-1:0] o1 [0:2];
81,6 → 79,9
generate begin : gBCDadd
for (g = 0; g < N; g = g + 1) begin
for (k = 0; k < 3; k = k + 1) begin
initial begin
c[k][g] <= 'b0;
end
BCDAdd u1 (
.ci(k==0 && g==0 ? ci : 1'b0),
.a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
97,9 → 98,8
always_ff @(posedge clk)
begin
o <= o1[2];
co <= c[2][N-1];
co <= c[2][N-1]|c[1][N-1]|c[0][N-1];
end
end
endgenerate
endmodule
 
/rtl/verilog2/BCDMath.sv
126,34 → 126,7
endgenerate
 
endmodule
/*
module BCDAdd8NClk(clk, a, b, o, ci, co);
parameter N=33;
input clk;
input [N*8-1:0] a;
input [N*8-1:0] b;
output [N*8-1:0] o;
input ci;
output co;
 
reg [N:0] c;
wire [N:0] d;
assign c[0] = ci;
assign co = c[N];
 
genvar g;
generate begin : gBCDadd
for (g = 0; g < N; g = g + 1) begin
BCDAdd u1 (c[g],a[g*8+7:g*8],b[g*8+7:g*8],o[g*8+7:g*8],d[g+1]);
 
always_ff @(posedge clk)
c[g+1] <= d[g+1];
end
end
endgenerate
endmodule
*/
 
module BCDSub(ci,a,b,o,c);
input ci; // carry input
input [7:0] a;
220,35 → 193,8
endgenerate
 
endmodule
 
/*
module BCDSub8NClk(clk, a, b, o, ci, co);
parameter N=33;
input clk;
input [N*8-1:0] a;
input [N*8-1:0] b;
output [N*8-1:0] o;
input ci;
output co;
 
reg [N:0] c;
wire [N:0] d;
assign c[0] = ci;
assign co = c[N];
 
genvar g;
generate begin : gBCDsub
for (g = 0; g < N; g = g + 1) begin
BCDSub u1 (c[g],a[g*8+7:g*8],b[g*8+7:g*8],o[g*8+7:g*8],d[g+1]);
 
always_ff @(posedge clk)
c[g+1] <= d[g+1];
end
end
endgenerate
endmodule
*/
 
module BCDAddAdjust(i,o,c);
input [4:0] i;
output [3:0] o;
/rtl/verilog2/BCDSub8NClk.sv
61,16 → 61,14
//---------------
// 199999999 <- second row result
 
module BCDSub8NClk(clk, ld, a, b, o, ci, co, done);
module BCDSub8NClk(clk, a, b, o, ci, co);
parameter N=33;
input clk;
input ld;
input [N*8-1:0] a;
input [N*8-1:0] b;
output reg [N*8-1:0] o;
input ci;
output reg co;
output reg done;
 
reg [N-1:0] c [0:2];
wire [N*8-1:0] o1 [0:2];
81,6 → 79,9
generate begin : gBCDadd
for (g = 0; g < N; g = g + 1) begin
for (k = 0; k < 3; k = k + 1) begin
initial begin
c[k][g] <= 'b0;
end
BCDSub u1 (
.ci(k==0 && g==0 ? ci : 1'b0),
.a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
97,7 → 98,7
always_ff @(posedge clk)
begin
o <= o1[2];
co <= c[2][N-1];
co <= c[2][N-1]|c[1][N-1]|c[0][N-1];
end
end
endgenerate
/rtl/verilog2/DFPAddsub128.sv
119,7 → 119,6
reg xa_gt_xb2;
reg [N*4-1:0] siga2, sigb2;
reg sigeq, siga_gt_sigb;
reg xa_gt_xb2;
reg expeq;
reg sxo2;
 
/rtl/verilog2/DFPMultiply128.sv
112,7 → 112,6
 
wire under, over;
wire [15:0] sum_ex = au.exp + bu.exp - bias;
reg [15:0] sum_ex;
reg sx0;
wire done1;
assign under = &sum_ex[15:14];
/rtl/verilog2/DFPRound128.sv
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2006-2021 Robert Finch, Waterloo
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
/rtl/verilog2/dfdiv.v
59,7 → 59,7
 
reg [3:0] cnt; // iteration count
reg [7:0] dcnt; // digit count
reg [9:0] clkcnt;
reg [15:0] clkcnt;
reg [5:0] digcnt;
reg [FPWID*2-1:0] qi = 0;
reg [FPWID+4-1:0] ri = 0;
72,17 → 72,19
(* retiming_forward = 1 *)
wire co1;
 
BCDSub8NClk #(.N((N+1)/2)) ubcds1
generate begin : gSub
BCDSub8NClk #(.N((N+2)/2)) ubcds1
(
.clk(clk),
.a(ri),
.b({4'd0,bi}),
.a(~N[0] ? {ri,4'h0} : ri),
.b(~N[0] ? {4'd0,bi,4'h0} : {4'd0,bi}),
.o(dif),
.ci(1'b0),
.co(co)
);
end
endgenerate
 
 
always @(posedge clk)
begin
case(st)
91,7 → 93,7
digcnt <= digcnt - 1'd1;
if (digcnt=='d0) begin
clkcnt <= clkcnt + 1'd1;
digcnt <= 6'd3;
digcnt <= 6'd4;
if (co) begin
ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
qi <= {qi[FPWID*2-5:0],cnt};
132,8 → 134,9
end
end
end
else begin
ri <= dif;
else
begin
ri <= N[0] ? dif : dif[FPWID+4-1:4];
cnt <= cnt + 1'd1;
end
end
151,8 → 154,8
if (ld) begin
clkcnt <= 10'd0;
cnt <= 4'd0;
digcnt <= 6'd3;
dcnt <= (FPWID*2)/4;
digcnt <= 6'd4;
dcnt <= $ceil((FPWID*2)/4);
qi <= {a,{FPWID{1'd0}}};
ri <= {FPWID{1'd0}};
bi <= b;
169,16 → 172,16
 
reg clk;
reg ld;
reg [107:0] a, b;
wire [215:0] q;
wire [107:0] r;
reg [135:0] a, b;
wire [271:0] q;
wire [135:0] r;
wire [7:0] lzcnt;
 
initial begin
clk = 1'b0;
ld = 1'b0;
a = 108'h099_00000000_00000000_00000000;
b = 108'h560_00000000_00000000_00000000;
a = 136'h10_00000000_00000000_00000000_00000000;
b = 136'h20_00000000_00000000_00000000_00000000;
#20 ld = 1'b1;
#40 ld = 1'b0;
end
185,7 → 188,7
 
always #5 clk = ~clk;
 
dfdiv #(.N(27)) u1 (
dfdiv #(.N(34)) u1 (
.clk(clk),
.ld(ld),
.a(a),

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