URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
Subversion Repositories ft816float
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- This comparison shows the changes necessary to convert path
/ft816float
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/trunk/rtl/verilog/fpAddsub_L10.v
343,11 → 343,11
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always @(posedge clk) |
if (ce) |
casez({xinf9,anbInf9,aNan9,bNan9}) |
4'b1???: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero |
4'b01??: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add |
4'b001?: mo <= {1'b0,fracta9[FMSB+1:0],{FMSB{1'b0}}}; |
4'b0001: mo <= {1'b0,fractb9[FMSB+1:0],{FMSB{1'b0}}}; |
casez({anbInf9,aNan9,bNan9,xinf9}) |
4'b1???: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add |
4'b01??: mo <= {1'b0,fracta9[FMSB+1:0],{FMSB{1'b0}}}; |
4'b001?: mo <= {1'b0,fractb9[FMSB+1:0],{FMSB{1'b0}}}; |
4'b0001: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero |
default: mo <= {mab9,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits |
endcase |
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