OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /ft816float
    from Rev 64 to Rev 65
    ↔ Reverse comparison
  •

Rev 64 → Rev 65

/trunk/rtl/verilog2/dfdiv.v
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
60,21 → 60,29
reg [3:0] cnt; // iteration count
reg [7:0] dcnt; // digit count
reg [9:0] clkcnt;
reg [5:0] digcnt;
reg [FPWID*2-1:0] qi = 0;
reg [FPWID+4-1:0] ri = 0;
reg [FPWID-1:0] bi = 0;
wire co;
wire [FPWID+4-1:0] dif;
reg gotnz; // got a non-zero digit
(* retiming_forward = 1 *)
wire [FPWID+4-1:0] dif1;
(* retiming_forward = 1 *)
wire co1;
 
BCDSubN #(.N((FPWID+4)/4)) u1
BCDSub8NClk #(.N((N+1)/2)) ubcds1
(
.ci(1'b0),
.clk(clk),
.a(ri),
.b({4'd0,bi}),
.o(dif),
.ci(1'b0),
.co(co)
);
 
 
always @(posedge clk)
begin
case(st)
81,26 → 89,10
SUBN:
begin
clkcnt <= clkcnt + 1'd1;
if (co) begin
ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
qi <= {qi[FPWID*2-5:0],cnt};
cnt <= 4'd0;
dcnt <= dcnt - 1'd1;
if (dcnt==6'd0)
st <= DONE;
if (dcnt <= FPWID/4) begin
if (|cnt)
gotnz <= 1'b1;
else if (!gotnz) begin
if (lzcnt[3:0]==4'd9)
lzcnt <= lzcnt + 4'd7;
else
lzcnt <= lzcnt + 1'd1;
end
end
end
else begin
if (clkcnt > 600) begin
digcnt <= digcnt - 1'd1;
if (digcnt=='d0) begin
digcnt <= 6'd3;
if (co) begin
ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
qi <= {qi[FPWID*2-5:0],cnt};
cnt <= 4'd0;
119,8 → 111,28
end
end
else begin
ri <= dif;
cnt <= cnt + 1'd1;
if (clkcnt > 600) begin
ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
qi <= {qi[FPWID*2-5:0],cnt};
cnt <= 4'd0;
dcnt <= dcnt - 1'd1;
if (dcnt==6'd0)
st <= DONE;
if (dcnt <= FPWID/4) begin
if (|cnt)
gotnz <= 1'b1;
else if (!gotnz) begin
if (lzcnt[3:0]==4'd9)
lzcnt <= lzcnt + 4'd7;
else
lzcnt <= lzcnt + 1'd1;
end
end
end
else begin
ri <= dif;
cnt <= cnt + 1'd1;
end
end
end
end
136,6 → 148,7
if (ld) begin
clkcnt <= 10'd0;
cnt <= 4'd0;
digcnt <= 6'd3;
dcnt <= (FPWID*2)/4;
qi <= {a,{FPWID{1'd0}}};
ri <= {FPWID{1'd0}};
/trunk/rtl/verilog2/dfmul.sv
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
55,7 → 55,6
parameter ADDN = 2'd1;
parameter DONE = 2'd2;
 
reg [3:0] cnt; // iteration count
reg [7:0] dcnt; // digit count
reg [9:0] clkcnt;
reg [FPWID*2-1:0] pi = 0;
62,17 → 61,19
reg [FPWID-1:0] ai = 0;
reg [FPWID*2-1:0] bi = 0;
wire [FPWID*2-1:0] sum;
reg [5:0] digcnt;
 
BCDAddN #(.N((FPWID*2)/4)) u1
BCDAdd8NClk #(.N(FPWID/4)) ubcdm1
(
.ci(1'b0),
.clk(clk),
.a(pi),
.b(bi),
.o(sum),
.ci(1'b0),
.co()
);
 
always @(posedge clk)
always_ff @(posedge clk)
begin
case(st)
ADDN:
79,9 → 80,13
begin
clkcnt <= clkcnt + 1'd1;
if (ai[FPWID-1:FPWID-4]!=4'h0) begin
pi <= sum;
ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;
cnt <= cnt + 1'd1;
if (digcnt=='d0) begin
pi <= sum;
digcnt <= 6'd3;
ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;
end
else
digcnt <= digcnt - 1'd1;
end
else begin
ai <= {ai,4'h0};
88,7 → 93,7
bi <= {4'h0,bi[FPWID*2-1:4]};
pi <= pi;
dcnt <= dcnt - 1'd1;
if (dcnt==6'd0)
if (dcnt=='d0)
st <= DONE;
end
end
102,7 → 107,7
endcase
if (ld) begin
clkcnt <= 10'd0;
cnt <= 4'd0;
digcnt <= 6'd3;
dcnt <= (FPWID*2)/4;
pi <= {FPWID*2{1'b0}};
ai <= a;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.