URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/funbase_ip_library/trunk/TUT/ip.hwp.storage
- from Rev 145 to Rev 147
- ↔ Reverse comparison
Rev 145 → Rev 147
/sdram_io.absDef/1.0/sdram_io.absDef.1.0.xml
1,5 → 1,8
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus210:07:14 09.03.2012--> |
<!-- Created by Kactus2 - Open source IP-Xact toolset --> |
<!-- http://sourceforge.net/projects/kactus2/ --> |
<!-- Date: 28.08.2012 --> |
<!-- Time: 17:12:26 --> |
<spirit:abstractionDefinition xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.storage</spirit:library> |
/sdram_io.busdef/1.0/sdram_io.busdef.1.0.xml
1,5 → 1,8
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus210:07:14 09.03.2012--> |
<!-- Created by Kactus2 - Open source IP-Xact toolset --> |
<!-- http://sourceforge.net/projects/kactus2/ --> |
<!-- Date: 28.08.2012 --> |
<!-- Time: 17:12:26 --> |
<spirit:busDefinition xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.storage</spirit:library> |
/fifos/fifo_mk2/1.0/vhd/ram_1clk.vhd
6,7 → 6,7
-- Author : Lasse Lehtonen |
-- Company : |
-- Created : 2011-01-13 |
-- Last update: 2011-10-19 |
-- Last update: 2012-06-14 |
-- Platform : |
-- Standard : VHDL'93 |
------------------------------------------------------------------------------- |
51,7 → 51,7
type ram_type is array (0 to depth_g-1) |
of std_logic_vector(data_width_g-1 downto 0); |
|
signal ram_r : ram_type; |
signal ram_r : ram_type := (others => (others => '0')); |
signal read_addr_r : integer range 0 to depth_g-1; |
|
begin -- architecture rtl |