OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

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  • This comparison shows the changes necessary to convert path 
    /funbase_ip_library/trunk/TUT/soc/basic_tester_example
    from Rev 145 to Rev 150
    ↔ Reverse comparison
  •

Rev 145 → Rev 150

/1.0/vhd/basic_tester_hibi_example.vhd
1,7 → 1,7
-- ***************************************************
-- File: basic_tester_hibi_example.vhd
-- Creation date: 02.07.2012
-- Creation time: 15:50:14
-- Creation date: 21.11.2012
-- Creation time: 14:28:17
-- Description: Simple example on how to use basic_tester with hibi.
-- Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.
--
29,8 → 29,8
signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY : std_logic;
signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D : std_logic;
signal basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE : std_logic;
signal clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK : std_logic;
signal rst_r_nRESETn : std_logic;
signal clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK : std_logic;
signal rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn : std_logic;
signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV : std_logic;
signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM : std_logic_vector(4 downto 0);
signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA : std_logic_vector(31 downto 0);
114,10 → 114,14
 
component hibi_segment
generic (
hibi_addr_0_g : integer := 16#01000000#; -- HIBI address for interface 0
hibi_addr_1_g : integer := 16#03000000#; -- HIBI address for interface 1
hibi_addr_2_g : integer := 16#05000000#; -- HIBI address for interface 2
hibi_addr_3_g : integer := 16#07000000# -- HIBI address for interface 3
ip_mslave_0_addr_end : integer := 2; -- HIBI end address for interface 0
ip_mslave_0_addr_start : integer := 1; -- HIBI address for interface 0
ip_mslave_1_addr_end : integer := 4; -- HIBI end address for interface 1
ip_mslave_1_addr_start : integer := 3; -- HIBI address for interface 1
ip_mslave_2_addr_end : integer := 6; -- HIBI end address for interface 2
ip_mslave_2_addr_start : integer := 5; -- HIBI address for interface 2
ip_mslave_3_addr_end : integer := 8; -- HIBI end address for interface 3
ip_mslave_3_addr_start : integer := 7 -- HIBI address for interface 3
 
);
port (
138,16 → 142,16
 
-- Interface: clocks_2
-- Clock inputs interface for hibi wrapper_3
-- agent_clk_2 : in std_logic;
-- agent_sync_clk_2 : in std_logic;
-- bus_clk_2 : in std_logic;
agent_clk_2 : in std_logic;
agent_sync_clk_2 : in std_logic;
bus_clk_2 : in std_logic;
bus_sync_clk_2 : in std_logic;
 
-- Interface: clocks_3
-- Clock inputs interface for hibi wrapper_3
-- agent_clk_3 : in std_logic;
-- agent_sync_clk_3 : in std_logic;
-- bus_clk_3 : in std_logic;
agent_clk_3 : in std_logic;
agent_sync_clk_3 : in std_logic;
bus_clk_3 : in std_logic;
bus_sync_clk_3 : in std_logic;
 
-- Interface: ip_mMaster_0
282,8 → 286,8
agent_empty_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
agent_one_d_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
agent_re_out => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
rst_n => rst_r_nRESETn
clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
);
 
basic_tester_tx_0 : basic_tester_tx
297,22 → 301,16
agent_full_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
agent_one_p_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
agent_we_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
rst_n => rst_r_nRESETn
clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
);
 
clk_gen_0 : clk_gen
port map (
clk_out => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK
clk_out => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK
);
 
hibi_segment_0 : hibi_segment(structural)
generic map (
hibi_addr_0_g => 16#07000000#,
hibi_addr_1_g => 16#05000000#,
hibi_addr_2_g => 16#03000000#,
hibi_addr_3_g => 16#01000000#
)
hibi_segment_0 : hibi_segment
port map (
agent_av_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
agent_av_in_1 => '0',
319,8 → 317,10
agent_av_in_2 => '0',
agent_av_in_3 => '0',
agent_av_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
agent_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
agent_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
agent_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
agent_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
agent_clk_2 => '0',
agent_clk_3 => '0',
agent_comm_in(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
agent_comm_in_1 => (others => '0'),
agent_comm_in_2 => (others => '0'),
339,24 → 339,28
agent_re_in_1 => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
agent_re_in_2 => '0',
agent_re_in_3 => '0',
agent_sync_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
agent_sync_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
agent_sync_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
agent_sync_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
agent_sync_clk_2 => '0',
agent_sync_clk_3 => '0',
agent_we_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
agent_we_in_1 => '0',
agent_we_in_2 => '0',
agent_we_in_3 => '0',
bus_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
bus_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
bus_sync_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
bus_sync_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
bus_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
bus_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
bus_clk_2 => '0',
bus_clk_3 => '0',
bus_sync_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
bus_sync_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
bus_sync_clk_2 => '0',
bus_sync_clk_3 => '0',
rst_n => rst_r_nRESETn
rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
);
 
rst_gen_0 : rst_gen
port map (
rst_n_out => rst_r_nRESETn
rst_n_out => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
);
 
end structural_seg;
/1.0/ip_xact/basic_tester_hibi_example.design.1.0.xml
1,8 → 1,8
<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 02.07.2012 -->
<!-- Time: 17:03:47 -->
<!-- Date: 21.11.2012 -->
<!-- Time: 16:10:19 -->
<spirit:design xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
10,26 → 10,35
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>basic_tester_tx_0</spirit:instanceName>
<spirit:instanceName>clk_gen_0</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="basic_tester_tx" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="conf_file_g">&quot;test_tx.txt&quot;</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clk_gen" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="390" y="60"/>
<kactus2:position x="390" y="450"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clock">
<kactus2:position x="-80" y="90"/>
<kactus2:portPosition kactus2:busRef="Generated_clk">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="hibi_master">
<kactus2:position x="-80" y="40"/>
<kactus2:portPosition kactus2:busRef="Generated_hibi_clk">
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="hibi_slave">
<kactus2:position x="-80" y="60"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
</kactus2:portPositions>
<kactus2:adHocVisibilities/>
<kactus2:propertyValues/>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>rst_gen_0</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="rst_gen" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="390" y="360"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="Generated_reset">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
</kactus2:portPositions>
66,37 → 75,28
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>rst_gen_0</spirit:instanceName>
<spirit:instanceName>basic_tester_tx_0</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="rst_gen" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="basic_tester_tx" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="conf_file_g">&quot;test_tx.txt&quot;</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<kactus2:position x="390" y="360"/>
<kactus2:position x="390" y="60"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="Generated_reset">
<kactus2:position x="80" y="40"/>
<kactus2:portPosition kactus2:busRef="clock">
<kactus2:position x="-80" y="90"/>
</kactus2:portPosition>
</kactus2:portPositions>
<kactus2:adHocVisibilities/>
<kactus2:propertyValues/>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>clk_gen_0</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clk_gen" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="390" y="450"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="Generated_clk">
<kactus2:portPosition kactus2:busRef="hibi_master">
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="hibi_slave">
<kactus2:position x="-80" y="60"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="Generated_hibi_clk">
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
</kactus2:portPositions>
<kactus2:adHocVisibilities/>
<kactus2:propertyValues/>
107,16 → 107,7
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_segment" spirit:version="3.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="hibi_addr_0_g">16#01000000#</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_addr_1_g">16#03000000#</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_addr_2_g">16#03000000#</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_addr_3_g">16#07000000#</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_end_addr_0_g">16#03000000#-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_end_addr_1_g">16#03000000#-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_end_addr_2_g">16#07000000#-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="hibi_end_addr_3_g">16#09000000#-1</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="130" y="60"/>
<kactus2:portPositions>
167,39 → 158,39
</spirit:componentInstances>
<spirit:interconnections>
<spirit:interconnection>
<spirit:name>clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0</spirit:name>
<spirit:name>basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_hibi_clk"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="clocks_0"/>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="hibi_master"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="ip_mMaster_1"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_1</spirit:name>
<spirit:name>basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_hibi_clk"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="clocks_1"/>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="hibi_slave"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="ip_mSlave_1"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>rst_gen_0_Generated_reset_to_hibi_segment_0_rst_n</spirit:name>
<spirit:name>clk_gen_0_Generated_clk_to_basic_tester_tx_0_clock</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="rst_gen_0" spirit:busRef="Generated_reset"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="rst_n"/>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_clk"/>
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="clock"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_master</spirit:name>
<spirit:name>clk_gen_0_Generated_clk_to_basic_tester_rx_0_clock</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="ip_mMaster_0"/>
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="hibi_master"/>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_clk"/>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="clock"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>rst_t_n</spirit:name>
<spirit:name>rst_r_n</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="rst_gen_0" spirit:busRef="Generated_reset"/>
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="reset"/>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="reset"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slave</spirit:name>
209,39 → 200,39
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="hibi_slave"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>rst_r_n</spirit:name>
<spirit:name>rst_t_n</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="rst_gen_0" spirit:busRef="Generated_reset"/>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="reset"/>
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="reset"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>clk_gen_0_Generated_clk_to_basic_tester_rx_0_clock</spirit:name>
<spirit:name>hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_master</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_clk"/>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="clock"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="ip_mMaster_0"/>
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="hibi_master"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>clk_gen_0_Generated_clk_to_basic_tester_tx_0_clock</spirit:name>
<spirit:name>rst_gen_0_Generated_reset_to_hibi_segment_0_rst_n</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_clk"/>
<spirit:activeInterface spirit:componentRef="basic_tester_tx_0" spirit:busRef="clock"/>
<spirit:activeInterface spirit:componentRef="rst_gen_0" spirit:busRef="Generated_reset"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="rst_n"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1</spirit:name>
<spirit:name>clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_1</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="hibi_slave"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="ip_mSlave_1"/>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_hibi_clk"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="clocks_1"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1</spirit:name>
<spirit:name>clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="basic_tester_rx_0" spirit:busRef="hibi_master"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="ip_mMaster_1"/>
<spirit:activeInterface spirit:componentRef="clk_gen_0" spirit:busRef="Generated_hibi_clk"/>
<spirit:activeInterface spirit:componentRef="hibi_segment_0" spirit:busRef="clocks_0"/>
</spirit:interconnection>
</spirit:interconnections>
<spirit:vendorExtensions>
250,59 → 241,59
<kactus2:column name="Components" contentType="2" allowedItems="2" minWidth="259" width="259"/>
</kactus2:columnLayout>
<kactus2:routes>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0" kactus2:offPage="false">
<kactus2:position x="310" y="520"/>
<kactus2:position x="230" y="520"/>
<kactus2:position x="230" y="480"/>
<kactus2:position x="210" y="480"/>
<kactus2:route kactus2:connRef="basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1" kactus2:offPage="false">
<kactus2:position x="310" y="240"/>
<kactus2:position x="210" y="240"/>
</kactus2:route>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_1" kactus2:offPage="false">
<kactus2:position x="310" y="520"/>
<kactus2:position x="230" y="520"/>
<kactus2:position x="230" y="560"/>
<kactus2:position x="210" y="560"/>
<kactus2:route kactus2:connRef="basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1" kactus2:offPage="false">
<kactus2:position x="310" y="260"/>
<kactus2:position x="210" y="260"/>
</kactus2:route>
<kactus2:route kactus2:connRef="rst_gen_0_Generated_reset_to_hibi_segment_0_rst_n" kactus2:offPage="false">
<kactus2:position x="470" y="400"/>
<kactus2:position x="490" y="400"/>
<kactus2:position x="490" y="350"/>
<kactus2:position x="210" y="350"/>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_clk_to_basic_tester_tx_0_clock" kactus2:offPage="true">
<kactus2:position x="500" y="490"/>
<kactus2:position x="280" y="150"/>
</kactus2:route>
<kactus2:route kactus2:connRef="hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_master" kactus2:offPage="false">
<kactus2:position x="210" y="100"/>
<kactus2:position x="310" y="100"/>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_clk_to_basic_tester_rx_0_clock" kactus2:offPage="true">
<kactus2:position x="500" y="490"/>
<kactus2:position x="280" y="310"/>
</kactus2:route>
<kactus2:route kactus2:connRef="rst_t_n" kactus2:offPage="false">
<kactus2:route kactus2:connRef="rst_r_n" kactus2:offPage="false">
<kactus2:position x="470" y="400"/>
<kactus2:position x="500" y="400"/>
<kactus2:position x="500" y="100"/>
<kactus2:position x="470" y="100"/>
<kactus2:position x="500" y="290"/>
<kactus2:position x="470" y="290"/>
</kactus2:route>
<kactus2:route kactus2:connRef="hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slave" kactus2:offPage="false">
<kactus2:position x="210" y="120"/>
<kactus2:position x="310" y="120"/>
</kactus2:route>
<kactus2:route kactus2:connRef="rst_r_n" kactus2:offPage="false">
<kactus2:route kactus2:connRef="rst_t_n" kactus2:offPage="false">
<kactus2:position x="470" y="400"/>
<kactus2:position x="500" y="400"/>
<kactus2:position x="500" y="290"/>
<kactus2:position x="470" y="290"/>
<kactus2:position x="500" y="100"/>
<kactus2:position x="470" y="100"/>
</kactus2:route>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_clk_to_basic_tester_rx_0_clock" kactus2:offPage="true">
<kactus2:position x="500" y="490"/>
<kactus2:position x="280" y="310"/>
<kactus2:route kactus2:connRef="hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_master" kactus2:offPage="false">
<kactus2:position x="210" y="100"/>
<kactus2:position x="310" y="100"/>
</kactus2:route>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_clk_to_basic_tester_tx_0_clock" kactus2:offPage="true">
<kactus2:position x="500" y="490"/>
<kactus2:position x="280" y="150"/>
<kactus2:route kactus2:connRef="rst_gen_0_Generated_reset_to_hibi_segment_0_rst_n" kactus2:offPage="false">
<kactus2:position x="470" y="400"/>
<kactus2:position x="490" y="400"/>
<kactus2:position x="490" y="350"/>
<kactus2:position x="210" y="350"/>
</kactus2:route>
<kactus2:route kactus2:connRef="basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1" kactus2:offPage="false">
<kactus2:position x="310" y="260"/>
<kactus2:position x="210" y="260"/>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_1" kactus2:offPage="false">
<kactus2:position x="310" y="520"/>
<kactus2:position x="240" y="520"/>
<kactus2:position x="240" y="560"/>
<kactus2:position x="210" y="560"/>
</kactus2:route>
<kactus2:route kactus2:connRef="basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1" kactus2:offPage="false">
<kactus2:position x="310" y="240"/>
<kactus2:position x="210" y="240"/>
<kactus2:route kactus2:connRef="clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0" kactus2:offPage="false">
<kactus2:position x="310" y="520"/>
<kactus2:position x="230" y="520"/>
<kactus2:position x="230" y="480"/>
<kactus2:position x="210" y="480"/>
</kactus2:route>
</kactus2:routes>
</spirit:vendorExtensions>
/1.0/ip_xact/basic_tester_hibi_example.designcfg.1.0.xml
1,8 → 1,8
<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 02.07.2012 -->
<!-- Time: 17:03:47 -->
<!-- Date: 21.11.2012 -->
<!-- Time: 16:10:19 -->
<spirit:designConfiguration xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
/1.0/ip_xact/basic_tester_hibi_example.1.0.xml
1,8 → 1,8
<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 04.07.2012 -->
<!-- Time: 14:04:47 -->
<!-- Date: 21.11.2012 -->
<!-- Time: 16:10:19 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
59,6 → 59,12
 
This works with both versions (seg and wra)</spirit:description>
</spirit:file>
<spirit:file>
<spirit:name>../sim/basic_tester_hibi_example.structural.create_makefile.do</spirit:name>
<spirit:userFileType>ModelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:description>Script file for Modelsim that compiles all files for view structural_seg.</spirit:description>
</spirit:file>
<spirit:defaultFileBuilder>
<spirit:userFileType>Modelsim script</spirit:userFileType>
<spirit:command>say &quot;do script_name.do&quot; in Modelsim</spirit:command>
/1.0/sim/basic_tester_hibi_example.structural.create_makefile.do
1,5 → 1,6
# Script compiles all vhdl-files and generates a makefile for them
# This script is tested for Modelsim version 6.6a
# Based on file D:/user/matilail/funbase/repos/daci_repo/soc/basic_tester_example/1.0/ip_xact/basic_tester_hibi_example.1.0.xml and its view "structural_seg"
 
.main clear
 
9,63 → 10,155
echo "Processing file set rtl of component TUT:ip.hwp.communication:basic_tester_tx:1.0."
echo " Adding library work"
vlib work
vcom -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/basic_tester/1.0/vhd/txt_util.vhd
vcom -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/basic_tester/1.0/vhd/basic_tester_pkg.vhd
vcom -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/basic_tester/1.0/vhd/basic_tester_tx.vhd
vcom -check_synthesis D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/basic_tester/1.0/vhd/txt_util.vhd
vcom -check_synthesis D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/basic_tester/1.0/vhd/basic_tester_pkg.vhd
vcom -check_synthesis D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/basic_tester/1.0/vhd/basic_tester_tx.vhd
 
echo "Processing component TUT:ip.hwp.interface:clk_gen:1.0"
echo "Processing file set behavioral of component TUT:ip.hwp.interface:clk_gen:1.0."
vcom -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.interface/clock/1.0/vhd/clk_gen.vhd
 
echo "Processing component TUT:ip.hwp.communication:basic_tester_rx:1.0"
echo "Processing file set rtl of component TUT:ip.hwp.communication:basic_tester_rx:1.0."
vcom -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/basic_tester/1.0/vhd/basic_tester_rx.vhd
vcom -check_synthesis D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/basic_tester/1.0/vhd/basic_tester_rx.vhd
 
echo "Processing component TUT:ip.hwp.interface:rst_gen:1.0"
echo "Processing file set behavioral of component TUT:ip.hwp.interface:rst_gen:1.0."
vcom D:/user/ege/Svn/daci_ip/trunk/ip.hwp.interface/reset/1.0/vhd/rst_gen.vhd
vcom D:/user/matilail/funbase/repos/daci_repo/ip.hwp.interface/reset/1.0/vhd/rst_gen.vhd
 
echo "Processing component TUT:ip.hwp.communication:hibi_segment_small:3.0"
echo "Processing file set hdlSources of component TUT:ip.hwp.communication:hibi_segment_small:3.0."
echo "Processing component TUT:ip.hwp.interface:clk_gen:1.0"
echo "Processing file set behavioral of component TUT:ip.hwp.interface:clk_gen:1.0."
vcom -check_synthesis D:/user/matilail/funbase/repos/daci_repo/ip.hwp.interface/clock/1.0/vhd/clk_gen.vhd
 
echo "Processing component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0"
echo "Processing file set hdlSources of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
echo " Adding library hibi"
vlib hibi
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/hibiv3_pkg.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/addr_data_demux_read.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/addr_data_mux_write.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/addr_decoder.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/cfg_init_pkg.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/cfg_mem.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/double_fifo_demux_wr.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/double_fifo_mux_rd.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/dyn_arb.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/fifo_demux_wr.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/fifo_mux_rd.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/lfsr.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/receiver.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/rx_control.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/transmitter.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/tx_control.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r1.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r3.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r4.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/hibi_segment_small.vhd
vcom -quiet -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.communication/hibi/3.0/vhd/hibi_segment_v3.vhd
echo "Processing file set fifo_rtl of component TUT:ip.hwp.communication:hibi_segment_small:3.0."
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
vcom -check_synthesis -work hibi D:/user/ege/Svn/daci_ip/trunk/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibiv3_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r1.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r4.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/lfsr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/receiver.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/rx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/transmitter.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/tx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/addr_decoder.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_init_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_mem.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/dyn_arb.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_demux_wr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_demux_wr.vhd
echo "Processing file set fifo_rtl of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
echo "Processing file set hdlSources of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibiv3_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r1.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r4.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/lfsr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/receiver.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/rx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/transmitter.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/tx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/addr_decoder.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_init_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_mem.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/dyn_arb.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_demux_wr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_demux_wr.vhd
echo "Processing file set fifo_rtl of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
 
echo "Processing component TUT:ip.hwp.communication:hibi_orbus:3.0"
echo "Processing file set hdlSources of component TUT:ip.hwp.communication:hibi_orbus:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_orbus_small.vhd
 
echo "Processing component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0"
echo "Processing file set hdlSources of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibiv3_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r1.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r4.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/lfsr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/receiver.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/rx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/transmitter.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/tx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/addr_decoder.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_init_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_mem.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/dyn_arb.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_demux_wr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_demux_wr.vhd
echo "Processing file set fifo_rtl of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
echo "Processing file set hdlSources of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibiv3_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r1.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_wrapper_r4.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/lfsr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/receiver.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/rx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/transmitter.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/tx_control.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/addr_decoder.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_init_pkg.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/cfg_mem.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/dyn_arb.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/fifo_demux_wr.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_mux_rd.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/double_fifo_demux_wr.vhd
echo "Processing file set fifo_rtl of component TUT:ip.hwp.communication:hibi_wrapper_r4:3.0."
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
vcom -work hibi -check_synthesis -quiet D:/user/matilail/funbase/repos/daci_repo/ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
 
echo "Processing component TUT:ip.hwp.communication:hibi_segment:3.0"
echo "Processing file set structural_vhdlSource of component TUT:ip.hwp.communication:hibi_segment:3.0."
vcom -quiet -check_synthesis -work work D:/user/matilail/funbase/repos/daci_repo/ip.hwp.communication/hibi/3.0/vhd/hibi_segment.vhd
 
echo "Processing component TUT:soc:basic_tester_hibi_example:1.0"
echo "Processing file set structural_vhdlSource of component TUT:soc:basic_tester_hibi_example:1.0."
vcom -quiet -check_synthesis -work work D:/user/ege/Svn/daci_ip/trunk/soc/basic_tester_example/1.0/vhd/basic_tester_hibi_example.vhd
vcom -quiet -check_synthesis -work work D:/user/matilail/funbase/repos/daci_repo/soc/basic_tester_example/1.0/vhd/basic_tester_hibi_example.vhd
 
echo " Creating a new Makefile"
 
/1.0/sim/test_rx.txt
12,9 → 12,9
# Moreover, comm (last param) can simply be omitted
# and then no checking is done.
 
0025 03000000 00000100 02
0050 03000001 00000101 02
0012 03000002 00000102 03
0025 00000003 00000100 02
0050 00000003 00000101 02
0012 00000003 00000102 03
# There can be empty lines as shown below
 
# Address 0...0 means that it must not change from previous transfer
/1.0/sim/test_tx.txt
4,9 → 4,9
# delay_in_cycles addr data cmd(optional)
# The values are in hexadecimal format
 
000A 03000000 00000100 02
0005 03000001 00000101 02
0008 03000002 00000102 03
000A 00000003 00000100 02
0005 00000003 00000101 02
0008 00000003 00000102 03
 
# There can be empty lines as shown below
 

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