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https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
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Rev 15 → Rev 16
/TUT/ip.hwp.communication/n2h2/Sopc_64b/cb_generator.pl
0,0 → 1,1159
# | file: cb_generator.pl |
# | |
# | This SOPC Builder Generator program is provided by |
# | the Component Builder application. It is copied |
# | straight across and is data-driven from its command |
# | line arguments and the PTF files referenced. |
# | |
# | Its purpose is to construct an HDL "wrapper" for |
# | a particular instance of a particular SOPC Builder |
# | peripheral. This wrapper resolves the instance |
# | name and any HDL parameterization. |
# | |
# +------------------------------------------- |
|
|
|
# +------------------------------------------- |
# | |
|
use strict; |
use format_conversion_utils; |
use ptf_parse; |
use wiz_utils; |
use europa_all; |
use run_system_command_utils; |
|
# | |
# +------------------------------------------- |
|
|
|
# +------------------------------------------- |
# | |
# | first pass: include all of generator_libarary.pm RIGHT HERE. |
# | dvb04.08.02 |
# | then prune down to actual functionality. |
# | |
# | TODO: Rewrite this whole file into something readable |
# | this is much more confusing than I'm comfortable with. dvb04. |
# | (though it does seem to work.) |
# | |
|
my $DEBUG_DEFAULT_GEN = 1; |
|
#This is the global hash of arguments passed in by the generator program |
|
my $generator_hr = { |
wrapper_args => { |
make_wrapper => 0, |
top_module_name => "", |
simulate_hdl => 1, |
ports => "", |
}, |
class_ptf_hr => "", |
module_ptf_hr => "", |
system_ptf_hr => "", |
language => "", |
external_args => "", |
external_args_hr => "", |
project_path_widget => "__PROJECT_DIRECTORY__", |
generator_mode => "silent", |
}; |
|
|
sub generator_print_verbose |
{ |
my ($info) = (@_); |
|
if($generator_hr->{generator_mode} eq "verbose"){ |
print("cb_generator.pl: ".$info); |
} |
} |
|
sub generator_enable_mode |
{ |
my ($mode) = (@_); |
$generator_hr->{generator_mode} = $mode; |
} |
|
sub generator_get_system_ptf_handle |
{ |
return $generator_hr->{system_ptf_hr}; |
} |
|
sub generator_get_language |
{ |
return $generator_hr->{language}; |
} |
|
sub generator_get_class_ptf_handle |
{ |
return $generator_hr->{class_ptf_hr}; |
} |
|
sub default_ribbit |
{ |
my ($arg) = (@_); |
&ribbit("\n\n--Error: default_gen_lib: $arg\n"); |
} |
|
|
sub _copy_files |
{ |
my ($dest_dir, $source_dir, @files) = (@_); |
my $function_name; |
|
#validate args |
&default_ribbit("No target dir for function copy_files!") |
unless ($dest_dir ne ""); |
|
&default_ribbit("No source dir for function copy_files!") |
unless ($source_dir ne ""); |
|
&default_ribbit("No files for function copy_files!") |
unless (@files != 0); |
|
|
#check for valid directories |
opendir (SDIR, $source_dir) or |
&default_ribbit("can't open $source_dir !"); |
|
opendir (DDIR, $dest_dir) or |
&default_ribbit("can't open $dest_dir !"); |
|
|
foreach my $source_file(@files){ |
# | |
# | Separate out the source subdir and the source filename |
# | |
my $source_subdir = ""; |
my $source_filename = $source_file; |
|
if($source_filename =~ /^(.*)\/(.*)$/) # break on last slash |
{ |
$source_subdir = "/$1"; # embed its leading slash, for concatty |
$source_filename = $2; |
} |
|
my $source_fullpath = "$source_dir$source_subdir/$source_filename"; |
my $dest_fullpath = "$dest_dir/$source_filename"; |
|
&Perlcopy($source_fullpath, $dest_fullpath); |
&generator_print_verbose("Copying file: \"$source_fullpath\"" |
. " to \"$dest_fullpath\".\n"); |
} |
|
closedir (SDIR); |
closedir (DDIR); |
} |
|
|
sub get_module_wrapper_arg_hash_from_system_ptf_file |
{ |
my $module_ptf_hr = $generator_hr->{module_ptf_hr}; |
|
my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING"); |
my @port_list; |
foreach my $section(@list_of_sections){ |
my $number = get_child_count($module_ptf_hr, $section); |
|
for(my $initial=0; $initial < $number; $initial++){ |
|
my $interface_section = get_child($module_ptf_hr, $initial, $section); |
my $interface_section_name = get_data($interface_section); |
|
my $port_wiring_section; |
if($section ne "PORT_WIRING"){ |
$port_wiring_section = |
get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING"); |
}else{ |
$port_wiring_section = |
get_child_by_path($module_ptf_hr, $section); |
} |
my $num_ports = get_child_count($port_wiring_section, "PORT"); |
foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){ |
my $port = get_child($port_wiring_section, $port_count, "PORT"); |
|
my %port_info_struct; |
$port_info_struct{name} = get_data($port); |
$port_info_struct{direction} = get_data_by_path($port, "direction"); |
$port_info_struct{width} = get_data_by_path($port, "width"); |
$port_info_struct{vhdl_record_name} = get_data_by_path($port, "vhdl_record_name"); |
$port_info_struct{vhdl_record_type} = get_data_by_path($port, "vhdl_record_type"); |
|
push(@port_list, \%port_info_struct); |
|
} |
} |
} |
$generator_hr->{wrapper_args}{ports} = \@port_list; |
} |
|
|
sub generator_make_module_wrapper |
{ |
my ($simulate_hdl, $top_module_name, $module_language) = (@_); |
|
&default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n") |
if($simulate_hdl eq ''); |
|
&default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n") |
unless($top_module_name); |
|
$generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl; |
$generator_hr->{wrapper_args}{top_module_name} = $top_module_name; |
$generator_hr->{wrapper_args}{make_wrapper} = 1; |
$generator_hr->{wrapper_args}{module_language} = $module_language; |
|
} |
|
|
|
|
# | |
# | recognize varous number forms, |
# | return 'h0123abcd-ish. |
# | |
sub turn_anything_into_appropriate_string($$$$) |
{ |
my ($value,$type,$editable,$module_language) = (@_); |
|
return $value if($value =~ /^\"/); # quoted string: unscathed |
return $value if($type eq "string"); # string: anything is ok |
|
return $value if(!$editable); # and you know, if you can't change it, keep it! |
|
|
# | |
# | first, convert to a number |
# | |
my $base = 10; |
my $n = $value; |
my $width = 32; |
my $number = 0; |
|
$value = lc($value); # lower case |
|
if($value =~ /^([0-9]*)\'([hbo])(.*)$/) |
{ |
# | tick notation: AOK for verilog |
if($module_language eq "verilog") |
{ |
$number = $value; |
} |
# | |
# | note: at this point, we could notice if the |
# | result should be vhdl binary, and convert |
# | to that, avoiding the precision-losing |
# | integer intermediary |
# | |
# | (alternatively, we could use a binary string |
# | always as the intermediate form, rather than |
# | a precision-losing int.) |
# | |
else |
{ |
$width = $1; |
my $baseletter = $2; |
my $digits = $3; |
|
if($baseletter eq "h") |
{ |
$base = 16; |
} |
elsif($baseletter eq "b") |
{ |
$base = 2; |
} |
elsif($baseletter eq "o") # must be |
{ |
$base = 8; |
} |
|
$digits =~ s/[ _-]//g; # crush out dividing value |
|
while(length($digits) > 0) |
{ |
my $digit = substr($digits,0,1); |
$digits = substr($digits,1); |
my $digitvalue = hex($digit); # how handy |
$number = $number * $base + $digitvalue; |
} |
} |
} |
elsif($value =~ /^0x(.*)$/) |
{ |
$number = hex($1); |
} |
else # try for decimal |
{ |
$number = int(1 * $value); |
} |
|
# | |
# | ok, we have a number. If our target type |
# | is "std_logic_vector(this downto that)" |
# | for tricky VHDL, we |
# | must quote a binary string out of it. |
# | |
|
if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/)) |
{ |
my ($high_bit,$low_bit) = ($1,$2); |
my $binary = ""; |
for(my $bit = $low_bit; $bit <= $high_bit; $bit++) |
{ |
$binary = ($number % 2) . $binary; |
$number = int($number >> 1); |
} |
|
$number = '"' . $binary . '"'; |
} |
|
return $number; |
} |
|
# |
# return @array of vhdl libraries, if any, from the class.ptf |
sub get_libraries() |
{ |
my $class_ptf = generator_get_class_ptf_handle(); |
my @libraries; |
my $libraries_ptf = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/LIBRARIES"); |
|
if($libraries_ptf) |
{ |
my $library_count = get_child_count($libraries_ptf,"library"); |
for(my $i = 0; $i < $library_count; $i++) |
{ |
my $library_ptf = get_child($libraries_ptf,$i,"library"); |
my $library_name = get_data($library_ptf); |
push(@libraries,$library_name); |
} |
} |
|
return @libraries; |
} |
|
|
|
sub _generator_make_module_wrapper |
{ |
|
my $wrapper_args = $generator_hr->{wrapper_args}; |
my $no_black_box = $wrapper_args->{simulate_hdl}; |
my $top_module_name = $wrapper_args->{top_module_name}; |
my $language = $generator_hr->{language}; |
my @external_args = @{$generator_hr->{external_args}}; |
my $module_ptf_hr = $generator_hr->{module_ptf_hr}; |
|
### Build Module |
my $project = e_project->new(@external_args); |
my $top = $project->top(); |
|
# add the ports to the system module |
my @ports; |
|
foreach my $port_hash(@{$wrapper_args->{ports}}){ |
my $porto = e_port->new({ |
name => $port_hash->{name}, |
width => $port_hash->{width}, |
direction => $port_hash->{direction}, |
vhdl_record_name => $port_hash->{vhdl_record_name}, |
vhdl_record_type => $port_hash->{vhdl_record_type} |
}); |
push(@ports, $porto); |
} |
$top->add_contents(@ports); |
|
|
|
|
|
# +---------------------------------------- |
# | Get parameters from class.ptf |
# | create @array of parameters, eacho |
# | one like name=>, default=>, type=>, |
# | |
# | These are the definitions of parameters for |
# | ANY instance of this module; we need to |
# | have them in the "wrapee" module so that |
# | when the system bus is knitted together |
# | the parameter types can be properly used. |
# | |
# | (as it turns out, verilog doesnt need |
# | them, but vhld does) |
# | |
# | dvb2004 |
|
|
my @e_hdl_parameters; # list of e_parameters |
|
my $class_ptf = generator_get_class_ptf_handle(); |
my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS"); |
|
my @libraries = get_libraries(); |
|
my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER"); |
|
my $module_language = $generator_hr->{wrapper_args}{module_language}; |
|
for(my $i = 0; $i < $hdl_parameter_count; $i++) |
{ |
my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER"); |
my $parameter_editable = get_data_by_path($a_parameter,"editable"); |
if($parameter_editable) |
{ |
my $boring_name = get_data($a_parameter); # legal guinevere-ized |
my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name |
my $default = get_data_by_path($a_parameter,"default_value"); |
my $type = get_data_by_path($a_parameter,"type"); |
|
$default = turn_anything_into_appropriate_string($default,$type,1,$module_language); |
|
my $a_parameter = e_parameter->new |
({ |
name => $name, |
default => $default, |
type => $type |
}); |
|
push (@e_hdl_parameters,$a_parameter); |
} |
} |
|
|
|
# | and @e_hdl_parameters is used below in the wrapee module |
# +-------------------------------------------- |
|
# +-------------------------------------------- |
# | Now, we build a "hdl_parameter_map", which is just |
# | your basic hash table with keys (parameters) |
# | and values (parameter values). |
# | |
# | these are the particular values for this instance. |
# | |
|
my %hdl_parameter_map; |
my $module_ptf = $generator_hr->{module_ptf_hr}; |
my $hdl_parameters_ptf = |
get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters"); |
|
my $child_count = get_child_count($hdl_parameters_ptf); |
|
for(my $i = 0; $i < $child_count; $i++) |
{ |
my $a_parameter = get_child($hdl_parameters_ptf,$i); |
|
my $boring_name = get_name($a_parameter); |
my $value = get_data($a_parameter); |
|
# refer back to the original HDL name... |
my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name"); |
my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name"); |
my $parameter_type = get_data_by_path($parameter_definition_ptf,"type"); |
my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable"); |
|
$value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language); |
|
# | |
# | our internal _dummy assignment shows up here |
# | without a corresponding hdl entry. we |
# | ignore it. |
# | |
|
if(($parameter_name ne "") and $parameter_editable) |
{ |
$hdl_parameter_map{$parameter_name} = $value; |
} |
} |
|
my $wrapee_module; |
$wrapee_module = e_module->new({ |
name => $top_module_name, |
contents => [@ports,@e_hdl_parameters], |
do_black_box => 0, |
do_ptf => 0, |
_hdl_generated => 1, |
_explicitly_empty_module => 1, |
}); |
|
# VHDL Libraries, from PTF file... |
$wrapee_module->add_vhdl_libraries(@libraries); |
$top->add_vhdl_libraries(@libraries); |
|
|
$top->add_contents ( |
e_instance->new({ |
module => $wrapee_module, |
parameter_map => \%hdl_parameter_map |
}), |
); |
|
$project->top()->do_ptf(0); |
$project->do_write_ptf(0); |
|
|
my $module_file = $project->_target_module_name().".v"; |
$module_file = $project->_target_module_name().".vhd" |
if($language eq "vhdl"); |
|
$module_file = $generator_hr->{project_path_widget}."/".$module_file; |
&generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file)); |
$project->output(); |
|
|
# if you don't want a simulation model, you don't get a simulation model |
if($no_black_box eq "0") |
{ |
my $black_project = e_project->new(@external_args); |
$black_project->_target_module_name($top_module_name); |
my $black_top = $black_project->top(); |
|
|
|
$black_top->add_contents(@ports); |
my $black_top_instance; |
$black_top_instance = e_module->new({ |
name => $wrapper_args->{top_module_name}."_bb", |
contents => [@ports], |
do_black_box => 1, |
do_ptf => 0, |
_hdl_generated => 0, |
_explicitly_empty_module => 1, |
}); |
|
$black_top->add_contents ( |
e_instance->new({ |
module => $black_top_instance, |
}), |
); |
|
|
|
|
$black_project->top()->do_ptf(0); |
$black_project->do_write_ptf(0); |
|
my $black_module_file = $black_project->_target_module_name().".v"; |
$black_module_file = $black_project->_target_module_name().".vhd" |
if($language eq "vhdl"); |
|
|
$black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file; |
&generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file)); |
|
# &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file); |
|
|
$black_project->output(); |
} |
|
} |
|
#### |
# Args: $file_type : "synthesis", "synthesis_only", "simulation" |
# @file_list : an array of files. This list of files is assumed to be relative to the |
# component's directory |
|
|
my $decoder_ring_hr = { |
quartus_only => { |
copy => 1, |
copy_to => "project", |
ptf_set => 0, |
}, |
simulation_only => { |
copy => 1, |
copy_to => "simulation", |
ptf_set => 1, |
ptf_section => "Simulation_HDL_Files", |
}, |
simulation_and_quartus => { |
copy => 1, |
copy_to => "project", |
ptf_set => 1, |
ptf_section => "Synthesis_HDL_Files", |
}, |
precompiled_simulation_files => { |
copy => 0, |
ptf_set => 1, |
ptf_section => "Precompiled_Simulation_Library_Files", |
}, |
}; |
|
|
|
|
sub generator_copy_files_and_set_system_ptf |
{ |
my ($hdl_section, @file_list) = (@_); |
|
my $ptf_path_prefix = ""; |
my $external_args_hr = $generator_hr->{external_args_hr}; |
my @new_file_array; |
|
#validate first |
my $decoder_hash = $decoder_ring_hr->{$hdl_section}; |
&default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n") |
unless($decoder_ring_hr->{$hdl_section} ne ""); |
|
&generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n"); |
|
#copy second |
my @new_file_array; |
|
# If we need to copy over some files, then we need to make sure we are |
# keeping track of what files we copy over. |
# Otherwise, we just need to keep track of the files that the user has asked to copy over |
# and use these instead. |
if($decoder_hash->{copy}){ |
my $copy_to_location; |
my $copy_from_location; |
|
if($decoder_hash->{copy_to} eq "project"){ |
$copy_to_location = $external_args_hr->{system_directory}; |
}elsif($decoder_hash->{copy_to} eq "simulation"){ |
$copy_to_location = $external_args_hr->{system_sim_dir}; |
}else{ |
&default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n"); |
} |
|
$copy_from_location = $external_args_hr->{class_directory}; |
@new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list); |
}else{ |
@new_file_array = @file_list; |
} |
|
#scribble on PTF hash last |
if($decoder_hash->{ptf_set}){ |
|
if($decoder_hash->{copy_to} eq "project"){ |
foreach my $file(@new_file_array){ |
$file =~ s/^.*\/(.*?)$/$1/; |
$file = $generator_hr->{project_path_widget}."/".$file; |
} |
} |
&generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n"); |
if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){ |
@new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array; |
} |
&generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array); |
} |
} |
|
|
|
#### |
# Name: generator_set_files_in_system_ptf |
# Args: $hdl_section |
# @list_of_files |
# Returns: 1 or 0 |
# Purpose: This is an internal function used to set files in the module's section in the system PTF file |
# |
sub generator_set_files_in_system_ptf |
{ |
my ($hdl_section, @list_of_files) = (@_); |
|
my $file_list = join(",", @list_of_files); |
my $previous_data; |
|
&generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n"); |
my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section); |
if($previous_data){ |
$file_list = $previous_data . ", $file_list"; # spr 132177 |
# swapping order, dvb 2003 |
} |
&set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list); |
} |
|
#### |
# Name: generator_copy_files |
# Args: $target_directory |
# $source_directory |
# @list_of_files |
# Returns: The list of files which has been copied (suitable for framing!) |
# Purpose: This is an internal function used to copy files around in the generator program. |
# |
sub generator_copy_files |
{ |
my ($target_directory, $source_directory, @list_of_files) = (@_); |
|
my @new_file_array; |
|
foreach my $file_name(@list_of_files){ |
$file_name =~ s|\\|\/|g; |
if($file_name =~ /\*\.*/){ |
$file_name =~ s/\*/$1/; |
my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name); |
push(@new_file_array, @found_list); |
}else{ |
&generator_print_verbose("Copying: ".$file_name."\n"); |
push(@new_file_array, $file_name); |
} |
} |
|
&_copy_files($target_directory, $source_directory, @new_file_array); |
return @new_file_array; |
} |
|
|
|
sub _find_all_dir_files_with_ext |
{ |
my ($dir, |
$ext) = (@_); |
|
opendir (DIR, $dir) or |
&default_ribbit("can't open $dir !"); |
|
my @all_files = readdir(DIR); |
my @new_file_list; |
|
|
foreach my $file (@all_files){ |
if($file =~ /^.*($ext)$/){ |
push(@new_file_list, $file); |
} |
} |
|
return @new_file_list; |
} |
|
#### |
# Name: generator_begin |
# Args: Array of generator program launcher args |
# Returns: A hash reference to the module's section in the system PTF file |
# Purpose: This is the first subroutine a user should call before running the rest of their |
# generator program. |
# |
|
sub generator_begin |
{ |
my @external_args = (@_); |
|
my ($external_args_hr, |
$temp_user_defined, |
$temp_db_Module, |
$temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args); |
|
&generator_print_verbose("generator_begin: initializing\n"); |
|
$generator_hr->{external_args_hr} = $external_args_hr; |
$generator_hr->{external_args} = \@external_args; |
|
# open up class.ptf and |
$generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf"); |
|
# get the system.ptf |
$generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"); |
$generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}"); |
my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class"); |
|
# find the default generator section |
$generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language"); |
|
# get some wrapper settings |
&get_module_wrapper_arg_hash_from_system_ptf_file(); |
|
# clear system ptf's HDL section |
&delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO"); |
|
return $generator_hr->{module_ptf_hr}; |
} |
|
#### |
# Name: generator_end |
# Args: none |
# Returns: nothing |
# Purpose: This is the last subroutine a user should call from their generator program. |
# Not calling this subroutine will make you very sad... =< |
# |
|
sub generator_end |
{ |
# o.k., time to make the wrapper and output it. |
if($generator_hr->{wrapper_args}{make_wrapper}){ |
&_generator_make_module_wrapper(); |
} |
|
|
my $external_args_hr = $generator_hr->{external_args_hr}; |
my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"; |
&generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n"); |
|
default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n") |
unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf")); |
} |
|
sub generator_end_read_module_wrapper_string |
{ |
my $language = &generator_get_language(); |
my $ls; |
|
if($language =~ /vhdl/){ |
$ls = ".vhd"; |
}elsif($language =~ /verilog/){ |
$ls = ".v"; |
}else{ |
&ribbit("generator_end_read_module_wrapper_string invoked with unkown language"); |
} |
my $system_dir = $generator_hr->{external_args_hr}->{system_directory}; |
my $module_name = $generator_hr->{external_args_hr}->{target_module_name}; |
|
my $file = $system_dir."/".$module_name.$ls; |
&generator_print_verbose("generator library reading file into string: $file\n"); |
|
open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n"; |
my $return_string; |
while (<FILE>) |
{ |
$return_string .= $_; |
} |
close (FILE); |
return($return_string); |
} |
|
sub generator_end_write_module_wrapper_string |
{ |
my $string = shift or ribbit "no string specified\n"; |
|
my $language = &generator_get_language(); |
my $ls; |
|
print $language; |
|
if($language =~ /vhdl/){ |
$ls = ".vhd"; |
}elsif($language =~ /verilog/){ |
$ls = ".v"; |
}else{ |
&ribbit("generator_end_read_module_wrapper_string invoked with unkown language"); |
} |
my $system_dir = $generator_hr->{external_args_hr}->{system_directory}; |
my $module_name = $generator_hr->{external_args_hr}->{target_module_name}; |
|
my $file = $system_dir."/".$module_name.$ls; |
&generator_print_verbose("generator library writing string into file: $file\n"); |
|
open (FILE,">$file") or ribbit "cannot open file ($file) ($!)\n"; |
print FILE $string; |
close (FILE); |
} |
# end of generator_library.pm |
|
|
|
|
|
# |
# |
# |
# |
# --------------------------------------------------------------------- |
|
# +---------------------------------------------------- |
# | emit_system_h |
# | |
# | if "is_cpu", attempt to emit a system.h |
# | memory map. |
# | |
|
sub emit_system_h($$$) |
{ |
my ($sopc_directory,$master,$system_ptf) = (@_); |
|
# | |
# | Build a system.h file for masters. |
# | |
|
|
# as of quartus 5.0, we prefer gtf-generate in sopc_builder directly |
|
my $gtf_generate = "$sopc_directory/bin/gtf-generate"; |
my $gtf_filename = "$sopc_directory/bin/gtf/system.h.gtf"; |
|
if(! -f $gtf_generate) |
{ |
# but if sopc_builder is missing it for whatever reason, |
# try the one in sopc_kit_nios2 |
|
my $sopc_kit_nios2 = $ENV{SOPC_KIT_NIOS2}; |
if($sopc_kit_nios2 ne "") |
{ |
$gtf_generate = "$sopc_kit_nios2/bin/gtf-generate"; |
$gtf_filename = "$sopc_kit_nios2/bin/gtf/system.h.gtf"; |
} |
} |
|
# | |
# | xml template |
# | |
|
my $stf_template = <<EOP; |
<?xml version="1.0" encoding="UTF-8"?> |
<stf> |
<!-- This file generated on --date-- by --whoami-- --> |
<project name="--project_name--" |
ptf="--system_ptf--" |
dir="--output_directory--" |
/> |
<cpu name="--master--" /> |
</stf> |
|
EOP |
|
# | |
# | THINK |
# | |
|
my $output_directory = "./${master}_map"; |
my $project_name = "ignored"; |
my $stf_filename = "./${master}_project.stf"; |
|
# | |
# | build up template variables |
# | |
|
my %template_vars; |
$template_vars{date} = fcu_date_time(); |
$template_vars{whoami} = $0; |
$template_vars{project_name} = $project_name; |
$template_vars{system_ptf} = $system_ptf; |
$template_vars{output_directory} = $output_directory; |
$template_vars{master} = $master; |
|
# | |
# | poke in the values to the template |
# | |
|
foreach my $key (sort(keys(%template_vars))) |
{ |
$stf_template =~ s/--$key--/$template_vars{$key}/gs; |
} |
|
## debug print $stf_template; |
|
# | |
# | write out the stf file, so we can soon use it |
# | |
|
fcu_write_file($stf_filename,$stf_template); |
|
# | |
# | and use it |
# | |
|
if(-e $gtf_generate && -e $gtf_filename) |
{ |
|
my $generate_cmd = $gtf_generate; |
|
$generate_cmd .= " --output-directory=$output_directory"; |
$generate_cmd .= " --gtf=$gtf_filename"; |
$generate_cmd .= " --stf=$stf_filename"; |
|
r_system($sopc_directory,$generate_cmd); |
|
# | |
# | done with it |
# | |
|
r_system($sopc_directory,"rm $stf_filename"); |
|
fcu_print_command("Generated memory map \"$output_directory/system.h\""); |
} |
else |
{ |
fcu_print_command("Warning: did NOT emit system.h for $master"); |
} |
|
|
|
|
} |
|
|
sub r_system($$) |
{ |
my ($sopc_directory,$cmd) = (@_); |
fcu_print_command($cmd); |
return Run_Command_In_Unix_Like_Shell($sopc_directory,$cmd); |
} |
|
|
|
|
|
|
|
# +------------------------------------------ |
# | synthesis and simulation files are are |
# | listed in CLASS/CB_GENERATOR/HDL_FILES. |
# | |
|
sub get_synthesis_files($) |
{ |
my ($class_ptf) = (@_); |
my $synthesis_files = ""; |
my $simulation_files = ""; |
|
my $hdl_files = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/HDL_FILES"); |
my $child_count = get_child_count($hdl_files); |
for(my $i = 0; $i < $child_count; $i++) |
{ |
my $hdl_file = get_child($hdl_files,$i); |
if(get_name($hdl_file) eq "FILE") |
{ |
my $filename = get_data_by_path($hdl_file,"filepath"); |
my $use_in_synthesis = get_data_by_path($hdl_file,"use_in_synthesis"); |
my $use_in_simulation = get_data_by_path($hdl_file,"use_in_simulation"); |
|
if($use_in_synthesis) |
{ |
$synthesis_files .= ", " if $synthesis_files; |
$synthesis_files .= $filename; |
} |
|
if($use_in_simulation) |
{ |
$simulation_files .= ", " if $simulation_files; |
$simulation_files .= $filename; |
} |
} |
} |
|
return $synthesis_files; |
} |
|
|
|
|
|
|
|
|
sub main |
{ |
|
push(@ARGV,"--verbose=1") if 0; |
my %args = fcu_parse_args(@ARGV); |
|
if(0) |
{ |
foreach my $key (sort(keys(%args))) |
{ |
print("--$key = $args{$key} \n"); |
} |
} |
|
# | |
# | get the arguments we care about |
# | |
|
my $class_dir = fcu_get_switch(\%args,"module_lib_dir"); |
|
|
my $target_module_name = fcu_get_switch(\%args,"target_module_name"); |
my $system_name = fcu_get_switch(\%args,"system_name"); |
my $sopc_directory = fcu_get_switch(\%args,"sopc_directory"); |
|
# | |
# | preflight the arguments a little |
# | |
|
my $error_count = 0; |
|
my $class_ptf_path = "$class_dir/class.ptf"; |
if(!-f $class_ptf_path) |
{ |
print "error: no class.ptf at \"$class_dir\"\n"; |
$error_count++; |
} |
|
die "$error_count errors" if($error_count > 0); |
|
# +------------------------------------------- |
# | ok, let us get to work |
# | |
|
|
my $class_ptf = new_ptf_from_file($class_ptf_path); |
|
# | |
# | emit system.h for this module |
# | TODO iff Is_CPU i guess. |
# | |
|
my $do_emit_system_h = get_data_by_path($class_ptf, |
"CLASS/CB_GENERATOR/emit_system_h"); |
if($do_emit_system_h) |
{ |
emit_system_h($sopc_directory, |
$target_module_name, |
"./$system_name.ptf"); |
} |
|
my $top_module_name = get_data_by_path($class_ptf, |
"CLASS/CB_GENERATOR/top_module_name"); |
my $file_name = ""; |
|
# | stored as file_name.v:module_name, so we break it open |
if($top_module_name =~ /^(.*):(.*)$/) |
{ |
$file_name = $1; |
my $module_name = $2; |
$top_module_name = $module_name; |
} |
|
# | language of this particular module... |
|
my $module_language = "verilog"; |
if($file_name =~ /^.*\.vhd$/) |
{ |
$module_language = "vhdl"; |
} |
|
# | |
# | consult the CB_GENERATOR/HDL_FILES section regarding |
# | where our HDL files for synthesis are. |
# | |
|
|
my $synthesis_files = get_synthesis_files($class_ptf); |
|
|
my $instantiate_in_system_module = get_data_by_path($class_ptf, |
"CLASS/MODULE_DEFAULTS/SYSTEM_BUILDER_INFO/Instantiate_In_System_Module"); |
|
|
|
if($instantiate_in_system_module) |
{ |
generator_enable_mode ("terse"); |
|
|
generator_begin (@ARGV); |
|
|
generator_make_module_wrapper(1,$top_module_name,$module_language); |
|
generator_copy_files_and_set_system_ptf |
( |
"simulation_and_quartus", |
split(/ *, */,$synthesis_files) |
# "$synthesis_files" |
); |
|
generator_end (); |
} |
|
exit (0); |
} |
|
$| = 1; # always polite to flush. |
main() |
|
# end of file |
/TUT/ip.hwp.communication/n2h2/Sopc_64b/class.ptf
0,0 → 1,2493
# |
# This class.ptf file built by Component Editor |
# 2007.06.26.15:46:43 |
# |
# DO NOT MODIFY THIS FILE |
# If you hand-modify this file you will likely |
# interfere with Component Editor's ability to |
# read and edit it. And then Component Editor |
# will overwrite your changes anyway. So, for |
# the very best results, just relax and |
# DO NOT MODIFY THIS FILE |
# |
CLASS n2h2_ver02 |
{ |
CB_GENERATOR |
{ |
HDL_FILES |
{ |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = "vhdl"; |
filepath = "hdl/n2h2_chan.vhd"; |
} |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = "vhdl"; |
filepath = "hdl/n2h2_rx_chan.vhd"; |
} |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = "vhdl"; |
filepath = "hdl/n2h2_rx_channels.vhd"; |
} |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = "vhdl"; |
filepath = "hdl/n2h2_tx_vl.vhd"; |
} |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = "vhdl"; |
filepath = "hdl/one_hot_mux.vhd"; |
} |
} |
top_module_name = "n2h2_chan.vhd:n2h2"; |
emit_system_h = "1"; |
LIBRARIES |
{ |
library = "ieee.std_logic_1164.all"; |
library = "std.standard.all"; |
} |
} |
MODULE_DEFAULTS global_signals |
{ |
class = "n2h2_ver02"; |
class_version = "0.2"; |
SYSTEM_BUILDER_INFO |
{ |
Instantiate_In_System_Module = "1"; |
Has_Clock = "0"; |
Top_Level_Ports_Are_Enumerated = "1"; |
} |
COMPONENT_BUILDER |
{ |
GLS_SETTINGS |
{ |
} |
} |
PORT_WIRING |
{ |
PORT rst_n |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "reset_n"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_empty_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_comm_in |
{ |
width = "3"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_re_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_full_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_comm_out |
{ |
width = "3"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_we_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
WIZARD_SCRIPT_ARGUMENTS |
{ |
hdl_parameters |
{ |
data_width_g = "32"; |
addr_width_g = "32"; |
amount_width_g = "16"; |
n_chans_g = "8"; |
n_chans_bits_g = "3"; |
hibi_addr_cmp_lo_g = "20"; |
hibi_addr_cmp_hi_g = "27"; |
} |
} |
SIMULATION |
{ |
DISPLAY |
{ |
} |
} |
SLAVE cfg |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
Address_Group = "1"; |
Has_Clock = "1"; |
Address_Width = "-1"; |
Address_Alignment = "dynamic"; |
Data_Width = "8"; |
Has_Base_Address = "1"; |
Has_IRQ = "1"; |
Setup_Time = "0cycles"; |
Hold_Time = "0cycles"; |
Read_Wait_States = "1cycles"; |
Write_Wait_States = "1cycles"; |
Read_Latency = "0"; |
Maximum_Pending_Read_Transactions = "0"; |
Active_CS_Through_Read_Latency = "0"; |
Is_Printable_Device = "0"; |
Is_Memory_Device = "1"; |
Is_Readable = "1"; |
Is_Writable = "1"; |
Minimum_Uninterrupted_Run_Length = "1"; |
} |
COMPONENT_BUILDER |
{ |
AVS_SETTINGS |
{ |
Setup_Value = "0"; |
Read_Wait_Value = "1"; |
Write_Wait_Value = "1"; |
Hold_Value = "0"; |
Timing_Units = "cycles"; |
Read_Latency_Value = "0"; |
Minimum_Arbitration_Shares = "1"; |
Active_CS_Through_Read_Latency = "0"; |
Max_Pending_Read_Transactions_Value = "1"; |
Address_Alignment = "dynamic"; |
Is_Printable_Device = "0"; |
Interleave_Bursts = "0"; |
interface_name = "Avalon Slave"; |
external_wait = "0"; |
Is_Memory_Device = "1"; |
} |
} |
PORT_WIRING |
{ |
PORT clk_cfg |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT rx_irq_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "irq"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_addr_in |
{ |
width = "-1"; |
width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; |
direction = "input"; |
type = "address"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_we_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "write"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_re_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "read"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_cs_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "chipselect"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_writedata_in |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "writedata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_readdata_out |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "readdata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
MASTER tx |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
Address_Group = "2"; |
Has_Clock = "1"; |
Address_Width = "4"; |
Data_Width = "8"; |
Do_Stream_Reads = "1"; |
Do_Stream_Writes = "0"; |
Is_Asynchronous = "0"; |
Has_IRQ = "0"; |
Irq_Scheme = "none"; |
Interrupt_Range = ""; |
Is_Readable = "1"; |
Is_Writable = "0"; |
Is_Big_Endian = "0"; |
Register_Outgoing_Signals = "0"; |
} |
COMPONENT_BUILDER |
{ |
AVM_SETTINGS |
{ |
stream_reads = "1"; |
stream_writes = "0"; |
irq_width = "0"; |
irq_number_width = "0"; |
irq_scheme = "none"; |
Is_Asynchronous = "0"; |
Is_Big_Endian = "0"; |
} |
} |
PORT_WIRING |
{ |
PORT clk_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out_tx |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "address"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_re_out_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "read"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_readdata_in_tx |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "readdata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitrequest_in_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "waitrequest"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_readdatavalid_in_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "readdatavalid"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
MASTER rx |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
Address_Group = "3"; |
Has_Clock = "1"; |
Address_Width = "4"; |
Data_Width = "8"; |
Do_Stream_Reads = "0"; |
Do_Stream_Writes = "1"; |
Is_Asynchronous = "0"; |
Has_IRQ = "0"; |
Irq_Scheme = "none"; |
Interrupt_Range = ""; |
Is_Readable = "0"; |
Is_Writable = "1"; |
Is_Big_Endian = "0"; |
Register_Outgoing_Signals = "0"; |
} |
COMPONENT_BUILDER |
{ |
AVM_SETTINGS |
{ |
stream_reads = "0"; |
stream_writes = "1"; |
irq_width = "0"; |
irq_number_width = "0"; |
irq_scheme = "none"; |
Is_Asynchronous = "0"; |
Is_Big_Endian = "0"; |
} |
} |
PORT_WIRING |
{ |
PORT clk_rx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out_rx |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "address"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_we_out_rx |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "write"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_be_out_rx |
{ |
width = "-1"; |
width_expression = "(((data_width_g / 8) - 1)) - (0) + 1"; |
direction = "output"; |
type = "byteenable"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_writedata_out_rx |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "writedata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitrequest_in_rx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "waitrequest"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
} |
USER_INTERFACE |
{ |
USER_LABELS |
{ |
name = "n2h2_ver02"; |
technology = "n2h2"; |
} |
WIZARD_UI the_wizard_ui |
{ |
title = "n2h2_ver02 - {{ $MOD }}"; |
CONTEXT |
{ |
H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters"; |
M = ""; |
SBI_global_signals = "SYSTEM_BUILDER_INFO"; |
SBI_cfg = "SLAVE cfg/SYSTEM_BUILDER_INFO"; |
SBI_tx = "MASTER tx/SYSTEM_BUILDER_INFO"; |
SBI_rx = "MASTER rx/SYSTEM_BUILDER_INFO"; |
# The following signals have parameterized widths: |
PORT_hibi_data_in = "PORT_WIRING/PORT hibi_data_in"; |
PORT_hibi_data_out = "PORT_WIRING/PORT hibi_data_out"; |
PORT_avalon_cfg_addr_in = "SLAVE cfg/PORT_WIRING/PORT avalon_cfg_addr_in"; |
PORT_avalon_cfg_writedata_in = "SLAVE cfg/PORT_WIRING/PORT avalon_cfg_writedata_in"; |
PORT_avalon_cfg_readdata_out = "SLAVE cfg/PORT_WIRING/PORT avalon_cfg_readdata_out"; |
PORT_avalon_addr_out_tx = "MASTER tx/PORT_WIRING/PORT avalon_addr_out_tx"; |
PORT_avalon_readdata_in_tx = "MASTER tx/PORT_WIRING/PORT avalon_readdata_in_tx"; |
PORT_avalon_addr_out_rx = "MASTER rx/PORT_WIRING/PORT avalon_addr_out_rx"; |
PORT_avalon_be_out_rx = "MASTER rx/PORT_WIRING/PORT avalon_be_out_rx"; |
PORT_avalon_writedata_out_rx = "MASTER rx/PORT_WIRING/PORT avalon_writedata_out_rx"; |
} |
PAGES main |
{ |
PAGE 1 |
{ |
align = "left"; |
title = "<b>n2h2_ver02 0.2</b> Settings"; |
layout = "vertical"; |
TEXT |
{ |
title = "Built on: 2007.06.26.15:46:43"; |
} |
TEXT |
{ |
title = "Class name: n2h2_ver02"; |
} |
TEXT |
{ |
title = "Class version: 0.2"; |
} |
TEXT |
{ |
title = "Component name: n2h2_ver02"; |
} |
TEXT |
{ |
title = "Component Group: n2h2"; |
} |
GROUP parameters |
{ |
scroll = "1"; |
title = "Parameters"; |
layout = "form"; |
align = "left"; |
EDIT e1 |
{ |
id = "data_width_g"; |
editable = "1"; |
title = "data_width_g:"; |
columns = "40"; |
tooltip = "default value: 32"; |
DATA |
{ |
$H/data_width_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/data_width_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/data_width_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/data_width_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/data_width_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/data_width_g,'ugly_-?[0-9]+')))'data_width_g must be numeric constant, not '+$H/data_width_g; }}"; |
} |
EDIT e2 |
{ |
id = "addr_width_g"; |
editable = "1"; |
title = "addr_width_g:"; |
columns = "40"; |
tooltip = "default value: 32"; |
DATA |
{ |
$H/addr_width_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/addr_width_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/addr_width_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/addr_width_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/addr_width_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/addr_width_g,'ugly_-?[0-9]+')))'addr_width_g must be numeric constant, not '+$H/addr_width_g; }}"; |
} |
EDIT e3 |
{ |
id = "amount_width_g"; |
editable = "1"; |
title = "amount_width_g:"; |
columns = "40"; |
tooltip = "default value: 16"; |
DATA |
{ |
$H/amount_width_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/amount_width_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/amount_width_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/amount_width_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/amount_width_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/amount_width_g,'ugly_-?[0-9]+')))'amount_width_g must be numeric constant, not '+$H/amount_width_g; }}"; |
} |
EDIT e4 |
{ |
id = "n_chans_g"; |
editable = "1"; |
title = "n_chans_g:"; |
columns = "40"; |
tooltip = "default value: 8"; |
DATA |
{ |
$H/n_chans_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/n_chans_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/n_chans_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/n_chans_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/n_chans_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/n_chans_g,'ugly_-?[0-9]+')))'n_chans_g must be numeric constant, not '+$H/n_chans_g; }}"; |
} |
EDIT e5 |
{ |
id = "n_chans_bits_g"; |
editable = "1"; |
title = "n_chans_bits_g:"; |
columns = "40"; |
tooltip = "default value: 3"; |
DATA |
{ |
$H/n_chans_bits_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/n_chans_bits_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_-?[0-9]+')))'n_chans_bits_g must be numeric constant, not '+$H/n_chans_bits_g; }}"; |
} |
EDIT e6 |
{ |
id = "hibi_addr_cmp_lo_g"; |
editable = "1"; |
title = "hibi_addr_cmp_lo_g:"; |
columns = "40"; |
tooltip = "default value: 20"; |
DATA |
{ |
$H/hibi_addr_cmp_lo_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_-?[0-9]+')))'hibi_addr_cmp_lo_g must be numeric constant, not '+$H/hibi_addr_cmp_lo_g; }}"; |
} |
EDIT e7 |
{ |
id = "hibi_addr_cmp_hi_g"; |
editable = "1"; |
title = "hibi_addr_cmp_hi_g:"; |
columns = "40"; |
tooltip = "default value: 27"; |
DATA |
{ |
$H/hibi_addr_cmp_hi_g = "$"; |
} |
q = "'"; |
warning = "{{ if(!(regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_-?[0-9]+')))'hibi_addr_cmp_hi_g must be numeric constant, not '+$H/hibi_addr_cmp_hi_g; }}"; |
} |
} |
GROUP variable_port_widths |
{ |
# This group is for display only, to preview parameterized port widths |
title = "Parameterized Signal Widths"; |
layout = "form"; |
align = "left"; |
EDIT hibi_data_in_width |
{ |
id = "hibi_data_in_width"; |
editable = "0"; |
title = "hibi_data_in[((data_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>hibi_data_in[((data_width_g - 1)) - (0) + 1]</b><br> direction: input<br> signal type: export"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_hibi_data_in/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_hibi_data_in/width = "$"; |
} |
warning = "{{ if($PORT_hibi_data_in/width <= 0)('width of hibi_data_in must be greater than zero' ) }}"; |
} |
EDIT hibi_data_out_width |
{ |
id = "hibi_data_out_width"; |
editable = "0"; |
title = "hibi_data_out[((data_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>hibi_data_out[((data_width_g - 1)) - (0) + 1]</b><br> direction: output<br> signal type: export"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_hibi_data_out/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_hibi_data_out/width = "$"; |
} |
warning = "{{ if($PORT_hibi_data_out/width <= 0)('width of hibi_data_out must be greater than zero' ) }}"; |
} |
EDIT avalon_cfg_addr_in_width |
{ |
id = "avalon_cfg_addr_in_width"; |
editable = "0"; |
title = "avalon_cfg_addr_in[(((n_chans_bits_g + 4) - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_cfg_addr_in[(((n_chans_bits_g + 4) - 1)) - (0) + 1]</b><br> direction: input<br> signal type: address"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_cfg_addr_in/width = (int(((( ( $H/n_chans_bits_g ) + 4) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_cfg/Address_Width = $PORT_avalon_cfg_addr_in/width; }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_cfg_addr_in/width = "$"; |
} |
warning = "{{ if($PORT_avalon_cfg_addr_in/width <= 0)('width of avalon_cfg_addr_in must be greater than zero' ) }}"; |
} |
EDIT avalon_cfg_writedata_in_width |
{ |
id = "avalon_cfg_writedata_in_width"; |
editable = "0"; |
title = "avalon_cfg_writedata_in[((addr_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_cfg_writedata_in[((addr_width_g - 1)) - (0) + 1]</b><br> direction: input<br> signal type: writedata"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_cfg_writedata_in/width = (int((( ( $H/addr_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_cfg/Data_Width = 2 ^ int(log2($PORT_avalon_cfg_writedata_in/width - 1) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_cfg_writedata_in/width = "$"; |
} |
warning = "{{ if($PORT_avalon_cfg_writedata_in/width <= 0)('width of avalon_cfg_writedata_in must be greater than zero' ) }}"; |
} |
EDIT avalon_cfg_readdata_out_width |
{ |
id = "avalon_cfg_readdata_out_width"; |
editable = "0"; |
title = "avalon_cfg_readdata_out[((addr_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_cfg_readdata_out[((addr_width_g - 1)) - (0) + 1]</b><br> direction: output<br> signal type: readdata"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_cfg_readdata_out/width = (int((( ( $H/addr_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_cfg/Data_Width = 2 ^ int(log2($PORT_avalon_cfg_readdata_out/width - 1) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_cfg_readdata_out/width = "$"; |
} |
warning = "{{ if($PORT_avalon_cfg_readdata_out/width <= 0)('width of avalon_cfg_readdata_out must be greater than zero' ) }}"; |
} |
EDIT avalon_addr_out_tx_width |
{ |
id = "avalon_addr_out_tx_width"; |
editable = "0"; |
title = "avalon_addr_out_tx[((addr_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_addr_out_tx[((addr_width_g - 1)) - (0) + 1]</b><br> direction: output<br> signal type: address"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_addr_out_tx/width = (int((( ( $H/addr_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_tx/Address_Width = $PORT_avalon_addr_out_tx/width; }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_addr_out_tx/width = "$"; |
} |
warning = "{{ if($PORT_avalon_addr_out_tx/width <= 0)('width of avalon_addr_out_tx must be greater than zero' ) }}"; |
} |
EDIT avalon_readdata_in_tx_width |
{ |
id = "avalon_readdata_in_tx_width"; |
editable = "0"; |
title = "avalon_readdata_in_tx[((data_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_readdata_in_tx[((data_width_g - 1)) - (0) + 1]</b><br> direction: input<br> signal type: readdata"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_readdata_in_tx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_tx/Data_Width = 2 ^ int(log2($PORT_avalon_readdata_in_tx/width - 1) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_readdata_in_tx/width = "$"; |
} |
warning = "{{ if($PORT_avalon_readdata_in_tx/width <= 0)('width of avalon_readdata_in_tx must be greater than zero' ) }}"; |
} |
EDIT avalon_addr_out_rx_width |
{ |
id = "avalon_addr_out_rx_width"; |
editable = "0"; |
title = "avalon_addr_out_rx[((addr_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_addr_out_rx[((addr_width_g - 1)) - (0) + 1]</b><br> direction: output<br> signal type: address"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_addr_out_rx/width = (int((( ( $H/addr_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_rx/Address_Width = $PORT_avalon_addr_out_rx/width; }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_addr_out_rx/width = "$"; |
} |
warning = "{{ if($PORT_avalon_addr_out_rx/width <= 0)('width of avalon_addr_out_rx must be greater than zero' ) }}"; |
} |
EDIT avalon_be_out_rx_width |
{ |
id = "avalon_be_out_rx_width"; |
editable = "0"; |
title = "avalon_be_out_rx[(((data_width_g / 8) - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_be_out_rx[(((data_width_g / 8) - 1)) - (0) + 1]</b><br> direction: output<br> signal type: byteenable"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_be_out_rx/width = (int(((( ( $H/data_width_g ) / 8) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_be_out_rx/width = "$"; |
} |
warning = "{{ if($PORT_avalon_be_out_rx/width <= 0)('width of avalon_be_out_rx must be greater than zero' ) }}"; |
} |
EDIT avalon_writedata_out_rx_width |
{ |
id = "avalon_writedata_out_rx_width"; |
editable = "0"; |
title = "avalon_writedata_out_rx[((data_width_g - 1)) - (0) + 1]:"; |
tooltip = "<b>avalon_writedata_out_rx[((data_width_g - 1)) - (0) + 1]</b><br> direction: output<br> signal type: writedata"; |
# This expression should emulate the HDL, and assign the port width |
dummy = "{{ $PORT_avalon_writedata_out_rx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; |
dummy_dummy = "{{ $SBI_rx/Data_Width = 2 ^ int(log2($PORT_avalon_writedata_out_rx/width - 1) + 1); }}"; |
DATA |
{ |
# The EDIT field is noneditable, so this just reads the current width. |
$PORT_avalon_writedata_out_rx/width = "$"; |
} |
warning = "{{ if($PORT_avalon_writedata_out_rx/width <= 0)('width of avalon_writedata_out_rx must be greater than zero' ) }}"; |
} |
} |
} |
} |
} |
} |
SOPC_Builder_Version = "6.00"; |
COMPONENT_BUILDER |
{ |
HDL_PARAMETERS |
{ |
# generated by CBDocument.getParameterContainer |
# used only by Component Editor |
HDL_PARAMETER data_width_g |
{ |
parameter_name = "data_width_g"; |
type = "integer"; |
default_value = "32"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER addr_width_g |
{ |
parameter_name = "addr_width_g"; |
type = "integer"; |
default_value = "32"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER amount_width_g |
{ |
parameter_name = "amount_width_g"; |
type = "integer"; |
default_value = "16"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER n_chans_g |
{ |
parameter_name = "n_chans_g"; |
type = "integer"; |
default_value = "8"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER n_chans_bits_g |
{ |
parameter_name = "n_chans_bits_g"; |
type = "integer"; |
default_value = "3"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_cmp_lo_g |
{ |
parameter_name = "hibi_addr_cmp_lo_g"; |
type = "integer"; |
default_value = "20"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_cmp_hi_g |
{ |
parameter_name = "hibi_addr_cmp_hi_g"; |
type = "integer"; |
default_value = "27"; |
editable = "1"; |
tooltip = ""; |
} |
} |
SW_FILES |
{ |
} |
built_on = "2007.06.26.15:46:43"; |
CACHED_HDL_INFO |
{ |
# cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection |
# used only by Component Builder |
FILE n2h2_chan.vhd |
{ |
file_mod = "Tue Jun 26 10:23:48 EEST 2007"; |
quartus_map_start = "Tue Jun 26 10:36:09 EEST 2007"; |
quartus_map_finished = "Tue Jun 26 10:36:15 EEST 2007"; |
#found 1 valid modules |
WRAPPER n2h2 |
{ |
CLASS n2h2 |
{ |
CB_GENERATOR |
{ |
HDL_FILES |
{ |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = ""; |
filepath = "F:/SVN/Hibi/trunk/Hibi/IP/Adapters/N2H2/V2/Ver_02/n2h2_chan.vhd"; |
} |
} |
top_module_name = "n2h2"; |
emit_system_h = "0"; |
LIBRARIES |
{ |
library = "ieee.std_logic_1164.all"; |
library = "std.standard.all"; |
} |
} |
MODULE_DEFAULTS global_signals |
{ |
class = "n2h2"; |
class_version = "1.0"; |
SYSTEM_BUILDER_INFO |
{ |
Instantiate_In_System_Module = "1"; |
} |
SLAVE cfg |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT clk_cfg |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
SLAVE tx |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT clk_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
SLAVE rx |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT clk_rx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT rx_irq_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "irq"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
SLAVE avalon_slave_0 |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT rst_n |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out_rx |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_we_out_rx |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_be_out_rx |
{ |
width = "-1"; |
width_expression = "(((data_width_g / 8) - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_writedata_out_rx |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitrequest_in_rx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_addr_in |
{ |
width = "-1"; |
width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_we_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_re_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_cs_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out_tx |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_re_out_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_readdata_in_tx |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitrequest_in_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_readdatavalid_in_tx |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_empty_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_comm_in |
{ |
width = "3"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_re_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_full_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_comm_out |
{ |
width = "3"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_we_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
SLAVE avalon_cfg |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT avalon_cfg_writedata_in |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "writedata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_readdata_out |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "readdata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
} |
USER_INTERFACE |
{ |
USER_LABELS |
{ |
name = "n2h2"; |
technology = "imported components"; |
} |
} |
SOPC_Builder_Version = "0.0"; |
COMPONENT_BUILDER |
{ |
HDL_PARAMETERS |
{ |
# generated by CBDocument.getParameterContainer |
# used only by Component Editor |
HDL_PARAMETER data_width_g |
{ |
parameter_name = "data_width_g"; |
type = "integer"; |
default_value = "32"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER addr_width_g |
{ |
parameter_name = "addr_width_g"; |
type = "integer"; |
default_value = "32"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER amount_width_g |
{ |
parameter_name = "amount_width_g"; |
type = "integer"; |
default_value = "16"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER n_chans_g |
{ |
parameter_name = "n_chans_g"; |
type = "integer"; |
default_value = "8"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER n_chans_bits_g |
{ |
parameter_name = "n_chans_bits_g"; |
type = "integer"; |
default_value = "3"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_cmp_lo_g |
{ |
parameter_name = "hibi_addr_cmp_lo_g"; |
type = "integer"; |
default_value = "20"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_cmp_hi_g |
{ |
parameter_name = "hibi_addr_cmp_hi_g"; |
type = "integer"; |
default_value = "27"; |
editable = "1"; |
tooltip = ""; |
} |
} |
} |
} |
} |
} |
FILE n2h2_rx_chan.vhd |
{ |
file_mod = "Thu Jun 21 11:35:40 EEST 2007"; |
quartus_map_start = "Tue Jun 26 10:36:18 EEST 2007"; |
quartus_map_finished = "Tue Jun 26 10:36:23 EEST 2007"; |
#found 1 valid modules |
WRAPPER n2h2_rx_chan |
{ |
CLASS n2h2_rx_chan |
{ |
CB_GENERATOR |
{ |
HDL_FILES |
{ |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = ""; |
filepath = "F:/SVN/Hibi/trunk/Hibi/IP/Adapters/N2H2/V2/Ver_02/n2h2_rx_chan.vhd"; |
} |
} |
top_module_name = "n2h2_rx_chan"; |
emit_system_h = "0"; |
LIBRARIES |
{ |
library = "ieee.std_logic_1164.all"; |
library = "ieee.std_logic_arith.all"; |
library = "ieee.std_logic_unsigned.all"; |
library = "std.standard.all"; |
} |
} |
MODULE_DEFAULTS global_signals |
{ |
class = "n2h2_rx_chan"; |
class_version = "1.0"; |
SYSTEM_BUILDER_INFO |
{ |
Instantiate_In_System_Module = "1"; |
} |
SLAVE avalon_slave_0 |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT rst_n |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_in |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_addr_in |
{ |
width = "-1"; |
width_expression = "((hibi_addr_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT irq_amount_in |
{ |
width = "-1"; |
width_expression = "((amount_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_in |
{ |
width = "-1"; |
width_expression = "((hibi_addr_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_empty_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT init_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT irq_ack_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitreq_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_we_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_we_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_be_out |
{ |
width = "-1"; |
width_expression = "(((data_width_g / 8) - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT addr_match_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT irq_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "irq"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
PORT_WIRING |
{ |
PORT clk |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
USER_INTERFACE |
{ |
USER_LABELS |
{ |
name = "n2h2_rx_chan"; |
technology = "imported components"; |
} |
} |
SOPC_Builder_Version = "0.0"; |
COMPONENT_BUILDER |
{ |
HDL_PARAMETERS |
{ |
# generated by CBDocument.getParameterContainer |
# used only by Component Editor |
HDL_PARAMETER data_width_g |
{ |
parameter_name = "data_width_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_width_g |
{ |
parameter_name = "hibi_addr_width_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER addr_width_g |
{ |
parameter_name = "addr_width_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER amount_width_g |
{ |
parameter_name = "amount_width_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER addr_cmp_lo_g |
{ |
parameter_name = "addr_cmp_lo_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER addr_cmp_hi_g |
{ |
parameter_name = "addr_cmp_hi_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
} |
} |
} |
} |
} |
FILE n2h2_rx_channels.vhd |
{ |
file_mod = "Mon Jun 25 15:19:31 EEST 2007"; |
quartus_map_start = "Tue Jun 26 10:36:23 EEST 2007"; |
quartus_map_finished = "Tue Jun 26 10:36:27 EEST 2007"; |
#found 1 valid modules |
WRAPPER n2h2_rx_channels |
{ |
CLASS n2h2_rx_channels |
{ |
CB_GENERATOR |
{ |
HDL_FILES |
{ |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = ""; |
filepath = "F:/SVN/Hibi/trunk/Hibi/IP/Adapters/N2H2/V2/Ver_02/n2h2_rx_channels.vhd"; |
} |
} |
top_module_name = "n2h2_rx_channels"; |
emit_system_h = "0"; |
LIBRARIES |
{ |
library = "ieee.std_logic_1164.all"; |
library = "ieee.std_logic_arith.all"; |
library = "ieee.std_logic_unsigned.all"; |
library = "std.standard.all"; |
} |
} |
MODULE_DEFAULTS global_signals |
{ |
class = "n2h2_rx_channels"; |
class_version = "1.0"; |
SYSTEM_BUILDER_INFO |
{ |
Instantiate_In_System_Module = "1"; |
} |
SLAVE avalon_slave_0 |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT rst_n |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_we_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_be_out |
{ |
width = "-1"; |
width_expression = "(((data_width_g / 8) - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_writedata_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitrequest_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_empty_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_comm_in |
{ |
width = "3"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_re_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_addr_in |
{ |
width = "-1"; |
width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_we_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_re_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_cs_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_start_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_comm_out |
{ |
width = "3"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_mem_addr_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_hibi_addr_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_amount_out |
{ |
width = "-1"; |
width_expression = "((amount_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_status_done_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
SLAVE avalon_cfg |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT avalon_cfg_writedata_in |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "writedata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_cfg_readdata_out |
{ |
width = "-1"; |
width_expression = "((addr_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "readdata"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
SLAVE rx |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT rx_irq_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "irq"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
PORT_WIRING |
{ |
PORT clk |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
USER_INTERFACE |
{ |
USER_LABELS |
{ |
name = "n2h2_rx_channels"; |
technology = "imported components"; |
} |
} |
SOPC_Builder_Version = "0.0"; |
COMPONENT_BUILDER |
{ |
HDL_PARAMETERS |
{ |
# generated by CBDocument.getParameterContainer |
# used only by Component Editor |
HDL_PARAMETER n_chans_g |
{ |
parameter_name = "n_chans_g"; |
type = "integer"; |
default_value = "3"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER n_chans_bits_g |
{ |
parameter_name = "n_chans_bits_g"; |
type = "integer"; |
default_value = "2"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER data_width_g |
{ |
parameter_name = "data_width_g"; |
type = "integer"; |
default_value = "1"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER addr_width_g |
{ |
parameter_name = "addr_width_g"; |
type = "integer"; |
default_value = "1"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_cmp_hi_g |
{ |
parameter_name = "hibi_addr_cmp_hi_g"; |
type = "integer"; |
default_value = "1"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER hibi_addr_cmp_lo_g |
{ |
parameter_name = "hibi_addr_cmp_lo_g"; |
type = "integer"; |
default_value = "1"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER amount_width_g |
{ |
parameter_name = "amount_width_g"; |
type = "integer"; |
default_value = "1"; |
editable = "1"; |
tooltip = ""; |
} |
} |
} |
} |
} |
} |
FILE n2h2_tx_vl.vhd |
{ |
file_mod = "Mon Feb 19 10:43:46 EET 2007"; |
quartus_map_start = "Tue Jun 26 10:36:27 EEST 2007"; |
quartus_map_finished = "Tue Jun 26 10:36:31 EEST 2007"; |
#found 1 valid modules |
WRAPPER n2h2_tx |
{ |
CLASS n2h2_tx |
{ |
CB_GENERATOR |
{ |
HDL_FILES |
{ |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = ""; |
filepath = "F:/SVN/Hibi/trunk/Hibi/IP/Adapters/N2H2/V2/Ver_02/n2h2_tx_vl.vhd"; |
} |
} |
top_module_name = "n2h2_tx"; |
emit_system_h = "0"; |
LIBRARIES |
{ |
library = "ieee.std_logic_1164.all"; |
library = "ieee.std_logic_arith.all"; |
library = "ieee.std_logic_unsigned.all"; |
library = "std.standard.all"; |
} |
} |
MODULE_DEFAULTS global_signals |
{ |
class = "n2h2_tx"; |
class_version = "1.0"; |
SYSTEM_BUILDER_INFO |
{ |
Instantiate_In_System_Module = "1"; |
} |
SLAVE avalon_slave_0 |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT rst_n |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_addr_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_re_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_readdata_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_waitrequest_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT avalon_readdatavalid_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_data_out |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_av_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_full_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_comm_out |
{ |
width = "3"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT hibi_we_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_start_in |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_status_done_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_comm_in |
{ |
width = "3"; |
width_expression = ""; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_hibi_addr_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_ram_addr_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT tx_amount_in |
{ |
width = "-1"; |
width_expression = "((amount_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
PORT_WIRING |
{ |
PORT clk |
{ |
width = "1"; |
width_expression = ""; |
direction = "input"; |
type = "clk"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
USER_INTERFACE |
{ |
USER_LABELS |
{ |
name = "n2h2_tx"; |
technology = "imported components"; |
} |
} |
SOPC_Builder_Version = "0.0"; |
COMPONENT_BUILDER |
{ |
HDL_PARAMETERS |
{ |
# generated by CBDocument.getParameterContainer |
# used only by Component Editor |
HDL_PARAMETER data_width_g |
{ |
parameter_name = "data_width_g"; |
type = "integer"; |
default_value = "32"; |
editable = "1"; |
tooltip = ""; |
} |
HDL_PARAMETER amount_width_g |
{ |
parameter_name = "amount_width_g"; |
type = "integer"; |
default_value = "16"; |
editable = "1"; |
tooltip = ""; |
} |
} |
} |
} |
} |
} |
FILE one_hot_mux.vhd |
{ |
file_mod = "Mon Jun 25 10:14:23 EEST 2007"; |
quartus_map_start = "Tue Jun 26 10:36:31 EEST 2007"; |
quartus_map_finished = "Tue Jun 26 10:36:36 EEST 2007"; |
#found 1 valid modules |
WRAPPER one_hot_mux |
{ |
CLASS one_hot_mux |
{ |
CB_GENERATOR |
{ |
HDL_FILES |
{ |
FILE |
{ |
use_in_simulation = "1"; |
use_in_synthesis = "1"; |
type = ""; |
filepath = "F:/SVN/Hibi/trunk/Hibi/IP/Adapters/N2H2/V2/Ver_02/one_hot_mux.vhd"; |
} |
} |
top_module_name = "one_hot_mux"; |
emit_system_h = "0"; |
LIBRARIES |
{ |
library = "ieee.std_logic_1164.all"; |
library = "ieee.std_logic_arith.all"; |
library = "ieee.std_logic_unsigned.all"; |
library = "ieee.std_logic_misc.all"; |
library = "std.standard.all"; |
} |
} |
MODULE_DEFAULTS global_signals |
{ |
class = "one_hot_mux"; |
class_version = "1.0"; |
SYSTEM_BUILDER_INFO |
{ |
Instantiate_In_System_Module = "1"; |
} |
SLAVE avalon_slave_0 |
{ |
SYSTEM_BUILDER_INFO |
{ |
Bus_Type = "avalon"; |
} |
PORT_WIRING |
{ |
PORT data_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT sel_in |
{ |
width = "-1"; |
width_expression = "((data_width_g - 1)) - (0) + 1"; |
direction = "input"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
PORT data_out |
{ |
width = "1"; |
width_expression = ""; |
direction = "output"; |
type = "export"; |
is_shared = "0"; |
vhdl_record_name = ""; |
vhdl_record_type = ""; |
} |
} |
} |
} |
USER_INTERFACE |
{ |
USER_LABELS |
{ |
name = "one_hot_mux"; |
technology = "imported components"; |
} |
} |
SOPC_Builder_Version = "0.0"; |
COMPONENT_BUILDER |
{ |
HDL_PARAMETERS |
{ |
# generated by CBDocument.getParameterContainer |
# used only by Component Editor |
HDL_PARAMETER data_width_g |
{ |
parameter_name = "data_width_g"; |
type = "integer"; |
default_value = "0"; |
editable = "1"; |
tooltip = ""; |
} |
} |
} |
} |
} |
} |
} |
} |
ASSOCIATED_FILES |
{ |
Add_Program = "the_wizard_ui"; |
Edit_Program = "the_wizard_ui"; |
Generator_Program = "cb_generator.pl"; |
} |
} |
/TUT/ip.hwp.communication/n2h2/vhd/n2h2_chan_hw.tcl
0,0 → 1,281
# TCL File Generated by Component Editor 10.0sp1 |
# Mon Feb 28 13:30:16 EET 2011 |
# DO NOT MODIFY |
|
|
# +----------------------------------- |
# | |
# | n2h2_chan "n2h2_chan" v1.0 |
# | null 2011.02.28.13:30:16 |
# | |
# | |
# | D:/user/lehton87/work/n2h2/vhd/n2h2_chan.vhd |
# | |
# | ./n2h2_chan.vhd syn, sim |
# | ./n2h2_rx_chan.vhd syn, sim |
# | ./n2h2_rx_channels.vhd syn, sim |
# | ./n2h2_tx_vl.vhd syn, sim |
# | ./one_hot_mux.vhd syn, sim |
# | ./step_counter2.vhd syn, sim |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | request TCL package from ACDS 10.0 |
# | |
package require -exact sopc 10.0 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | module n2h2_chan |
# | |
set_module_property NAME n2h2_chan |
set_module_property VERSION 1.0 |
set_module_property INTERNAL false |
set_module_property GROUP Other |
set_module_property DISPLAY_NAME n2h2_chan |
set_module_property TOP_LEVEL_HDL_FILE n2h2_chan.vhd |
set_module_property TOP_LEVEL_HDL_MODULE n2h2 |
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
set_module_property EDITABLE true |
set_module_property ANALYZE_HDL TRUE |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | files |
# | |
add_file n2h2_chan.vhd {SYNTHESIS SIMULATION} |
add_file n2h2_rx_chan.vhd {SYNTHESIS SIMULATION} |
add_file n2h2_rx_channels.vhd {SYNTHESIS SIMULATION} |
add_file n2h2_tx_vl.vhd {SYNTHESIS SIMULATION} |
add_file one_hot_mux.vhd {SYNTHESIS SIMULATION} |
add_file step_counter2.vhd {SYNTHESIS SIMULATION} |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | parameters |
# | |
add_parameter data_width_g INTEGER 32 |
set_parameter_property data_width_g DEFAULT_VALUE 32 |
set_parameter_property data_width_g DISPLAY_NAME data_width_g |
set_parameter_property data_width_g TYPE INTEGER |
set_parameter_property data_width_g UNITS None |
set_parameter_property data_width_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property data_width_g AFFECTS_GENERATION false |
set_parameter_property data_width_g HDL_PARAMETER true |
add_parameter addr_width_g INTEGER 32 |
set_parameter_property addr_width_g DEFAULT_VALUE 32 |
set_parameter_property addr_width_g DISPLAY_NAME addr_width_g |
set_parameter_property addr_width_g TYPE INTEGER |
set_parameter_property addr_width_g UNITS None |
set_parameter_property addr_width_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property addr_width_g AFFECTS_GENERATION false |
set_parameter_property addr_width_g HDL_PARAMETER true |
add_parameter amount_width_g INTEGER 16 |
set_parameter_property amount_width_g DEFAULT_VALUE 16 |
set_parameter_property amount_width_g DISPLAY_NAME amount_width_g |
set_parameter_property amount_width_g TYPE INTEGER |
set_parameter_property amount_width_g UNITS None |
set_parameter_property amount_width_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property amount_width_g AFFECTS_GENERATION false |
set_parameter_property amount_width_g HDL_PARAMETER true |
add_parameter n_chans_g INTEGER 8 |
set_parameter_property n_chans_g DEFAULT_VALUE 8 |
set_parameter_property n_chans_g DISPLAY_NAME n_chans_g |
set_parameter_property n_chans_g TYPE INTEGER |
set_parameter_property n_chans_g UNITS None |
set_parameter_property n_chans_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property n_chans_g AFFECTS_GENERATION false |
set_parameter_property n_chans_g HDL_PARAMETER true |
add_parameter n_chans_bits_g INTEGER 3 |
set_parameter_property n_chans_bits_g DEFAULT_VALUE 3 |
set_parameter_property n_chans_bits_g DISPLAY_NAME n_chans_bits_g |
set_parameter_property n_chans_bits_g TYPE INTEGER |
set_parameter_property n_chans_bits_g UNITS None |
set_parameter_property n_chans_bits_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property n_chans_bits_g AFFECTS_GENERATION false |
set_parameter_property n_chans_bits_g HDL_PARAMETER true |
add_parameter hibi_addr_cmp_lo_g INTEGER 8 |
set_parameter_property hibi_addr_cmp_lo_g DEFAULT_VALUE 8 |
set_parameter_property hibi_addr_cmp_lo_g DISPLAY_NAME hibi_addr_cmp_lo_g |
set_parameter_property hibi_addr_cmp_lo_g TYPE INTEGER |
set_parameter_property hibi_addr_cmp_lo_g UNITS None |
set_parameter_property hibi_addr_cmp_lo_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property hibi_addr_cmp_lo_g AFFECTS_GENERATION false |
set_parameter_property hibi_addr_cmp_lo_g HDL_PARAMETER true |
add_parameter hibi_addr_cmp_hi_g INTEGER 31 |
set_parameter_property hibi_addr_cmp_hi_g DEFAULT_VALUE 31 |
set_parameter_property hibi_addr_cmp_hi_g DISPLAY_NAME hibi_addr_cmp_hi_g |
set_parameter_property hibi_addr_cmp_hi_g TYPE INTEGER |
set_parameter_property hibi_addr_cmp_hi_g UNITS None |
set_parameter_property hibi_addr_cmp_hi_g ALLOWED_RANGES -2147483648:2147483647 |
set_parameter_property hibi_addr_cmp_hi_g AFFECTS_GENERATION false |
set_parameter_property hibi_addr_cmp_hi_g HDL_PARAMETER true |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | display items |
# | |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_slave_0 |
# | |
add_interface avalon_slave_0 avalon end |
set_interface_property avalon_slave_0 addressAlignment DYNAMIC |
set_interface_property avalon_slave_0 associatedClock clock_sink |
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false |
set_interface_property avalon_slave_0 explicitAddressSpan 0 |
set_interface_property avalon_slave_0 holdTime 0 |
set_interface_property avalon_slave_0 isMemoryDevice false |
set_interface_property avalon_slave_0 isNonVolatileStorage false |
set_interface_property avalon_slave_0 linewrapBursts false |
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 |
set_interface_property avalon_slave_0 printableDevice false |
set_interface_property avalon_slave_0 readLatency 0 |
set_interface_property avalon_slave_0 readWaitTime 1 |
set_interface_property avalon_slave_0 setupTime 0 |
set_interface_property avalon_slave_0 timingUnits Cycles |
set_interface_property avalon_slave_0 writeWaitTime 0 |
|
set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_sink |
set_interface_property avalon_slave_0 ENABLED true |
|
add_interface_port avalon_slave_0 avalon_cfg_addr_in address Input n_chans_bits_g+4 |
add_interface_port avalon_slave_0 avalon_cfg_we_in write Input 1 |
add_interface_port avalon_slave_0 avalon_cfg_re_in read Input 1 |
add_interface_port avalon_slave_0 avalon_cfg_cs_in chipselect Input 1 |
add_interface_port avalon_slave_0 avalon_cfg_waitrequest_out waitrequest Output 1 |
add_interface_port avalon_slave_0 avalon_cfg_writedata_in writedata Input addr_width_g |
add_interface_port avalon_slave_0 avalon_cfg_readdata_out readdata Output addr_width_g |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point conduit_end |
# | |
add_interface conduit_end conduit end |
|
set_interface_property conduit_end ENABLED true |
|
add_interface_port conduit_end hibi_data_in export Input data_width_g |
add_interface_port conduit_end hibi_av_in export Input 1 |
add_interface_port conduit_end hibi_empty_in export Input 1 |
add_interface_port conduit_end hibi_comm_in export Input 5 |
add_interface_port conduit_end hibi_re_out export Output 1 |
add_interface_port conduit_end hibi_data_out export Output data_width_g |
add_interface_port conduit_end hibi_av_out export Output 1 |
add_interface_port conduit_end hibi_full_in export Input 1 |
add_interface_port conduit_end hibi_comm_out export Output 5 |
add_interface_port conduit_end hibi_we_out export Output 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock_sink |
# | |
add_interface clock_sink clock end |
|
set_interface_property clock_sink ENABLED true |
|
add_interface_port clock_sink clk_cfg clk Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock_sink_reset |
# | |
add_interface clock_sink_reset reset end |
set_interface_property clock_sink_reset associatedClock clock_sink |
set_interface_property clock_sink_reset synchronousEdges DEASSERT |
|
set_interface_property clock_sink_reset ASSOCIATED_CLOCK clock_sink |
set_interface_property clock_sink_reset ENABLED true |
|
add_interface_port clock_sink_reset rst_n reset_n Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock_sink_1 |
# | |
add_interface clock_sink_1 clock end |
|
set_interface_property clock_sink_1 ENABLED true |
|
add_interface_port clock_sink_1 clk_tx clk Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock_sink_2 |
# | |
add_interface clock_sink_2 clock end |
|
set_interface_property clock_sink_2 ENABLED true |
|
add_interface_port clock_sink_2 clk_rx clk Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point interrupt_sender |
# | |
add_interface interrupt_sender interrupt end |
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0 |
set_interface_property interrupt_sender associatedClock clock_sink |
set_interface_property interrupt_sender associatedReset clock_sink_reset |
|
set_interface_property interrupt_sender ASSOCIATED_CLOCK clock_sink |
set_interface_property interrupt_sender ENABLED true |
|
add_interface_port interrupt_sender rx_irq_out irq Output 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_master |
# | |
add_interface avalon_master avalon start |
set_interface_property avalon_master associatedClock clock_sink_1 |
set_interface_property avalon_master burstOnBurstBoundariesOnly false |
set_interface_property avalon_master doStreamReads false |
set_interface_property avalon_master doStreamWrites false |
set_interface_property avalon_master linewrapBursts false |
|
set_interface_property avalon_master ASSOCIATED_CLOCK clock_sink_1 |
set_interface_property avalon_master ENABLED true |
|
add_interface_port avalon_master avalon_addr_out_rx address Output addr_width_g |
add_interface_port avalon_master avalon_we_out_rx write Output 1 |
add_interface_port avalon_master avalon_be_out_rx byteenable Output data_width_g/8 |
add_interface_port avalon_master avalon_writedata_out_rx writedata Output data_width_g |
add_interface_port avalon_master avalon_waitrequest_in_rx waitrequest Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_master_1 |
# | |
add_interface avalon_master_1 avalon start |
set_interface_property avalon_master_1 associatedClock clock_sink_2 |
set_interface_property avalon_master_1 burstOnBurstBoundariesOnly false |
set_interface_property avalon_master_1 doStreamReads false |
set_interface_property avalon_master_1 doStreamWrites false |
set_interface_property avalon_master_1 linewrapBursts false |
|
set_interface_property avalon_master_1 ASSOCIATED_CLOCK clock_sink_2 |
set_interface_property avalon_master_1 ENABLED true |
|
add_interface_port avalon_master_1 avalon_readdatavalid_in_tx readdatavalid Input 1 |
add_interface_port avalon_master_1 avalon_waitrequest_in_tx waitrequest Input 1 |
add_interface_port avalon_master_1 avalon_readdata_in_tx readdata Input data_width_g |
add_interface_port avalon_master_1 avalon_re_out_tx read Output 1 |
add_interface_port avalon_master_1 avalon_addr_out_tx address Output addr_width_g |
# | |
# +----------------------------------- |
/TUT/ip.hwp.communication/n2h2/vhd/n2h2_chan.vhd
0,0 → 1,232
------------------------------------------------------------------------------- |
-- Title : N2H2 Top level |
-- Project : |
------------------------------------------------------------------------------- |
-- File : n2h2.vhd |
-- Author : kulmala3 |
-- Created : 30.03.2005 |
-- Last update: 2011-04-04 |
-- Description: Wires together rx and tx |
------------------------------------------------------------------------------- |
-- Copyright (c) 2005 |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 30.03.2005 1.0 AK Created |
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
--use work.log2_pkg.all; |
|
entity n2h2 is |
|
generic ( |
data_width_g : integer := 32; -- 32 and 64 supported |
addr_width_g : integer := 32; |
amount_width_g : integer := 16; |
n_chans_g : integer := 8; |
n_chans_bits_g : integer := 3; -- how many bits to show n_chans |
-- eg 2 for 4, 3 for 5, basically log2(n_chans_g) |
hibi_addr_cmp_lo_g : integer := 8; |
hibi_addr_cmp_hi_g : integer := 31 |
); |
|
port ( |
clk_cfg : in std_logic; -- not even used... |
clk_tx : in std_logic; |
clk_rx : in std_logic; |
rst_n : in std_logic; -- THIS IS ACTIVE HIGH! |
|
-- avalon master (rx) if |
avalon_addr_out_rx : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_we_out_rx : out std_logic; |
avalon_be_out_rx : out std_logic_vector(data_width_g/8-1 downto 0); |
avalon_writedata_out_rx : out std_logic_vector(data_width_g-1 downto 0); |
avalon_waitrequest_in_rx : in std_logic; |
|
--avalon slave if (config) |
avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0); |
avalon_cfg_writedata_in : in std_logic_vector(addr_width_g-1 downto 0); |
avalon_cfg_we_in : in std_logic; |
avalon_cfg_readdata_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_cfg_re_in : in std_logic; |
avalon_cfg_cs_in : in std_logic; |
avalon_cfg_waitrequest_out : out std_logic; |
|
-- Avalon master read interface (tx) |
avalon_addr_out_tx : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_re_out_tx : out std_logic; |
avalon_readdata_in_tx : in std_logic_vector(data_width_g-1 downto 0); |
avalon_waitrequest_in_tx : in std_logic; |
avalon_readdatavalid_in_tx : in std_logic; |
|
-- hibi (rx) if |
hibi_data_in : in std_logic_vector(data_width_g-1 downto 0); |
hibi_av_in : in std_logic; |
hibi_empty_in : in std_logic; |
hibi_comm_in : in std_logic_vector(4 downto 0); |
hibi_re_out : out std_logic; |
|
-- hibi write interface (tx) |
hibi_data_out : out std_logic_vector(data_width_g-1 downto 0); |
hibi_av_out : out std_logic; |
hibi_full_in : in std_logic; |
hibi_comm_out : out std_logic_vector(4 downto 0); |
hibi_we_out : out std_logic; |
|
rx_irq_out : out std_logic |
|
); |
|
end n2h2; |
|
architecture structural of n2h2 is |
|
signal tx_start_from_rx : std_logic; |
signal tx_comm_from_rx : std_logic_vector(4 downto 0); |
signal tx_mem_addr_from_rx : std_logic_vector(addr_width_g-1 downto 0); |
signal tx_hibi_addr_from_rx : std_logic_vector(addr_width_g-1 downto 0); |
signal tx_amount_from_rx : std_logic_vector(amount_width_g-1 downto 0); |
signal tx_status_done_to_rx : std_logic; |
signal real_rst_n : std_logic; |
|
component n2h2_rx_channels |
generic ( |
n_chans_g : integer; |
n_chans_bits_g : integer; |
data_width_g : integer; |
addr_width_g : integer; |
hibi_addr_cmp_hi_g : integer; |
hibi_addr_cmp_lo_g : integer; |
amount_width_g : integer); |
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_we_out : out std_logic; |
avalon_be_out : out std_logic_vector(data_width_g/8-1 downto 0); |
avalon_writedata_out : out std_logic_vector(data_width_g-1 downto 0); |
avalon_waitrequest_in : in std_logic; |
hibi_data_in : in std_logic_vector(data_width_g-1 downto 0); |
hibi_av_in : in std_logic; |
hibi_empty_in : in std_logic; |
hibi_comm_in : in std_logic_vector(4 downto 0); |
hibi_re_out : out std_logic; |
avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0); |
avalon_cfg_writedata_in : in std_logic_vector(addr_width_g-1 downto 0); |
avalon_cfg_we_in : in std_logic; |
avalon_cfg_readdata_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_cfg_re_in : in std_logic; |
avalon_cfg_cs_in : in std_logic; |
avalon_cfg_waitrequest_out : out std_logic; |
rx_irq_out : out std_logic; |
tx_start_out : out std_logic; |
tx_comm_out : out std_logic_vector(4 downto 0); |
tx_mem_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
tx_hibi_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
tx_amount_out : out std_logic_vector(amount_width_g-1 downto 0); |
tx_status_done_in : in std_logic); |
end component; |
|
component n2h2_tx |
generic ( |
data_width_g : integer; |
addr_width_g : integer; |
amount_width_g : integer); |
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_re_out : out std_logic; |
avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0); |
avalon_waitrequest_in : in std_logic; |
avalon_readdatavalid_in : in std_logic; |
|
hibi_data_out : out std_logic_vector(data_width_g-1 downto 0); |
hibi_av_out : out std_logic; |
hibi_full_in : in std_logic; |
hibi_comm_out : out std_logic_vector(4 downto 0); |
hibi_we_out : out std_logic; |
tx_start_in : in std_logic; |
tx_status_done_out : out std_logic; |
tx_comm_in : in std_logic_vector(4 downto 0); |
tx_hibi_addr_in : in std_logic_vector(addr_width_g-1 downto 0); |
tx_ram_addr_in : in std_logic_vector(addr_width_g-1 downto 0); |
tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0)); |
end component; |
|
|
begin -- structural |
|
|
|
real_rst_n <= rst_n; |
|
assert data_width_g = 64 or data_width_g = 32 report "Data width other than 32 or 64 not currently supported" severity failure; |
|
n2h2_rx_chan_1 : n2h2_rx_channels |
generic map ( |
n_chans_g => n_chans_g, |
n_chans_bits_g => n_chans_bits_g, |
data_width_g => data_width_g, |
addr_width_g => addr_width_g, |
hibi_addr_cmp_hi_g => hibi_addr_cmp_hi_g, |
hibi_addr_cmp_lo_g => hibi_addr_cmp_lo_g, |
amount_width_g => amount_width_g |
) |
port map ( |
clk => clk_rx, |
rst_n => real_rst_n, |
avalon_addr_out => avalon_addr_out_rx, |
avalon_we_out => avalon_we_out_rx, |
avalon_be_out => avalon_be_out_rx, |
avalon_writedata_out => avalon_writedata_out_rx, |
avalon_waitrequest_in => avalon_waitrequest_in_rx, |
hibi_data_in => hibi_data_in, |
hibi_av_in => hibi_av_in, |
hibi_empty_in => hibi_empty_in, |
hibi_comm_in => hibi_comm_in, |
hibi_re_out => hibi_re_out, |
avalon_cfg_addr_in => avalon_cfg_addr_in, |
avalon_cfg_writedata_in => avalon_cfg_writedata_in, |
avalon_cfg_we_in => avalon_cfg_we_in, |
avalon_cfg_readdata_out => avalon_cfg_readdata_out, |
avalon_cfg_re_in => avalon_cfg_re_in, |
avalon_cfg_cs_in => avalon_cfg_cs_in, |
avalon_cfg_waitrequest_out => avalon_cfg_waitrequest_out, |
rx_irq_out => rx_irq_out, |
tx_start_out => tx_start_from_rx, |
tx_comm_out => tx_comm_from_rx, |
tx_mem_addr_out => tx_mem_addr_from_rx, |
tx_hibi_addr_out => tx_hibi_addr_from_rx, |
tx_amount_out => tx_amount_from_rx, |
tx_status_done_in => tx_status_done_to_rx |
); |
|
n2h2_tx_1 : n2h2_tx |
generic map ( |
data_width_g => data_width_g, |
addr_width_g => addr_width_g, |
amount_width_g => amount_width_g) |
port map ( |
clk => clk_tx, |
rst_n => real_rst_n, |
avalon_addr_out => avalon_addr_out_tx, |
avalon_re_out => avalon_re_out_tx, |
avalon_readdata_in => avalon_readdata_in_tx, |
avalon_waitrequest_in => avalon_waitrequest_in_tx, |
avalon_readdatavalid_in => avalon_readdatavalid_in_tx, |
hibi_data_out => hibi_data_out, |
hibi_av_out => hibi_av_out, |
hibi_full_in => hibi_full_in, |
hibi_comm_out => hibi_comm_out, |
hibi_we_out => hibi_we_out, |
tx_start_in => tx_start_from_rx, |
tx_status_done_out => tx_status_done_to_rx, |
tx_hibi_addr_in => tx_hibi_addr_from_rx, |
tx_comm_in => tx_comm_from_rx, |
tx_ram_addr_in => tx_mem_addr_from_rx, |
tx_amount_in => tx_amount_from_rx |
); |
|
end structural; |
/TUT/ip.hwp.communication/n2h2/vhd/one_hot_mux.vhd
0,0 → 1,55
------------------------------------------------------------------------------- |
-- Title : one hot mux for one bit |
-- Project : |
------------------------------------------------------------------------------- |
-- File : one_hot_mux.vhd |
-- Author : kulmala3 |
-- Created : 16.06.2005 |
-- Last update: 25.06.2007 |
-- Description: select signal is one-hot, otherwise - a mux for one bit. |
-- Asynchronous. |
------------------------------------------------------------------------------- |
-- Copyright (c) 2005 |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 16.06.2005 1.0 AK Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_misc.all; |
|
entity one_hot_mux is |
|
generic ( |
data_width_g : integer := 0); |
|
port ( |
data_in : in std_logic_vector(data_width_g-1 downto 0); |
sel_in : in std_logic_vector(data_width_g-1 downto 0); |
data_out : out std_logic |
); |
|
end one_hot_mux; |
|
architecture rtl of one_hot_mux is |
|
begin -- rtl |
|
m: process (data_in, sel_in) |
variable temp : std_logic_vector(data_width_g-1 downto 0); |
begin -- process m |
|
for i in 0 to data_width_g-1 loop |
temp(i) := sel_in(i) and data_in(i); |
end loop; -- i |
|
data_out <= or_reduce(temp); |
|
end process m; |
|
|
end rtl; |
/TUT/ip.hwp.communication/n2h2/vhd/n2h2_tx_vl.vhd
0,0 → 1,313
------------------------------------------------------------------------------- |
-- Title : N2H2 TX with variable latency support |
-- Project : |
------------------------------------------------------------------------------- |
-- File : n2h2_tx.vhd |
-- Author : kulmala3 |
-- Created : 30.03.2005 |
-- Last update: 2011-02-02 |
-- Description: Bufferless transmitter for N2H2. new version to be used |
-- with memories of all latencies. |
-- |
-- REQUIRES: |
-- step_counter2.vhd |
------------------------------------------------------------------------------- |
-- Copyright (c) 2005 |
-- New version of TX. uses step_counter2.vhd, supports streaming. |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 30.03.2005 1.0 AK Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity n2h2_tx is |
|
generic ( |
|
data_width_g : integer := 32; |
addr_width_g : integer := 32; |
amount_width_g : integer := 16); |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
-- Avalon master read interface |
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_re_out : out std_logic; |
avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0); |
avalon_waitrequest_in : in std_logic; |
avalon_readdatavalid_in : in std_logic; |
|
-- hibi write interface |
hibi_data_out : out std_logic_vector(data_width_g-1 downto 0); |
hibi_av_out : out std_logic; |
hibi_full_in : in std_logic; |
hibi_comm_out : out std_logic_vector(4 downto 0); |
hibi_we_out : out std_logic; |
|
-- DMA conf interface |
tx_start_in : in std_logic; |
tx_status_done_out : out std_logic; |
tx_comm_in : in std_logic_vector(4 downto 0); |
tx_hibi_addr_in : in std_logic_vector(addr_width_g-1 downto 0); |
tx_ram_addr_in : in std_logic_vector(addr_width_g-1 downto 0); |
tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0) |
); |
|
end n2h2_tx; |
|
architecture rtl of n2h2_tx is |
|
type control_states is (idle, transmit_addr, transmit, hfull); |
signal control_r : control_states; |
constant addr_offset_c : integer := data_width_g/8; |
|
component step_counter2 |
generic ( |
step_size_g : integer; |
width_g : integer |
); |
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
en_in : in std_logic; |
value_in : in std_logic_vector(width_g-1 downto 0); |
load_in : in std_logic; |
value_out : out std_logic_vector(width_g-1 downto 0)); |
end component; |
|
signal addr_cnt_en_r : std_logic; |
signal addr_cnt_value_r : std_logic_vector(addr_width_g-1 downto 0); |
signal addr_cnt_load_r : std_logic; |
signal addr_r : std_logic_vector(addr_width_g-1 downto 0); |
signal amount_cnt_en_r : std_logic; |
signal amount_cnt_value_r : std_logic_vector(addr_width_g-1 downto 0); |
signal amount_cnt_load_r : std_logic; |
signal amount_r : std_logic_vector(addr_width_g-1 downto 0); |
|
signal addr_amount_eq : std_logic; |
|
signal addr_to_stop_r : std_logic_vector(addr_width_g-1 downto 0); |
signal avalon_re_r : std_logic; |
signal start_re_r : std_logic; |
|
signal hibi_write_addr_r : std_logic; |
signal data_src_sel : std_logic; |
signal hibi_we_r : std_logic; |
signal hibi_stop_we_r : std_logic; |
|
|
begin -- rtl |
|
----------------------------------------------------------------------------- |
-- 1) waitrequest affects the data reading |
-- 2) readdatavalid data write to hibi |
-- 3) avalon side read must control the amount of data |
-- 4) whenever readdatavalid is asserted, data is written to HIBI |
-- 5) HIBI full is problematic. A counter must be added to see from which |
-- address we have succesfully read the data so far. We cannot |
-- save the data to register, because we are unaware of the latency. |
-- So when full comes, the read process from avalon must be started |
-- again. |
-- 6) write and read signals should be asynchronously controlled by |
-- signals from hibi and avalon in order to react as fast as possible. |
-- 7) after full the write should be ceased. readdatavalid from older data |
-- should be taken care of. Write continues only after read enable has |
-- been asserted again? |
-- 8) read from avalon must proceed as fast as possible. for example, |
-- start already when writing address to hibi. (at least one clock |
-- cycle latency expected, should be safe). Or after full. |
-- 9) data to hibi comes from either register input (address) or |
-- straight from the memory. mux is needed. |
----------------------------------------------------------------------------- |
|
hibi_comm_out <= tx_comm_in; |
-- minus here and and addition in first store? could reduce the |
-- cricital path... |
avalon_addr_out <= addr_r; |
|
addr_counter2_1 : step_counter2 |
generic map ( |
step_size_g => addr_offset_c, |
width_g => addr_width_g) |
port map ( |
clk => clk, |
rst_n => rst_n, |
en_in => addr_cnt_en_r, |
value_in => addr_cnt_value_r, |
load_in => addr_cnt_load_r, |
value_out => addr_r |
); |
|
addr_cnt_load_r <= (tx_start_in or hibi_full_in); |
addr_cnt : process (tx_ram_addr_in, amount_r, tx_start_in) |
begin -- process addr_cnt |
if tx_start_in = '1' then |
-- addr from input |
addr_cnt_value_r <= tx_ram_addr_in; |
else |
-- addr from counter |
addr_cnt_value_r <= amount_r; |
end if; |
end process addr_cnt; |
|
|
|
amount_counter2_1 : step_counter2 |
generic map ( |
step_size_g => addr_offset_c, |
width_g => addr_width_g) |
port map ( |
clk => clk, |
rst_n => rst_n, |
en_in => amount_cnt_en_r, |
value_in => amount_cnt_value_r, |
load_in => amount_cnt_load_r, |
value_out => amount_r |
); |
-- amount counted only when data is written |
amount_cnt_en_r <= hibi_we_r and (not data_src_sel); |
-- hibi_we depends on readdatavalid and full + control signal for |
-- address writing |
-- start address writing right when the signal comes in. |
-- no old readdatavalids should be written if full is short. |
hibi_we_out <= hibi_we_r; |
hibi_we_r <= ((data_src_sel) or (avalon_readdatavalid_in and (not hibi_stop_we_r))) |
and (not hibi_full_in); |
|
data_src_sel <= tx_start_in or hibi_write_addr_r; |
hibi_av_out <= data_src_sel; |
|
addr_data : process (tx_hibi_addr_in, avalon_readdata_in, data_src_sel) |
begin -- process addr_data |
if data_src_sel = '1' then |
hibi_data_out <= (others => '0'); |
hibi_data_out(addr_width_g-1 downto 0) <= tx_hibi_addr_in; |
else |
hibi_data_out <= avalon_readdata_in; |
end if; |
end process addr_data; |
|
-- if we're reading and not forced to wait, |
-- increase the address. we want to cease reading if hibi goes full |
-- (reload address) |
addr_cnt_en_r <= (avalon_re_r and (not avalon_waitrequest_in)) and |
(not hibi_full_in); |
avalon_re_out <= avalon_re_r; |
-- read enable depends on the amount transferred, if a |
-- transmission is ongoing. shoot as soon as possible, |
-- whenever new transmission is assigned. |
-- CHECK OUT THIS ONE! could be used to fasten n2h2 up! |
avalon_re_r <= start_re_r;-- or (tx_start_in and (not hibi_full_in)); |
|
comparison : process (addr_r, addr_to_stop_r) |
begin -- process comparison |
-- addr_offset added here, because addr_to_stop process caused two |
-- back-to-back adders, now they should be in parallel |
if addr_r = addr_to_stop_r then |
addr_amount_eq <= '1'; |
else |
addr_amount_eq <= '0'; |
end if; |
end process comparison; |
|
addr_to_stop : process (tx_amount_in, tx_ram_addr_in) |
begin -- process addr_to_stop |
addr_to_stop_r <= tx_ram_addr_in + conv_std_logic_vector( |
conv_integer(tx_amount_in)*addr_offset_c, addr_width_g); |
-- conv_integer(tx_amount_in+1)*addr_offset_c, data_width_g); |
end process addr_to_stop; |
|
amount_cnt_value_r <= tx_ram_addr_in; |
amount_cnt_load_r <= tx_start_in; |
|
main : process (clk, rst_n) |
begin -- process main |
if rst_n = '0' then -- asynchronous reset (active low) |
control_r <= idle; |
start_re_r <= '0'; |
hibi_write_addr_r <= '0'; |
tx_status_done_out <= '1'; |
hibi_stop_we_r <= '0'; |
|
elsif clk'event and clk = '1' then -- rising clock edge |
case control_r is |
when idle => |
hibi_write_addr_r <= '0'; |
start_re_r <= '0'; |
tx_status_done_out <= '1'; |
hibi_stop_we_r <= '1'; |
|
if tx_start_in = '1' then |
-- avalon read address |
-- address which contents written to hibi |
tx_status_done_out <= '0'; |
hibi_stop_we_r <= '0'; |
|
if hibi_full_in = '0' then |
-- address will be transferred in this clock cycle |
control_r <= transmit; |
start_re_r <= '1'; |
else |
hibi_write_addr_r <= '1'; |
control_r <= transmit_addr; |
end if; |
end if; |
|
when transmit_addr => |
-- if we're here, hibi was full |
if hibi_full_in = '0' then |
-- we wrote the addr |
start_re_r <= '1'; |
control_r <= transmit; |
hibi_write_addr_r <= '0'; |
else |
start_re_r <= '0'; |
control_r <= transmit_addr; |
hibi_write_addr_r <= '1'; |
end if; |
|
when transmit => |
if hibi_full_in = '1' then |
start_re_r <= '0'; |
control_r <= hfull; |
hibi_stop_we_r <= '1'; |
else |
start_re_r <= '1'; |
hibi_stop_we_r <= '0'; |
control_r <= transmit; |
end if; |
|
-- if addr_amount_eq = '1' and hibi_full_in = '0' then |
if addr_amount_eq = '1' and hibi_we_r = '1' then |
control_r <= idle; |
-- stopped transferring |
tx_status_done_out <= '1'; |
hibi_stop_we_r <= '1'; |
end if; |
|
when hfull => |
if hibi_full_in = '0' and avalon_readdatavalid_in = '0' then |
-- datavalid has to go down before proceed. |
-- so we make sure that no invalid data is written |
-- when there's a short full. |
start_re_r <= '1'; |
hibi_stop_we_r <= '0'; |
control_r <= transmit; |
else |
start_re_r <= '0'; |
hibi_stop_we_r <= '1'; |
control_r <= hfull; |
end if; |
|
when others => null; |
end case; |
end if; |
end process main; |
|
end rtl; |
/TUT/ip.hwp.communication/n2h2/vhd/n2h2_rx_chan.vhd
0,0 → 1,192
------------------------------------------------------------------------------- |
-- Title : N2H2 rx channel |
-- Project : |
------------------------------------------------------------------------------- |
-- File : n2h2_rx_chan.vhd |
-- Author : kulmala3 |
-- Created : 02.06.2005 |
-- Last update: 2011-04-06 |
-- Description: One channel for N2H2 |
-- supports 32 and 64b data widths only due to low cost implemementation :) |
------------------------------------------------------------------------------- |
-- Copyright (c) 2005 |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 02.06.2005 1.0 AK Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity n2h2_rx_chan is |
|
generic ( |
data_width_g : integer := 0; |
hibi_addr_width_g : integer := 0; |
addr_width_g : integer := 0; |
amount_width_g : integer := 0; |
addr_cmp_lo_g : integer := 0; |
addr_cmp_hi_g : integer := 0 |
); |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
|
-- keep still until a new init |
avalon_addr_in : in std_logic_vector(addr_width_g-1 downto 0); |
hibi_addr_in : in std_logic_vector(hibi_addr_width_g-1 downto 0); |
irq_amount_in : in std_logic_vector(amount_width_g-1 downto 0); |
|
hibi_data_in : in std_logic_vector(hibi_addr_width_g-1 downto 0); |
hibi_av_in : in std_logic; |
hibi_empty_in : in std_logic; |
init_in : in std_logic; |
irq_ack_in : in std_logic; |
avalon_waitreq_in : in std_logic; |
avalon_we_in : in std_logic; |
|
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_we_out : out std_logic; |
avalon_be_out : out std_logic_vector(data_width_g/8-1 downto 0); |
addr_match_out : out std_logic; |
addr_match_cmb_out : out std_logic; |
irq_out : out std_logic |
); |
|
end n2h2_rx_chan; |
|
architecture rtl of n2h2_rx_chan is |
constant dont_care_c : std_logic := 'X'; |
constant addr_offset_c : integer := data_width_g/8; |
|
constant words_per_hibi_data_c : integer := data_width_g/32; |
constant upper_valid_c : std_logic := '0'; -- in case of odd data amount, is |
-- either uppoer ('1') or lower ('0') half-word valid? |
constant be_width_c : integer := data_width_g/8; |
signal addr_match_r : std_logic; |
signal addr_match_cmb_s : std_logic; |
signal avalon_addr_r : std_logic_vector(addr_width_g-1 downto 0); |
signal enable_r : std_logic; |
signal ena_av_empty : std_logic_vector(2 downto 0); |
signal irq_counter_r : std_logic_vector(amount_width_g-1 downto 0); |
signal irq_r : std_logic; |
signal we_match_waitreq : std_logic_vector(2 downto 0); |
|
|
begin -- rtl |
|
we_match_waitreq <= avalon_we_in & addr_match_r & avalon_waitreq_in; |
avalon_we_out <= addr_match_r and enable_r; |
irq_out <= irq_r; |
|
addr_match_out <= addr_match_r and enable_r; |
addr_match_cmb_out <= addr_match_cmb_s; |
avalon_addr_out <= avalon_addr_r; |
|
ena_av_empty <= enable_r & hibi_av_in & hibi_empty_in; |
|
addr_match : process (hibi_data_in, hibi_addr_in, addr_match_r, ena_av_empty) |
begin -- process addr_match |
|
case ena_av_empty is |
when "000" | "010" | "011" | "001" => |
addr_match_cmb_s <= '0'; |
when "110" => |
if hibi_data_in(addr_cmp_hi_g downto addr_cmp_lo_g) = |
hibi_addr_in(addr_cmp_hi_g downto addr_cmp_lo_g) then |
addr_match_cmb_s <= '1'; |
else |
addr_match_cmb_s <= '0'; |
end if; |
when others => |
addr_match_cmb_s <= addr_match_r; |
end case; |
|
end process addr_match; |
|
addr_match_reg : process (clk, rst_n) |
begin -- process addr_matching |
if rst_n = '0' then -- asynchronous reset (active low) |
addr_match_r <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
|
addr_match_r <= addr_match_cmb_s; |
|
end if; |
end process addr_match_reg; |
|
|
ena : process (clk, rst_n) |
variable inter_addr : std_logic_vector(addr_width_g-1 downto 0); |
begin -- process ena |
if rst_n = '0' then -- asynchronous reset (active low) |
enable_r <= '0'; |
irq_counter_r <= (others => '1'); |
avalon_addr_r <= (others => dont_care_c); |
irq_r <= '0'; |
|
elsif clk'event and clk = '1' then -- rising clock edge |
|
if init_in = '1' then |
enable_r <= '1'; |
irq_counter_r <= irq_amount_in; |
avalon_addr_r <= avalon_addr_in; |
else |
enable_r <= enable_r; |
irq_counter_r <= irq_counter_r; |
avalon_addr_r <= avalon_addr_r; |
end if; |
|
if irq_ack_in = '1' then |
irq_r <= '0'; |
else |
irq_r <= irq_r; |
end if; |
|
case we_match_waitreq is |
when "110" => |
-- we're writing here |
if irq_counter_r <= conv_std_logic_vector(words_per_hibi_data_c, amount_width_g) then |
avalon_addr_r <= avalon_addr_r+addr_offset_c; -- what if not increased? |
enable_r <= '0'; |
irq_r <= '1'; |
irq_counter_r <= irq_counter_r; |
else |
avalon_addr_r <= avalon_addr_r +addr_offset_c; |
irq_counter_r <= irq_counter_r-words_per_hibi_data_c; |
enable_r <= '1'; |
-- irq_r <= '0'; --already assigned earlier |
end if; |
|
when others => |
-- irq_counter_r <= irq_counter_r; |
-- enable_r <= enable_r; |
-- irq_r <= '0'; |
end case; |
|
-- purpose: sets the avalon byteenable signal |
|
|
end if; |
end process ena; |
|
byteena : process (irq_counter_r) |
begin -- process byteena |
if irq_counter_r = conv_std_logic_vector(1, amount_width_g) and words_per_hibi_data_c = 2 then |
-- odd number of words wanted, e.g. 64 bit hibi, wanted 5 32-bit |
-- words |
avalon_be_out(be_width_c-1 downto be_width_c/2) <= (others => upper_valid_c); |
avalon_be_out(be_width_c/2-1 downto 0) <= (others => (not upper_valid_c)); |
else |
avalon_be_out <= (others => '1'); |
end if; |
|
end process byteena; |
|
|
|
end rtl; |
/TUT/ip.hwp.communication/n2h2/vhd/step_counter2.vhd
0,0 → 1,78
------------------------------------------------------------------------------- |
-- Title : Step counter2 |
-- Project : |
------------------------------------------------------------------------------- |
-- File : step_counter2.vhd |
-- Author : kulmala3 |
-- Created : 01.06.2005 |
-- Last update: 21.11.2005 |
-- Description: A simple counter which step size is parametrizable. |
-- no synch clear. |
------------------------------------------------------------------------------- |
-- Copyright (c) 2005 |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 01.06.2005 1.0 AK Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity step_counter2 is |
|
generic ( |
step_size_g : integer := 4; |
width_g : integer := 32); |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
en_in : in std_logic; |
value_in : in std_logic_vector(width_g-1 downto 0); |
load_in : in std_logic; |
value_out : out std_logic_vector(width_g-1 downto 0) |
); |
|
end step_counter2; |
|
architecture rtl of step_counter2 is |
signal value_r : std_logic_vector(width_g-1 downto 0); |
signal load_en_r : std_logic_vector(1 downto 0); |
begin -- rtl |
load_en_r <= load_in & en_in; |
value_out <= value_r; |
|
process (clk, rst_n) |
begin -- process |
if rst_n = '0' then -- asynchronous reset (active low) |
value_r <= (others => '0'); |
|
elsif clk'event and clk = '1' then -- rising clock edge |
case conv_integer(unsigned(load_en_r)) is |
-- when "1-0" => |
when 2 | 3 => |
value_r <= value_in; |
|
-- when "010" => |
when 1 => |
value_r <= value_r + conv_std_logic_vector(step_size_g, width_g); |
-- when 0 => |
when others => |
value_r <= value_r; |
|
-- when "--1" => |
-- when others => |
-- value_r <= (others => '0'); |
|
end case; |
|
|
end if; |
end process; |
|
|
|
end rtl; |
/TUT/ip.hwp.communication/n2h2/vhd/n2h2_rx_channels.vhd
0,0 → 1,592
------------------------------------------------------------------------------- |
-- Title : Nios to HIBI version 2 |
-- Project : |
------------------------------------------------------------------------------- |
-- File : n2h2_rx_channels.vhdl |
-- Author : kulmala3 |
-- Created : 22.03.2005 |
-- Last update: 2011-04-19 |
-- Description: This version acts as a real dma. |
-- |
-- Currently there's no double-registers in config - the user |
-- must take care when configuring the device. (datas can go to |
-- wrong address etc, if configured while still receiving data from |
-- source) |
-- |
-- Needs 2 clock cycles to propagate the IRQ (ack->irq down-> irq req) |
------------------------------------------------------------------------------- |
-- Copyright (c) 2005 |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 22.03.2005 1.0 AK Created |
------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_misc.all; |
--use work.txt_util.all; |
--use work.log2_pkg.all; |
|
entity n2h2_rx_channels is |
|
generic ( |
|
n_chans_g : integer := 3; |
n_chans_bits_g : integer := 2; -- how many bits to represent n_chans |
-- eg 2 for 4, 3 for 5, basically log2(n_chans_g) |
|
data_width_g : integer := 1; |
addr_width_g : integer := 1; -- the memory addr width |
hibi_addr_cmp_hi_g : integer := 1; -- the highest bit used for comparing address |
hibi_addr_cmp_lo_g : integer := 1; -- the lowest bit |
amount_width_g : integer := 1); -- in bits, maximum amount of data |
-- supposes that amount is always in 32 bit words! |
-- (due to Nios II 32-bitness) |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
-- avalon master (rx) if |
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_we_out : out std_logic; |
avalon_be_out : out std_logic_vector(data_width_g/8-1 downto 0); |
avalon_writedata_out : out std_logic_vector(data_width_g-1 downto 0); |
avalon_waitrequest_in : in std_logic; |
-- hibi if |
hibi_data_in : in std_logic_vector(data_width_g-1 downto 0); |
hibi_av_in : in std_logic; |
hibi_empty_in : in std_logic; |
hibi_comm_in : in std_logic_vector(4 downto 0); |
hibi_re_out : out std_logic; |
|
--avalon slave if (config) |
--conf_bits_c bits for each channel |
avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0); |
avalon_cfg_writedata_in : in std_logic_vector(addr_width_g-1 downto 0); |
avalon_cfg_we_in : in std_logic; |
avalon_cfg_readdata_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_cfg_re_in : in std_logic; |
avalon_cfg_cs_in : in std_logic; |
avalon_cfg_waitrequest_out : out std_logic; |
|
rx_irq_out : out std_logic; |
|
-- to/from tx |
tx_start_out : out std_logic; |
tx_comm_out : out std_logic_vector(4 downto 0); |
tx_mem_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
tx_hibi_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
tx_amount_out : out std_logic_vector(amount_width_g-1 downto 0); |
tx_status_done_in : in std_logic |
|
); |
|
end n2h2_rx_channels; |
|
architecture rtl of n2h2_rx_channels is |
|
-- NOTE!! Also have to change to interface!! avalon_cfg_addr_in !!! |
constant conf_bits_c : integer := 4; -- number of configuration bits in CPU |
-- side address |
constant control_bits_c : integer := 2; -- how many bits in ctrl reg |
constant status_bits_c : integer := 2; -- how many bits in ctrl reg |
constant addr_offset_c : integer := data_width_g/8; |
constant be_width_c : integer := data_width_g/8; |
|
constant hibi_addr_width_c : integer := addr_width_g; |
|
type chan_addr_array is array (n_chans_g-1 downto 0) of std_logic_vector(addr_width_g-1 downto 0); |
type chan_be_array is array (n_chans_g-1 downto 0) of std_logic_vector(be_width_c-1 downto 0); |
type chan_amount_array is array (n_chans_g-1 downto 0) of std_logic_vector(amount_width_g-1 downto 0); |
|
-- registers the CPU will set |
signal mem_addr_r : chan_addr_array; |
signal sender_addr_r : chan_addr_array; |
signal irq_amount_r : chan_amount_array; |
signal control_r : std_logic_vector(control_bits_c-1 downto 0); |
signal tx_mem_addr_r : std_logic_vector(addr_width_g-1 downto 0); |
signal tx_hibi_addr_r : std_logic_vector(hibi_addr_width_c-1 downto 0); |
signal tx_amount_r : std_logic_vector(amount_width_g-1 downto 0); |
signal tx_comm_r : std_logic_vector(4 downto 0); |
|
-- cpu sets, n2h clears |
signal init_chan_r : std_logic_vector(n_chans_g-1 downto 0); |
|
signal irq_chan_r : std_logic_vector(n_chans_g-1 downto 0); |
signal irq_type_r : std_logic; -- 0: rx ready, 1: unknown rx |
|
-- cpu can read |
-- tells where the next data is stored |
signal current_mem_addr_r : chan_addr_array; |
signal current_be_r : chan_be_array; |
signal avalon_be_r : std_logic_vector(be_width_c-1 downto 0); |
|
signal status_r : std_logic_vector(status_bits_c-1 downto 0); |
|
|
-- counter of how many datas gotten (irq nullifies) |
signal irq_counter_r : chan_amount_array; |
signal irq_r : std_logic; |
signal irq_given_r : std_logic_vector(n_chans_g-1 downto 0); |
signal irq_reset_r : std_logic; -- irq was reseted last cycle |
|
|
signal hibi_re_r : std_logic; |
signal avalon_we_r : std_logic; |
|
signal unknown_rx : std_logic; -- high when not expecting this rx |
signal unknown_rx_irq_r : std_logic; |
signal unknown_rx_r : std_logic; |
|
-- high when tx is overriding previous one |
-- (user didn't poll if previous tx is still in progress) |
signal tx_illegal : std_logic; |
signal tx_illegal_r : std_logic; |
signal ignore_tx_write : std_logic; |
signal ignored_last_tx_r : std_logic; |
|
-- calc_chan signals |
signal avalon_addr_r : std_logic_vector(addr_width_g-1 downto 0); |
signal curr_chan_avalon_we_r : std_logic; -- 0 if no channel found |
|
|
component n2h2_rx_chan |
generic ( |
data_width_g : integer := 0; |
hibi_addr_width_g : integer := 0; |
addr_width_g : integer; |
amount_width_g : integer; |
addr_cmp_lo_g : integer; |
addr_cmp_hi_g : integer); |
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
avalon_addr_in : in std_logic_vector(addr_width_g-1 downto 0); |
hibi_addr_in : in std_logic_vector(hibi_addr_width_g-1 downto 0); |
irq_amount_in : in std_logic_vector(amount_width_g-1 downto 0); |
hibi_data_in : in std_logic_vector(hibi_addr_width_g-1 downto 0); |
hibi_av_in : in std_logic; |
hibi_empty_in : in std_logic; |
init_in : in std_logic; |
irq_ack_in : in std_logic; |
avalon_waitreq_in : in std_logic; |
avalon_we_in : in std_logic; |
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0); |
avalon_we_out : out std_logic; |
avalon_be_out : out std_logic_vector(data_width_g/8-1 downto 0); |
addr_match_out : out std_logic; |
addr_match_cmb_out : out std_logic; |
irq_out : out std_logic); |
end component; |
-- signal irq_amount_r : chan_amount_array; |
signal avalon_wes : std_logic_vector(n_chans_g-1 downto 0); |
signal matches : std_logic_vector(n_chans_g-1 downto 0); |
signal matches_cmb : std_logic_vector(n_chans_g-1 downto 0); |
signal irq_ack_r : std_logic_vector(n_chans_g-1 downto 0); |
|
component one_hot_mux |
generic ( |
data_width_g : integer); |
port ( |
data_in : in std_logic_vector(data_width_g-1 downto 0); |
sel_in : in std_logic_vector(data_width_g-1 downto 0); |
data_out : out std_logic); |
end component; |
|
type chan_addr_switched is array (addr_width_g-1 downto 0) of std_logic_vector(n_chans_g-1 downto 0); |
type chan_be_switched is array (be_width_c-1 downto 0) of std_logic_vector(n_chans_g-1 downto 0); |
|
signal avalon_addr_temp : chan_addr_switched; |
signal avalon_be_temp : chan_be_switched; |
|
|
signal avalon_cfg_waitrequest_out_r : std_logic; |
signal avalon_cfg_waitrequest_out_s : std_logic; |
|
signal cfg_write : std_logic; |
signal cfg_reg : integer range (2**conf_bits_c)-1 downto 0; |
|
-- high when tx conf registers (8-11) are being written |
signal cfg_tx_reg_used : std_logic; |
|
|
begin -- rtl |
|
|
----------------------------------------------------------------------------- |
-- Handle waitrequest for config interface |
----------------------------------------------------------------------------- |
|
avalon_cfg_waitrequest_out <= avalon_cfg_waitrequest_out_s; |
|
cfg_write <= avalon_cfg_we_in and avalon_cfg_cs_in; |
|
avalon_cfg_waitrequest_out_s <= ((not avalon_cfg_waitrequest_out_r) |
and avalon_cfg_re_in |
and avalon_cfg_cs_in); |
|
wait_p : process (clk, rst_n) |
begin -- process wait_p |
if rst_n = '0' then -- asynchronous reset (active low) |
avalon_cfg_waitrequest_out_r <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
avalon_cfg_waitrequest_out_r <= avalon_cfg_waitrequest_out_s; |
end if; |
end process wait_p; |
|
----------------------------------------------------------------------------- |
-- Handle txs, dismiss tx if previous one is still in progress |
----------------------------------------------------------------------------- |
|
cfg_reg <= conv_integer(avalon_cfg_addr_in(conf_bits_c-1 downto 0)); |
|
cfg_tx_p: process (cfg_reg) |
begin -- process cfg_tx_p |
case cfg_reg is |
when 8 | 9 | 10 | 11 => cfg_tx_reg_used <= '1'; |
when others => cfg_tx_reg_used <= '0'; |
end case; |
end process cfg_tx_p; |
|
tx_illegal <= (not tx_status_done_in) and cfg_tx_reg_used and cfg_write; |
|
tx_illegal_p: process (clk, rst_n) |
begin -- process tx_illegal_p |
if rst_n = '0' then -- asynchronous reset (active low) |
tx_illegal_r <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
if tx_illegal_r = '0' then |
tx_illegal_r <= tx_illegal; |
elsif tx_illegal_r = '1' and cfg_reg = 4 and cfg_tx_reg_used = '1' |
and cfg_write = '1' |
then |
tx_illegal_r <= '0'; |
elsif cfg_reg = 7 and cfg_write = '1' |
and avalon_cfg_writedata_in(data_width_g-2) = '1' |
then |
tx_illegal_r <= '0'; |
else |
tx_illegal_r <= '1'; |
end if; |
end if; |
end process tx_illegal_p; |
|
ignore_tx_write <= tx_illegal or tx_illegal_r; |
|
----------------------------------------------------------------------------- |
-- Rest of the stuff |
----------------------------------------------------------------------------- |
|
avalon_we_r <= hibi_empty_in nor hibi_av_in; |
avalon_we_out <= avalon_we_r and curr_chan_avalon_we_r; -- and not_dirty_chan_we_r; |
|
-- hibi_re_r <= (not avalon_waitrequest_in) or hibi_av_in; |
hibi_re_r <= not (avalon_waitrequest_in and avalon_we_r |
and curr_chan_avalon_we_r) |
and not (unknown_rx or unknown_rx_irq_r); |
|
unknown_rx <= (not or_reduce(matches_cmb) and |
(hibi_av_in and not hibi_empty_in)); |
|
hibi_re_out <= hibi_re_r and not unknown_rx; |
avalon_writedata_out <= hibi_data_in; |
|
avalon_addr_out <= avalon_addr_r; |
avalon_be_out <= avalon_be_r; |
|
channels : for i in 0 to n_chans_g-1 generate |
|
n2h2_rx_chan_1 : n2h2_rx_chan |
generic map ( |
data_width_g => data_width_g, |
hibi_addr_width_g => hibi_addr_width_c, |
addr_width_g => addr_width_g, |
amount_width_g => amount_width_g, |
addr_cmp_lo_g => hibi_addr_cmp_lo_g, |
addr_cmp_hi_g => hibi_addr_cmp_hi_g) |
port map ( |
clk => clk, |
rst_n => rst_n, |
avalon_addr_in => mem_addr_r(i), |
hibi_addr_in => sender_addr_r(i), |
irq_amount_in => irq_amount_r(i), |
hibi_data_in => hibi_data_in(hibi_addr_width_c-1 downto 0), |
hibi_av_in => hibi_av_in, |
hibi_empty_in => hibi_empty_in, |
init_in => init_chan_r(i), |
irq_ack_in => irq_ack_r(i), |
avalon_waitreq_in => avalon_waitrequest_in, |
avalon_we_in => avalon_we_r, |
avalon_addr_out => current_mem_addr_r(i), |
avalon_we_out => avalon_wes(i), |
avalon_be_out => current_be_r(i), |
addr_match_out => matches(i), |
addr_match_cmb_out => matches_cmb(i), |
irq_out => irq_chan_r(i) |
); |
|
end generate channels; |
|
one_hot_mux_1 : one_hot_mux |
generic map ( |
data_width_g => n_chans_g) |
port map ( |
data_in => avalon_wes, |
sel_in => matches, |
data_out => curr_chan_avalon_we_r |
); |
|
|
ava_temp : for i in 0 to n_chans_g-1 generate |
j : for j in 0 to addr_width_g-1 generate |
avalon_addr_temp(j)(i) <= current_mem_addr_r(i)(j); |
end generate j; |
|
k : for k in 0 to be_width_c-1 generate |
avalon_be_temp(k)(i) <= current_be_r(i)(k); |
end generate k; |
end generate ava_temp; |
|
|
avalon_address : for i in 0 to addr_width_g-1 generate |
one_hot_mux_addr_i : one_hot_mux |
generic map ( |
data_width_g => n_chans_g) |
port map ( |
data_in => avalon_addr_temp(i), |
sel_in => matches, |
data_out => avalon_addr_r(i) |
); |
end generate avalon_address; |
|
|
be : for i in 0 to be_width_c-1 generate |
one_hot_mux_be_i : one_hot_mux |
generic map ( |
data_width_g => n_chans_g) |
port map ( |
data_in => avalon_be_temp(i), |
sel_in => matches, |
data_out => avalon_be_r(i) |
); |
end generate be; |
|
|
cpu_side : process (clk, rst_n) |
variable legal_write : std_logic; |
variable legal_read : std_logic; |
variable n_chan : integer range n_chans_g-1 downto 0; |
variable n_dest : integer range (2**conf_bits_c)-1 downto 0; |
begin -- process cpu |
if rst_n = '0' then -- asynchronous reset (active low) |
for i in n_chans_g-1 downto 0 loop |
mem_addr_r(i) <= (others => '0'); |
sender_addr_r(i) <= (others => '0'); |
irq_amount_r(i) <= (others => '1'); |
end loop; -- i |
avalon_cfg_readdata_out <= (others => '0'); |
init_chan_r <= (others => '0'); |
control_r <= (others => '0'); |
-- status for only rx signals.. |
status_r(1) <= '0'; |
-- status_r(1) <= '0'; |
-- status_r <= (others => '0'); |
-- irq_chan_r <= (others => '0'); |
tx_mem_addr_r <= (others => '0'); |
tx_comm_r <= (others => '0'); |
tx_amount_r <= (others => '0'); |
rx_irq_out <= '0'; |
irq_reset_r <= '0'; |
unknown_rx_irq_r <= '0'; |
unknown_rx_r <= '0'; |
ignored_last_tx_r <= '0'; |
|
elsif clk'event and clk = '1' then -- rising clock edge |
|
unknown_rx_r <= unknown_rx; |
|
if unknown_rx = '1' and unknown_rx_r = '0' then |
unknown_rx_irq_r <= '1'; |
end if; |
|
|
-- set the IRQ. may be changed below if some IRQ |
-- is cleared and others are pending. |
if unknown_rx_irq_r = '1' or ignored_last_tx_r = '1' or |
(irq_chan_r /= 0 and irq_reset_r = '0') then |
-- irq ena bit... |
rx_irq_out <= control_r(1); |
end if; |
|
irq_reset_r <= '0'; -- default |
|
control_r(0) <= '0'; |
-- nullifies the tx start after CPU has set it |
-- otherwise CPU can't keep up with N2H2 with small transfers |
|
irq_ack_r <= (others => '0'); |
|
legal_write := avalon_cfg_cs_in and avalon_cfg_we_in; |
legal_read := avalon_cfg_cs_in and avalon_cfg_re_in; |
n_chan := conv_integer(avalon_cfg_addr_in(n_chans_bits_g+conf_bits_c-1 downto conf_bits_c)); |
n_dest := conv_integer(avalon_cfg_addr_in(conf_bits_c-1 downto 0)); |
|
if legal_write = '1' then |
case n_dest is |
when 0 => -- mem_addr |
mem_addr_r(n_chan) <= avalon_cfg_writedata_in; |
when 1 => -- sender addr |
sender_addr_r(n_chan) <= avalon_cfg_writedata_in; |
when 2 => -- irq_amount |
irq_amount_r(n_chan) <= |
avalon_cfg_writedata_in(amount_width_g-1 downto 0); |
-- 3 is unwritable, curr addr ptr |
when 4 => -- control |
if ignore_tx_write = '0' then |
control_r <= avalon_cfg_writedata_in(control_bits_c-1 downto 0); |
end if; |
|
-- remember wether a tx gets lost or not |
if ignore_tx_write = '1' then |
ignored_last_tx_r <= '1'; |
else |
ignored_last_tx_r <= ignored_last_tx_r; |
end if; |
|
when 5 => -- init channel |
init_chan_r <= avalon_cfg_writedata_in(n_chans_g-1 downto 0); |
when 7 => -- IRQ chan |
|
-- goes down so that generates an edge |
-- when many interrupts are pending. |
rx_irq_out <= '0'; |
irq_reset_r <= '1'; |
|
irq_ack_r <= avalon_cfg_writedata_in(n_chans_g-1 downto 0); |
|
if avalon_cfg_writedata_in(data_width_g-1) = '1' then |
unknown_rx_irq_r <= '0'; |
end if; |
|
if avalon_cfg_writedata_in(data_width_g-2) = '1' then |
ignored_last_tx_r <= '0'; |
end if; |
|
|
-- NOW TX SIGNALS |
when 8 => |
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then |
tx_mem_addr_r <= avalon_cfg_writedata_in; |
end if; |
when 9 => |
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then |
tx_amount_r <= avalon_cfg_writedata_in(amount_width_g-1 downto 0); |
end if; |
when 10 => |
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then |
tx_comm_r <= avalon_cfg_writedata_in(4 downto 0); |
end if; |
when 11 => |
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then |
tx_hibi_addr_r <= avalon_cfg_writedata_in; |
end if; |
when others => |
|
-- do nothing |
|
end case; |
end if; |
|
if legal_read = '1' then |
case n_dest is |
when 0 => -- mem_addr |
avalon_cfg_readdata_out <= mem_addr_r(n_chan); |
when 1 => -- sender addr |
avalon_cfg_readdata_out <= sender_addr_r(n_chan); |
when 2 => -- irq amount |
avalon_cfg_readdata_out(addr_width_g-1 downto amount_width_g) <= (others => '0'); |
avalon_cfg_readdata_out(amount_width_g-1 downto 0) <= irq_amount_r(n_chan); |
when 3 => -- current addr ptr |
avalon_cfg_readdata_out <= current_mem_addr_r(n_chan); |
when 4 => -- control and status regs |
avalon_cfg_readdata_out(15 downto control_bits_c) <= (others => '0'); |
avalon_cfg_readdata_out(control_bits_c-1 downto 0) <= control_r; |
avalon_cfg_readdata_out(31 downto status_bits_c+15) <= (others => '0'); |
avalon_cfg_readdata_out(status_bits_c+15 downto 16) <= status_r; |
when 5 => -- Init Channel |
avalon_cfg_readdata_out(addr_width_g-1 downto n_chans_g) <= (others => '0'); |
avalon_cfg_readdata_out(n_chans_g-1 downto 0) <= init_chan_r; |
-- 6 is reserved |
when 7 => -- IRQ chan |
avalon_cfg_readdata_out(addr_width_g-1) <= unknown_rx_irq_r; |
avalon_cfg_readdata_out(addr_width_g-2) <= ignored_last_tx_r; |
avalon_cfg_readdata_out(addr_width_g-3 downto n_chans_g) <= (others => '0'); |
avalon_cfg_readdata_out(n_chans_g-1 downto 0) <= irq_chan_r; |
|
when 12 => |
|
avalon_cfg_readdata_out(31 downto 0) <= hibi_data_in; |
|
when others => |
-- do nothing; |
end case; |
end if; |
|
-- status reg |
--status_r <= status_r; |
-- busy bit |
status_r(1) <= avalon_we_r; |
|
if init_chan_r /= conv_std_logic_vector(0, n_chans_g) then |
init_chan_r <= (others => '0'); |
end if; |
|
-- -- irq req |
-- if irq_r = '1' then |
-- irq_chan_r(curr_chan_r) <= '1'; |
-- end if; |
|
|
end if; |
end process cpu_side; |
|
|
|
|
-- tx signals |
-- done bit, start tx |
status_r(0) <= tx_status_done_in; |
tx_amount_out <= tx_amount_r; |
tx_mem_addr_out <= tx_mem_addr_r; |
tx_comm_out <= tx_comm_r; |
tx_hibi_addr_out <= tx_hibi_addr_r; |
|
tx_start : process (clk, rst_n) |
variable was_high_r : std_logic; |
begin -- process sel_tx_start |
if rst_n = '0' then -- asynchronous reset (active low) |
was_high_r := '0'; |
tx_start_out <= '0'; |
|
elsif clk'event and clk = '1' then -- rising clock edge |
if control_r(0) = '1' then |
if was_high_r = '0' then |
was_high_r := '1'; |
tx_start_out <= '1'; |
else |
was_high_r := '1'; |
tx_start_out <= '0'; |
end if; |
else |
was_high_r := '0'; |
tx_start_out <= '0'; |
end if; |
end if; |
end process tx_start; |
|
end rtl; |
|
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Index: TUT/ip.hwp.communication/n2h2/tb/tbrx_conf_hibisend.dat
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+0 70 12
+0 80 12
Index: TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_str.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_str.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_str.do (revision 16)
@@ -0,0 +1,22 @@
+
+quit -sim
+
+vlib work
+
+# HW files
+
+vcom -check_synthesis -pedantic ../vhd/one_hot_mux.vhd
+vcom -check_synthesis -pedantic ../vhd/step_counter2.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_chan.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_channels.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_tx_vl.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_chan.vhd
+
+
+# TB files
+
+vcom ./blocks/sram_scalable_v3.vhd
+vcom ./blocks/tb_n2h2_tx_str.vhd
+
+vsim -t 1ns work.tb_n2h2_tx
+do blocks/wave_tb_n2h2_tx_str.do
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/support.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/support.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/support.h (revision 16)
@@ -0,0 +1,50 @@
+/*
+ *
+ * Author : Lasse Lehtonen
+ * Last modification : 29.03.2011
+ *
+ * N2H support functions
+ *
+ */
+
+/* NB
+ *
+ * Remember to modify below
+ * #define N2H2_CHAN_BASE
+ * #define N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID
+ * #define N2H2_CHAN_IRQ
+ *
+ */
+
+#ifndef SUPPORT_H
+#define SUPPORT_H
+
+#include "n2h_isr_fifo.h"
+#include "system.h"
+#include "N2H_registers_and_macros.h"
+#include "tut_n2h_regs.h"
+
+
+#define N2H2_CHAN_BASE N2H2_CHAN_1_BASE
+#define N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID N2H2_CHAN_1_IRQ_INTERRUPT_CONTROLLER_ID
+#define N2H2_CHAN_IRQ N2H2_CHAN_1_IRQ
+
+
+/* where to read how much target address */
+void n2h_send(int data_src_addr, int amount, int hibi_addr);
+
+/* which channel where to store, amount address to match*/
+void n2h_init_rx(int rx_channel, int rx_addr, int rx_amount, int hibi_addr);
+
+/* Returns the position of the first occurrence of '1' from LSB (rigth)*/
+int onehot2int(int num);
+
+/* ISR handler*/
+void n2h2_isr(void* context);
+
+/* Init interrupt service */
+void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo);
+
+
+#endif
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/tut_n2h_regs.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/tut_n2h_regs.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/tut_n2h_regs.c (revision 16)
@@ -0,0 +1,179 @@
+#include "tut_n2h_regs.h"
+#include "N2H_registers_and_macros.h"
+
+
+#if defined(API)
+struct Channel_reservation {
+
+ int mem_addr;
+ int amount;
+
+};
+
+static struct Channel_reservation
+ channel_reservations[N2H_NUMBER_OF_CHANNELS] = {};
+
+
+// Common interrupt service routine. Clear IRQ and call N2H_RX_DONE.
+void isr() {
+
+ int chan = N2H_GET_IRQ_CHAN(N2H_REGISTERS_BASE_ADDRESS);
+ N2H_RX_DONE( chan, channel_reservations[chan].mem_addr, channel_reservations[chan].amount );
+ channel_reservations[chan].mem_addr = 0;
+ channel_reservations[chan].amount = 0;
+ N2H_RX_CLEAR_IRQ(chan,N2H_REGISTERS_BASE_ADDRESS);
+}
+
+
+
+// eCos specific interrupt handling
+#if defined(ECOS)
+#include
+#include
+#include
+
+static cyg_interrupt l_rxIrq;
+static cyg_handle_t l_rxIrqHandle;
+extern void cyg_interrupt_post_dsr(CYG_ADDRWORD intr_handle);
+
+cyg_uint32 RxIrqIsr(cyg_vector_t vector, cyg_addrword_t data) {
+ cyg_interrupt_mask(vector);
+ cyg_interrupt_post_dsr(l_rxIrqHandle);
+ return (CYG_ISR_HANDLED);
+}
+
+void RxIrqDsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
+ isr();
+ cyg_interrupt_unmask(vector);
+
+}
+
+
+// NIOSII specific interrupt handling
+#else
+void n2h_isr( void* context, int id ) {
+ isr();
+}
+#endif
+
+void N2H_INIT_ISR() {
+
+// eCos specific interrupt init
+#if defined(ECOS)
+ cyg_interrupt_create(
+ N2H_RX_IRQ,
+ N2H_RX_IRQ_PRI,
+ 0,
+ &RxIrqIsr,
+ &RxIrqDsr,
+ &l_rxIrqHandle,
+ &l_rxIrq);
+ cyg_interrupt_attach(l_rxIrqHandle);
+ cyg_interrupt_unmask(N2H_RX_IRQ);
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+
+// NIOSII specific interrupt init
+#else
+ alt_irq_register( N2H_RX_IRQ, 0, n2h_isr );
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+#endif
+}
+
+void N2H_GET_RX_BUFFER( int* dst, int src, int amount ) {
+
+ // TODO: check that src is inside RX buffer
+ // TODO: if src and dst are same, do nothing
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *(dst + i) = *((int*)src + i);
+ }
+}
+
+void N2H_PUT_TX_BUFFER( int dst, int* src, int amount ) {
+
+ // TODO: check that dst is inside TX buffer
+ // TODO: if src and dst are same, do nothing
+
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *((int*)dst + i) = *(src + i);
+ }
+
+}
+#endif // API
+
+/*
+* DMA engine configuration functions (Updated on 27/04/2005)
+*/
+
+// Prepare channel for receiving data.
+void N2H_CHAN_CONF(int channel, int dst_mem_addr, int rx_haddr, int amount,
+ int* base)
+{
+#ifdef API
+ channel_reservations[channel].mem_addr = dst_mem_addr;
+ channel_reservations[channel].amount = amount;
+#endif
+ N2H_CHAN_MEM_ADDR(channel, dst_mem_addr, base);
+ N2H_CHAN_HIBI_ADDR(channel, rx_haddr, base);
+ N2H_CHAN_AMOUNT(channel, amount, base);
+ N2H_CHAN_INIT(channel, base);
+}
+
+void N2H_SEND(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE(base);
+ N2H_TX_START(base);
+}
+
+// Parameter types were uint32. Int works in other places, so why not here?
+void N2H_SEND_READ(int mem_addr, int amount, int haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(haddr, base);
+ N2H_TX_COMM_READ(base);
+ N2H_TX_START(base);
+}
+
+void N2H_SEND_MSG(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE_MSG(base);
+ N2H_TX_START(base);
+}
+
+// Return 0 if transmission is not done yet, 1 otherwise.
+int N2H_TX_DONE(int* base) {
+ int y = 0;
+ N2H_GET_TX_DONE(y, base);
+ return y;
+}
+
+void N2H_CLEAR_IRQ(int chan, int* base) {
+ N2H_RX_CLEAR_IRQ(chan, base);
+}
+
+// Returns first channel number which has IRQ flag up.
+// If no interrupts have been received -1 is returned.
+int N2H_GET_IRQ_CHAN(int* base)
+{
+ volatile int * apu = base + 7;
+ int irq_reg = *apu;
+ int mask = 1;
+ int shift = 0;
+ for (shift = 0; shift < 32; shift++) {
+ if ((irq_reg & (mask << shift)) != 0) {
+ return shift;
+ }
+ }
+ return -1;
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/main.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/main.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/main.c (revision 16)
@@ -0,0 +1,268 @@
+/*
+ * main.c
+ *
+ * Created on: 22.2.2011
+ * Author: lehton87
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "system.h"
+#include "N2H_registers_and_macros.h"
+#include "tut_n2h_regs.h"
+#include "n2h_isr_fifo.h"
+
+#include "support.h"
+
+
+int main()
+{
+ int n_received = 0;
+ int rx_data[20];
+ int rx_amount = 8;
+ int tx_amount = 8;
+ int send = 0;
+
+ int channels[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+ N2H_isr_fifo* n2h_isr_fifo = n2h_isr_fifo_create();
+
+ // Init N2H interrupt
+ n2h_isr_init(n2h_isr_fifo);
+
+ int tx_data1[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
+ int tx_data2[] = {0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18};
+ int tx_data3[] = {0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28};
+ int tx_data4[] = {0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38};
+
+ usleep(20);
+
+ printf("CPU1: starts\n");
+
+ memcpy((int*)N2H_REGISTERS_TX_BUFFER_START, (int*)tx_data1,
+ tx_amount*sizeof(int));
+
+ memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START + tx_amount*sizeof(int)),
+ (int*)tx_data2, tx_amount*sizeof(int));
+
+ memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START + 2*tx_amount*sizeof(int)),
+ (int*)tx_data3, tx_amount*sizeof(int));
+
+ memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START + 3*tx_amount*sizeof(int)),
+ (int*)tx_data4, tx_amount*sizeof(int));
+
+
+ //
+ // Add/remove some these sends if you want more/less traffic
+ //
+
+ // poll until tx is empty and then send
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {/* idle */}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START, tx_amount, 0x001);
+
+ /*
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START, tx_amount, 0x401);
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START + tx_amount*sizeof(int),
+ tx_amount, 0x000);
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START + tx_amount*sizeof(int),
+ tx_amount, 0x400);
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START + 2*tx_amount*sizeof(int),
+ tx_amount, 0x002);
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START + 2*tx_amount*sizeof(int),
+ tx_amount, 0x402);
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START + 3*tx_amount*sizeof(int),
+ tx_amount, 0x003);
+
+ while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START + 3*tx_amount*sizeof(int),
+ tx_amount, 0x403);
+ */
+
+ //
+
+ while(1)
+ {
+ if(n2h_isr_fifo_size(n2h_isr_fifo))
+ {
+ N2H_isr_info* info = n2h_isr_fifo_pop(n2h_isr_fifo);
+
+ switch(info->isr_type)
+ {
+ case RX_READY:
+
+ printf("CPU1: received %ith packet to channel %i\n",
+ ++n_received, info->rx_channel);
+
+
+ if(channels[info->rx_channel] == 2)
+ {
+ channels[info->rx_channel] = 0;
+ break;
+ }
+
+ memcpy((int*)rx_data, (int*)(N2H_REGISTERS_RX_BUFFER_START +
+ info->rx_channel * rx_amount*
+ sizeof(int)),
+ rx_amount*sizeof(int));
+
+ printf("CPU1: read data from channel %i : %X %X %X %X %X "
+ "%X %X %X\n",
+ info->rx_channel, rx_data[0], rx_data[1], rx_data[2],
+ rx_data[3], rx_data[4], rx_data[5], rx_data[6],
+ rx_data[7]);
+
+ channels[info->rx_channel] = 0;
+
+ // Init rx chan half the time
+ int src = (rand() % 2 == 0) ? 0x00 : 0x20;
+ if(rand() % 2 == 0)
+ {
+ int i = 0;
+
+ for(i = 0; i < 5; ++i)
+ {
+ if(channels[i] == 0)
+ {
+ channels[i] = 1;
+ n2h_init_rx(i, 8*i*sizeof(int), 8, 0x200 + i + src);
+ break;
+ }
+ }
+ }
+
+ send++;
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+
+ break;
+
+ case RX_UNKNOWN:
+ {
+ int cha = 0;
+
+ for(cha = 0; cha < 8; ++cha)
+ {
+ if(channels[cha] == 0)
+ {
+ channels[cha] = (info->dst_address == 0x3FF) ? 2 : 1;
+
+ printf("CPU1: received data to unconfigured "
+ "address 0x%X, assigning to channel %i\n",
+ info->dst_address, cha);
+
+ if(!(0x200 <= info->dst_address &&
+ info->dst_address <= 0x3FF))
+ {
+ printf("CPU1: %i is invalid address, FAILURE\n",
+ info->dst_address);
+ }
+
+ // Initialize some channel to receive
+ n2h_init_rx(cha, cha * rx_amount*sizeof(int), rx_amount,
+ info->dst_address);
+
+ break;
+ }
+ }
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+
+ }
+ break;
+
+ case TX_IGNORED:
+ {
+ printf("CPU1: A transfer was ignored because it overlapped"
+ " previous one\n");
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+ }
+ break;
+
+ }
+
+ // Free memory
+ free(info); info = NULL;
+ }
+ else if(send > 0 && (((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 1))
+ {
+ // Send packet to a random target's random address
+ int target_addr;
+ int tx_data[8];
+ int tx_slot = (rand() % 8);
+ int cha;
+
+ if(rand() % 2 == 0)
+ {
+ target_addr = 0x010 + tx_slot;
+ }
+ else
+ {
+ target_addr = 0x410 + tx_slot;
+ }
+
+ for(cha = 0; cha < 8; ++cha)
+ tx_data[cha] = 0x81000000 | ((cha+1) << 16) | target_addr;
+
+ memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int)),
+ (int*)tx_data, tx_amount*sizeof(int));
+
+ printf("CPU1: sending packet to 0x%X\n", target_addr);
+
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int),
+ tx_amount, target_addr);
+
+ send--;
+
+
+ // Overlapping with previous one hopefully
+ if((rand() % 100) < 50)
+ {
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int),
+ tx_amount, 0x5FF);
+ printf("CPU1: sending hazard packet\n");
+ }
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+ }
+ }
+
+ //
+
+ printf("CPU1: retires!\n");
+ while(1); return 0;
+}
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/n2h_isr_fifo.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/n2h_isr_fifo.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/n2h_isr_fifo.c (revision 16)
@@ -0,0 +1,77 @@
+/*
+ *
+ * Fifo for saving interrupt information, implementation
+ *
+ * Lasse Lehtonen
+ *
+ */
+
+
+
+#include "n2h_isr_fifo.h"
+
+#include
+#include
+
+
+// Store item to last place, called only from ISR
+void n2h_isr_fifo_push(N2H_isr_fifo* fifo, N2H_isr_info* item)
+{
+ N2H_isr_info* temp = fifo->root;
+
+ item->next = NULL;
+
+ while(temp != NULL && temp->next != NULL)
+ {
+ temp = temp->next;
+ }
+
+ if(fifo->size < 1)
+ {
+ fifo->root = item;
+ }
+ else
+ {
+ temp->next = item;
+ }
+
+ fifo->size++;
+}
+
+// Returns the first item, remember to free its memory!
+N2H_isr_info* n2h_isr_fifo_pop (N2H_isr_fifo* fifo)
+{
+ N2H_isr_info* temp;
+
+ if(fifo->size < 1)
+ {
+ return NULL;
+ }
+
+ // Prevent ISR from messing with fifo
+ alt_irq_context cntx = alt_irq_disable_all();
+ {
+ temp = fifo->root;
+ fifo->root = temp->next;
+ fifo->size--;
+ }
+ alt_irq_enable_all(cntx);
+
+ temp->next = NULL;
+ return temp;
+}
+
+int n2h_isr_fifo_size(N2H_isr_fifo* fifo)
+{
+ return fifo->size;
+}
+
+N2H_isr_fifo* n2h_isr_fifo_create()
+{
+ //Allocate space for new and initialize data
+ N2H_isr_fifo* fifo = (N2H_isr_fifo*) malloc(sizeof(N2H_isr_fifo));
+ fifo->root = NULL;
+ fifo->size = 0;
+ return fifo;
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/tut_n2h_regs.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/tut_n2h_regs.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/tut_n2h_regs.h (revision 16)
@@ -0,0 +1,209 @@
+/*
+* History:
+* 10/08/2005 by ollil
+* + Copied minor modifications implemented by Ari.
+* This fixed a crash bug in DCT HW based system
+* 03/10/2008 by tapiok
+* fixed N2H_RX_IRQ_DIS
+* 08/2009 kojo2
+* Added following functions: N2H_INIT_ISR, N2H_RX_DONE,
+* N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER
+*/
+#ifndef __tut_n2h_regs_h_
+#define __tut_n2h_regs_h_
+
+#ifdef NIOS_II
+#include "io.h"
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)
+#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)
+#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))
+#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 | (IORD(base,4))))
+#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))
+#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)
+#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)
+#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)
+#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)
+#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)
+#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)
+#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)
+#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)
+#define N2H_TX_COMM_READ(base) IOWR(base,10,4)
+#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)
+#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)
+#define N2H_TX_START(base) IOWR(base, 4, (0x1 | (IORD(base,4))))
+#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)
+#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))
+#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))
+
+
+#else
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 1; \
+ *apu=hibi_addr; \
+ }
+
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4); \
+ *apu=addr; \
+ }
+
+#define N2H_CHAN_AMOUNT(chan, amount, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 2; \
+ *apu=amount; \
+ }
+
+#define N2H_CHAN_INIT(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ *apu=1 << (chan); \
+ }
+
+#define N2H_RX_IRQ_ENA(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu | 0x2; \
+ }
+
+#define N2H_RX_IRQ_DIS(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu & 0xfffffffd; \
+ }
+
+#define N2H_GET_STAT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu >> 16; \
+ }
+
+#define N2H_GET_CONF_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu & 0x0000ffff; \
+ }
+
+#define N2H_GET_INIT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ var = *apu; \
+ }
+
+#define N2H_GET_IRQ_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ var = *apu; \
+ }
+
+#define N2H_GET_CURR_PTR(var, chan, base) \
+ { \
+ volatile int * apu = (int*)base + 3; \
+ apu = apu + ((chan) << 4); \
+ var = *apu; \
+ }
+
+#define N2H_TX_MEM_ADDR(addr, base) \
+ { \
+ volatile int * apu = (int*)base + 8; \
+ *apu = addr; \
+ }
+
+#define N2H_TX_AMOUNT(amount, base) \
+ { \
+ volatile int * apu = (int*)base + 9; \
+ *apu = amount; \
+ }
+
+#define N2H_TX_HIBI_ADDR(haddr, base) \
+ { \
+ volatile int * apu = (int*)base + 11; \
+ *apu = haddr; \
+ }
+
+#define N2H_TX_COMM(comm, base) \
+ { \
+ volatile int * apu = (int*)base +10; \
+ *apu = comm; \
+ }
+
+#define N2H_TX_COMM_WRITE(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 2; \
+ }
+
+#define N2H_TX_COMM_READ(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 4; \
+ }
+
+#define N2H_TX_COMM_WRITE_MSG(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 3; \
+ }
+
+#define N2H_TX_START(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu = *apu | 0x1; \
+ *apu = *apu & 0xfffffffe; \
+ }
+#define N2H_GET_TX_DONE(y, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ y = *apu >> 16; \
+ y = y & 0x1; \
+ }
+
+#define N2H_RX_CLEAR_IRQ(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ *apu = 1 << (chan); \
+ }
+
+
+
+#endif
+
+
+#ifdef API
+extern void N2H_INIT_ISR();
+extern void N2H_RX_DONE( int chan, int mem_addr, int amount );
+extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );
+extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );
+#endif
+
+
+/*
+* DMA engine configuration
+*/
+
+extern void N2H_CHAN_CONF( int channel,
+ int mem_addr,
+ int rx_addr,
+ int amount,
+ int* base );
+
+extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);
+
+extern int N2H_TX_DONE(int* base);
+
+extern void N2H_CLEAR_IRQ(int chan, int* base);
+
+extern int N2H_GET_IRQ_CHAN(int* base);
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/N2H_registers_and_macros.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/N2H_registers_and_macros.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/N2H_registers_and_macros.h (revision 16)
@@ -0,0 +1,47 @@
+// *****************************************************************************
+// File : N2H_registers_and_macros.h
+// Author : Tero Arpinen
+// Date : 22.12.2004
+// Decription : This file contains customizable register address
+// definitions
+// for N2H interface and some needed macros
+//
+// Version history : 22.12.2004 tar Original version
+// : 06.07.2005 tar Modified to work with N2H2
+// : 02.10.2009 tko Removed unneeded macros
+// *****************************************************************************
+
+#ifndef N2H_REGISTERS_AND_MACROS_H
+#define N2H_REGISTERS_AND_MACROS_H
+
+// DEFINE FOLLOWING REGISTERS ACCORDING TO NIOS OR NIOS II HARDWARE
+// CONFIGURATION
+
+// N2H2 Avalon slave base address
+#define N2H_REGISTERS_BASE_ADDRESS ((void*) N2H2_CHAN_1_BASE)
+
+// Buffer start address in cpu's memory
+#define N2H_REGISTERS_BUFFER_START (SHARED_MEM_1_BASE)
+
+// Writeable registers
+// set bit 31 to 1 so that writes and reads bypass cache
+#define N2H_REGISTERS_TX_BUFFER_START (0x80000000 | SHARED_MEM_1_BASE)
+
+#define N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH (0x00000400)
+#define N2H_REGISTERS_TX_BUFFER_END (N2H_REGISTERS_TX_BUFFER_START + \
+ N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH - 1)
+
+// Readable registers
+#define N2H_REGISTERS_RX_BUFFER_START (N2H_REGISTERS_TX_BUFFER_START + N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH)
+#define N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH (0x00000C00)
+#define N2H_REGISTERS_RX_BUFFER_END (N2H_REGISTERS_RX_BUFFER_START + \
+ N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH \
+ - 1)
+// N2H Interrupt registers, numbers and priorities
+#define N2H_RX_IRQ (2)
+#define N2H_RX_IRQ_PRI (3)
+
+// N2H Channels
+#define N2H_NUMBER_OF_CHANNELS (8)
+
+#endif // N2H_REGISTERS_AND_MACROS_H
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/support.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/support.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/support.c (revision 16)
@@ -0,0 +1,137 @@
+/*
+ *
+ * Author : Lasse Lehtonen
+ * Last modification : 29.03.2011
+ *
+ * N2H support functions
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "support.h"
+
+
+void n2h_send(int data_src_addr, int amount, int hibi_addr)
+{
+ // Poll N2H, until it's not sending previous tx anymore
+ //while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) { }
+ // Set data source address
+ IOWR(N2H2_CHAN_BASE, 8, data_src_addr);
+ // Set amount to send
+ IOWR(N2H2_CHAN_BASE, 9, amount);
+ // Set target hibi command
+ IOWR(N2H2_CHAN_BASE, 10, 2);
+ // Set target hibi address
+ IOWR(N2H2_CHAN_BASE, 11, hibi_addr);
+ // Start the transfer
+ IOWR(N2H2_CHAN_BASE, 4, (0x1 | (IORD(N2H2_CHAN_BASE,4))));
+}
+
+
+void n2h_init_rx(int rx_channel, int rx_addr, int rx_amount, int hibi_addr)
+{
+ // Set receive mem address for incoming data
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4), N2H_REGISTERS_RX_BUFFER_START +
+ rx_addr);
+ // Set amount to receive
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4) + 2, rx_amount);
+ // Set hibi address to receive data
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4) + 1, hibi_addr);
+ // Initialize receiving
+ IOWR(N2H2_CHAN_BASE, 5 , 1 << rx_channel);
+}
+
+
+
+int onehot2int(int num)
+{
+ int i = 0;
+ for(; i < 31; ++i)
+ {
+ if(num & (1 << i))
+ {
+ return i;
+ }
+ }
+ return -1;
+}
+
+
+void n2h2_isr(void* context)
+{
+ N2H_isr_fifo* fifo = (N2H_isr_fifo*) context;
+
+ // Read the cause of the interrupt
+ int interrupter = IORD(N2H2_CHAN_BASE, 7);
+
+
+ if((0x80000000 & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = RX_UNKNOWN;
+
+ // Read in incoming hibi address
+ info->dst_address = IORD(N2H2_CHAN_BASE, 12);
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, 0x80000000);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+
+ if((0x40000000 & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = TX_IGNORED;
+
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, 0x40000000);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+
+ while((0x3FFFFFFF & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = RX_READY;
+
+ // Store interrupted channel
+ info->rx_channel = onehot2int(interrupter);
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, (1 << info->rx_channel));
+
+ interrupter = interrupter & ~(1 << info->rx_channel);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+}
+
+
+// Init interrupt
+void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo)
+{
+ // Register N2H2 ISR
+ if(alt_ic_isr_register(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID,
+ N2H2_CHAN_IRQ, n2h2_isr, (void*)n2h_isr_fifo, 0)
+ != 0)
+ {
+ printf("CPU0: registering n2h2_isr failed!\n");
+ }
+ // Enable interrupt on CPU side
+ if(alt_ic_irq_enable(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID,
+ N2H2_CHAN_IRQ) != 0)
+ {
+ printf("CPU0: enabling n2h2 interrupt failed!\n");
+ }
+ // Enable interrupts on N2H2 side
+ IOWR(N2H2_CHAN_BASE, 4, (2 | (IORD(N2H2_CHAN_BASE,4))));
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/n2h_isr_fifo.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/n2h_isr_fifo.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu1/n2h_isr_fifo.h (revision 16)
@@ -0,0 +1,44 @@
+/*
+ *
+ * Fifo for saving interrupt information, header
+ *
+ * Lasse Lehtonen
+ *
+ */
+
+#ifndef N2H_ISR_FIFO_HH
+#define N2H_ISR_FIFO_HH
+
+// Tells what caused N2H2 to interrupt
+typedef enum {RX_READY, RX_UNKNOWN, TX_IGNORED} N2H_isr_type;
+
+
+// Item stored in fifo
+typedef struct N2H_isr_info N2H_isr_info;
+typedef struct N2H_isr_info
+{
+ N2H_isr_type isr_type;
+ union {
+ int rx_channel;
+ int dst_address;
+ };
+
+ N2H_isr_info* next;
+};
+
+
+typedef struct
+{
+ N2H_isr_info* root;
+ volatile int size;
+
+} N2H_isr_fifo;
+
+// used fifo item to store
+void n2h_isr_fifo_push(N2H_isr_fifo* fifo, N2H_isr_info* item);
+N2H_isr_info* n2h_isr_fifo_pop(N2H_isr_fifo* fifo);
+int n2h_isr_fifo_size(N2H_isr_fifo* fifo);
+// Creates new fifo
+N2H_isr_fifo* n2h_isr_fifo_create();
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/support.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/support.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/support.h (revision 16)
@@ -0,0 +1,48 @@
+/*
+ *
+ * Author : Lasse Lehtonen
+ * Last modification : 29.03.2011
+ *
+ * N2H support functions
+ *
+ */
+
+/* NB
+ *
+ * Remember to #define N2H2_CHAN_BASE as N2H's base address
+ * Also #define N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID and
+ * #define N2H2_CHAN_IRQ
+ *
+ */
+
+#ifndef SUPPORT_H
+#define SUPPORT_H
+
+#include "n2h_isr_fifo.h"
+#include "system.h"
+#include "N2H_registers_and_macros.h"
+#include "tut_n2h_regs.h"
+
+#define N2H2_CHAN_BASE N2H2_CHAN_2_BASE
+#define N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID N2H2_CHAN_2_IRQ_INTERRUPT_CONTROLLER_ID
+#define N2H2_CHAN_IRQ N2H2_CHAN_2_IRQ
+
+
+/* where to read how much target address */
+void n2h_send(int data_src_addr, int amount, int hibi_addr);
+
+/* which channel where to store, amount address to match*/
+void n2h_init_rx(int rx_channel, int rx_addr, int rx_amount, int hibi_addr);
+
+/* Returns the position of the first occurrence of '1' from LSB (rigth)*/
+int onehot2int(int num);
+
+/* ISR handler */
+void n2h2_isr(void* context);
+
+/* Init interrupt service */
+void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo);
+
+
+#endif
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/tut_n2h_regs.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/tut_n2h_regs.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/tut_n2h_regs.c (revision 16)
@@ -0,0 +1,179 @@
+#include "tut_n2h_regs.h"
+#include "N2H_registers_and_macros.h"
+
+
+#if defined(API)
+struct Channel_reservation {
+
+ int mem_addr;
+ int amount;
+
+};
+
+static struct Channel_reservation
+ channel_reservations[N2H_NUMBER_OF_CHANNELS] = {};
+
+
+// Common interrupt service routine. Clear IRQ and call N2H_RX_DONE.
+void isr() {
+
+ int chan = N2H_GET_IRQ_CHAN(N2H_REGISTERS_BASE_ADDRESS);
+ N2H_RX_DONE( chan, channel_reservations[chan].mem_addr, channel_reservations[chan].amount );
+ channel_reservations[chan].mem_addr = 0;
+ channel_reservations[chan].amount = 0;
+ N2H_RX_CLEAR_IRQ(chan,N2H_REGISTERS_BASE_ADDRESS);
+}
+
+
+
+// eCos specific interrupt handling
+#if defined(ECOS)
+#include
+#include
+#include
+
+static cyg_interrupt l_rxIrq;
+static cyg_handle_t l_rxIrqHandle;
+extern void cyg_interrupt_post_dsr(CYG_ADDRWORD intr_handle);
+
+cyg_uint32 RxIrqIsr(cyg_vector_t vector, cyg_addrword_t data) {
+ cyg_interrupt_mask(vector);
+ cyg_interrupt_post_dsr(l_rxIrqHandle);
+ return (CYG_ISR_HANDLED);
+}
+
+void RxIrqDsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
+ isr();
+ cyg_interrupt_unmask(vector);
+
+}
+
+
+// NIOSII specific interrupt handling
+#else
+void n2h_isr( void* context, int id ) {
+ isr();
+}
+#endif
+
+void N2H_INIT_ISR() {
+
+// eCos specific interrupt init
+#if defined(ECOS)
+ cyg_interrupt_create(
+ N2H_RX_IRQ,
+ N2H_RX_IRQ_PRI,
+ 0,
+ &RxIrqIsr,
+ &RxIrqDsr,
+ &l_rxIrqHandle,
+ &l_rxIrq);
+ cyg_interrupt_attach(l_rxIrqHandle);
+ cyg_interrupt_unmask(N2H_RX_IRQ);
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+
+// NIOSII specific interrupt init
+#else
+ alt_irq_register( N2H_RX_IRQ, 0, n2h_isr );
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+#endif
+}
+
+void N2H_GET_RX_BUFFER( int* dst, int src, int amount ) {
+
+ // TODO: check that src is inside RX buffer
+ // TODO: if src and dst are same, do nothing
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *(dst + i) = *((int*)src + i);
+ }
+}
+
+void N2H_PUT_TX_BUFFER( int dst, int* src, int amount ) {
+
+ // TODO: check that dst is inside TX buffer
+ // TODO: if src and dst are same, do nothing
+
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *((int*)dst + i) = *(src + i);
+ }
+
+}
+#endif // API
+
+/*
+* DMA engine configuration functions (Updated on 27/04/2005)
+*/
+
+// Prepare channel for receiving data.
+void N2H_CHAN_CONF(int channel, int dst_mem_addr, int rx_haddr, int amount,
+ int* base)
+{
+#ifdef API
+ channel_reservations[channel].mem_addr = dst_mem_addr;
+ channel_reservations[channel].amount = amount;
+#endif
+ N2H_CHAN_MEM_ADDR(channel, dst_mem_addr, base);
+ N2H_CHAN_HIBI_ADDR(channel, rx_haddr, base);
+ N2H_CHAN_AMOUNT(channel, amount, base);
+ N2H_CHAN_INIT(channel, base);
+}
+
+void N2H_SEND(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE(base);
+ N2H_TX_START(base);
+}
+
+// Parameter types were uint32. Int works in other places, so why not here?
+void N2H_SEND_READ(int mem_addr, int amount, int haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(haddr, base);
+ N2H_TX_COMM_READ(base);
+ N2H_TX_START(base);
+}
+
+void N2H_SEND_MSG(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE_MSG(base);
+ N2H_TX_START(base);
+}
+
+// Return 0 if transmission is not done yet, 1 otherwise.
+int N2H_TX_DONE(int* base) {
+ int y = 0;
+ N2H_GET_TX_DONE(y, base);
+ return y;
+}
+
+void N2H_CLEAR_IRQ(int chan, int* base) {
+ N2H_RX_CLEAR_IRQ(chan, base);
+}
+
+// Returns first channel number which has IRQ flag up.
+// If no interrupts have been received -1 is returned.
+int N2H_GET_IRQ_CHAN(int* base)
+{
+ volatile int * apu = base + 7;
+ int irq_reg = *apu;
+ int mask = 1;
+ int shift = 0;
+ for (shift = 0; shift < 32; shift++) {
+ if ((irq_reg & (mask << shift)) != 0) {
+ return shift;
+ }
+ }
+ return -1;
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/main.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/main.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/main.c (revision 16)
@@ -0,0 +1,205 @@
+/*
+ * main.c
+ *
+ * Created on: 22.2.2011
+ * Author: lehton87
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "system.h"
+#include "N2H_registers_and_macros.h"
+#include "tut_n2h_regs.h"
+
+#include "n2h_isr_fifo.h"
+
+#include "support.h"
+
+
+int main()
+{
+ int n_received = 0;
+ int rx_data[20];
+ int rx_amount = 8;
+ int tx_amount = 8;
+ int send = 0;
+
+ int channels[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+ N2H_isr_fifo* n2h_isr_fifo = n2h_isr_fifo_create();
+
+ // Init N2H interrupt
+ n2h_isr_init(n2h_isr_fifo);
+
+ printf("CPU2: starts\n");
+
+ while(1)
+ {
+ if(n2h_isr_fifo_size(n2h_isr_fifo))
+ {
+ N2H_isr_info* info = n2h_isr_fifo_pop(n2h_isr_fifo);
+
+ switch(info->isr_type)
+ {
+ case RX_READY:
+
+ printf("CPU2: received %ith packet to channel %i\n",
+ ++n_received, info->rx_channel);
+
+ if(channels[info->rx_channel] == 2)
+ {
+ channels[info->rx_channel] = 0;
+ break;
+ }
+
+ memcpy((int*)rx_data, (int*)(N2H_REGISTERS_RX_BUFFER_START +
+ info->rx_channel * rx_amount *
+ sizeof(int)),
+ rx_amount*sizeof(int));
+
+ printf("CPU2: read data from channel %i : %X %X %X %X %X "
+ "%X %X %X\n",
+ info->rx_channel, rx_data[0], rx_data[1], rx_data[2],
+ rx_data[3], rx_data[4], rx_data[5], rx_data[6],
+ rx_data[7]);
+
+ channels[info->rx_channel] = 0;
+
+ // Init rx chan half the time
+ int src = (rand() % 2 == 0) ? 0x00 : 0x10;
+
+ if(rand() % 2 == 0)
+ {
+ int i = 0;
+
+ for(i = 0; i < 5; ++i)
+ {
+ if(channels[i] == 0)
+ {
+ channels[i] = 1;
+ n2h_init_rx(i, 8*i*sizeof(int), 8, 0x400 + i + src);
+ break;
+ }
+ }
+ }
+
+ send++;
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU2: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+
+ break;
+
+ case RX_UNKNOWN:
+ {
+ int cha = 0;
+
+ for(cha = 0; cha < 8; ++cha)
+ {
+ if(channels[cha] == 0)
+ {
+ channels[cha] = (info->dst_address == 0x5FF) ? 2 : 1;
+
+ printf("CPU2: received data to unconfigured "
+ "address 0x%X, assigning to channel %i\n",
+ info->dst_address, cha);
+
+ if(!(0x400 <= info->dst_address &&
+ info->dst_address <= 0x5FF))
+ {
+ printf("CPU2: %i is invalid address, FAILURE\n",
+ info->dst_address);
+ }
+
+ // Initialize some channel to receive
+ n2h_init_rx(cha, cha * rx_amount*sizeof(int), rx_amount,
+ info->dst_address);
+
+ break;
+ }
+ }
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU2: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+
+ }
+ break;
+
+ case TX_IGNORED:
+ {
+ printf("CPU2: A transfer was ignored because it overlapped"
+ " previous one\n");
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU2: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+ }
+ break;
+
+ }
+
+ // Free memory
+ free(info); info = NULL;
+ }
+ else if(send > 0 && (((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 1))
+ {
+ // Sent packet to a random target's random address
+ int target_addr;
+ int tx_data[8];
+ int tx_slot = (rand() % 8);
+ int cha;
+
+ if(rand() % 2 == 0)
+ {
+ target_addr = 0x020 + tx_slot;
+ }
+ else
+ {
+ target_addr = 0x220 + tx_slot;
+ }
+
+ for(cha = 0; cha < 8; ++cha)
+ tx_data[cha] = 0x82000000 | ((cha+1) << 16) | target_addr;
+
+ memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int)),
+ (int*)tx_data, tx_amount*sizeof(int));
+
+ printf("CPU2: sending packet to 0x%X\n", target_addr);
+
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int),
+ tx_amount, target_addr);
+
+ send--;
+
+ // Overlapping with previous one
+ if((rand() % 100) < 50)
+ {
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int),
+ tx_amount, 0x1FF);
+ printf("CPU2: sending hazard packet\n");
+ }
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU2: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+ }
+ }
+
+ printf("CPU2: retires!\n");
+ while(1); return 0;
+}
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/n2h_isr_fifo.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/n2h_isr_fifo.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/n2h_isr_fifo.c (revision 16)
@@ -0,0 +1,77 @@
+/*
+ *
+ * Fifo for saving interrupt information, implementation
+ *
+ * Lasse Lehtonen
+ *
+ */
+
+
+
+#include "n2h_isr_fifo.h"
+
+#include
+#include
+
+
+// Store item to last place, called only from ISR
+void n2h_isr_fifo_push(N2H_isr_fifo* fifo, N2H_isr_info* item)
+{
+ N2H_isr_info* temp = fifo->root;
+
+ item->next = NULL;
+
+ while(temp != NULL && temp->next != NULL)
+ {
+ temp = temp->next;
+ }
+
+ if(fifo->size < 1)
+ {
+ fifo->root = item;
+ }
+ else
+ {
+ temp->next = item;
+ }
+
+ fifo->size++;
+}
+
+// Returns the first item, remember to free its memory!
+N2H_isr_info* n2h_isr_fifo_pop (N2H_isr_fifo* fifo)
+{
+ N2H_isr_info* temp;
+
+ if(fifo->size < 1)
+ {
+ return NULL;
+ }
+
+ // Prevent ISR from messing with fifo
+ alt_irq_context cntx = alt_irq_disable_all();
+ {
+ temp = fifo->root;
+ fifo->root = temp->next;
+ fifo->size--;
+ }
+ alt_irq_enable_all(cntx);
+
+ temp->next = NULL;
+ return temp;
+}
+
+int n2h_isr_fifo_size(N2H_isr_fifo* fifo)
+{
+ return fifo->size;
+}
+
+N2H_isr_fifo* n2h_isr_fifo_create()
+{
+ //Allocate space for new and initialize data
+ N2H_isr_fifo* fifo = (N2H_isr_fifo*) malloc(sizeof(N2H_isr_fifo));
+ fifo->root = NULL;
+ fifo->size = 0;
+ return fifo;
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/tut_n2h_regs.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/tut_n2h_regs.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/tut_n2h_regs.h (revision 16)
@@ -0,0 +1,209 @@
+/*
+* History:
+* 10/08/2005 by ollil
+* + Copied minor modifications implemented by Ari.
+* This fixed a crash bug in DCT HW based system
+* 03/10/2008 by tapiok
+* fixed N2H_RX_IRQ_DIS
+* 08/2009 kojo2
+* Added following functions: N2H_INIT_ISR, N2H_RX_DONE,
+* N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER
+*/
+#ifndef __tut_n2h_regs_h_
+#define __tut_n2h_regs_h_
+
+#ifdef NIOS_II
+#include "io.h"
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)
+#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)
+#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))
+#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 | (IORD(base,4))))
+#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))
+#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)
+#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)
+#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)
+#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)
+#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)
+#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)
+#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)
+#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)
+#define N2H_TX_COMM_READ(base) IOWR(base,10,4)
+#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)
+#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)
+#define N2H_TX_START(base) IOWR(base, 4, (0x1 | (IORD(base,4))))
+#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)
+#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))
+#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))
+
+
+#else
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 1; \
+ *apu=hibi_addr; \
+ }
+
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4); \
+ *apu=addr; \
+ }
+
+#define N2H_CHAN_AMOUNT(chan, amount, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 2; \
+ *apu=amount; \
+ }
+
+#define N2H_CHAN_INIT(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ *apu=1 << (chan); \
+ }
+
+#define N2H_RX_IRQ_ENA(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu | 0x2; \
+ }
+
+#define N2H_RX_IRQ_DIS(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu & 0xfffffffd; \
+ }
+
+#define N2H_GET_STAT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu >> 16; \
+ }
+
+#define N2H_GET_CONF_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu & 0x0000ffff; \
+ }
+
+#define N2H_GET_INIT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ var = *apu; \
+ }
+
+#define N2H_GET_IRQ_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ var = *apu; \
+ }
+
+#define N2H_GET_CURR_PTR(var, chan, base) \
+ { \
+ volatile int * apu = (int*)base + 3; \
+ apu = apu + ((chan) << 4); \
+ var = *apu; \
+ }
+
+#define N2H_TX_MEM_ADDR(addr, base) \
+ { \
+ volatile int * apu = (int*)base + 8; \
+ *apu = addr; \
+ }
+
+#define N2H_TX_AMOUNT(amount, base) \
+ { \
+ volatile int * apu = (int*)base + 9; \
+ *apu = amount; \
+ }
+
+#define N2H_TX_HIBI_ADDR(haddr, base) \
+ { \
+ volatile int * apu = (int*)base + 11; \
+ *apu = haddr; \
+ }
+
+#define N2H_TX_COMM(comm, base) \
+ { \
+ volatile int * apu = (int*)base +10; \
+ *apu = comm; \
+ }
+
+#define N2H_TX_COMM_WRITE(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 2; \
+ }
+
+#define N2H_TX_COMM_READ(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 4; \
+ }
+
+#define N2H_TX_COMM_WRITE_MSG(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 3; \
+ }
+
+#define N2H_TX_START(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu = *apu | 0x1; \
+ *apu = *apu & 0xfffffffe; \
+ }
+#define N2H_GET_TX_DONE(y, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ y = *apu >> 16; \
+ y = y & 0x1; \
+ }
+
+#define N2H_RX_CLEAR_IRQ(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ *apu = 1 << (chan); \
+ }
+
+
+
+#endif
+
+
+#ifdef API
+extern void N2H_INIT_ISR();
+extern void N2H_RX_DONE( int chan, int mem_addr, int amount );
+extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );
+extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );
+#endif
+
+
+/*
+* DMA engine configuration
+*/
+
+extern void N2H_CHAN_CONF( int channel,
+ int mem_addr,
+ int rx_addr,
+ int amount,
+ int* base );
+
+extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);
+
+extern int N2H_TX_DONE(int* base);
+
+extern void N2H_CLEAR_IRQ(int chan, int* base);
+
+extern int N2H_GET_IRQ_CHAN(int* base);
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/N2H_registers_and_macros.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/N2H_registers_and_macros.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/N2H_registers_and_macros.h (revision 16)
@@ -0,0 +1,47 @@
+// *****************************************************************************
+// File : N2H_registers_and_macros.h
+// Author : Tero Arpinen
+// Date : 22.12.2004
+// Decription : This file contains customizable register address
+// definitions
+// for N2H interface and some needed macros
+//
+// Version history : 22.12.2004 tar Original version
+// : 06.07.2005 tar Modified to work with N2H2
+// : 02.10.2009 tko Removed unneeded macros
+// *****************************************************************************
+
+#ifndef N2H_REGISTERS_AND_MACROS_H
+#define N2H_REGISTERS_AND_MACROS_H
+
+// DEFINE FOLLOWING REGISTERS ACCORDING TO NIOS OR NIOS II HARDWARE
+// CONFIGURATION
+
+// N2H2 Avalon slave base address
+#define N2H_REGISTERS_BASE_ADDRESS ((void*) N2H2_CHAN_2_BASE)
+
+// Buffer start address in cpu's memory
+#define N2H_REGISTERS_BUFFER_START (SHARED_MEM_2_BASE)
+
+// Writeable registers
+// set bit 31 to 1 so that writes and reads bypass cache
+#define N2H_REGISTERS_TX_BUFFER_START (0x80000000 | SHARED_MEM_2_BASE)
+
+#define N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH (0x00000400)
+#define N2H_REGISTERS_TX_BUFFER_END (N2H_REGISTERS_TX_BUFFER_START + \
+ N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH - 1)
+
+// Readable registers
+#define N2H_REGISTERS_RX_BUFFER_START (N2H_REGISTERS_TX_BUFFER_START + N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH)
+#define N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH (0x00000C00)
+#define N2H_REGISTERS_RX_BUFFER_END (N2H_REGISTERS_RX_BUFFER_START + \
+ N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH \
+ - 1)
+// N2H Interrupt registers, numbers and priorities
+#define N2H_RX_IRQ (2)
+#define N2H_RX_IRQ_PRI (3)
+
+// N2H Channels
+#define N2H_NUMBER_OF_CHANNELS (8)
+
+#endif // N2H_REGISTERS_AND_MACROS_H
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/support.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/support.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/support.c (revision 16)
@@ -0,0 +1,138 @@
+/*
+ *
+ * Author : Lasse Lehtonen
+ * Last modification : 29.03.2011
+ *
+ * N2H support functions
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "support.h"
+
+
+void n2h_send(int data_src_addr, int amount, int hibi_addr)
+{
+ // Poll N2H, until it's not sending previous tx anymore
+ //while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) { }
+ // Set data source address
+ IOWR(N2H2_CHAN_BASE, 8, data_src_addr);
+ // Set amount to send
+ IOWR(N2H2_CHAN_BASE, 9, amount);
+ // Set target hibi command
+ IOWR(N2H2_CHAN_BASE, 10, 2);
+ // Set target hibi address
+ IOWR(N2H2_CHAN_BASE, 11, hibi_addr);
+ // Start the transfer
+ IOWR(N2H2_CHAN_BASE, 4, (0x1 | (IORD(N2H2_CHAN_BASE,4))));
+}
+
+
+void n2h_init_rx(int rx_channel, int rx_addr, int rx_amount, int hibi_addr)
+{
+ // Set receive mem address for incoming data
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4), N2H_REGISTERS_RX_BUFFER_START +
+ rx_addr);
+ // Set amount to receive
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4) + 2, rx_amount);
+ // Set hibi address to receive data
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4) + 1, hibi_addr);
+ // Initialize receiving
+ IOWR(N2H2_CHAN_BASE, 5 , 1 << rx_channel);
+}
+
+
+
+int onehot2int(int num)
+{
+ int i = 0;
+ for(; i < 31; ++i)
+ {
+ if(num & (1 << i))
+ {
+ return i;
+ }
+ }
+ return -1;
+}
+
+
+void n2h2_isr(void* context)
+{
+ N2H_isr_fifo* fifo = (N2H_isr_fifo*) context;
+
+ // Read the cause of the interrupt
+ int interrupter = IORD(N2H2_CHAN_BASE, 7);
+
+
+ if((0x80000000 & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = RX_UNKNOWN;
+
+ // Read in incoming hibi address
+ info->dst_address = IORD(N2H2_CHAN_BASE, 12);
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, 0x80000000);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+
+ if((0x40000000 & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = TX_IGNORED;
+
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, 0x40000000);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+
+ while((0x3FFFFFFF & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = RX_READY;
+
+ // Store interrupted channel
+ info->rx_channel = onehot2int(interrupter);
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, (1 << info->rx_channel));
+
+ interrupter = interrupter & ~(1 << info->rx_channel);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+}
+
+
+
+// Init interrupt
+void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo)
+{
+ // Register N2H2 ISR
+ if(alt_ic_isr_register(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID,
+ N2H2_CHAN_IRQ, n2h2_isr, (void*)n2h_isr_fifo, 0)
+ != 0)
+ {
+ printf("CPU0: registering n2h2_isr failed!\n");
+ }
+ // Enable interrupt on CPU side
+ if(alt_ic_irq_enable(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID,
+ N2H2_CHAN_IRQ) != 0)
+ {
+ printf("CPU0: enabling n2h2 interrupt failed!\n");
+ }
+ // Enable interrupts on N2H2 side
+ IOWR(N2H2_CHAN_BASE, 4, (2 | (IORD(N2H2_CHAN_BASE,4))));
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/n2h_isr_fifo.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/n2h_isr_fifo.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/src_cpu2/n2h_isr_fifo.h (revision 16)
@@ -0,0 +1,44 @@
+/*
+ *
+ * Fifo for saving interrupt information, header
+ *
+ * Lasse Lehtonen
+ *
+ */
+
+#ifndef N2H_ISR_FIFO_HH
+#define N2H_ISR_FIFO_HH
+
+// Tells what caused N2H2 to interrupt
+typedef enum {RX_READY, RX_UNKNOWN, TX_IGNORED} N2H_isr_type;
+
+
+// Item stored in fifo
+typedef struct N2H_isr_info N2H_isr_info;
+typedef struct N2H_isr_info
+{
+ N2H_isr_type isr_type;
+ union {
+ int rx_channel;
+ int dst_address;
+ };
+
+ N2H_isr_info* next;
+};
+
+
+typedef struct
+{
+ N2H_isr_info* root;
+ volatile int size;
+
+} N2H_isr_fifo;
+
+// used fifo item to store
+void n2h_isr_fifo_push(N2H_isr_fifo* fifo, N2H_isr_info* item);
+N2H_isr_info* n2h_isr_fifo_pop(N2H_isr_fifo* fifo);
+int n2h_isr_fifo_size(N2H_isr_fifo* fifo);
+// Creates new fifo
+N2H_isr_fifo* n2h_isr_fifo_create();
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/tb/system/hibiv3_r4.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/hibiv3_r4.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/hibiv3_r4.vhd (revision 16)
@@ -0,0 +1,566 @@
+-------------------------------------------------------------------------------
+-- Title : Hibi toplevel using r4 wrappers
+-- Project :
+-------------------------------------------------------------------------------
+-- File : hibiv3_r4.vhd
+-- Author : Lasse Lehtonen, modified from Jussi Nieminen's HWTG hibi
+-- top level
+-- Company :
+-- Last update: 2011-04-04
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description: Semi-generic toplevel, add as many agents as you like. Just
+-- be sure to create enough addresses in the tables (scroll down).
+-- Every segment has equal number of wrappers and are connected
+-- as a chain.
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2009/06/23 1.0 niemin95 Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.hibiv3_pkg.all;
+
+
+entity hibiv3_r4 is
+
+ generic (
+ -- HIBI generics
+ id_width_g : integer := 4;
+ addr_width_g : integer := 16;
+ data_width_g : integer := 32;
+ comm_width_g : integer := 5;
+ counter_width_g : integer := 8;
+ rel_agent_freq_g : integer := 1;
+ rel_bus_freq_g : integer := 1;
+ arb_type_g : integer := 3;
+ fifo_sel_g : integer := 0;
+ rx_fifo_depth_g : integer := 4;
+ rx_msg_fifo_depth_g : integer := 4;
+ tx_fifo_depth_g : integer := 4;
+ tx_msg_fifo_depth_g : integer := 4;
+ max_send_g : integer := 20;
+ n_cfg_pages_g : integer := 1;
+ n_time_slots_g : integer := 0;
+ keep_slot_g : integer := 0;
+ n_extra_params_g : integer := 1;
+
+ cfg_re_g : integer := 1;
+ cfg_we_g : integer := 1;
+ debug_width_g : integer := 0;
+
+ n_agents_g : integer := 12;
+ n_segments_g : integer := 3;
+
+ separate_addr_g : integer := 0
+ );
+
+ port (
+ clk_ip : in std_logic;
+ clk_noc : in std_logic;
+ rst_n : in std_logic;
+
+ agent_comm_in : in std_logic_vector(n_agents_g*comm_width_g-1 downto 0);
+ agent_data_in : in std_logic_vector(n_agents_g*data_width_g-1 downto 0);
+ agent_av_in : in std_logic_vector(n_agents_g-1 downto 0);
+ agent_we_in : in std_logic_vector(n_agents_g-1 downto 0);
+ agent_re_in : in std_logic_vector(n_agents_g-1 downto 0);
+ agent_comm_out : out std_logic_vector(n_agents_g*comm_width_g-1 downto 0);
+ agent_data_out : out std_logic_vector(n_agents_g*data_width_g-1 downto 0);
+ agent_av_out : out std_logic_vector(n_agents_g-1 downto 0);
+ agent_full_out : out std_logic_vector(n_agents_g-1 downto 0);
+ agent_one_p_out : out std_logic_vector(n_agents_g-1 downto 0);
+ agent_empty_out : out std_logic_vector(n_agents_g-1 downto 0);
+ agent_one_d_out : out std_logic_vector(n_agents_g-1 downto 0)
+
+ );
+
+end hibiv3_r4;
+
+
+
+architecture structural of hibiv3_r4 is
+
+ -----------------------------------------------------------------------------
+ -- HIBI ADDRESSES
+ -----------------------------------------------------------------------------
+
+ type gen_addr_array_type is array (1 to 4) of integer;
+ type gen_addr_array_3d_type is array (0 to 2) of gen_addr_array_type;
+ type gen_bridge_addr_array is array (0 to 1) of integer;
+
+ -- addresses_c(segment index)(wrapper index in the segment)
+ constant addresses_lo_c : gen_addr_array_3d_type :=
+ ((16#00000000#, 16#00000200#, 16#00000400#, 16#00000000#),
+ (16#00000000#, 16#00000130#, 16#00000000#, 16#00000000#),
+ (16#00000000#, 16#00000330#, 16#00000000#, 16#00000000#));
+
+ constant addresses_hi_c : gen_addr_array_3d_type :=
+ ((16#000001FF#, 16#000003FF#, 16#000005FF#, 16#00000000#),
+ (16#00000000#, 16#00000000#, 16#00000000#, 16#00000000#),
+ (16#00000000#, 16#00000000#, 16#00000000#, 16#00000000#));
+
+ constant bridge_a_addr_base_c : gen_bridge_addr_array :=
+ (16#00000000#, 16#00000000#);
+ constant bridge_a_addr_limit_c : gen_bridge_addr_array :=
+ (16#000000FF#, 16#000001FF#);
+ constant bridge_b_addr_base_c : gen_bridge_addr_array :=
+ (16#00000000#, 16#00000000#);
+ constant bridge_b_addr_limit_c : gen_bridge_addr_array :=
+ (16#000000FF#, 16#000001FF#);
+
+ constant bridge_a_id_min_c : gen_bridge_addr_array :=
+ (1, 1);
+ constant bridge_a_id_max_c : gen_bridge_addr_array :=
+ (5, 11);
+ constant bridge_b_id_min_c : gen_bridge_addr_array :=
+ (1, 1);
+ constant bridge_b_id_max_c : gen_bridge_addr_array :=
+ (5, 11);
+
+ constant bridge_a_inv_addr_c : gen_bridge_addr_array :=
+ (1, 1);
+ constant bridge_b_inv_addr_c : gen_bridge_addr_array :=
+ (0, 0);
+
+
+
+
+
+
+
+ -----------------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------------
+
+ -- purpose: to resolve the number of agents in each segment
+ function n_agents_in_segment (
+ constant segment, n_segments, wrappers_per_seg : integer)
+ return integer is
+ begin -- n_agents_in_segment
+
+ if n_segments = 1 then
+ return wrappers_per_seg;
+ elsif segment = 0 or segment = n_segments - 1 then
+ -- end segment, only one bridge
+ return wrappers_per_seg + 1;
+ else
+ -- middle segment
+ return wrappers_per_seg + 2;
+ end if;
+
+ end n_agents_in_segment;
+
+ function priority_a (
+ constant segment, n_segments, wrappers_per_seg : integer)
+ return integer is
+ begin
+
+ if n_segments = 1 then
+ return 0;
+ elsif segment = 0 or segment = n_segments - 1 then
+ -- end segment, only one bridge
+ return wrappers_per_seg + 1;
+ else
+ -- middle segment
+ return wrappers_per_seg + 2;
+ end if;
+
+ end priority_a;
+
+ function priority_b (
+ constant segment, n_segments, wrappers_per_seg : integer)
+ return integer is
+ begin
+
+ if n_segments = 1 then
+ return 0;
+ elsif segment = 0 or segment = n_segments - 1 then
+ -- end segment, only one bridge
+ return wrappers_per_seg + 1;
+ else
+ -- middle segment
+ return wrappers_per_seg + 1;
+ end if;
+
+ end priority_b;
+
+ function id_agent (
+ constant segment, n_segments, wrappers_per_seg : integer)
+ return integer is
+ begin
+
+ if n_segments = 1 then
+ return 1;
+ elsif segment = 0 then
+ -- first segment
+ return 1;
+ elsif segment = n_segments - 1 then
+ -- last segment
+ return segment*(wrappers_per_seg+2);
+ else
+ -- middle segment
+ return segment*(wrappers_per_seg+2);
+ end if;
+
+ end id_agent;
+
+ function id_a (
+ constant segment, n_segments, wrappers_per_seg : integer)
+ return integer is
+ begin
+
+ if n_segments = 1 then
+ return 0;
+ elsif segment = 0 then
+ -- first segment
+ return wrappers_per_seg + 1;
+ elsif segment = n_segments - 1 then
+ -- last segment
+ return 0;
+ else
+ -- middle segment
+ return segment*(wrappers_per_seg+2)+wrappers_per_seg;
+ end if;
+
+ end id_a;
+
+ function id_b (
+ constant segment, n_segments, wrappers_per_seg : integer)
+ return integer is
+ begin
+
+ if n_segments = 1 then
+ return 0;
+ elsif segment = 0 then
+ -- first segment
+ return 0;
+ elsif segment = n_segments - 1 then
+ return segment*(wrappers_per_seg+2)+wrappers_per_seg;
+ else
+ -- middle segment
+ return segment*(wrappers_per_seg+2)+wrappers_per_seg+1;
+ end if;
+
+ end id_b;
+
+
+ constant wrappers_per_segment_c : integer := n_agents_g / n_segments_g;
+
+ type bus_data_segments_array is array (0 to n_segments_g-1) of
+ std_logic_vector(data_width_g-1 downto 0);
+ type bus_comm_segments_array is array (0 to n_segments_g-1) of
+ std_logic_vector(comm_width_c-1 downto 0);
+
+ signal bus_wra_data : bus_data_segments_array;
+ signal bus_wra_comm : bus_comm_segments_array;
+ signal bus_wra_av : std_logic_vector(n_segments_g-1 downto 0);
+ signal bus_wra_full : std_logic_vector(n_segments_g-1 downto 0);
+ signal bus_wra_lock : std_logic_vector(n_segments_g-1 downto 0);
+
+ -- +1, because there might be bridges in the segment. This is not optimal,
+ -- but much easier and extra signals should be optimized away in synthesis
+ type data_to_bus_type is array (0 to wrappers_per_segment_c+1) of
+ std_logic_vector(data_width_g-1 downto 0);
+ type comm_to_bus_type is array (0 to wrappers_per_segment_c+1) of
+ std_logic_vector(comm_width_c-1 downto 0);
+
+ type data_segments_array is array (0 to n_segments_g-1) of data_to_bus_type;
+ type comm_segments_array is array (0 to n_segments_g-1) of comm_to_bus_type;
+ type cntr_segments_array is array (0 to n_segments_g-1) of std_logic_vector
+ (wrappers_per_segment_c + 1 downto 0);
+
+ signal wra_bus_data : data_segments_array;
+ signal wra_bus_comm : comm_segments_array;
+ signal wra_bus_av : cntr_segments_array;
+ signal wra_bus_full : cntr_segments_array;
+ signal wra_bus_lock : cntr_segments_array;
+
+-------------------------------------------------------------------------------
+begin -- structural
+-------------------------------------------------------------------------------
+
+ -- if there is more than 1 segment, wrappers must distribute evenly
+ assert n_segments_g = 1 or n_agents_g mod n_segments_g = 0
+ report "With more than one segment wrappers distribute evenly"
+ severity failure;
+
+
+ segments : for seg in 0 to n_segments_g-1 generate
+
+ wrappers : for wra in 0 to wrappers_per_segment_c-1 generate
+
+ wrapper : entity work.hibi_wrapper_r4
+ generic map (
+ id_g => id_agent
+ (seg, n_segments_g, wrappers_per_segment_c) + wra,
+ addr_g => addresses_lo_c(seg)(wra + 1),
+ addr_limit_g => addresses_hi_c(seg)(wra + 1),
+ inv_addr_en_g => 0,
+ id_width_g => id_width_g,
+ addr_width_g => addr_width_g,
+ data_width_g => data_width_g,
+ separate_addr_g => separate_addr_g,
+ comm_width_g => comm_width_g,
+ counter_width_g => counter_width_g,
+ rel_agent_freq_g => rel_agent_freq_g,
+ rel_bus_freq_g => rel_bus_freq_g,
+ arb_type_g => arb_type_g,
+ fifo_sel_g => fifo_sel_g,
+ rx_fifo_depth_g => rx_fifo_depth_g,
+ rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
+ tx_fifo_depth_g => tx_fifo_depth_g,
+ tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
+ prior_g => wra + 1,
+ max_send_g => max_send_g,
+ -- n_agents_g should be num of ips + num of bridges in the segment
+ n_agents_g => n_agents_in_segment
+ (seg, n_segments_g, wrappers_per_segment_c),
+ n_cfg_pages_g => n_cfg_pages_g,
+ n_time_slots_g => n_time_slots_g,
+ keep_slot_g => keep_slot_g,
+ n_extra_params_g => n_extra_params_g,
+
+ cfg_re_g => cfg_re_g,
+ cfg_we_g => cfg_we_g,
+ debug_width_g => debug_width_g
+ )
+ port map (
+ bus_clk => clk_noc,
+ agent_clk => clk_ip,
+ bus_sync_clk => clk_noc,
+ agent_sync_clk => clk_ip,
+ rst_n => rst_n,
+ bus_comm_in => bus_wra_comm(seg),
+ bus_data_in => bus_wra_data(seg),
+ bus_full_in => bus_wra_full(seg),
+ bus_lock_in => bus_wra_lock(seg),
+ bus_av_in => bus_wra_av(seg),
+ agent_comm_in => agent_comm_in((seg*wrappers_per_segment_c+wra+1)*
+ comm_width_g-1 downto
+ (seg*wrappers_per_segment_c+wra)*
+ comm_width_g),
+ agent_data_in => agent_data_in((seg*wrappers_per_segment_c+wra+1)*
+ data_width_g-1 downto
+ (seg*wrappers_per_segment_c+wra)*
+ data_width_g),
+ agent_av_in => agent_av_in(seg*wrappers_per_segment_c+wra),
+ agent_we_in => agent_we_in(seg*wrappers_per_segment_c+wra),
+ agent_re_in => agent_re_in(seg*wrappers_per_segment_c+wra),
+ bus_comm_out => wra_bus_comm(seg)(wra),
+ bus_data_out => wra_bus_data(seg)(wra),
+ bus_full_out => wra_bus_full(seg)(wra),
+ bus_lock_out => wra_bus_lock(seg)(wra),
+ bus_av_out => wra_bus_av(seg)(wra),
+ agent_comm_out => agent_comm_out((seg*wrappers_per_segment_c+wra+1)*
+ comm_width_g-1 downto
+ (seg*wrappers_per_segment_c+wra)*
+ comm_width_g),
+ agent_data_out => agent_data_out((seg*wrappers_per_segment_c+wra+1)*
+ data_width_g-1 downto
+ (seg*wrappers_per_segment_c+wra)*
+ data_width_g),
+ agent_av_out => agent_av_out(seg*wrappers_per_segment_c+wra),
+ agent_full_out => agent_full_out(seg*wrappers_per_segment_c+wra),
+ agent_one_p_out => agent_one_p_out(seg*wrappers_per_segment_c+wra),
+ agent_empty_out => agent_empty_out(seg*wrappers_per_segment_c+wra),
+ agent_one_d_out => agent_one_d_out(seg*wrappers_per_segment_c+wra)
+ -- synthesis translate_off
+ ,
+ debug_out => open,
+ debug_in => (others => '0')
+ -- synthesis translate_on
+ );
+
+
+ end generate wrappers;
+
+
+ bridge_needed : if seg > 0 generate
+
+ i_bridge : entity work.hibi_bridge
+ generic map (
+ a_id_g =>
+ id_a(seg-1, n_segments_g, wrappers_per_segment_c),
+ a_addr_g => bridge_a_addr_base_c(seg-1),
+ a_inv_addr_en_g => bridge_a_inv_addr_c(seg-1),
+ a_id_width_g => id_width_g,
+ a_addr_width_g => addr_width_g,
+ a_data_width_g => data_width_g,
+ a_separate_addr_g => separate_addr_g,
+ a_comm_width_g => comm_width_g,
+ a_counter_width_g => counter_width_g,
+ a_rx_fifo_depth_g => rx_fifo_depth_g,
+ a_tx_fifo_depth_g => tx_fifo_depth_g,
+ a_rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
+ a_tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
+ a_arb_type_g => arb_type_g,
+ a_fifo_sel_g => fifo_sel_g,
+
+ a_debug_width_g => debug_width_g,
+ a_prior_g =>
+ priority_a(seg-1, n_segments_g, wrappers_per_segment_c),
+ a_max_send_g => max_send_g,
+ a_n_agents_g =>
+ n_agents_in_segment(seg-1, n_segments_g, wrappers_per_segment_c),
+ a_n_cfg_pages_g => n_cfg_pages_g,
+ a_n_time_slots_g => n_time_slots_g,
+ a_n_extra_params_g => n_extra_params_g,
+ a_cfg_re_g => cfg_re_g,
+ a_cfg_we_g => cfg_we_g,
+
+ b_id_g =>
+ id_b(seg, n_segments_g, wrappers_per_segment_c),
+ b_addr_g => bridge_b_addr_base_c(seg-1),
+ b_inv_addr_en_g => bridge_b_inv_addr_c(seg-1),
+ b_id_width_g => id_width_g,
+ b_addr_width_g => addr_width_g,
+ b_data_width_g => data_width_g,
+ b_separate_addr_g => separate_addr_g,
+ b_comm_width_g => comm_width_g,
+ b_counter_width_g => counter_width_g,
+ b_rx_fifo_depth_g => rx_fifo_depth_g,
+ b_tx_fifo_depth_g => tx_fifo_depth_g,
+ b_rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
+ b_tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
+ b_arb_type_g => arb_type_g,
+ b_fifo_sel_g => fifo_sel_g,
+
+ b_debug_width_g => debug_width_g,
+ b_prior_g =>
+ priority_b(seg, n_segments_g, wrappers_per_segment_c),
+ b_max_send_g => max_send_g,
+ b_n_agents_g =>
+ n_agents_in_segment(seg, n_segments_g, wrappers_per_segment_c),
+ b_n_cfg_pages_g => n_cfg_pages_g,
+ b_n_time_slots_g => n_time_slots_g,
+ b_n_extra_params_g => n_extra_params_g,
+ b_cfg_re_g => cfg_re_g,
+ b_cfg_we_g => cfg_we_g,
+
+ a_id_min_g => bridge_a_id_min_c(seg-1),
+ a_id_max_g => bridge_a_id_max_c(seg-1),
+ a_addr_limit_g => bridge_a_addr_limit_c(seg-1),
+
+ b_id_min_g => bridge_b_id_min_c(seg-1),
+ b_id_max_g => bridge_b_id_max_c(seg-1),
+ b_addr_limit_g => bridge_b_addr_limit_c(seg-1)
+
+ )
+ port map (
+ a_clk => clk_noc,
+ a_rst_n => rst_n,
+ b_clk => clk_noc,
+ b_rst_n => rst_n,
+ a_bus_av_in => bus_wra_av(seg-1),
+ a_bus_data_in => bus_wra_data(seg-1),
+ a_bus_comm_in => bus_wra_comm(seg-1),
+ a_bus_full_in => bus_wra_full(seg-1),
+ a_bus_lock_in => bus_wra_lock(seg-1),
+ b_bus_av_in => bus_wra_av(seg),
+ b_bus_data_in => bus_wra_data(seg),
+ b_bus_comm_in => bus_wra_comm(seg),
+ b_bus_full_in => bus_wra_full(seg),
+ b_bus_lock_in => bus_wra_lock(seg),
+ a_bus_av_out => wra_bus_av(seg-1)(wrappers_per_segment_c),
+ a_bus_data_out => wra_bus_data(seg-1)(wrappers_per_segment_c),
+ a_bus_comm_out => wra_bus_comm(seg-1)(wrappers_per_segment_c),
+ a_bus_lock_out => wra_bus_lock(seg-1)(wrappers_per_segment_c),
+ a_bus_full_out => wra_bus_full(seg-1)(wrappers_per_segment_c),
+ b_bus_av_out => wra_bus_av(seg)(wrappers_per_segment_c+1),
+ b_bus_data_out => wra_bus_data(seg)(wrappers_per_segment_c+1),
+ b_bus_comm_out => wra_bus_comm(seg)(wrappers_per_segment_c+1),
+ b_bus_lock_out => wra_bus_lock(seg)(wrappers_per_segment_c+1),
+ b_bus_full_out => wra_bus_full(seg)(wrappers_per_segment_c+1)
+ -- synthesis translate_off
+ ,
+ a_debug_out => open,
+ a_debug_in => (others => '0'),
+ b_debug_out => open,
+ b_debug_in => (others => '0')
+ -- synthesis translate_on
+ );
+
+ -- nullify extra signals
+ nullify_first_seg : if seg = 1 generate
+ -- no b-side on the first segment
+ wra_bus_av(seg-1)(wrappers_per_segment_c+1) <= '0';
+ wra_bus_full(seg-1)(wrappers_per_segment_c+1) <= '0';
+ wra_bus_lock(seg-1)(wrappers_per_segment_c+1) <= '0';
+ wra_bus_comm(seg-1)(wrappers_per_segment_c+1) <= (others => '0');
+ wra_bus_data(seg-1)(wrappers_per_segment_c+1) <= (others => '0');
+ end generate nullify_first_seg;
+
+ nullify_last_seg : if seg = n_segments_g-1 generate
+ -- no a-side here
+ wra_bus_av(seg)(wrappers_per_segment_c) <= '0';
+ wra_bus_full(seg)(wrappers_per_segment_c) <= '0';
+ wra_bus_lock(seg)(wrappers_per_segment_c) <= '0';
+ wra_bus_comm(seg)(wrappers_per_segment_c) <= (others => '0');
+ wra_bus_data(seg)(wrappers_per_segment_c) <= (others => '0');
+ end generate nullify_last_seg;
+
+ end generate bridge_needed;
+
+
+ no_bridges : if n_segments_g = 1 generate
+
+ -- no bridges, nullify extra all signals
+ wra_bus_av(seg)(wrappers_per_segment_c) <= '0';
+ wra_bus_full(seg)(wrappers_per_segment_c) <= '0';
+ wra_bus_lock(seg)(wrappers_per_segment_c) <= '0';
+ wra_bus_comm(seg)(wrappers_per_segment_c) <= (others => '0');
+ wra_bus_data(seg)(wrappers_per_segment_c) <= (others => '0');
+ wra_bus_av(seg)(wrappers_per_segment_c+1) <= '0';
+ wra_bus_full(seg)(wrappers_per_segment_c+1) <= '0';
+ wra_bus_lock(seg)(wrappers_per_segment_c+1) <= '0';
+ wra_bus_comm(seg)(wrappers_per_segment_c+1) <= (others => '0');
+ wra_bus_data(seg)(wrappers_per_segment_c+1) <= (others => '0');
+
+ end generate no_bridges;
+
+
+ end generate segments;
+
+
+ -- making the bus
+ form_bus : process (wra_bus_data, wra_bus_comm, wra_bus_av,
+ wra_bus_full, wra_bus_lock)
+ variable tmp_data_v : bus_data_segments_array;
+ variable tmp_comm_v : bus_comm_segments_array;
+ variable tmp_av_v : std_logic_vector(n_segments_g-1 downto 0);
+ variable tmp_full_v : std_logic_vector(n_segments_g-1 downto 0);
+ variable tmp_lock_v : std_logic_vector(n_segments_g-1 downto 0);
+ begin -- process form_bus
+
+ for seg in 0 to n_segments_g-1 loop
+
+ tmp_data_v(seg) := wra_bus_data(seg)(0);
+ tmp_comm_v(seg) := wra_bus_comm(seg)(0);
+ tmp_av_v(seg) := wra_bus_av(seg)(0);
+ tmp_full_v(seg) := wra_bus_full(seg)(0);
+ tmp_lock_v(seg) := wra_bus_lock(seg)(0);
+
+ for n in 1 to wrappers_per_segment_c+1 loop
+
+ tmp_data_v(seg) := wra_bus_data(seg)(n) or tmp_data_v(seg);
+ tmp_comm_v(seg) := wra_bus_comm(seg)(n) or tmp_comm_v(seg);
+ tmp_av_v(seg) := wra_bus_av(seg)(n) or tmp_av_v(seg);
+ tmp_full_v(seg) := wra_bus_full(seg)(n) or tmp_full_v(seg);
+ tmp_lock_v(seg) := wra_bus_lock(seg)(n) or tmp_lock_v(seg);
+
+ end loop; -- n
+
+ bus_wra_data(seg) <= tmp_data_v(seg);
+ bus_wra_comm(seg) <= tmp_comm_v(seg);
+ bus_wra_av(seg) <= tmp_av_v(seg);
+ bus_wra_full(seg) <= tmp_full_v(seg);
+ bus_wra_lock(seg) <= tmp_lock_v(seg);
+
+ end loop; -- seg
+
+ end process form_bus;
+
+end structural;
Index: TUT/ip.hwp.communication/n2h2/tb/system/support/hibi_add.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/support/hibi_add.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/support/hibi_add.vhd (revision 16)
@@ -0,0 +1,217 @@
+
+
+-- CODE INSERTED BETWEEN HERE
+
+signal cpu_0_reset : std_logic;
+signal cpu_1_reset : std_logic;
+signal cpu_2_reset : std_logic;
+
+signal cpu_0_reset_taken : std_logic;
+signal cpu_1_reset_taken : std_logic;
+signal cpu_2_reset_taken : std_logic;
+
+signal comm_from_n : std_logic_vector(5*3-1 downto 0);
+signal data_from_n : std_logic_vector(32*3-1 downto 0);
+signal av_from_n : std_logic_vector(3-1 downto 0);
+signal we_from_n : std_logic_vector(3-1 downto 0);
+signal re_from_n : std_logic_vector(3-1 downto 0);
+signal comm_to_n : std_logic_vector(5*3-1 downto 0);
+signal data_to_n : std_logic_vector(32*3-1 downto 0);
+signal av_to_n : std_logic_vector(3-1 downto 0);
+signal full_to_n : std_logic_vector(3-1 downto 0);
+signal one_p_to_n : std_logic_vector(3-1 downto 0);
+signal empty_to_n : std_logic_vector(3-1 downto 0);
+signal one_d_to_n : std_logic_vector(3-1 downto 0);
+
+-- AND HERE WILL BE PRESERVED
+
+
+begin
+
+ --
+ -- CHECK DUTS NAME !
+ --
+
+ --Set us up the Dut
+ DUT : n2h2_s
+ port map(
+ cpu_resettaken_from_the_cpu_0 => cpu_resettaken_from_the_cpu_0,
+ cpu_resettaken_from_the_cpu_1 => cpu_resettaken_from_the_cpu_1,
+ cpu_resettaken_from_the_cpu_2 => cpu_resettaken_from_the_cpu_2,
+ hibi_av_out_from_the_n2h2_chan_0 => hibi_av_out_from_the_n2h2_chan_0,
+ hibi_av_out_from_the_n2h2_chan_1 => hibi_av_out_from_the_n2h2_chan_1,
+ hibi_av_out_from_the_n2h2_chan_2 => hibi_av_out_from_the_n2h2_chan_2,
+ hibi_comm_out_from_the_n2h2_chan_0 => hibi_comm_out_from_the_n2h2_chan_0,
+ hibi_comm_out_from_the_n2h2_chan_1 => hibi_comm_out_from_the_n2h2_chan_1,
+ hibi_comm_out_from_the_n2h2_chan_2 => hibi_comm_out_from_the_n2h2_chan_2,
+ hibi_data_out_from_the_n2h2_chan_0 => hibi_data_out_from_the_n2h2_chan_0,
+ hibi_data_out_from_the_n2h2_chan_1 => hibi_data_out_from_the_n2h2_chan_1,
+ hibi_data_out_from_the_n2h2_chan_2 => hibi_data_out_from_the_n2h2_chan_2,
+ hibi_re_out_from_the_n2h2_chan_0 => hibi_re_out_from_the_n2h2_chan_0,
+ hibi_re_out_from_the_n2h2_chan_1 => hibi_re_out_from_the_n2h2_chan_1,
+ hibi_re_out_from_the_n2h2_chan_2 => hibi_re_out_from_the_n2h2_chan_2,
+ hibi_we_out_from_the_n2h2_chan_0 => hibi_we_out_from_the_n2h2_chan_0,
+ hibi_we_out_from_the_n2h2_chan_1 => hibi_we_out_from_the_n2h2_chan_1,
+ hibi_we_out_from_the_n2h2_chan_2 => hibi_we_out_from_the_n2h2_chan_2,
+ clk_0 => clk_0,
+ cpu_resetrequest_to_the_cpu_0 => cpu_resetrequest_to_the_cpu_0,
+ cpu_resetrequest_to_the_cpu_1 => cpu_resetrequest_to_the_cpu_1,
+ cpu_resetrequest_to_the_cpu_2 => cpu_resetrequest_to_the_cpu_2,
+ hibi_av_in_to_the_n2h2_chan_0 => hibi_av_in_to_the_n2h2_chan_0,
+ hibi_av_in_to_the_n2h2_chan_1 => hibi_av_in_to_the_n2h2_chan_1,
+ hibi_av_in_to_the_n2h2_chan_2 => hibi_av_in_to_the_n2h2_chan_2,
+ hibi_comm_in_to_the_n2h2_chan_0 => hibi_comm_in_to_the_n2h2_chan_0,
+ hibi_comm_in_to_the_n2h2_chan_1 => hibi_comm_in_to_the_n2h2_chan_1,
+ hibi_comm_in_to_the_n2h2_chan_2 => hibi_comm_in_to_the_n2h2_chan_2,
+ hibi_data_in_to_the_n2h2_chan_0 => hibi_data_in_to_the_n2h2_chan_0,
+ hibi_data_in_to_the_n2h2_chan_1 => hibi_data_in_to_the_n2h2_chan_1,
+ hibi_data_in_to_the_n2h2_chan_2 => hibi_data_in_to_the_n2h2_chan_2,
+ hibi_empty_in_to_the_n2h2_chan_0 => hibi_empty_in_to_the_n2h2_chan_0,
+ hibi_empty_in_to_the_n2h2_chan_1 => hibi_empty_in_to_the_n2h2_chan_1,
+ hibi_empty_in_to_the_n2h2_chan_2 => hibi_empty_in_to_the_n2h2_chan_2,
+ hibi_full_in_to_the_n2h2_chan_0 => hibi_full_in_to_the_n2h2_chan_0,
+ hibi_full_in_to_the_n2h2_chan_1 => hibi_full_in_to_the_n2h2_chan_1,
+ hibi_full_in_to_the_n2h2_chan_2 => hibi_full_in_to_the_n2h2_chan_2,
+ reset_n => reset_n
+ );
+
+
+ process
+ begin
+ clk_0 <= '0';
+ loop
+ wait for 10 ns;
+ clk_0 <= not clk_0;
+ end loop;
+ end process;
+ PROCESS
+ BEGIN
+ reset_n <= '0';
+ wait for 200 ns;
+ reset_n <= '1';
+ WAIT;
+ END PROCESS;
+
+
+-- CODE INSERTED BETWEEN HERE
+
+ cpu_0_reset_taken <= cpu_resettaken_from_the_cpu_0;
+ cpu_1_reset_taken <= cpu_resettaken_from_the_cpu_1;
+ cpu_2_reset_taken <= cpu_resettaken_from_the_cpu_2;
+
+ cpu_resetrequest_to_the_cpu_0 <= cpu_0_reset;
+ cpu_resetrequest_to_the_cpu_1 <= cpu_1_reset;
+ cpu_resetrequest_to_the_cpu_2 <= cpu_2_reset;
+
+ av_from_n(0) <= hibi_av_out_from_the_n2h2_chan_0;
+ av_from_n(1) <= hibi_av_out_from_the_n2h2_chan_1;
+ av_from_n(2) <= hibi_av_out_from_the_n2h2_chan_2;
+
+ comm_from_n(5*1-1 downto 5*0) <= hibi_comm_out_from_the_n2h2_chan_0;
+ comm_from_n(5*2-1 downto 5*1) <= hibi_comm_out_from_the_n2h2_chan_1;
+ comm_from_n(5*3-1 downto 5*2) <= hibi_comm_out_from_the_n2h2_chan_2;
+
+ data_from_n(32*1-1 downto 32*0) <= hibi_data_out_from_the_n2h2_chan_0;
+ data_from_n(32*2-1 downto 32*1) <= hibi_data_out_from_the_n2h2_chan_1;
+ data_from_n(32*3-1 downto 32*2) <= hibi_data_out_from_the_n2h2_chan_2;
+
+ re_from_n(0) <= hibi_re_out_from_the_n2h2_chan_0;
+ re_from_n(1) <= hibi_re_out_from_the_n2h2_chan_1;
+ re_from_n(2) <= hibi_re_out_from_the_n2h2_chan_2;
+
+ we_from_n(0) <= hibi_we_out_from_the_n2h2_chan_0;
+ we_from_n(1) <= hibi_we_out_from_the_n2h2_chan_1;
+ we_from_n(2) <= hibi_we_out_from_the_n2h2_chan_2;
+
+ hibi_av_in_to_the_n2h2_chan_0 <= av_to_n(0);
+ hibi_av_in_to_the_n2h2_chan_1 <= av_to_n(1);
+ hibi_av_in_to_the_n2h2_chan_2 <= av_to_n(2);
+
+ hibi_comm_in_to_the_n2h2_chan_0 <= comm_to_n(5*1-1 downto 5*0);
+ hibi_comm_in_to_the_n2h2_chan_1 <= comm_to_n(5*2-1 downto 5*1);
+ hibi_comm_in_to_the_n2h2_chan_2 <= comm_to_n(5*3-1 downto 5*2);
+
+ hibi_data_in_to_the_n2h2_chan_0 <= data_to_n(32*1-1 downto 32*0);
+ hibi_data_in_to_the_n2h2_chan_1 <= data_to_n(32*2-1 downto 32*1);
+ hibi_data_in_to_the_n2h2_chan_2 <= data_to_n(32*3-1 downto 32*2);
+
+ hibi_empty_in_to_the_n2h2_chan_0 <= empty_to_n(0);
+ hibi_empty_in_to_the_n2h2_chan_1 <= empty_to_n(1);
+ hibi_empty_in_to_the_n2h2_chan_2 <= empty_to_n(2);
+
+ hibi_full_in_to_the_n2h2_chan_0 <= full_to_n(0);
+ hibi_full_in_to_the_n2h2_chan_1 <= full_to_n(1);
+ hibi_full_in_to_the_n2h2_chan_2 <= full_to_n(2);
+
+
+
+ hibiv3_r4_1: entity work.hibiv3_r4
+ generic map (
+ id_width_g => 6,
+ addr_width_g => 32,
+ data_width_g => 32,
+ comm_width_g => 5,
+ counter_width_g => 8,
+ rel_agent_freq_g => 1,
+ rel_bus_freq_g => 1,
+ arb_type_g => 3,
+ fifo_sel_g => 0,
+ rx_fifo_depth_g => 4,
+ rx_msg_fifo_depth_g => 4,
+ tx_fifo_depth_g => 4,
+ tx_msg_fifo_depth_g => 4,
+ max_send_g => 20,
+ n_cfg_pages_g => 1,
+ n_time_slots_g => 0,
+ keep_slot_g => 0,
+ n_extra_params_g => 1,
+ cfg_re_g => 1,
+ cfg_we_g => 1,
+ debug_width_g => 1,
+ n_agents_g => 3,
+ n_segments_g => 1,
+ separate_addr_g => 0)
+ port map (
+ clk_ip => clk_0,
+ clk_noc => clk_0,
+ rst_n => reset_n,
+ agent_comm_in => comm_from_n,
+ agent_data_in => data_from_n,
+ agent_av_in => av_from_n,
+ agent_we_in => we_from_n,
+ agent_re_in => re_from_n,
+ agent_comm_out => comm_to_n,
+ agent_data_out => data_to_n,
+ agent_av_out => av_to_n,
+ agent_full_out => full_to_n,
+ agent_one_p_out => one_p_to_n,
+ agent_empty_out => empty_to_n,
+ agent_one_d_out => one_d_to_n);
+
+
+ cpu_reset_p: process
+ begin -- process cpu_reset_p
+
+ cpu_0_reset <= '1';
+ cpu_1_reset <= '1';
+ cpu_2_reset <= '1';
+
+ wait for 100 us;
+
+ cpu_0_reset <= '0';
+ cpu_1_reset <= '0';
+ cpu_2_reset <= '0';
+
+ wait;
+
+ end process cpu_reset_p;
+
+
+-- AND HERE WILL BE PRESERVED
+
+
+end europa;
+
+
+
+--synthesis translate_on
Index: TUT/ip.hwp.communication/n2h2/tb/system/support/basic_waves.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/support/basic_waves.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/support/basic_waves.do (revision 16)
@@ -0,0 +1,784 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider Top
+add wave -noupdate -format Logic /test_bench/clk_0
+add wave -noupdate -format Logic /test_bench/cpu_resetrequest_to_the_cpu_0
+add wave -noupdate -format Logic /test_bench/cpu_resetrequest_to_the_cpu_1
+add wave -noupdate -format Logic /test_bench/cpu_resetrequest_to_the_cpu_2
+add wave -noupdate -format Logic /test_bench/cpu_resettaken_from_the_cpu_0
+add wave -noupdate -format Logic /test_bench/cpu_resettaken_from_the_cpu_1
+add wave -noupdate -format Logic /test_bench/cpu_resettaken_from_the_cpu_2
+add wave -noupdate -color Tan -format Logic /test_bench/hibi_av_in_to_the_n2h2_chan_0
+add wave -noupdate -color Tan -format Logic /test_bench/hibi_av_in_to_the_n2h2_chan_1
+add wave -noupdate -color Tan -format Logic /test_bench/hibi_av_in_to_the_n2h2_chan_2
+add wave -noupdate -color Gold -format Logic /test_bench/hibi_av_out_from_the_n2h2_chan_0
+add wave -noupdate -color Gold -format Logic /test_bench/hibi_av_out_from_the_n2h2_chan_1
+add wave -noupdate -color Gold -format Logic /test_bench/hibi_av_out_from_the_n2h2_chan_2
+add wave -noupdate -format Literal /test_bench/hibi_comm_in_to_the_n2h2_chan_0
+add wave -noupdate -format Literal /test_bench/hibi_comm_in_to_the_n2h2_chan_1
+add wave -noupdate -format Literal /test_bench/hibi_comm_in_to_the_n2h2_chan_2
+add wave -noupdate -format Literal /test_bench/hibi_comm_out_from_the_n2h2_chan_0
+add wave -noupdate -format Literal /test_bench/hibi_comm_out_from_the_n2h2_chan_1
+add wave -noupdate -format Literal /test_bench/hibi_comm_out_from_the_n2h2_chan_2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_in_to_the_n2h2_chan_0
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_in_to_the_n2h2_chan_1
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_in_to_the_n2h2_chan_2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_out_from_the_n2h2_chan_0
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_out_from_the_n2h2_chan_1
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_out_from_the_n2h2_chan_2
+add wave -noupdate -format Logic /test_bench/hibi_empty_in_to_the_n2h2_chan_0
+add wave -noupdate -format Logic /test_bench/hibi_empty_in_to_the_n2h2_chan_1
+add wave -noupdate -format Logic /test_bench/hibi_empty_in_to_the_n2h2_chan_2
+add wave -noupdate -color Orchid -format Logic /test_bench/hibi_full_in_to_the_n2h2_chan_0
+add wave -noupdate -color Orchid -format Logic /test_bench/hibi_full_in_to_the_n2h2_chan_1
+add wave -noupdate -color Orchid -format Logic /test_bench/hibi_full_in_to_the_n2h2_chan_2
+add wave -noupdate -format Logic /test_bench/hibi_re_out_from_the_n2h2_chan_0
+add wave -noupdate -format Logic /test_bench/hibi_re_out_from_the_n2h2_chan_1
+add wave -noupdate -format Logic /test_bench/hibi_re_out_from_the_n2h2_chan_2
+add wave -noupdate -color Plum -format Logic /test_bench/hibi_we_out_from_the_n2h2_chan_0
+add wave -noupdate -color Plum -format Logic /test_bench/hibi_we_out_from_the_n2h2_chan_1
+add wave -noupdate -color Plum -format Logic /test_bench/hibi_we_out_from_the_n2h2_chan_2
+add wave -noupdate -format Logic /test_bench/reset_n
+add wave -noupdate -format Literal /test_bench/comm_from_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/data_from_n
+add wave -noupdate -format Literal /test_bench/av_from_n
+add wave -noupdate -format Literal /test_bench/we_from_n
+add wave -noupdate -format Literal /test_bench/re_from_n
+add wave -noupdate -format Literal /test_bench/comm_to_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/data_to_n
+add wave -noupdate -format Literal /test_bench/av_to_n
+add wave -noupdate -format Literal /test_bench/full_to_n
+add wave -noupdate -format Literal /test_bench/one_p_to_n
+add wave -noupdate -format Literal /test_bench/empty_to_n
+add wave -noupdate -format Literal /test_bench/one_d_to_n
+add wave -noupdate -divider Hibi_0
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_sync_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_sync_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/rst_n
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_data_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_full_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_lock_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_av_in
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_data_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_av_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_we_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_re_in
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_data_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_full_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_lock_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_av_out
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_data_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_av_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_full_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_one_p_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_empty_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_one_d_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/data_dw_h
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/comm_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/av_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/we_0_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/we_1_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/full_0_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/full_1_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_p_0_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_p_1_h_dw
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/data_0_h_mr
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/comm_0_h_mr
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/data_1_h_mr
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/comm_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/av_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/av_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/re_0_mr_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/re_1_mr_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/empty_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/empty_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_d_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_d_1_h_mr
+add wave -noupdate -divider Hibi_1
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_sync_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_sync_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/rst_n
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_data_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_full_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_lock_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_av_in
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_data_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_av_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_we_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_re_in
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_data_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_full_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_lock_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_av_out
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_data_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_av_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_full_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_one_p_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_empty_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_one_d_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/data_dw_h
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/comm_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/av_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/we_0_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/we_1_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/full_0_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/full_1_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_p_0_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_p_1_h_dw
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/data_0_h_mr
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/comm_0_h_mr
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/data_1_h_mr
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/comm_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/av_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/av_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/re_0_mr_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/re_1_mr_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/empty_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/empty_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_d_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_d_1_h_mr
+add wave -noupdate -divider Hibi_2
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_sync_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_sync_clk
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/rst_n
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_data_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_full_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_lock_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_av_in
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_data_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_av_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_we_in
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_re_in
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_data_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_full_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_lock_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_av_out
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_data_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_av_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_full_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_one_p_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_empty_out
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_one_d_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/data_dw_h
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/comm_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/av_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/we_0_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/we_1_dw_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/full_0_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/full_1_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_p_0_h_dw
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_p_1_h_dw
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/data_0_h_mr
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/comm_0_h_mr
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/data_1_h_mr
+add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/comm_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/av_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/av_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/re_0_mr_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/re_1_mr_h
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/empty_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/empty_1_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_d_0_h_mr
+add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_d_1_h_mr
+add wave -noupdate -divider N2H2_0
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/clk_cfg
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/clk_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/clk_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_addr_out_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_we_out_rx
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_be_out_rx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_writedata_out_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_waitrequest_in_rx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_writedata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_we_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_readdata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_re_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_cs_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_waitrequest_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_addr_out_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_re_out_tx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_readdata_in_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_waitrequest_in_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_readdatavalid_in_tx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_data_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_av_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_empty_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_comm_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_data_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_av_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_full_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_comm_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_we_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/rx_irq_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_start_from_rx
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_comm_from_rx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_mem_addr_from_rx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_hibi_addr_from_rx
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_amount_from_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_status_done_to_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/real_rst_n
+add wave -noupdate -divider {n2h2_0 channels}
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/clk
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_addr_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_we_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_be_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_writedata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_waitrequest_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_data_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_av_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_empty_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_comm_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_writedata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_we_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_readdata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_re_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_cs_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_waitrequest_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/rx_irq_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_start_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_mem_addr_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_hibi_addr_out
+add wave -noupdate -format Literal -radix unsigned /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_amount_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_status_done_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/sender_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_amount_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/control_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_hibi_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_amount_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_comm_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/init_chan_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_chan_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/current_mem_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/current_be_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_be_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/status_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_reset_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_we_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/unknown_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/unknown_rx_irq_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/unknown_rx_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_illegal
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_illegal_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/ignore_tx_write
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/ignored_last_tx_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/curr_chan_avalon_we_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_wes
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/matches
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/matches_cmb
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_ack_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_addr_temp
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_be_temp
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_s
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/cfg_write
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/cfg_reg
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/cfg_tx_reg_used
+add wave -noupdate -divider {n2h_0 tx}
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/clk
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_addr_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_readdata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_waitrequest_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_readdatavalid_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_data_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_av_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_full_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_comm_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_we_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_start_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_status_done_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_hibi_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_ram_addr_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_amount_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/control_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_cnt_en_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_cnt_value_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_cnt_load_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_cnt_en_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_cnt_value_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_cnt_load_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_amount_eq
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_to_stop_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/start_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_write_addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/data_src_sel
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_we_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_stop_we_r
+add wave -noupdate -divider N2H2_1
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/avalon_cfg_addr_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_cfg_we_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_cfg_re_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_cfg_cs_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_cfg_writedata_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_cfg_readdata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/avalon_cfg_waitrequest_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/hibi_data_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_av_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_empty_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/hibi_comm_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/hibi_data_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_av_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_full_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/hibi_comm_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_we_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/clk_cfg
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/rst_n
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/clk_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/clk_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/rx_irq_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_addr_out_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_we_out_rx
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/avalon_be_out_rx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_writedata_out_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_waitrequest_in_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_readdatavalid_in_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_waitrequest_in_tx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_readdata_in_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_re_out_tx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_addr_out_tx
+add wave -noupdate -divider {n2h_1 channels}
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/clk
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_addr_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_we_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_be_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_writedata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_waitrequest_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_data_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_av_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_empty_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_comm_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_re_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_writedata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_we_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_readdata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_re_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_cs_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_waitrequest_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/rx_irq_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_start_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_mem_addr_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_hibi_addr_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_amount_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_status_done_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/sender_addr_r
+add wave -noupdate -format Literal -radix unsigned /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_amount_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/control_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_hibi_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_amount_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_comm_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/init_chan_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_chan_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/current_mem_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/current_be_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_be_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/status_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_reset_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_we_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/unknown_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/unknown_rx_irq_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/unknown_rx_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_illegal
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_illegal_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/ignore_tx_write
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/ignored_last_tx_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/curr_chan_avalon_we_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_wes
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/matches
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/matches_cmb
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_ack_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_addr_temp
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_be_temp
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_s
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/cfg_write
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/cfg_reg
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/cfg_tx_reg_used
+add wave -noupdate -divider {n2h_1 tx}
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/clk
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_addr_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_readdata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_waitrequest_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_readdatavalid_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_data_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_av_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_full_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_comm_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_we_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_start_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_status_done_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_hibi_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_ram_addr_in
+add wave -noupdate -format Literal -radix unsigned /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_amount_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/control_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_cnt_en_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_cnt_value_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_cnt_load_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_cnt_en_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_cnt_value_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_cnt_load_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_amount_eq
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_to_stop_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/start_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_write_addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/data_src_sel
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_we_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_stop_we_r
+add wave -noupdate -divider N2H2_2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_cfg_addr_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_cfg_we_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_cfg_re_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_cfg_cs_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_cfg_writedata_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_cfg_readdata_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/hibi_data_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_av_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_empty_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/hibi_comm_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/hibi_data_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_av_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_full_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/hibi_comm_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_we_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/clk_cfg
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/rst_n
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/clk_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/clk_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/rx_irq_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_addr_out_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_we_out_rx
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/avalon_be_out_rx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_writedata_out_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_waitrequest_in_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_readdatavalid_in_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_waitrequest_in_tx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_readdata_in_tx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_re_out_tx
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_addr_out_tx
+add wave -noupdate -divider {n2h_2 channels}
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/clk
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_addr_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_we_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_be_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_writedata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_waitrequest_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_data_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_av_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_empty_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_comm_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_re_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_writedata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_we_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_readdata_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_re_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_cs_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_waitrequest_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/rx_irq_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_start_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_mem_addr_out
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_hibi_addr_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_amount_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_status_done_in
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/sender_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_amount_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/control_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_hibi_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_amount_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_comm_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/init_chan_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_chan_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/current_mem_addr_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/current_be_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_be_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/status_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_reset_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_we_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/unknown_rx
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/unknown_rx_irq_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/unknown_rx_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_illegal
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_illegal_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/ignore_tx_write
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/ignored_last_tx_r
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/curr_chan_avalon_we_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_wes
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/matches
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/matches_cmb
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_ack_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_addr_temp
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_be_temp
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_s
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/cfg_write
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/cfg_reg
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/cfg_tx_reg_used
+add wave -noupdate -divider {n2h_2 tx}
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/clk
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/rst_n
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_addr_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_re_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_readdata_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_waitrequest_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_readdatavalid_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_data_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_av_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_full_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_comm_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_we_out
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_start_in
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_status_done_out
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_comm_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_hibi_addr_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_ram_addr_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_amount_in
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/control_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_cnt_en_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_cnt_value_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_cnt_load_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_cnt_en_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_cnt_value_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_cnt_load_r
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_amount_eq
+add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_to_stop_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/start_re_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_write_addr_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/data_src_sel
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_we_r
+add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_stop_we_r
+add wave -noupdate -divider jtag_uart_1
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_1/av_address
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_irq
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_read_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_1/av_readdata
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_waitrequest
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_write_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_1/av_writedata
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/dataavailable
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/readyfordata
+add wave -noupdate -divider cpu_2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/i_readdata
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/i_readdatavalid
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/i_waitrequest
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/i_address
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/i_read
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/clk
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/reset_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_readdata
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_waitrequest
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_address
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_byteenable
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_read
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_writedata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_irq
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_readdatavalid
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/cpu_resetrequest
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/cpu_resettaken
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_pcb
+add wave -noupdate -format Literal -radix ascii /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_vinst
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_valid
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_iw
+add wave -noupdate -divider onchip_memory2_1
+add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_1/chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_1/write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_1/address
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_onchip_memory2_1/byteenable
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_1/readdata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_1/writedata
+add wave -noupdate -divider cpu_0
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/i_readdata
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/i_readdatavalid
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/i_waitrequest
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/i_address
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/i_read
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/clk
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/reset_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_readdata
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_waitrequest
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_address
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_byteenable
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_read
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_writedata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_irq
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_readdatavalid
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/cpu_resetrequest
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/cpu_resettaken
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_pcb
+add wave -noupdate -format Literal -radix ascii /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_vinst
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_valid
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_iw
+add wave -noupdate -divider jtag_uart_0
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_0/av_address
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_irq
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_read_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_0/av_readdata
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_waitrequest
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_write_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_0/av_writedata
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/dataavailable
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/readyfordata
+add wave -noupdate -divider onchip_memory2_0
+add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_0/chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_0/write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_0/address
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_onchip_memory2_0/byteenable
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_0/readdata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_0/writedata
+add wave -noupdate -divider shared_mem_0
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/address
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_0/byteenable
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/readdata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/writedata
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/chipselect2
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/write2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/address2
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_0/byteenable2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/readdata2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/writedata2
+add wave -noupdate -divider cpu_1
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/i_readdata
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/i_readdatavalid
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/i_waitrequest
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/i_address
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/i_read
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/clk
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/reset_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_readdata
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_waitrequest
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_address
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_byteenable
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_read
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_writedata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_irq
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_readdatavalid
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/cpu_resetrequest
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/cpu_resettaken
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_pcb
+add wave -noupdate -format Literal -radix ascii /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_vinst
+add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_valid
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_iw
+add wave -noupdate -divider jtag_uart_2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_2/av_address
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_irq
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_read_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_2/av_readdata
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_waitrequest
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_write_n
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_2/av_writedata
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/dataavailable
+add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/readyfordata
+add wave -noupdate -divider shared_mem_2
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/address
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_2/byteenable
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/readdata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/writedata
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/chipselect2
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/write2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/address2
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_2/byteenable2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/readdata2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/writedata2
+add wave -noupdate -divider shared_mem_1
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/address
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_1/byteenable
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/readdata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/writedata
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/chipselect2
+add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/write2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/address2
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_1/byteenable2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/readdata2
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/writedata2
+add wave -noupdate -divider onchip_memory2_2
+add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_2/chipselect
+add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_2/write
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_2/address
+add wave -noupdate -format Literal -radix binary /test_bench/dut/the_onchip_memory2_2/byteenable
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_2/readdata
+add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_2/writedata
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {29713541667 ps} 0}
+configure wave -namecolwidth 240
+configure wave -valuecolwidth 168
+configure wave -justifyvalue right
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ms
+update
+WaveRestoreZoom {0 ps} {105 ms}
Index: TUT/ip.hwp.communication/n2h2/tb/system/support/msim_includes.txt
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/support/msim_includes.txt (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/support/msim_includes.txt (revision 16)
@@ -0,0 +1,23 @@
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/hibiv3_pkg.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/addr_data_demux_read.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/addr_data_mux_write.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/addr_decoder.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/cfg_init_pkg.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/cfg_mem.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/double_fifo_demux_wr.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/double_fifo_mux_rd.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/dyn_arb.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/fifo_demux_wr.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/fifo_mux_rd.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/hibi_wrapper_r1.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/hibi_wrapper_r4.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/lfsr.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/receiver.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/rx_control.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/transmitter.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/tx_control.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/vhd/hibi_bridge_v2.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/interconnections/hibi_v3/tb/sad_tb/hibiv3_r4.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/memories/fifos/fifo.vhd
+vcom -93 -explicit ABSOLUTE_PATH/svn/koski/lib/hw_lib/ips/memories/fifos/multi_clk/Vhdl/multiclk_fifo_v4.vhd
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/support.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/support.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/support.h (revision 16)
@@ -0,0 +1,48 @@
+/*
+ *
+ * Author : Lasse Lehtonen
+ * Last modification : 29.03.2011
+ *
+ * N2H support functions
+ *
+ */
+
+/* NB
+ *
+ * Remember to #define N2H2_CHAN_BASE as N2H's base address
+ * Also #define N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID and
+ * #define N2H2_CHAN_IRQ
+ *
+ */
+
+#ifndef SUPPORT_H
+#define SUPPORT_H
+
+#include "n2h_isr_fifo.h"
+#include "system.h"
+#include "N2H_registers_and_macros.h"
+#include "tut_n2h_regs.h"
+
+#define N2H2_CHAN_BASE N2H2_CHAN_0_BASE
+#define N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID N2H2_CHAN_0_IRQ_INTERRUPT_CONTROLLER_ID
+#define N2H2_CHAN_IRQ N2H2_CHAN_0_IRQ
+
+
+/* where to read how much target address */
+void n2h_send(int data_src_addr, int amount, int hibi_addr);
+
+/* which channel where to store, amount address to match*/
+void n2h_init_rx(int rx_channel, int rx_addr, int rx_amount, int hibi_addr);
+
+/* Returns the position of the first occurrence of '1' from LSB (rigth)*/
+int onehot2int(int num);
+
+/* ISR handler */
+void n2h2_isr(void* context);
+
+/* Init interrupt service */
+void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo);
+
+
+#endif
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/tut_n2h_regs.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/tut_n2h_regs.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/tut_n2h_regs.c (revision 16)
@@ -0,0 +1,179 @@
+#include "tut_n2h_regs.h"
+#include "N2H_registers_and_macros.h"
+
+
+#if defined(API)
+struct Channel_reservation {
+
+ int mem_addr;
+ int amount;
+
+};
+
+static struct Channel_reservation
+ channel_reservations[N2H_NUMBER_OF_CHANNELS] = {};
+
+
+// Common interrupt service routine. Clear IRQ and call N2H_RX_DONE.
+void isr() {
+
+ int chan = N2H_GET_IRQ_CHAN(N2H_REGISTERS_BASE_ADDRESS);
+ N2H_RX_DONE( chan, channel_reservations[chan].mem_addr, channel_reservations[chan].amount );
+ channel_reservations[chan].mem_addr = 0;
+ channel_reservations[chan].amount = 0;
+ N2H_RX_CLEAR_IRQ(chan,N2H_REGISTERS_BASE_ADDRESS);
+}
+
+
+
+// eCos specific interrupt handling
+#if defined(ECOS)
+#include
+#include
+#include
+
+static cyg_interrupt l_rxIrq;
+static cyg_handle_t l_rxIrqHandle;
+extern void cyg_interrupt_post_dsr(CYG_ADDRWORD intr_handle);
+
+cyg_uint32 RxIrqIsr(cyg_vector_t vector, cyg_addrword_t data) {
+ cyg_interrupt_mask(vector);
+ cyg_interrupt_post_dsr(l_rxIrqHandle);
+ return (CYG_ISR_HANDLED);
+}
+
+void RxIrqDsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
+ isr();
+ cyg_interrupt_unmask(vector);
+
+}
+
+
+// NIOSII specific interrupt handling
+#else
+void n2h_isr( void* context, int id ) {
+ isr();
+}
+#endif
+
+void N2H_INIT_ISR() {
+
+// eCos specific interrupt init
+#if defined(ECOS)
+ cyg_interrupt_create(
+ N2H_RX_IRQ,
+ N2H_RX_IRQ_PRI,
+ 0,
+ &RxIrqIsr,
+ &RxIrqDsr,
+ &l_rxIrqHandle,
+ &l_rxIrq);
+ cyg_interrupt_attach(l_rxIrqHandle);
+ cyg_interrupt_unmask(N2H_RX_IRQ);
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+
+// NIOSII specific interrupt init
+#else
+ alt_irq_register( N2H_RX_IRQ, 0, n2h_isr );
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+#endif
+}
+
+void N2H_GET_RX_BUFFER( int* dst, int src, int amount ) {
+
+ // TODO: check that src is inside RX buffer
+ // TODO: if src and dst are same, do nothing
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *(dst + i) = *((int*)src + i);
+ }
+}
+
+void N2H_PUT_TX_BUFFER( int dst, int* src, int amount ) {
+
+ // TODO: check that dst is inside TX buffer
+ // TODO: if src and dst are same, do nothing
+
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *((int*)dst + i) = *(src + i);
+ }
+
+}
+#endif // API
+
+/*
+* DMA engine configuration functions (Updated on 27/04/2005)
+*/
+
+// Prepare channel for receiving data.
+void N2H_CHAN_CONF(int channel, int dst_mem_addr, int rx_haddr, int amount,
+ int* base)
+{
+#ifdef API
+ channel_reservations[channel].mem_addr = dst_mem_addr;
+ channel_reservations[channel].amount = amount;
+#endif
+ N2H_CHAN_MEM_ADDR(channel, dst_mem_addr, base);
+ N2H_CHAN_HIBI_ADDR(channel, rx_haddr, base);
+ N2H_CHAN_AMOUNT(channel, amount, base);
+ N2H_CHAN_INIT(channel, base);
+}
+
+void N2H_SEND(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE(base);
+ N2H_TX_START(base);
+}
+
+// Parameter types were uint32. Int works in other places, so why not here?
+void N2H_SEND_READ(int mem_addr, int amount, int haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(haddr, base);
+ N2H_TX_COMM_READ(base);
+ N2H_TX_START(base);
+}
+
+void N2H_SEND_MSG(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE_MSG(base);
+ N2H_TX_START(base);
+}
+
+// Return 0 if transmission is not done yet, 1 otherwise.
+int N2H_TX_DONE(int* base) {
+ int y = 0;
+ N2H_GET_TX_DONE(y, base);
+ return y;
+}
+
+void N2H_CLEAR_IRQ(int chan, int* base) {
+ N2H_RX_CLEAR_IRQ(chan, base);
+}
+
+// Returns first channel number which has IRQ flag up.
+// If no interrupts have been received -1 is returned.
+int N2H_GET_IRQ_CHAN(int* base)
+{
+ volatile int * apu = base + 7;
+ int irq_reg = *apu;
+ int mask = 1;
+ int shift = 0;
+ for (shift = 0; shift < 32; shift++) {
+ if ((irq_reg & (mask << shift)) != 0) {
+ return shift;
+ }
+ }
+ return -1;
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/main.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/main.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/main.c (revision 16)
@@ -0,0 +1,213 @@
+/*
+ * main.c
+ *
+ * Created on: 21.2.2011
+ * Author: Lasse Lehtonen
+ */
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "system.h"
+#include "alt_types.h"
+
+#include "N2H_registers_and_macros.h"
+#include "tut_n2h_regs.h"
+
+#include "n2h_isr_fifo.h"
+
+#include "support.h"
+
+
+int main()
+{
+ int n_received = 0;
+ int rx_data[20];
+
+ int rx_amount = 8;
+ int tx_amount = 8;
+ int send = 0;
+
+ int channels[8] = {1, 0, 0, 0, 0, 0, 0, 0};
+
+ N2H_isr_fifo* n2h_isr_fifo = n2h_isr_fifo_create();
+
+ // Init N2H interrupt
+ n2h_isr_init(n2h_isr_fifo);
+
+ // Initialize n2h rx_channel 0 to store 8 incoming words to 0x10 to
+ // rx buffer with offset 0
+ n2h_init_rx(0, 8*0, 8, 0x10);
+
+ printf("CPU0: starts\n");
+
+
+ while(1)
+ {
+ if(n2h_isr_fifo_size(n2h_isr_fifo))
+ {
+ N2H_isr_info* info = n2h_isr_fifo_pop(n2h_isr_fifo);
+
+ switch(info->isr_type)
+ {
+ case RX_READY:
+
+ printf("CPU0: received %ith packet to channel %i\n",
+ ++n_received, info->rx_channel);
+
+ if(channels[info->rx_channel] == 2)
+ {
+ channels[info->rx_channel] = 0;
+ break;
+ }
+
+ memcpy((int*)rx_data, (int*)(N2H_REGISTERS_RX_BUFFER_START +
+ info->rx_channel * rx_amount *
+ sizeof(int)),
+ rx_amount*sizeof(int));
+
+ printf("CPU0: read data from channel %i : %X %X %X %X %X "
+ "%X %X %X\n",
+ info->rx_channel, rx_data[0], rx_data[1], rx_data[2],
+ rx_data[3], rx_data[4], rx_data[5], rx_data[6],
+ rx_data[7]);
+
+ channels[info->rx_channel] = 0;
+
+ // Init rx chan half the time
+ int src = (rand() % 2 == 0) ? 0x10 : 0x20;
+ if(rand() % 2 == 0)
+ {
+ int i = 0;
+
+ for(i = 0; i < 5; ++i)
+ {
+ if(channels[i] == 0)
+ {
+ channels[i] = 1;
+ n2h_init_rx(i, 8*i*sizeof(int), 8, i);
+ break;
+ }
+ }
+ }
+
+ send++;
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU0: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+
+ break;
+
+ case RX_UNKNOWN:
+ {
+ int cha = 0;
+
+ for(cha = 0; cha < 8; ++cha)
+ {
+ if(channels[cha] == 0)
+ {
+ channels[cha] = (info->dst_address == 0x1FF) ? 2 : 1;
+
+ printf("CPU0: received data to unconfigured "
+ "address 0x%X, assigning to channel %i\n",
+ info->dst_address, cha);
+
+ if(!(0x00 <= info->dst_address &&
+ info->dst_address <= 0x1FF))
+ {
+ printf("CPU0: %i is invalid address, FAILURE\n",
+ info->dst_address);
+ }
+
+ // Initialize some channel to receive
+ n2h_init_rx(cha, cha * rx_amount*sizeof(int), rx_amount,
+ info->dst_address);
+
+ break;
+ }
+ }
+
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU0: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+
+ }
+ break;
+
+ case TX_IGNORED:
+ {
+ printf("CPU0: A transfer was ignored because it overlapped"
+ " previous one\n");
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU0: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+ }
+ break;
+ }
+
+ // Free memory
+ free(info); info = NULL;
+ }
+ else if (send > 0 && (((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 1))
+ {
+ // Sent packet to a random target's random address
+ int target_addr;
+ int tx_data[8];
+ int tx_slot = (rand() % 8);
+ int cha;
+
+ if(rand() % 2 == 0)
+ {
+ target_addr = 0x200 + tx_slot;
+ }
+ else
+ {
+ target_addr = 0x400 + tx_slot;
+ }
+
+ for(cha = 0; cha < 8; ++cha)
+ tx_data[cha] = 0x80000000 | ((cha+1) << 16) | target_addr;
+
+ memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int)),
+ (int*)tx_data, tx_amount*sizeof(int));
+
+ printf("CPU0: sending packet to 0x%X\n", target_addr);
+
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int),
+ tx_amount, target_addr);
+
+ send--;
+
+ // Overlapping with previous one, 50% change
+ if((rand() % 100) < 50)
+ {
+ n2h_send(N2H_REGISTERS_TX_BUFFER_START +
+ tx_slot*tx_amount*sizeof(int),
+ tx_amount, 0x3FF);
+ printf("CPU0: sending hazard packet\n");
+ }
+ int fre = 0;
+ int x = 0;
+ for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
+ printf("CPU0: %i to send, %i in FIFO, %i channels free\n",
+ send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
+ }
+ }
+
+ printf("CPU0: retires!\n");
+ while(1); return 0;
+}
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/n2h_isr_fifo.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/n2h_isr_fifo.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/n2h_isr_fifo.c (revision 16)
@@ -0,0 +1,76 @@
+/*
+ *
+ * Fifo for saving interrupt information, implementation
+ *
+ * Lasse Lehtonen
+ *
+ */
+
+
+
+#include "n2h_isr_fifo.h"
+
+#include
+#include
+
+
+// Store item to last place, called only from ISR
+void n2h_isr_fifo_push(N2H_isr_fifo* fifo, N2H_isr_info* item)
+{
+ N2H_isr_info* temp = fifo->root;
+
+ item->next = NULL;
+
+ while(temp != NULL && temp->next != NULL)
+ {
+ temp = temp->next;
+ }
+
+ if(fifo->size < 1)
+ {
+ fifo->root = item;
+ }
+ else
+ {
+ temp->next = item;
+ }
+
+ fifo->size++;
+}
+
+// Returns the first item, remember to free its memory!
+N2H_isr_info* n2h_isr_fifo_pop (N2H_isr_fifo* fifo)
+{
+ N2H_isr_info* temp;
+
+ // Prevent ISR from messing with fifo
+ alt_irq_context cntx = alt_irq_disable_all();
+ {
+ if(fifo->size < 1)
+ {
+ return NULL;
+ }
+ temp = fifo->root;
+ fifo->root = temp->next;
+ fifo->size--;
+ temp->next = NULL;
+ }
+ alt_irq_enable_all(cntx);
+
+ return temp;
+}
+
+int n2h_isr_fifo_size(N2H_isr_fifo* fifo)
+{
+ return fifo->size;
+}
+
+N2H_isr_fifo* n2h_isr_fifo_create()
+{
+ //Allocate space for new and initialize data
+ N2H_isr_fifo* fifo = (N2H_isr_fifo*) malloc(sizeof(N2H_isr_fifo));
+ fifo->root = NULL;
+ fifo->size = 0;
+ return fifo;
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/tut_n2h_regs.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/tut_n2h_regs.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/tut_n2h_regs.h (revision 16)
@@ -0,0 +1,209 @@
+/*
+* History:
+* 10/08/2005 by ollil
+* + Copied minor modifications implemented by Ari.
+* This fixed a crash bug in DCT HW based system
+* 03/10/2008 by tapiok
+* fixed N2H_RX_IRQ_DIS
+* 08/2009 kojo2
+* Added following functions: N2H_INIT_ISR, N2H_RX_DONE,
+* N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER
+*/
+#ifndef __tut_n2h_regs_h_
+#define __tut_n2h_regs_h_
+
+#ifdef NIOS_II
+#include "io.h"
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)
+#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)
+#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))
+#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 | (IORD(base,4))))
+#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))
+#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)
+#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)
+#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)
+#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)
+#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)
+#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)
+#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)
+#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)
+#define N2H_TX_COMM_READ(base) IOWR(base,10,4)
+#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)
+#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)
+#define N2H_TX_START(base) IOWR(base, 4, (0x1 | (IORD(base,4))))
+#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)
+#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))
+#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))
+
+
+#else
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 1; \
+ *apu=hibi_addr; \
+ }
+
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4); \
+ *apu=addr; \
+ }
+
+#define N2H_CHAN_AMOUNT(chan, amount, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 2; \
+ *apu=amount; \
+ }
+
+#define N2H_CHAN_INIT(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ *apu=1 << (chan); \
+ }
+
+#define N2H_RX_IRQ_ENA(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu | 0x2; \
+ }
+
+#define N2H_RX_IRQ_DIS(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu & 0xfffffffd; \
+ }
+
+#define N2H_GET_STAT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu >> 16; \
+ }
+
+#define N2H_GET_CONF_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu & 0x0000ffff; \
+ }
+
+#define N2H_GET_INIT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ var = *apu; \
+ }
+
+#define N2H_GET_IRQ_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ var = *apu; \
+ }
+
+#define N2H_GET_CURR_PTR(var, chan, base) \
+ { \
+ volatile int * apu = (int*)base + 3; \
+ apu = apu + ((chan) << 4); \
+ var = *apu; \
+ }
+
+#define N2H_TX_MEM_ADDR(addr, base) \
+ { \
+ volatile int * apu = (int*)base + 8; \
+ *apu = addr; \
+ }
+
+#define N2H_TX_AMOUNT(amount, base) \
+ { \
+ volatile int * apu = (int*)base + 9; \
+ *apu = amount; \
+ }
+
+#define N2H_TX_HIBI_ADDR(haddr, base) \
+ { \
+ volatile int * apu = (int*)base + 11; \
+ *apu = haddr; \
+ }
+
+#define N2H_TX_COMM(comm, base) \
+ { \
+ volatile int * apu = (int*)base +10; \
+ *apu = comm; \
+ }
+
+#define N2H_TX_COMM_WRITE(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 2; \
+ }
+
+#define N2H_TX_COMM_READ(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 4; \
+ }
+
+#define N2H_TX_COMM_WRITE_MSG(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 3; \
+ }
+
+#define N2H_TX_START(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu = *apu | 0x1; \
+ *apu = *apu & 0xfffffffe; \
+ }
+#define N2H_GET_TX_DONE(y, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ y = *apu >> 16; \
+ y = y & 0x1; \
+ }
+
+#define N2H_RX_CLEAR_IRQ(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ *apu = 1 << (chan); \
+ }
+
+
+
+#endif
+
+
+#ifdef API
+extern void N2H_INIT_ISR();
+extern void N2H_RX_DONE( int chan, int mem_addr, int amount );
+extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );
+extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );
+#endif
+
+
+/*
+* DMA engine configuration
+*/
+
+extern void N2H_CHAN_CONF( int channel,
+ int mem_addr,
+ int rx_addr,
+ int amount,
+ int* base );
+
+extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);
+
+extern int N2H_TX_DONE(int* base);
+
+extern void N2H_CLEAR_IRQ(int chan, int* base);
+
+extern int N2H_GET_IRQ_CHAN(int* base);
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/N2H_registers_and_macros.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/N2H_registers_and_macros.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/N2H_registers_and_macros.h (revision 16)
@@ -0,0 +1,47 @@
+// *****************************************************************************
+// File : N2H_registers_and_macros.h
+// Author : Tero Arpinen
+// Date : 22.12.2004
+// Decription : This file contains customizable register address
+// definitions
+// for N2H interface and some needed macros
+//
+// Version history : 22.12.2004 tar Original version
+// : 06.07.2005 tar Modified to work with N2H2
+// : 02.10.2009 tko Removed unneeded macros
+// *****************************************************************************
+
+#ifndef N2H_REGISTERS_AND_MACROS_H
+#define N2H_REGISTERS_AND_MACROS_H
+
+// DEFINE FOLLOWING REGISTERS ACCORDING TO NIOS OR NIOS II HARDWARE
+// CONFIGURATION
+
+// N2H2 Avalon slave base address
+#define N2H_REGISTERS_BASE_ADDRESS ((void*) (0x80000000 | N2H2_CHAN_0_BASE))
+
+// Buffer start address in cpu's memory
+#define N2H_REGISTERS_BUFFER_START (0x80000000 | SHARED_MEM_0_BASE)
+
+// Writeable registers
+// set bit 31 to 1 so that writes and reads bypass cache
+#define N2H_REGISTERS_TX_BUFFER_START (0x80000000 | SHARED_MEM_0_BASE)
+
+#define N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH (0x00000400)
+#define N2H_REGISTERS_TX_BUFFER_END (N2H_REGISTERS_TX_BUFFER_START + \
+ N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH - 1)
+
+// Readable registers
+#define N2H_REGISTERS_RX_BUFFER_START (N2H_REGISTERS_TX_BUFFER_START + N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH)
+#define N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH (0x00000C00)
+#define N2H_REGISTERS_RX_BUFFER_END (N2H_REGISTERS_RX_BUFFER_START + \
+ N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH \
+ - 1)
+// N2H Interrupt registers, numbers and priorities
+#define N2H_RX_IRQ (2)
+#define N2H_RX_IRQ_PRI (3)
+
+// N2H Channels
+#define N2H_NUMBER_OF_CHANNELS (8)
+
+#endif // N2H_REGISTERS_AND_MACROS_H
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/n2h_isr_fifo.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/n2h_isr_fifo.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/n2h_isr_fifo.h (revision 16)
@@ -0,0 +1,44 @@
+/*
+ *
+ * Fifo for saving interrupt information, header
+ *
+ * Lasse Lehtonen
+ *
+ */
+
+#ifndef N2H_ISR_FIFO_HH
+#define N2H_ISR_FIFO_HH
+
+// Tells what caused N2H2 to interrupt
+typedef enum {RX_READY, RX_UNKNOWN, TX_IGNORED} N2H_isr_type;
+
+
+// Item stored in fifo
+typedef struct N2H_isr_info N2H_isr_info;
+typedef struct N2H_isr_info
+{
+ N2H_isr_type isr_type;
+ union {
+ int rx_channel;
+ int dst_address;
+ };
+
+ N2H_isr_info* next;
+};
+
+
+typedef struct
+{
+ N2H_isr_info* root;
+ volatile int size;
+
+} N2H_isr_fifo;
+
+// used fifo item to store
+void n2h_isr_fifo_push(N2H_isr_fifo* fifo, N2H_isr_info* item);
+N2H_isr_info* n2h_isr_fifo_pop(N2H_isr_fifo* fifo);
+int n2h_isr_fifo_size(N2H_isr_fifo* fifo);
+// Creates new fifo
+N2H_isr_fifo* n2h_isr_fifo_create();
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/support.c
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/support.c (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/system/scr_cpu0/support.c (revision 16)
@@ -0,0 +1,137 @@
+/*
+ *
+ * Author : Lasse Lehtonen
+ * Last modification : 29.03.2011
+ *
+ * N2H support functions
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "support.h"
+
+
+void n2h_send(int data_src_addr, int amount, int hibi_addr)
+{
+ // Poll N2H, until it's not sending previous tx anymore
+ //while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) { }
+ // Set data source address
+ IOWR(N2H2_CHAN_BASE, 8, data_src_addr);
+ // Set amount to send
+ IOWR(N2H2_CHAN_BASE, 9, amount);
+ // Set target hibi command
+ IOWR(N2H2_CHAN_BASE, 10, 2);
+ // Set target hibi address
+ IOWR(N2H2_CHAN_BASE, 11, hibi_addr);
+ // Start the transfer
+ IOWR(N2H2_CHAN_BASE, 4, (0x1 | (IORD(N2H2_CHAN_BASE,4))));
+}
+
+
+void n2h_init_rx(int rx_channel, int rx_addr, int rx_amount, int hibi_addr)
+{
+ // Set receive mem address for incoming data
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4), N2H_REGISTERS_RX_BUFFER_START +
+ rx_addr);
+ // Set amount to receive
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4) + 2, rx_amount);
+ // Set hibi address to receive data
+ IOWR(N2H2_CHAN_BASE, (rx_channel << 4) + 1, hibi_addr);
+ // Initialize receiving
+ IOWR(N2H2_CHAN_BASE, 5 , 1 << rx_channel);
+}
+
+
+
+int onehot2int(int num)
+{
+ int i = 0;
+ for(; i < 31; ++i)
+ {
+ if(num & (1 << i))
+ {
+ return i;
+ }
+ }
+ return -1;
+}
+
+
+void n2h2_isr(void* context)
+{
+ N2H_isr_fifo* fifo = (N2H_isr_fifo*) context;
+
+ // Read the cause of the interrupt
+ int interrupter = IORD(N2H2_CHAN_BASE, 7);
+
+
+ if((0x80000000 & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = RX_UNKNOWN;
+
+ // Read in incoming hibi address
+ info->dst_address = IORD(N2H2_CHAN_BASE, 12);
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, 0x80000000);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+
+ if((0x40000000 & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = TX_IGNORED;
+
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, 0x40000000);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+
+ while((0x3FFFFFFF & interrupter) != 0)
+ {
+ N2H_isr_info* info = (N2H_isr_info*) malloc(sizeof(N2H_isr_info));
+ info->isr_type = RX_READY;
+
+ // Store interrupted channel
+ info->rx_channel = onehot2int(interrupter);
+ // Clear IRQ
+ IOWR(N2H2_CHAN_BASE, 7, (1 << info->rx_channel));
+
+ interrupter = interrupter & ~(1 << info->rx_channel);
+
+ // Store interrupt information to fifo
+ n2h_isr_fifo_push(fifo, info);
+ }
+}
+
+
+// Init interrupt
+void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo)
+{
+ // Register N2H2 ISR
+ if(alt_ic_isr_register(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID,
+ N2H2_CHAN_IRQ, n2h2_isr, (void*)n2h_isr_fifo, 0)
+ != 0)
+ {
+ printf("CPU0: registering n2h2_isr failed!\n");
+ }
+ // Enable interrupt on CPU side
+ if(alt_ic_irq_enable(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID,
+ N2H2_CHAN_IRQ) != 0)
+ {
+ printf("CPU0: enabling n2h2 interrupt failed!\n");
+ }
+ // Enable interrupts on N2H2 side
+ IOWR(N2H2_CHAN_BASE, 4, (2 | (IORD(N2H2_CHAN_BASE,4))));
+}
+
Index: TUT/ip.hwp.communication/n2h2/tb/tbrx_conf_rx.dat
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/tbrx_conf_rx.dat (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/tbrx_conf_rx.dat (revision 16)
@@ -0,0 +1,3 @@
+1111 1115 12
+1159 1116 12
+1207 1117 12
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/tb/gen_ram_init.sh
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/gen_ram_init.sh (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/gen_ram_init.sh (revision 16)
@@ -0,0 +1,12 @@
+#!/bin/bash
+
+echo
+echo "Generating ram_init.dat, don't mind the possible rm error"
+echo
+
+rm ram_init.dat
+
+for i in {1..102400}
+do
+ echo $i >> ram_init.dat
+done
Index: TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_rx.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_rx.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_rx.do (revision 16)
@@ -0,0 +1,38 @@
+# Configuration file formats:
+#
+# tbrx_conf_hibisend.dat : dest_agent_n, delay, amount
+# tbrx_conf_rx.dat : mem_addr, sender, irq_amount (=words to receive)
+# tbrx_data_file.dat : mem_addr, sender, irq_amount (=words to receive)
+#
+#
+
+
+
+quit -sim
+
+vlib work
+
+# HW files
+
+vcom -check_synthesis -pedantic ../vhd/one_hot_mux.vhd
+vcom -check_synthesis -pedantic ../vhd/step_counter2.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_chan.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_channels.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_tx_vl.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_chan.vhd
+
+
+# TB files
+
+vcom ./blocks/txt_util.vhd
+vcom ./blocks/fifo.vhd
+vcom ./blocks/tb_n2h2_pkg.vhd
+vcom ./blocks/hibi_sender_n2h2.vhd
+vcom ./blocks/avalon_cfg_reader.vhd
+vcom ./blocks/avalon_cfg_writer.vhd
+vcom ./blocks/avalon_reader.vhd
+vcom ./blocks/sram_scalable_v3.vhd
+vcom ./blocks/tb_n2h2_rx.vhd
+
+vsim -t 1ns work.tb_n2h2_rx
+do ./blocks/wave_tb_n2h2_rx.do
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx.do (revision 16)
@@ -0,0 +1,23 @@
+
+quit -sim
+
+vlib work
+
+# HW files
+
+vcom -check_synthesis -pedantic ../vhd/one_hot_mux.vhd
+vcom -check_synthesis -pedantic ../vhd/step_counter2.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_chan.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_channels.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_tx_vl.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_chan.vhd
+
+
+# TB files
+
+
+vcom ./blocks/sram_scalable_v3.vhd
+vcom ./blocks/tb_n2h2_rx.vhd
+
+vsim -t 1ns work.tb_n2h2_tx
+do blocks/wave_tb_n2h2_tx.do
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/tb/_readme.txt
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/_readme.txt (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/_readme.txt (revision 16)
@@ -0,0 +1,24 @@
+
+** SYSTEM LEVEL TESTBENCHES **
+
+Refer to doc/building_test_system.pptx for building the necessary SOPC
+and NIOS II projects to simulate these tests.
+
+
+** BLOCK LEVEL TESTBENCHES **
+
+Run setup*.do files in modelsim to create work lib, compile files and
+setup some waves for you.
+
+gen_ram_init.sh: to create ram_init.dat needed by some of the testbenches
+
+tb_n2h2_rx: halts on fourth rx on purpose, modify .dat files to change
+behaviour.
+
+Configuration file formats: (only used in tb_n2h2_rx)
+
+tbrx_conf_hibisend.dat : dest_agent_n, delay, amount
+tbrx_conf_rx.dat : mem_addr, sender, irq_amount (=words to receive)
+tbrx_data_file.dat : mem_addr, sender, irq_amount (=words to receive)
+
+
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_pkg.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_pkg.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_pkg.vhd (revision 16)
@@ -0,0 +1,107 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+--use work.txt_util.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+
+package tb_n2h2_pkg is
+
+ procedure read_data_file (
+ data : out integer;
+ file file_txt : text);
+
+ procedure read_conf_file (
+ mem_addr : out integer;
+ sender : out integer;
+ irq_amount : out integer;
+-- max_amount : out integer;
+ file file_txt : text);
+
+ function log2 (
+ constant x : integer)
+ return integer;
+
+
+ type addr_array is array (0 to 7) of integer;
+-- constant addresses_c : addr_array := (16#1000000#, 16#3000000#, 16#5000000#, 16#7000000#, 16#9000000#, 16#b000000#, 16#d000000#, 16#f000000#);
+ constant addresses_c : addr_array := (1111, 3333, 5555, 16#7000000#, 16#9000000#, 16#b000000#, 16#d000000#, 16#f000000#);
+-- constant ava_addresses_c : addr_array := (1000000, 3000000, 5000000, 7000000, 9000000, 11000000, 13000000, 15000000);
+ constant ava_addresses_c : addr_array := (1111,3333,5555, 7000000, 9000000, 11000000, 13000000, 15000000);
+
+ constant conf_bits_c : integer := 4; -- number of configuration bits in CPU
+
+end tb_n2h2_pkg;
+
+package body tb_n2h2_pkg is
+
+
+ procedure read_data_file (
+ data : out integer;
+ file file_txt : text) is
+ variable file_row : line;
+ variable file_sample : integer;
+ begin -- read_data_file
+ readline(file_txt, file_row);
+ read(file_row, file_sample);
+ data := file_sample;
+ end read_data_file;
+
+ procedure read_conf_file (
+ mem_addr : out integer;
+ sender : out integer;
+ irq_amount : out integer;
+-- max_amount : out integer;
+ file file_txt : text) is
+ variable file_row : line;
+ variable file_sample : integer;
+ variable file_sample_hex : std_logic_vector(31 downto 0);
+ variable good : boolean ;
+ begin -- read_data_file
+ readline(file_txt, file_row);
+
+-- hread(file_row, file_sample_hex);
+-- mem_addr := conv_integer(file_sample_hex);
+-- hread(file_row, file_sample_hex);
+-- sender := conv_integer(file_sample_hex);
+ read(file_row,file_sample,good);
+ assert good report "ei oo hyvä" severity note;
+ mem_addr := file_sample;
+ read(file_row, file_sample);
+ sender := file_sample;
+ read(file_row, file_sample);
+ irq_amount := file_sample;
+-- read(file_row, file_sample);
+-- max_amount := file_sample;
+ end read_conf_file;
+
+
+
+ function log2 (
+ constant x : integer)
+ return integer is
+
+ variable tmp_v : integer := 1;
+ variable i_v : integer := 0;
+ begin -- log2
+ report "x is " & integer'image(x);
+
+ for i in 0 to 31 loop
+ if tmp_v >= x then
+ -- report "ceil(log2(x)) is " & integer'image(i);
+
+ return i;
+ end if;
+ tmp_v := tmp_v * 2;
+
+ end loop; -- i
+
+ -- We should not ever come here, return definitely illegal value
+ return -1;
+
+ end log2;
+
+
+end tb_n2h2_pkg;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/sram_scalable_v3.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/sram_scalable_v3.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/sram_scalable_v3.vhd (revision 16)
@@ -0,0 +1,214 @@
+---------------------------------------------------------------------------------
+-- Original code modified by Vesa Lahtinen and Tero Kangas
+-- Both address and data width are now configurable
+--
+-- Modified by Ari Kulmala. Reads in integers and stores them into
+-- consequent addresses, interface modified
+-- to resemble the current scheme.
+--
+-- sram_scalable.vhdl
+--
+-- Original code:
+--
+-- sram64kx8.vhd
+-- standard SRAM vhdl code, 256K*32 Bit,
+-- simplistic model without timing
+-- with startup initialization from file
+--
+-- (C) 1993,1994 Norman Hendrich, Dept. Computer Science
+-- University of Hamburg
+-- 22041 Hamburg, Germany
+-- hendrich@informatik.uni-hamburg.de
+--
+-- initialization code taken and modified from DLX memory-behaviour.vhdl:
+-- Copyright (C) 1993, Peter J. Ashenden
+-- Mail: Dept. Computer Science
+-- University of Adelaide, SA 5005, Australia
+-- e-mail: petera@cs.adelaide.edu.au
+----------------------------------------------------------------------------------
+
+use std.textio.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_signed.all;
+use IEEE.std_logic_arith.all;
+
+entity sram_scalable is
+ generic (
+ rom_data_file_name_g : string := "none";
+ output_file_name_g : string := "none";
+ write_trigger_g : natural := 0; --dumps the memory contents to a file
+ addr_width_g : integer := 0; --width of address bus
+ data_width_g : integer := 0 --width of data bus
+ );
+ port (
+ cs1_n_in : in std_logic; -- not chip select 1
+ cs2_in : in std_logic; -- cs2. both have to be active
+ -- for memory to do something
+ addr_in : in std_logic_vector(addr_width_g-1 downto 0);
+ data_inout : inout std_logic_vector(data_width_g-1 downto 0);
+ we_n_in : in std_logic; -- not write enable
+ oe_n_in : in std_logic -- not output enable
+ );
+end sram_scalable;
+
+
+
+architecture sram_behaviour of sram_scalable is
+begin
+
+ mem : process
+
+ constant low_address_c : natural := 0;
+ constant high_address_c : natural := 2**addr_width_g - 1;
+
+ subtype word is std_logic_vector(data_width_g-1 downto 0);
+
+ type memory_array is
+ array (natural range low_address_c to high_address_c) of word;
+
+ variable mem_v : memory_array;
+
+
+ variable address_v : natural;
+ variable l : line;
+
+
+ ----------------------------------------------------------------------------
+ -- Load initial memory contents from text-file,
+ -- One decimal number per line is read
+ -- First value of line goes to location mem(0), value on 2nd line goes to mem(1) and so on
+ ---------------------------------------------------------------------------
+ procedure load(mem : out memory_array) is
+
+ file binary_file : text is in rom_data_file_name_g;
+ variable l : line;
+ variable a, i : natural;
+ variable val : natural;
+ variable c : integer;
+
+ begin
+
+ -- first initialize the ram array with zeroes
+ for a in low_address_c to high_address_c loop
+ mem(a) := (others => '0');
+ end loop;
+
+ a := low_address_c; -- turha sijoitus?
+
+
+ -- and now read the data file
+ for a in low_address_c to high_address_c loop
+ if not endfile(binary_file) then
+ readline(binary_file, l);
+ read (l, c);
+ -- convert integer value to std_logic_vector and store it into mem
+ mem(a) := conv_std_logic_vector(c, data_width_g);
+ end if;
+ end loop;
+ end load;
+
+
+ ----------------------------------------------------------------------------
+ -- Dump memory contents to a text-file
+ -- Line format: address data
+ -- Nuber format: decimal numbers
+ ---------------------------------------------------------------------------
+ procedure dump(mem : in memory_array) is
+
+ file binary_file : text is out output_file_name_g;
+ variable l : line;
+ variable i : natural;
+ variable val2 : integer;
+
+ begin
+ report "Dump memory contents into txt file";
+ -- and now write the data into a file
+ for i in 0 to high_address_c loop
+ val2 := conv_integer(mem(i));
+ write(l, i);
+ write(l, ' ');
+ write(l, val2);
+ writeline(binary_file, l);
+ end loop;
+ end dump;
+
+
+
+
+ begin -- mem : process
+
+ -- sram initialization:
+ -- first initialize the ram array with zeroes
+ for a in low_address_c to high_address_c loop
+ mem_v(a) := (others => '0');
+ end loop;
+
+
+ if (rom_data_file_name_g /= "none") then
+ load(mem_v);
+ end if;
+
+
+
+
+ ----------------------------------------------------------------------------
+ -- Process memory cycles,
+ -- after init the model stays in this loop forever
+ ---------------------------------------------------------------------------
+ loop
+ --
+ -- wait for chip-select,
+ --
+ if (cs1_n_in = '0') and (cs2_in = '1') then
+
+ -- decode address
+ address_v := conv_integer(unsigned(addr_in));
+
+ if we_n_in = '0' then
+ --- write cycle
+ mem_v(address_v) := data_inout;
+ data_inout <= (others => 'Z');
+
+ elsif we_n_in = '1' then
+ -- read cycle
+ if oe_n_in = '0' then
+ data_inout <= mem_v(address_v);
+ else
+ data_inout <= (others => 'Z');
+ end if;
+
+ else
+ data_inout <= (others => 'Z');
+ end if;
+ else
+ --
+ -- chip not selected, disable output
+ --
+ data_inout <= (others => 'Z');
+ end if;
+
+
+
+ -------------------------
+ -- For debugging: accessing certain location, dumps memory contents to file
+ if address_v = write_trigger_g then
+ if output_file_name_g /= "none" then
+ dump(mem_v);
+ end if;
+ end if;
+ -----------------------
+
+ wait on cs1_n_in, cs2_in, we_n_in, oe_n_in, addr_in, data_inout;
+ end loop;
+ end process;
+
+
+end sram_behaviour;
+
+
+configuration cfg_sram of sram_scalable is
+ for sram_behaviour
+ end for;
+end cfg_sram;
+
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_fo.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_fo.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_fo.do (revision 16)
@@ -0,0 +1,96 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {TB top}
+add wave -noupdate -format Literal /tb_n2h2_tx/test_control
+add wave -noupdate -format Literal /tb_n2h2_tx/test_case_control
+add wave -noupdate -format Logic /tb_n2h2_tx/clk
+add wave -noupdate -format Logic /tb_n2h2_tx/clk2
+add wave -noupdate -format Logic /tb_n2h2_tx/rst_n
+add wave -noupdate -format Logic /tb_n2h2_tx/tx_status_from_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/tx_irq_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/amount_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/amount_vec_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/dpram_vec_addr_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/dpram_addr_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/comm_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_vec_from_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_from_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_av_from_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_full_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_comm_from_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_from_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_addr_from_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_read_from_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_vec_readdata_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_readdata_to_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_n2h_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_readdatavalid_to_n2h_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/counter
+add wave -noupdate -format Literal /tb_n2h2_tx/new_hibi_addr
+add wave -noupdate -format Literal /tb_n2h2_tx/new_amount
+add wave -noupdate -format Literal /tb_n2h2_tx/new_dpram_addr
+add wave -noupdate -format Literal /tb_n2h2_tx/global_hibi_address
+add wave -noupdate -format Literal /tb_n2h2_tx/global_amount
+add wave -noupdate -format Literal /tb_n2h2_tx/global_comm
+add wave -noupdate -format Literal /tb_n2h2_tx/global_dpram_addr
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_data_counter
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_addr_counter
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_amount
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_addr_sent
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_last_addr
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_addr_came
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_counter
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_amount
+add wave -noupdate -divider {DUT tx}
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/clk
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/rst_n
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/avalon_addr_out
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_re_out
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/avalon_readdata_in
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_waitrequest_in
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_readdatavalid_in
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/hibi_data_out
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_av_out
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_full_in
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/hibi_comm_out
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_we_out
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/tx_start_in
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/tx_status_done_out
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_comm_in
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_hibi_addr_in
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_ram_addr_in
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_amount_in
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/control_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/addr_cnt_en_r
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/addr_cnt_value_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/addr_cnt_load_r
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/addr_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/amount_cnt_en_r
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/amount_cnt_value_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/amount_cnt_load_r
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/amount_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/addr_amount_eq
+add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/addr_to_stop_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_re_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/start_re_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_write_addr_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/data_src_sel
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_we_r
+add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_stop_we_r
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {100549517 ns} 0}
+configure wave -namecolwidth 211
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ms
+update
+WaveRestoreZoom {29948127 ns} {164575814 ns}
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_str.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_str.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_str.vhd (revision 16)
@@ -0,0 +1,468 @@
+-------------------------------------------------------------------------------
+-- Title : Testbench for design "n2h2_tx"
+-- Project :
+-------------------------------------------------------------------------------
+-- File : tb_n2h2_tx.vhd
+-- Author : kulmala3
+-- Created : 30.03.2005
+-- Last update: 2011-03-08
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 30.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+-------------------------------------------------------------------------------
+
+entity tb_n2h2_tx is
+
+end tb_n2h2_tx;
+
+-------------------------------------------------------------------------------
+
+architecture rtl of tb_n2h2_tx is
+
+
+ -- component generics
+ constant data_width_g : integer := 32;
+ constant amount_width_g : integer := 16;
+
+
+ constant wait_between_sends_c : integer := 2; -- unit: cycles
+ constant hibi_full_c : integer := 2;
+ constant avalon_waitr_c : integer := 7;
+ --constant avalon_waitr_up_cc_c : integer := 1;
+ constant amount_max_c : integer := 63; -- lingest transfer in words
+ constant incr_hibi_full_after_c : time := 1000000 ns; -- how often HIBI
+ -- goes full
+
+
+ -----------------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------------
+ -- clock and reset
+ signal Clk : std_logic;
+ signal Clk2 : std_logic; -- turha kello?
+ signal Rst_n : std_logic;
+ constant Period : time := 10 ns;
+
+ type main_control_type is (idle, send, wait_one);
+ signal main_ctrl_r : main_control_type;
+
+ signal amount_r : std_logic_vector(amount_width_g-1 downto 0);
+ signal mem_addr_r : std_logic_vector(data_width_g-1 downto 0);
+
+
+
+ component n2h2_tx
+ generic (
+ data_width_g : integer;
+ amount_width_g : integer);
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_re_out : out std_logic;
+ avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_readdatavalid_in : in std_logic;
+ avalon_waitrequest_in : in std_logic;
+ hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_out : out std_logic;
+ hibi_full_in : in std_logic;
+ hibi_comm_out : out std_logic_vector(4 downto 0);
+ hibi_we_out : out std_logic;
+ tx_start_in : in std_logic;
+ tx_status_done_out : out std_logic;
+ tx_comm_in : in std_logic_vector(4 downto 0);
+ tx_hibi_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ tx_ram_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0));
+ end component;
+
+
+ signal avalon_ready_r : std_logic;
+
+ signal avalon_addr_from_tx : std_logic_vector(data_width_g-1 downto 0);
+ signal avalon_re_from_tx : std_logic;
+ signal avalon_readdata_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
+
+ signal avalon_waitrequest_to_tx : std_logic;
+ signal avalon_waitrequest_to_tx2 : std_logic;
+ signal avalon_readdatavalid_to_tx : std_logic;
+ signal hibi_data_from_tx : std_logic_vector(data_width_g-1 downto 0);
+ signal hibi_av_from_tx : std_logic;
+ signal hibi_full_to_tx : std_logic := '0';
+ signal hibi_comm_from_tx : std_logic_vector(4 downto 0);
+ signal hibi_we_from_tx : std_logic;
+ signal tx_start_to_tx : std_logic := '0';
+ signal tx_status_done_from_tx : std_logic;
+
+ signal tx_comm_to_tx : std_logic_vector(4 downto 0) := (others => '0');
+
+ signal tx_hibi_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
+ signal tx_ram_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
+ signal tx_amount_to_tx : std_logic_vector(amount_width_g-1 downto 0) := (others => '0');
+
+
+ -----------------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------------
+ constant rom_data_file_name_g : string := "ram_init.dat";
+ constant output_file_name_g : string := "ram_contents.dat";
+ constant write_trigger_g : natural := 16#6543#;
+ constant ram_addr_width_g : integer := 16;
+
+ component sram_scalable
+ generic (
+ rom_data_file_name_g : string;
+ output_file_name_g : string;
+ write_trigger_g : natural;
+ addr_width_g : integer;
+ data_width_g : integer);
+ port (
+ cs1_n_in : in std_logic;
+ cs2_in : in std_logic;
+ addr_in : in std_logic_vector(addr_width_g-1 downto 0);
+ data_inout : inout std_logic_vector(data_width_g-1 downto 0);
+ we_n_in : in std_logic;
+ oe_n_in : in std_logic);
+ end component;
+
+ signal cs1_n_to_ram : std_logic;
+ signal cs2_to_ram : std_logic;
+ signal addr_to_ram : std_logic_vector(ram_addr_width_g-1 downto 0);
+ signal data_inout_ram : std_logic_vector(data_width_g-1 downto 0);
+ signal we_n_to_ram : std_logic;
+ signal oe_n_to_ram : std_logic;
+
+ signal delayed_data_from_ram_r : std_logic_vector(data_width_g-1 downto 0);
+
+
+
+ -----------------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------------
+ signal hibi_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal hibi_amount_r : std_logic_vector(amount_width_g-1 downto 0);
+ signal hibi_data_r : std_logic_vector(data_width_g-1 downto 0);
+ signal avalon_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal avalon_data_r : std_logic_vector(data_width_g-1 downto 0);
+ signal avalon_amount_r : std_logic_vector(amount_width_g-1 downto 0);
+ signal wait_cnt_r : integer range 0 to wait_between_sends_c;
+ signal avalon_waitr_cnt_r : integer range 0 to avalon_waitr_c-1;
+ signal hibi_we_was_up_r : std_logic;
+ -- signal hibi_full_cnt_r : integer range 0 to hibi_full_c;
+ signal hibi_full_cnt_r : integer;
+ signal hibi_ready_r : std_logic;
+
+ signal hibi_full_up_cc : integer := 0;
+
+
+
+begin -- rtl
+
+ cs1_n_to_ram <= '0'; -- avalon_waitrequest_to_tx;
+ cs2_to_ram <= avalon_re_from_tx;
+ addr_to_ram <= conv_std_logic_vector(conv_integer(avalon_addr_from_tx)/4, ram_addr_width_g);
+
+ avalon_waitrequest_to_tx2 <= avalon_waitrequest_to_tx or (not avalon_re_from_tx);
+ avalon_readdata_to_tx <= delayed_data_from_ram_r;
+
+
+ delay_valid : process (clk, rst_n)
+ begin -- process delay_valid
+ if rst_n = '0' then -- asynchronous reset (active low)
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ -- memory latency 2 (note below the same signal assignment)
+ avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
+
+ end if;
+ end process delay_valid;
+ -- memory latency 1
+ -- avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
+
+ we_n_to_ram <= '1';
+ oe_n_to_ram <= '0';
+
+
+ -----------------------------------------------------------------------------
+ -- component instantiation
+ --
+ ------------------------------------------------------------------------------
+ DUT : n2h2_tx
+ generic map (
+ data_width_g => data_width_g,
+ amount_width_g => amount_width_g)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+
+ avalon_addr_out => avalon_addr_from_tx,
+ avalon_re_out => avalon_re_from_tx,
+ avalon_readdata_in => avalon_readdata_to_tx,
+ avalon_waitrequest_in => avalon_waitrequest_to_tx2,
+ avalon_readdatavalid_in => avalon_readdatavalid_to_tx,
+
+ hibi_data_out => hibi_data_from_tx,
+ hibi_av_out => hibi_av_from_tx,
+ hibi_full_in => hibi_full_to_tx,
+ hibi_comm_out => hibi_comm_from_tx,
+ hibi_we_out => hibi_we_from_tx,
+
+ tx_start_in => tx_start_to_tx,
+ tx_status_done_out => tx_status_done_from_tx,
+ tx_comm_in => tx_comm_to_tx,
+ tx_hibi_addr_in => tx_hibi_addr_to_tx,
+ tx_ram_addr_in => tx_ram_addr_to_tx,
+ tx_amount_in => tx_amount_to_tx);
+
+
+
+ -----------------------------------------------------------------------------
+ -- Give commands to the tested block n2h2_tx
+ -- Asks to send longer and longer transfer
+ ------------------------------------------------------------------------------
+ test : process (clk, rst_n)
+ begin -- process test
+ if rst_n = '0' then -- asynchronous reset (active low)
+ tx_start_to_tx <= '0';
+ tx_hibi_addr_to_tx <= X"0000ffff";
+ tx_comm_to_tx <= (others => 'Z'); --'0');
+ tx_ram_addr_to_tx <= (others => 'Z'); -- '0');
+ tx_amount_to_tx <= (others => 'Z'); -- '0');
+ wait_cnt_r <= 0;
+ main_ctrl_r <= idle;
+ amount_r <= conv_std_logic_vector(1, amount_width_g); --(others => '0');
+ mem_addr_r <= (others => '0');
+
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+
+ case main_ctrl_r is
+
+ when idle =>
+ -- Wait that tx is ready then few cycles between asking transfers
+ -- Increase the source memory address for every transfer
+
+ tx_start_to_tx <= '0';
+
+ if tx_status_done_from_tx = '1' then
+ wait_cnt_r <= wait_cnt_r+1;
+
+ if wait_cnt_r = wait_between_sends_c-1 then
+ wait_cnt_r <= 0;
+ main_ctrl_r <= send;
+ if conv_integer(amount_r) > 1 then
+ mem_addr_r <= mem_addr_r+conv_integer(tx_amount_to_tx)*4;
+ else
+ mem_addr_r <= mem_addr_r+conv_integer(tx_amount_to_tx)*4;
+ end if;
+ end if;
+
+ end if;
+
+
+ when send =>
+ -- Ask to send a new transfer
+
+ tx_start_to_tx <= '1';
+ tx_ram_addr_to_tx <= mem_addr_r;
+ tx_hibi_addr_to_tx <= tx_hibi_addr_to_tx+1;
+ tx_amount_to_tx <= amount_r;
+ tx_comm_to_tx <= "00010";
+
+ -- Increase the transfer length for the next time
+ if conv_integer(amount_r) >= amount_max_c then
+ amount_r <= conv_std_logic_vector(1, amount_width_g);
+ else
+ amount_r <= amount_r+1;
+ end if;
+
+ main_ctrl_r <= idle;
+
+
+
+ when others =>
+ end case;
+ end if;
+ end process test;
+
+ -- avalon_readdata_to_tx <= avalon_data_r;
+
+
+ -----------------------------------------------------------------------------
+ -- Instantiate memory block
+ ------------------------------------------------------------------------------
+ sram_scalable_1 : sram_scalable
+ generic map (
+ rom_data_file_name_g => rom_data_file_name_g,
+ output_file_name_g => output_file_name_g,
+ write_trigger_g => write_trigger_g,
+ addr_width_g => ram_addr_width_g,
+ data_width_g => data_width_g)
+ port map (
+ cs1_n_in => cs1_n_to_ram,
+ cs2_in => cs2_to_ram,
+ addr_in => addr_to_ram,
+ data_inout => data_inout_ram,
+ we_n_in => we_n_to_ram,
+ oe_n_in => oe_n_to_ram
+ );
+
+
+
+ -----------------------------------------------------------------------------
+ -- Imitate Avalon switch fabric between mem and n2h2_tx:
+ -- - delay addr going to memory by one cycle
+ -- - delay data coming from memory by one cycle
+ ------------------------------------------------------------------------------
+ avalon : process (clk2, rst_n)
+ begin -- process avalon
+ if rst_n = '0' then -- asynchronous reset (active low)
+ avalon_waitrequest_to_tx <= '1';
+ delayed_data_from_ram_r <= (others => 'Z'); --data_inout_ram;
+ avalon_waitr_cnt_r <= 0;
+
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+
+ if tx_start_to_tx = '1' then
+ avalon_addr_r <= mem_addr_r;
+ end if;
+
+ delayed_data_from_ram_r <= data_inout_ram;
+
+ if avalon_re_from_tx = '1' then
+ if avalon_waitr_cnt_r = avalon_waitr_c-1 then
+ avalon_waitr_cnt_r <= 0;
+ avalon_waitrequest_to_tx <= '1';
+ else
+ avalon_waitr_cnt_r <= avalon_waitr_cnt_r+1;
+ avalon_waitrequest_to_tx <= '0';
+ end if;
+
+ else
+ avalon_waitrequest_to_tx <= '1';
+ end if;
+ end if;
+ --avalon_waitrequest_to_tx <= '0';
+ end process avalon;
+
+
+
+ -----------------------------------------------------------------------------
+ -- Imitate the HIBI wrapper that gets the data from n2h2_tx
+ ------------------------------------------------------------------------------
+ hibi : process (clk, rst_n)
+ begin -- process hibi
+ if rst_n = '0' then -- asynchronous reset (active low)
+ hibi_addr_r <= X"0000ffff";
+ hibi_full_to_tx <= '1';
+ hibi_data_r <= (others => '0');
+ hibi_amount_r <= (others => '0');
+ hibi_full_cnt_r <= 0;
+ hibi_we_was_up_r <= '1';
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+
+ if hibi_we_was_up_r = '1' then
+ hibi_full_cnt_r <= hibi_full_cnt_r+1;
+ hibi_full_to_tx <= '1';
+ if hibi_full_cnt_r = hibi_full_up_cc then
+ hibi_full_to_tx <= '0';
+ hibi_full_cnt_r <= 0;
+ hibi_we_was_up_r <= '0';
+ end if;
+ end if;
+
+
+ if hibi_we_from_tx = '1' then
+ if hibi_full_up_cc > 0 then
+ hibi_full_to_tx <= '1';
+ end if;
+ hibi_we_was_up_r <= '1';
+
+ assert hibi_comm_from_tx /= "00000" report "hibi comm error" severity error;
+
+ if hibi_av_from_tx = '1' then
+ -- address
+ -- +1 because of the main test program value
+ assert hibi_addr_r+1 = hibi_data_from_tx report "hibi addr error" severity error;
+ hibi_addr_r <= hibi_addr_r+1;
+ else
+ -- data
+
+ assert avalon_readdata_to_tx = hibi_data_from_tx report "hibi data error" severity error;
+ if hibi_data_r = 2**ram_addr_width_g-1 then
+ hibi_data_r <= (others => '0');
+ else
+ hibi_data_r <= hibi_data_r+1;
+ end if;
+
+ hibi_amount_r <= hibi_amount_r+1;
+ assert hibi_amount_r <= tx_amount_to_tx report "too many data" severity error;
+ end if;
+ else
+ if main_ctrl_r = send then
+ hibi_amount_r <= (others => '0');
+ end if;
+ end if;
+
+ end if;
+ end process hibi;
+
+
+ -----------------------------------------------------------------------------
+ --
+ ------------------------------------------------------------------------------
+ full_control: process
+ begin -- process full_control
+ wait for incr_hibi_full_after_c;
+ hibi_full_up_cc <= hibi_full_up_cc+1;
+ end process full_control;
+
+
+
+ -----------------------------------------------------------------------------
+ --
+ ------------------------------------------------------------------------------
+ CLOCK1 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ wait for PERIOD/2;
+ clktmp := not clktmp;
+ Clk <= clktmp;
+ end process CLOCK1;
+
+ CLOCK2 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ clktmp := not clktmp;
+ Clk2 <= clktmp;
+ wait for PERIOD/2;
+ end process CLOCK2;
+
+ RESET : process
+ begin
+ Rst_n <= '0'; -- Reset the testsystem
+ wait for 6*PERIOD; -- Wait
+ Rst_n <= '1'; -- de-assert reset
+ wait;
+ end process RESET;
+
+
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_reader.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_reader.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_reader.vhd (revision 16)
@@ -0,0 +1,168 @@
+-------------------------------------------------------------------------------
+-- Title : Avalon reader
+-- Project :
+-------------------------------------------------------------------------------
+-- File : avalon_reader.vhd
+-- Author : kulmala3
+-- Created : 22.03.2005
+-- Last update: 25.06.2007
+-- Description: testbench block to model the avalon bus
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 22.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use work.txt_util.all;
+use work.tb_n2h2_pkg.all;
+
+entity avalon_reader is
+
+ generic (
+ data_file_g : string := "";
+ addr_width_g : integer := 0;
+ data_width_g : integer
+ );
+
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ avalon_we_in : in std_logic;
+ avalon_be_in : in std_logic_vector(data_width_g/8-1 downto 0);
+ avalon_writedata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
+ avalon_waitrequest_out : out std_logic;
+ increment_data_ptr : in std_logic; -- hops over one data
+ waitrequest_real_in : in std_logic;
+
+ -- tb gets
+ not_my_addr_out : out std_logic;
+ --tb gives.
+ init_in : in std_logic;
+ my_own_addr_in : in std_logic_vector(data_width_g-1 downto 0)
+ );
+
+end avalon_reader;
+
+architecture rtl of avalon_reader is
+
+ constant addr_offset_c : integer := data_width_g/8;
+ constant assign_waitreq_c : integer := 10; -- between 10 datas...
+ constant release_waitreq_c : integer := 3;
+ signal addr_counter_r : std_logic_vector(addr_width_g-1 downto 0);
+ signal data_counter_r : integer;
+ signal waitreq_counter_r : integer;
+ signal release_counter_r : integer;
+ signal waitrequest_to_n2h_rx : std_logic;
+
+ constant data_fixed_width_c : integer := 32;
+ constant n_words_output_c : integer := data_width_g/ data_fixed_width_c;
+-- signal data_r : std_logic_vector(data_fixed_width_c-1 downto 0); -- 32 bit words always!
+
+begin -- rtl
+
+ avalon_waitrequest_out <= waitrequest_to_n2h_rx;
+
+ process (clk, rst_n)
+ begin -- process
+ if rst_n = '0' then
+ waitreq_counter_r <= 0;
+ waitrequest_to_n2h_rx <= '0';
+ release_counter_r <= 0;
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ if avalon_we_in = '1' then
+
+ if (waitreq_counter_r = assign_waitreq_c) then
+ waitreq_counter_r <= 0;
+ waitrequest_to_n2h_rx <= '1';
+ else
+ waitrequest_to_n2h_rx <= '0';
+ waitreq_counter_r <= waitreq_counter_r+1;
+ end if;
+
+ end if;
+
+ if waitrequest_to_n2h_rx = '1' then
+ release_counter_r <= release_counter_r+1;
+ if release_counter_r >= release_waitreq_c then
+ release_counter_r <= 0;
+ waitrequest_to_n2h_rx <= '0';
+ end if;
+ end if;
+
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ file data_file : text open read_mode is data_file_g;
+ variable data_r : integer;
+ variable data_to_check_v : integer;
+ variable not_my_addr_v : integer;
+
+ begin -- process
+ if rst_n = '0' then -- asynchronous reset (active low)
+ addr_counter_r <= (others => '0');
+ data_counter_r <= 0;
+ not_my_addr_out <= '0';
+ data_r := 0;
+ not_my_addr_v := 0;
+ elsif clk'event and clk = '1' then -- rising clock edge
+ if avalon_we_in = '1' and waitrequest_real_in = '0' then
+ if (addr_counter_r + my_own_addr_in) /= avalon_addr_in then
+ not_my_addr_out <= '1';
+ not_my_addr_v := 1;
+ else
+ not_my_addr_out <= '0';
+ not_my_addr_v := 0;
+ addr_counter_r <= addr_counter_r + addr_offset_c;
+ end if;
+ if not_my_addr_v = 0 then
+
+ for i in 0 to n_words_output_c-1 loop
+
+ if avalon_be_in((i+1)*4-1 downto i*4) = "1111" then
+ data_to_check_v := conv_integer(avalon_writedata_in(data_fixed_width_c*(i+1)-1 downto data_fixed_width_c*i));
+ if data_r /= data_to_check_v then
+ assert false report "data mismatch on avalon!" severity error;
+ assert false report "wait: " & str(data_r) & "got: " & str(data_to_check_v) severity error;
+ else
+ assert false report "Data OK" severity note;
+ end if;
+
+ data_r := data_r+1;
+ end if;
+ end loop; -- i
+ end if;
+
+ elsif increment_data_ptr = '1' and waitrequest_real_in = '0' and not_my_addr_v = 0 then
+ -- weren't actually writing, but data wre thrown away due to irq amount
+ -- -> update file here also
+-- read_data_file (
+-- data => data_r,
+-- file_txt => data_file
+-- );
+ -- ??? AK 25.06.2007
+-- data_r := data_r +1;
+
+ end if;
+
+
+
+ if init_in = '1' then
+ addr_counter_r <= (others => '0');
+ end if;
+
+ end if;
+ end process;
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_str.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_str.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_str.do (revision 16)
@@ -0,0 +1,94 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {TB top}
+add wave -noupdate -format Logic /tb_n2h2_tx/clk
+add wave -noupdate -format Logic /tb_n2h2_tx/clk2
+add wave -noupdate -format Logic /tb_n2h2_tx/rst_n
+add wave -noupdate -format Literal /tb_n2h2_tx/main_ctrl_r
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/amount_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/avalon_addr_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_re_from_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/avalon_readdata_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_tx2
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_readdatavalid_to_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/hibi_data_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_av_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_full_to_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_comm_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/tx_start_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/tx_status_done_from_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/tx_comm_to_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/tx_hibi_addr_to_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/tx_ram_addr_to_tx
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/tx_amount_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/cs1_n_to_ram
+add wave -noupdate -format Logic /tb_n2h2_tx/cs2_to_ram
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/addr_to_ram
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/data_inout_ram
+add wave -noupdate -format Logic /tb_n2h2_tx/we_n_to_ram
+add wave -noupdate -format Logic /tb_n2h2_tx/oe_n_to_ram
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/delayed_data_from_ram_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/hibi_addr_r
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/hibi_amount_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/hibi_data_r
+add wave -noupdate -format Literal /tb_n2h2_tx/wait_cnt_r
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_waitr_cnt_r
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_was_up_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_full_cnt_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_full_up_cc
+add wave -noupdate -divider {DUT tx}
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/clk
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/avalon_addr_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_re_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/avalon_readdata_in
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_waitrequest_in
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_readdatavalid_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/hibi_data_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_av_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_full_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/hibi_comm_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_we_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/tx_start_in
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/tx_status_done_out
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/tx_comm_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/tx_hibi_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/tx_ram_addr_in
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/tx_amount_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/control_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_cnt_en_r
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/addr_cnt_value_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_cnt_load_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/addr_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/amount_cnt_en_r
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/amount_cnt_value_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/amount_cnt_load_r
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/amount_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_amount_eq
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/addr_to_stop_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_re_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/start_re_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_write_addr_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/data_src_sel
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_we_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_stop_we_r
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {125 ns} 0}
+configure wave -namecolwidth 211
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ms
+update
+WaveRestoreZoom {45 ns} {201 ns}
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/hibi_sender_n2h2.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/hibi_sender_n2h2.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/hibi_sender_n2h2.vhd (revision 16)
@@ -0,0 +1,324 @@
+-------------------------------------------------------------------------------
+-- Title : A block which sends data to HIBI
+-- Project :
+-------------------------------------------------------------------------------
+-- File : hibi_sender_n2h2.vhd
+-- Author : kulmala3
+-- Created : 13.01.2005
+-- Last update: 2011-03-09
+-- Description: This blocks creates traffic for the HIBI block.
+-- This block is used within tb_eigth_hibi_r4.vhd.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 13.01.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use work.tb_n2h2_pkg.all;
+
+entity hibi_sender_n2h2 is
+
+ generic (
+ data_1_g : string := "";
+ conf_file_g : string := "";
+ own_number_g : integer := 0; -- 1-4
+ comm_width_g : integer := 5;
+ n_dest_g : integer := 3;
+ data_width_g : integer := 0);
+
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ pause_in : in std_logic;
+ pause_ack : out std_logic;
+ done_out : out std_logic; -- if this has finished
+
+ -- HIBI WRAPPER PORTS
+ agent_empty_out : out std_logic;
+ agent_re_in : in std_logic;
+ agent_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
+ agent_data_out : out std_logic_vector(data_width_g-1 downto 0);
+ agent_av_out : out std_logic
+
+-- note that this only sends, so signals
+-- agent_empty_in : in std_logic;
+-- agent_one_d_in : in std_logic;
+-- agent_re_out : out std_logic;
+-- agent_av_in : in std_logic;
+-- agent_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
+-- agent_data_in : in std_logic_vector(data_width_g-1 downto 0);
+-- aren't needed
+
+
+ );
+
+end hibi_sender_n2h2;
+
+
+architecture rtl of hibi_sender_n2h2 is
+
+
+
+
+ -- right now gives a lot of warnings when other than 0
+ constant dbg_level : integer range 0 to 3 := 0; -- 0= no debug, use 0 for synthesis
+
+ -- Registers may be reset to 'Z' to 'X' so that reset state is clearly
+ -- distinguished from active state. Using dbg_level+Rst_Value array, the rst value may
+ -- be easily set to '0' for synthesis.
+ constant rst_value_arr : std_logic_vector (6 downto 0) := 'X' & 'Z' & 'X' & 'Z' & 'X' & 'Z' & '0';
+
+ constant hibi_write_c : std_logic_vector(4 downto 0) := "00010";
+
+ -- reads the (opened) file given. the file line structure is as follows:
+ -- 1st integer: destination agent (1,2,3,4) (not own!)
+ -- 2nd integer: delay before sending
+ -- 3rd integer: amount of data to be sent.
+ procedure read_hibi_conf_file (
+ dest_agent_n : out integer;
+ delay : out integer;
+ amount : out integer;
+ file conf_dat : text) is
+
+ variable file_row : line;
+ variable dest_agent_n_var : integer;
+ variable delay_var : integer;
+ variable amount_var : integer;
+
+ begin -- read_hibi_conf_file
+ readline(conf_dat, file_row);
+ read (file_row, dest_agent_n_var);
+ read (file_row, delay_var);
+ read (file_row, amount_var);
+ dest_agent_n := dest_agent_n_var;
+ delay := delay_var;
+ amount := amount_var;
+ end read_hibi_conf_file;
+
+ type control_states is (read_hibi_conf, wait_sending, write_hibi, wait_hibi, finish, write_addr, pause);
+ signal control_r : control_states := read_hibi_conf;
+
+
+ -- fifo signals
+ signal data_to_fifo : std_logic_vector (1+5+data_width_g-1 downto 0);
+ signal we_to_fifo : std_logic;
+ signal full_from_fifo : std_logic;
+ signal one_p_from_fifo : std_logic;
+ signal re_to_fifo : std_logic;
+ signal data_from_fifo : std_logic_vector (1+5+data_width_g-1 downto 0);
+ signal empty_from_fifo : std_logic;
+ signal one_d_from_fifo : std_logic;
+
+ -- internal
+
+ signal agent_comm_to_fifo : std_logic_vector (comm_width_g-1 downto 0);
+ signal agent_data_to_fifo : std_logic_vector(data_width_g-1 downto 0);
+ signal agent_av_to_fifo : std_logic;
+
+--
+ constant data_fixed_width_c : integer := 32;
+ constant n_words_output_c : integer := data_width_g/ data_fixed_width_c;
+ type dest_amount_cnt_type is array (0 to n_dest_g-1) of std_logic_vector(data_fixed_width_c-1 downto 0);
+ signal data_r : dest_amount_cnt_type; -- 32 bit words always!
+
+ signal sent_packets_r : integer;
+
+begin -- rtl
+
+ agent_av_out <= data_from_fifo(1+5+data_width_g-1);
+ agent_comm_out <= data_from_fifo(4+data_width_g downto data_width_g);
+ agent_data_out <= data_from_fifo(data_width_g-1 downto 0);
+ data_to_fifo <= agent_av_to_fifo & agent_comm_to_fifo & agent_data_to_fifo;
+
+
+ fifo_1 : entity work.fifo
+ generic map (
+ data_width_g => 1+5+data_width_g, -- av, comm, data
+ depth_g => 10)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+ data_in => data_to_fifo,
+ we_in => we_to_fifo,
+ full_out => full_from_fifo,
+ one_p_out => one_p_from_fifo,
+ re_in => agent_re_in,
+ data_out => data_from_fifo,
+ empty_out => agent_empty_out,
+ one_d_out => one_d_from_fifo);
+
+
+ main : process (clk, rst_n)
+ file conf_data_file : text open read_mode is conf_file_g;
+-- file data_file_1 : text open read_mode is data_1_g;
+
+ variable delay_r : integer;
+ variable amount_r : integer;
+ variable dest_agent_n_r : integer;
+ variable file_number_r : integer;
+-- variable data_r : integer;
+ begin -- process main
+ if rst_n = '0' then -- asynchronous reset (active low)
+ control_r <= read_hibi_conf;
+ agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ agent_av_to_fifo <= '0';
+ agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ we_to_fifo <= '0';
+ done_out <= '0';
+ amount_r := 0;
+ delay_r := 0;
+ dest_agent_n_r := 0;
+ for i in 0 to n_dest_g-1 loop
+ data_r(i) <= (others => '0');
+ end loop; -- i
+ file_number_r := 0;
+ pause_ack <= '0';
+ sent_packets_r <= 0;
+
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ case control_r is
+ when read_hibi_conf =>
+ -- If there's still data left, we read the configuration
+ -- file and act accordingly. if some delay is specified,
+ -- we go and wait it (wait_sending). if delay = 0,
+ -- then we send the address right away
+ if pause_in = '1' then
+ control_r <= pause;
+ else
+
+ if endfile(conf_data_file) then
+ control_r <= finish;
+ assert false report "End of the configuration file reached" severity note;
+ end if;
+ read_hibi_conf_file (
+ dest_agent_n => dest_agent_n_r,
+ delay => delay_r,
+ amount => amount_r,
+ conf_dat => conf_data_file);
+ if delay_r = 0 then
+ control_r <= write_addr;
+ else
+ control_r <= wait_sending;
+ end if;
+ end if;
+ we_to_fifo <= '0';
+ agent_av_to_fifo <= '0';
+ agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
+
+
+ when wait_sending =>
+ -- lets wait the given amount of time before proceeding with sending
+ delay_r := delay_r-1;
+ if delay_r = 0 then
+ control_r <= write_addr;
+ end if;
+ dest_agent_n_r := dest_agent_n_r;
+ amount_r := amount_r;--dest_agent_n_r;
+
+ when write_addr =>
+ -- when hibi bus is free, we write the address to it and then
+ -- go to the state where the actual data is sent (write_hibi)
+ -- note that agent address is gotten from the array defined in
+ -- tb_eight_hibi_pkg.
+ if full_from_fifo = '0' then
+ we_to_fifo <= '1';
+ agent_av_to_fifo <= '1';
+ agent_comm_to_fifo <= hibi_write_c;
+ agent_data_to_fifo <= conv_std_logic_vector
+ (addresses_c(dest_agent_n_r)+
+ own_number_g+sent_packets_r, data_width_g);
+ sent_packets_r <= sent_packets_r + 1;
+ control_r <= write_hibi;
+ else
+ we_to_fifo <= '0';
+ agent_av_to_fifo <= '0';
+ agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ control_r <= write_addr;
+ end if;
+
+ when write_hibi =>
+
+ if full_from_fifo = '0' then
+
+ for i in 0 to n_words_output_c-1 loop
+ agent_data_to_fifo(data_fixed_width_c*(i+1)-1 downto data_fixed_width_c*i) <= data_r(dest_agent_n_r)+i;
+ amount_r := amount_r-1;
+ if amount_r = 0 then
+ control_r <= read_hibi_conf;
+ we_to_fifo <= '1';
+ exit;
+ end if;
+ end loop; -- i
+ data_r(dest_agent_n_r) <= data_r(dest_agent_n_r) + n_words_output_c;
+
+ agent_av_to_fifo <= '0';
+ agent_comm_to_fifo <= hibi_write_c;
+
+ if one_p_from_fifo = '1' then
+ control_r <= wait_hibi;
+ we_to_fifo <= '0';
+ end if;
+
+ else
+ control_r <= wait_hibi;
+ agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ we_to_fifo <= '0';
+ agent_av_to_fifo <= '0';
+ agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ end if;
+
+ when wait_hibi =>
+ -- hibi was full so we wait until it becames free again
+ if full_from_fifo = '0' then
+ control_r <= write_hibi;
+ we_to_fifo <= '1';
+ if amount_r = 0 then
+ control_r <= read_hibi_conf;
+ end if;
+ else
+ control_r <= wait_hibi;
+ we_to_fifo <= '0';
+ end if;
+-- agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
+-- agent_av_to_fifo <= '0';
+-- agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
+
+ when finish =>
+ -- notify that we're done.
+ done_out <= '1';
+ agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
+ we_to_fifo <= '0';
+ agent_av_to_fifo <= '0';
+ agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
+
+ when pause =>
+ if pause_in = '0' then
+ pause_ack <= '0';
+ control_r <= read_hibi_conf;
+ else
+ pause_ack <= '1';
+ control_r <= pause;
+ end if;
+ when others => null;
+ end case;
+
+
+
+ end if;
+ end process main;
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_rx.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_rx.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_rx.vhd (revision 16)
@@ -0,0 +1,377 @@
+-------------------------------------------------------------------------------
+-- Title : Testbench for design "n2h2_rx"
+-- Project :
+-------------------------------------------------------------------------------
+-- File : tb_n2h2_rx.vhdl
+-- Author : kulmala3
+-- Created : 22.03.2005
+-- Last update: 2011-03-09
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 22.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use work.tb_n2h2_pkg.all;
+-- use work.log2_pkg.all;
+-------------------------------------------------------------------------------
+
+entity tb_n2h2_rx is
+
+end tb_n2h2_rx;
+
+-------------------------------------------------------------------------------
+
+architecture tb of tb_n2h2_rx is
+
+ signal clk : std_logic := '0';
+ signal clk2 : std_logic := '0';
+ signal rst_n : std_logic := '0';
+
+ -- component n2h2 rx generics
+ constant n_chans_c : integer := 3;
+ constant n_chans_bits_c : integer := 2;
+ constant data_width_c : integer := 64; -- 32 and 64 legal
+ constant addr_width_c : integer := 32;
+ constant comm_width_c : integer := 5;
+ constant hibi_addr_cmp_hi_c : integer := 31;
+ constant hibi_addr_cmp_lo_c : integer := 0;
+ constant amount_width_c : integer := 5; -- 2**5 flits max
+
+ -- component ports
+ signal avalon_addr_from_rx : std_logic_vector(addr_width_c-1 downto 0);
+ signal avalon_we_from_rx : std_logic;
+ signal avalon_be_from_rx : std_logic_vector(data_width_c/8-1 downto 0);
+ signal avalon_writedata_from_rx : std_logic_vector(data_width_c-1 downto 0);
+ signal avalon_waitrequest_to_rx : std_logic;
+ signal avalon_waitreqvec_to_rx : std_logic_vector(n_chans_c-1 downto 0);
+ signal hibi_data_to_rx : std_logic_vector(data_width_c-1 downto 0);
+ signal hibi_av_to_rx : std_logic;
+ signal hibi_empty_to_rx : std_logic;
+ signal hibi_comm_to_rx : std_logic_vector(4 downto 0);
+
+ signal hibi_re_from_rx : std_logic;
+ signal avalon_cfg_addr_to_rx : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
+ signal avalon_cfg_writedata_to_rx : std_logic_vector(addr_width_c-1 downto 0);
+ signal avalon_cfg_we_to_rx : std_logic;
+ signal avalon_cfg_readdata_from_rx : std_logic_vector(addr_width_c-1 downto 0);
+ signal avalon_cfg_re_to_rx : std_logic;
+ signal avalon_cfg_cs_to_rx : std_logic;
+ signal rx_irq_from_rx : std_logic;
+ signal tx_start_from_rx : std_logic;
+ signal tx_status_done_to_rx : std_logic;
+
+ -- config writer
+ constant conf_file_c : string := "tbrx_conf_rx.dat";
+ constant conf_file_hsender_c : string := "tbrx_conf_hibisend.dat";
+ constant data_file_c : string := "tbrx_data_file.dat";
+ signal start_to_cfg : std_logic;
+ signal avalon_cfg_addr_from_cfg : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
+-- signal avalon_cfg_we_from_cfg : std_logic;
+ signal avalon_cfg_cs_from_cfg : std_logic;
+ signal done_from_cfg : std_logic;
+ signal init_to_cfg : std_logic;
+
+-- config reader
+ signal start_to_cfg_reader : std_logic;
+ signal avalon_cfg_addr_from_cfg_reader : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
+-- signal avalon_cfg_readdata_to_cfg_reader : std_logic_vector(data_width_c-1 downto 0);
+-- signal avalon_cfg_re_from_cfg_reader : std_logic;
+ signal avalon_cfg_cs_from_cfg_reader : std_logic;
+ signal done_from_cfg_reader : std_logic;
+
+ -- hibi writer
+ signal done_from_hibi_sender : std_logic;
+ signal pause_hibi_send : std_logic;
+ signal pause_ack_hibi_send : std_logic;
+-- avalon reader
+ signal init_to_reader : std_logic_vector(n_chans_c-1 downto 0);
+ signal not_my_addr_from_readers : std_logic_vector(n_chans_c-1 downto 0);
+
+
+ -- clock and reset
+ constant Period : time := 10 ns;
+
+ -- cpu side signals
+
+ -- system control signals
+ type system_control_states is (config, wait_for_config, check_config,
+ wait_check, wait_for_irq);
+ signal system_control_r : system_control_states;
+ signal hibi_sender_start : std_logic;
+ signal hibi_sender_rst_n : std_logic;
+ type chan_data_array is array (n_chans_c-1 downto 0) of std_logic_vector(data_width_c-1 downto 0);
+ signal my_own_addr_c : chan_data_array;
+-- signal reset_buses_r : std_logic;
+ signal avalon_reader_rst_n : std_logic;
+ signal hibi_data_read : std_logic;
+
+ signal irq_was_up : std_logic;
+ signal irq_counter : integer;
+begin -- tb
+ tx_status_done_to_rx <= '0';
+
+ hibi_sender_rst_n <= hibi_sender_start and rst_n;
+ process (clk, rst_n)
+ begin -- process
+ if rst_n = '0' then -- asynchronous reset (active low)
+ system_control_r <= config;
+ start_to_cfg_reader <= '0';
+ start_to_cfg <= '0';
+ hibi_sender_start <= '0';
+-- reset_buses_r <= '1';
+ init_to_cfg <= '0';
+ irq_was_up <= '0';
+ irq_counter <= 0;
+ pause_hibi_send <= '0';
+ for i in n_chans_c-1 downto 0 loop
+ init_to_reader(i) <= '0';
+ end loop; -- i
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ case system_control_r is
+ when config =>
+ -- write the dma config
+ start_to_cfg <= '1';
+ system_control_r <= wait_for_config;
+
+ when wait_for_config =>
+ start_to_cfg <= '0';
+ -- wait until it finishes configuring all channels
+ if done_from_cfg = '1' then
+ system_control_r <= check_config;
+ end if;
+
+ when check_config =>
+ -- check that the config is written alright
+ start_to_cfg_reader <= '1';
+ system_control_r <= wait_check;
+
+ when wait_check =>
+ -- wait for check to complete
+ start_to_cfg_reader <= '0';
+ if done_from_cfg_reader = '1' then
+ system_control_r <= wait_for_irq;
+ -- unleash the hibi_sender
+ hibi_sender_start <= '1';
+ end if;
+
+ when wait_for_irq =>
+ -- check that irq amounts etc are all right.
+ -- TODO stuff here.
+ init_to_cfg <= '0';
+ if done_from_cfg = '1' then
+ pause_hibi_send <= '0';
+ end if;
+
+ if rx_irq_from_rx = '1' and irq_was_up = '0' then
+ irq_counter <= irq_counter + 1;
+ irq_was_up <= '1';
+ elsif rx_irq_from_rx = '0' then
+ irq_was_up <= '0';
+ end if;
+
+ if irq_counter = n_chans_c then
+ if pause_ack_hibi_send = '1' and hibi_empty_to_rx = '1' then
+ init_to_cfg <= '1';
+ pause_hibi_send <= '1';
+ irq_counter <= 0;
+ else
+ init_to_cfg <= '0';
+ pause_hibi_send <= '1';
+ end if;
+ end if;
+
+ when others => null;
+ end case;
+
+
+
+ end if;
+ end process;
+
+ waitreq : process (avalon_waitreqvec_to_rx)
+ begin -- process waitreq
+ if avalon_waitreqvec_to_rx /= conv_std_logic_vector(0, n_chans_c) then
+ avalon_waitrequest_to_rx <= '1';
+ else
+ avalon_waitrequest_to_rx <= '0';
+ end if;
+
+ end process waitreq;
+
+
+ -- component instantiation
+ DUT : entity work.n2h2_rx_channels
+ generic map (
+ n_chans_g => n_chans_c,
+ n_chans_bits_g => n_chans_bits_c,
+ data_width_g => data_width_c,
+ addr_width_g => addr_width_c,
+ hibi_addr_cmp_hi_g => hibi_addr_cmp_hi_c,
+ hibi_addr_cmp_lo_g => hibi_addr_cmp_lo_c,
+ amount_width_g => amount_width_c)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+ avalon_addr_out => avalon_addr_from_rx,
+ avalon_we_out => avalon_we_from_rx,
+ avalon_be_out => avalon_be_from_rx,
+ avalon_writedata_out => avalon_writedata_from_rx,
+ avalon_waitrequest_in => avalon_waitrequest_to_rx,
+ hibi_data_in => hibi_data_to_rx,
+ hibi_av_in => hibi_av_to_rx,
+ hibi_empty_in => hibi_empty_to_rx,
+ hibi_comm_in => hibi_comm_to_rx,
+ hibi_re_out => hibi_re_from_rx,
+ avalon_cfg_addr_in => avalon_cfg_addr_to_rx,
+ avalon_cfg_writedata_in => avalon_cfg_writedata_to_rx,
+ avalon_cfg_we_in => avalon_cfg_we_to_rx,
+ avalon_cfg_readdata_out => avalon_cfg_readdata_from_rx,
+ avalon_cfg_re_in => avalon_cfg_re_to_rx,
+ avalon_cfg_cs_in => avalon_cfg_cs_to_rx,
+ rx_irq_out => rx_irq_from_rx,
+ tx_start_out => tx_start_from_rx,
+ tx_status_done_in => tx_status_done_to_rx);
+
+
+ cfg_mux : process (avalon_cfg_cs_from_cfg, avalon_cfg_cs_from_cfg_reader,
+ avalon_cfg_addr_from_cfg_reader, avalon_cfg_addr_from_cfg)
+ variable vector : std_logic_vector(1 downto 0);
+ begin -- process cfg mux
+ vector := avalon_cfg_cs_from_cfg & avalon_cfg_cs_from_cfg_reader;
+ case vector is
+ when "01" =>
+ avalon_cfg_addr_to_rx <= avalon_cfg_addr_from_cfg_reader;
+ avalon_cfg_cs_to_rx <= avalon_cfg_cs_from_cfg_reader;
+
+ when others =>
+-- when "00" | "10" | "11" =>
+ avalon_cfg_addr_to_rx <= avalon_cfg_addr_from_cfg;
+ avalon_cfg_cs_to_rx <= avalon_cfg_cs_from_cfg;
+
+ end case;
+
+ end process cfg_mux;
+
+ assert not_my_addr_from_readers /= "111" report "address mismatch on avalon!" severity error;
+
+ avalon_cfg_writer_1 : entity work.avalon_cfg_writer
+ generic map (
+ n_chans_g => n_chans_c,
+ data_width_g => addr_width_c,
+ conf_file_g => conf_file_c)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+ start_in => start_to_cfg,
+ avalon_cfg_addr_out => avalon_cfg_addr_from_cfg,
+ avalon_cfg_writedata_out => avalon_cfg_writedata_to_rx,
+ avalon_cfg_we_out => avalon_cfg_we_to_rx,
+ avalon_cfg_cs_out => avalon_cfg_cs_from_cfg,
+ init_in => init_to_cfg,
+ done_out => done_from_cfg
+ );
+-- different clock...
+ avalon_cfg_reader_1 : entity work.avalon_cfg_reader
+ generic map (
+ n_chans_g => n_chans_c,
+ data_width_g => addr_width_c,
+ conf_file_g => conf_file_c)
+ port map (
+ clk => clk2,
+ rst_n => rst_n,
+ start_in => start_to_cfg_reader,
+ avalon_cfg_addr_out => avalon_cfg_addr_from_cfg_reader,
+ avalon_cfg_readdata_in => avalon_cfg_readdata_from_rx,
+ avalon_cfg_re_out => avalon_cfg_re_to_rx,
+ avalon_cfg_cs_out => avalon_cfg_cs_from_cfg_reader,
+ done_out => done_from_cfg_reader
+ );
+
+ hibi_sender_n2h2_1 : entity work.hibi_sender_n2h2
+ generic map (
+ data_1_g => data_file_c,
+ conf_file_g => conf_file_hsender_c,
+ own_number_g => 4,
+ comm_width_g => comm_width_c,
+ data_width_g => data_width_c
+ )
+ port map (
+ clk => clk,
+ rst_n => hibi_sender_rst_n,
+ pause_in => pause_hibi_send,
+ pause_ack => pause_ack_hibi_send,
+ done_out => done_from_hibi_sender,
+ agent_empty_out => hibi_empty_to_rx,
+ agent_re_in => hibi_re_from_rx,
+ agent_comm_out => hibi_comm_to_rx,
+ agent_data_out => hibi_data_to_rx,
+ agent_av_out => hibi_av_to_rx
+ );
+
+ hibi_data_read <= hibi_empty_to_rx nor hibi_av_to_rx;
+ avalon_reader_rst_n <= rst_n;
+ avalon : for i in n_chans_c-1 downto 0 generate
+ my_own_addr_c(i) <= conv_std_logic_vector(ava_addresses_c(i), data_width_c);
+
+ avalon_reader_i : entity work.avalon_reader
+ generic map (
+ data_file_g => data_file_c,
+ addr_width_g => addr_width_c,
+ data_width_g => data_width_c
+ )
+ port map (
+ clk => clk,
+ rst_n => avalon_reader_rst_n,
+ avalon_we_in => avalon_we_from_rx,
+ avalon_be_in => avalon_be_from_rx,
+ increment_data_ptr => hibi_data_read,
+ waitrequest_real_in => avalon_waitrequest_to_rx,
+ avalon_writedata_in => avalon_writedata_from_rx,
+ avalon_addr_in => avalon_addr_from_rx,
+ avalon_waitrequest_out => avalon_waitreqvec_to_rx(i),
+ my_own_addr_in => my_own_addr_c(i),
+ not_my_addr_out => not_my_addr_from_readers(i),
+ init_in => pause_hibi_send
+ );
+ end generate avalon;
+
+
+
+ CLOCK1 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ wait for PERIOD/2;
+ clktmp := not clktmp;
+ Clk <= clktmp;
+ end process CLOCK1;
+
+ CLOCK2 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ clktmp := not clktmp;
+ Clk2 <= clktmp;
+ wait for PERIOD/2;
+ end process CLOCK2;
+
+ RESET : process
+ begin
+ Rst_n <= '0'; -- Reset the testsystem
+ wait for 6*PERIOD; -- Wait
+ Rst_n <= '1'; -- de-assert reset
+ wait;
+ end process RESET;
+
+
+
+end tb;
+
+-------------------------------------------------------------------------------
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx.vhd (revision 16)
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+-- Title : Testbench for design "n2h2_tx"
+-- Project :
+-------------------------------------------------------------------------------
+-- File : tb_n2h2_tx.vhd
+-- Author : kulmala3
+-- Created : 30.03.2005
+-- Last update: 2011-03-09
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 30.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+-------------------------------------------------------------------------------
+
+entity tb_n2h2_tx is
+
+end tb_n2h2_tx;
+
+-------------------------------------------------------------------------------
+
+architecture rtl of tb_n2h2_tx is
+
+
+ -- component generics
+ constant data_width_g : integer := 32; --0;
+ constant amount_width_g : integer := 16; --0;
+
+ -- component ports
+ signal clk : std_logic := '0';
+ signal rst_n : std_logic := '0';
+
+ signal avalon_addr_from_tx : std_logic_vector(data_width_g-1 downto 0);
+ signal avalon_re_from_tx : std_logic;
+ signal avalon_readdata_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
+ signal avalon_readdatavalid_to_tx : std_logic := '0';
+
+ signal avalon_waitrequest_to_tx : std_logic := '0';
+ signal hibi_data_from_tx : std_logic_vector(data_width_g-1 downto 0);
+ signal hibi_av_from_tx : std_logic;
+ signal hibi_full_to_tx : std_logic := '0';
+ signal hibi_comm_from_tx : std_logic_vector(4 downto 0);
+ signal hibi_we_from_tx : std_logic;
+ signal tx_start_to_tx : std_logic := '0';
+ signal tx_status_done_from_tx : std_logic;
+
+ signal tx_comm_to_tx : std_logic_vector(4 downto 0) := (others => '0');
+
+ signal tx_hibi_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
+ signal tx_ram_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
+ signal tx_amount_to_tx : std_logic_vector(amount_width_g-1 downto 0) := (others => '0');
+
+ -- clock and reset
+ signal Clk2 : std_logic;
+ constant Period : time := 10 ns;
+
+begin -- rtl
+
+
+
+
+ -- component instantiation
+ DUT : entity work.n2h2_tx
+ generic map (
+ data_width_g => data_width_g,
+ amount_width_g => amount_width_g)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+ avalon_addr_out => avalon_addr_from_tx,
+ avalon_re_out => avalon_re_from_tx,
+ avalon_readdata_in => avalon_readdata_to_tx,
+ avalon_waitrequest_in => avalon_waitrequest_to_tx,
+ avalon_readdatavalid_in => avalon_readdatavalid_to_tx,
+ hibi_data_out => hibi_data_from_tx,
+ hibi_av_out => hibi_av_from_tx,
+ hibi_full_in => hibi_full_to_tx,
+ hibi_comm_out => hibi_comm_from_tx,
+ hibi_we_out => hibi_we_from_tx,
+ tx_start_in => tx_start_to_tx,
+ tx_status_done_out => tx_status_done_from_tx,
+ tx_comm_in => tx_comm_to_tx,
+ tx_hibi_addr_in => tx_hibi_addr_to_tx,
+ tx_ram_addr_in => tx_ram_addr_to_tx,
+ tx_amount_in => tx_amount_to_tx);
+
+
+ CLOCK1 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ wait for PERIOD/2;
+ clktmp := not clktmp;
+ Clk <= clktmp;
+ end process CLOCK1;
+
+ CLOCK2 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ clktmp := not clktmp;
+ Clk2 <= clktmp;
+ wait for PERIOD/2;
+ end process CLOCK2;
+
+ RESET : process
+ begin
+ Rst_n <= '0'; -- Reset the testsystem
+ wait for 6*PERIOD; -- Wait
+ Rst_n <= '1'; -- de-assert reset
+ wait;
+ end process RESET;
+
+
+
+
+end rtl;
+
+-------------------------------------------------------------------------------
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_rx.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_rx.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_rx.do (revision 16)
@@ -0,0 +1,118 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {TB top}
+add wave -noupdate -format Logic /tb_n2h2_rx/clk
+add wave -noupdate -format Logic /tb_n2h2_rx/clk2
+add wave -noupdate -format Logic /tb_n2h2_rx/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_addr_from_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_we_from_rx
+add wave -noupdate -format Literal /tb_n2h2_rx/avalon_be_from_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_writedata_from_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_waitrequest_to_rx
+add wave -noupdate -format Literal /tb_n2h2_rx/avalon_waitreqvec_to_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/hibi_data_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/hibi_av_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/hibi_empty_to_rx
+add wave -noupdate -format Literal /tb_n2h2_rx/hibi_comm_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/hibi_re_from_rx
+add wave -noupdate -format Literal /tb_n2h2_rx/avalon_cfg_addr_to_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_cfg_writedata_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_we_to_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_cfg_readdata_from_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_re_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_cs_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/rx_irq_from_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/tx_start_from_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/tx_status_done_to_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/start_to_cfg
+add wave -noupdate -format Literal /tb_n2h2_rx/avalon_cfg_addr_from_cfg
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_cs_from_cfg
+add wave -noupdate -format Logic /tb_n2h2_rx/done_from_cfg
+add wave -noupdate -format Logic /tb_n2h2_rx/init_to_cfg
+add wave -noupdate -format Logic /tb_n2h2_rx/start_to_cfg_reader
+add wave -noupdate -format Literal /tb_n2h2_rx/avalon_cfg_addr_from_cfg_reader
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_cs_from_cfg_reader
+add wave -noupdate -format Logic /tb_n2h2_rx/done_from_cfg_reader
+add wave -noupdate -format Logic /tb_n2h2_rx/done_from_hibi_sender
+add wave -noupdate -format Logic /tb_n2h2_rx/pause_hibi_send
+add wave -noupdate -format Logic /tb_n2h2_rx/pause_ack_hibi_send
+add wave -noupdate -format Literal /tb_n2h2_rx/not_my_addr_from_readers
+add wave -noupdate -format Literal /tb_n2h2_rx/system_control_r
+add wave -noupdate -format Logic /tb_n2h2_rx/hibi_sender_start
+add wave -noupdate -format Logic /tb_n2h2_rx/hibi_sender_rst_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/my_own_addr_c
+add wave -noupdate -format Logic /tb_n2h2_rx/avalon_reader_rst_n
+add wave -noupdate -format Logic /tb_n2h2_rx/hibi_data_read
+add wave -noupdate -format Logic /tb_n2h2_rx/irq_was_up
+add wave -noupdate -format Literal /tb_n2h2_rx/irq_counter
+add wave -noupdate -divider {DUT rx}
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/clk
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/rst_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_addr_out
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_we_out
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_be_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_writedata_out
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_waitrequest_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/hibi_data_in
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_av_in
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_empty_in
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/hibi_comm_in
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_re_out
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_cfg_addr_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_cfg_writedata_in
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_cfg_we_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_cfg_readdata_out
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_cfg_re_in
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_cfg_cs_in
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/rx_irq_out
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/tx_start_out
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_comm_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_mem_addr_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_hibi_addr_out
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_amount_out
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/tx_status_done_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/sender_addr_r
+add wave -noupdate -format Literal -radix unsigned /tb_n2h2_rx/dut/irq_amount_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/control_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_hibi_addr_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_amount_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_comm_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/init_chan_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/irq_chan_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/current_mem_addr_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/current_be_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_be_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/status_r
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/irq_reset_r
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_re_r
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_we_r
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/unknown_rx
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/unknown_rx_irq_r
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/unknown_rx_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_addr_r
+add wave -noupdate -format Logic /tb_n2h2_rx/dut/curr_chan_avalon_we_r
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_wes
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/matches
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/matches_cmb
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/irq_ack_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_addr_temp
+add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_be_temp
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1191 ns} 0}
+configure wave -namecolwidth 211
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ms
+update
+WaveRestoreZoom {0 ns} {2052 ns}
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx.do (revision 16)
@@ -0,0 +1,94 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {TB top}
+add wave -noupdate -format Logic /tb_n2h2_tx/clk
+add wave -noupdate -format Logic /tb_n2h2_tx/clk2
+add wave -noupdate -format Logic /tb_n2h2_tx/rst_n
+add wave -noupdate -format Literal /tb_n2h2_tx/main_ctrl_r
+add wave -noupdate -format Literal /tb_n2h2_tx/amount_r
+add wave -noupdate -format Literal /tb_n2h2_tx/mem_addr_r
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_addr_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_re_from_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_readdata_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_tx2
+add wave -noupdate -format Logic /tb_n2h2_tx/avalon_readdatavalid_to_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_av_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_full_to_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_comm_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_from_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/tx_start_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/tx_status_done_from_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/tx_comm_to_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/tx_hibi_addr_to_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/tx_ram_addr_to_tx
+add wave -noupdate -format Literal /tb_n2h2_tx/tx_amount_to_tx
+add wave -noupdate -format Logic /tb_n2h2_tx/cs1_n_to_ram
+add wave -noupdate -format Logic /tb_n2h2_tx/cs2_to_ram
+add wave -noupdate -format Literal /tb_n2h2_tx/addr_to_ram
+add wave -noupdate -format Literal /tb_n2h2_tx/data_inout_ram
+add wave -noupdate -format Logic /tb_n2h2_tx/we_n_to_ram
+add wave -noupdate -format Logic /tb_n2h2_tx/oe_n_to_ram
+add wave -noupdate -format Literal /tb_n2h2_tx/delayed_data_from_ram_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_addr_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_amount_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_r
+add wave -noupdate -format Literal /tb_n2h2_tx/wait_cnt_r
+add wave -noupdate -format Literal /tb_n2h2_tx/avalon_waitr_cnt_r
+add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_was_up_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_full_cnt_r
+add wave -noupdate -format Literal /tb_n2h2_tx/hibi_full_up_cc
+add wave -noupdate -divider {DUT rx}
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/clk
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/rst_n
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/avalon_addr_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_re_out
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/avalon_readdata_in
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_waitrequest_in
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_readdatavalid_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/hibi_data_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_av_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_full_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/hibi_comm_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_we_out
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/tx_start_in
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/tx_status_done_out
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/tx_comm_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/tx_hibi_addr_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/tx_ram_addr_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/tx_amount_in
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/control_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_cnt_en_r
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/addr_cnt_value_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_cnt_load_r
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/addr_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/amount_cnt_en_r
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/amount_cnt_value_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/amount_cnt_load_r
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/amount_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_amount_eq
+add wave -noupdate -format Literal /tb_n2h2_tx/dut/addr_to_stop_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_re_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/start_re_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_write_addr_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/data_src_sel
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_we_r
+add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_stop_we_r
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1191 ns} 0}
+configure wave -namecolwidth 211
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ms
+update
+WaveRestoreZoom {0 ns} {2052 ns}
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/txt_util.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/txt_util.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/txt_util.vhd (revision 16)
@@ -0,0 +1,641 @@
+-- -------------------------------------------------------------------
+-- Design:
+--
+-- Package for VHDL text output
+--
+-- Note:
+-- -----
+-- This package uses the VHDL 95 standard.
+-- If VHDL 95 is not supported by your simulator
+-- you need to comment out the file access functions.
+--
+-- The package provides a means to output text and
+-- manipulate strings.
+--
+-- The basic usage is like this: >> print(s); <<
+-- (where s is any string)
+-- To print something which is not a string it has to be converted
+-- into a string first. For this purpose the package contains
+-- conversion functions called >> str(...) <<.
+-- For example a std_logic_vector slv would be printed like this:
+-- >> print(str(slv)); <<. To print several items on one line the
+-- items have to concatenated as strings with the "&" operator eg:
+-- >> print("The value of slv is "& str(slv)); <<
+-- The string functions can also be used in assert statements as shown
+-- in the example below:
+-- >> assert DIN = "0101" <<
+-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
+-- >> severity Error; <<
+--
+--
+--
+-- -------------------------------------------------------------------
+
+-- MODIFIED by ak 22.02.2007, support for numeric std unsigned
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+
+package txt_util is
+
+ -- prints a message to the screen
+ procedure print(text: string);
+
+ -- prints the message when active
+ -- useful for debug switches
+ procedure print(active: boolean; text: string);
+
+ -- converts std_logic into a character
+ function chr(sl: std_logic) return character;
+
+ -- converts std_logic into a string (1 to 1)
+ function str(sl: std_logic) return string;
+
+ -- converts std_logic_vector into a string (binary base)
+ function str(slv: std_logic_vector) return string;
+
+ -- converts std_logic_vector into a string (binary base)
+ function str(slv: unsigned) return string;
+
+ -- converts boolean into a string
+ function str(b: boolean) return string;
+
+ -- converts an integer into a single character
+ -- (can also be used for hex conversion and other bases)
+ function chr(int: integer) return character;
+
+ -- converts integer into string using specified base
+ function str(int: integer; base: integer) return string;
+
+ -- converts integer to string, using base 10
+ function str(int: integer) return string;
+
+ -- convert std_logic_vector into a string in hex format
+ function hstr(slv: std_logic_vector) return string;
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+ -- convert a character to upper case
+ function to_upper(c: character) return character;
+
+ -- convert a character to lower case
+ function to_lower(c: character) return character;
+
+ -- convert a string to upper case
+ function to_upper(s: string) return string;
+
+ -- convert a string to lower case
+ function to_lower(s: string) return string;
+
+
+
+ -- functions to convert strings into other formats
+ --------------------------------------------------
+
+ -- converts a character into std_logic
+ function to_std_logic(c: character) return std_logic;
+
+ -- converts a string into std_logic_vector
+ function to_std_logic_vector(s: string) return std_logic_vector;
+
+
+
+ -- file I/O
+ -----------
+
+ -- read variable length string from input file
+ procedure str_read(file in_file: TEXT;
+ res_string: out string);
+
+ -- print string to a file and start new line
+ procedure print(file out_file: TEXT;
+ new_string: in string);
+
+ -- print character to a file and start new line
+ procedure print(file out_file: TEXT;
+ char: in character);
+
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+ -- prints text to the screen
+
+ procedure print(text: string) is
+ variable msg_line: line;
+ begin
+ write(msg_line, text);
+ writeline(output, msg_line);
+ end print;
+
+
+
+
+ -- prints text to the screen when active
+
+ procedure print(active: boolean; text: string) is
+ begin
+ if active then
+ print(text);
+ end if;
+ end print;
+
+
+ -- converts std_logic into a character
+
+ function chr(sl: std_logic) return character is
+ variable c: character;
+ begin
+ case sl is
+ when 'U' => c:= 'U';
+ when 'X' => c:= 'X';
+ when '0' => c:= '0';
+ when '1' => c:= '1';
+ when 'Z' => c:= 'Z';
+ when 'W' => c:= 'W';
+ when 'L' => c:= 'L';
+ when 'H' => c:= 'H';
+ when '-' => c:= '-';
+ end case;
+ return c;
+ end chr;
+
+
+
+ -- converts std_logic into a string (1 to 1)
+
+ function str(sl: std_logic) return string is
+ variable s: string(1 to 1);
+ begin
+ s(1) := chr(sl);
+ return s;
+ end str;
+
+
+
+ -- converts std_logic_vector into a string (binary base)
+ -- (this also takes care of the fact that the range of
+ -- a string is natural while a std_logic_vector may
+ -- have an integer range)
+
+ function str(slv: std_logic_vector) return string is
+ variable result : string (1 to slv'length);
+ variable r : integer;
+ begin
+ r := 1;
+ for i in slv'range loop
+ result(r) := chr(slv(i));
+ r := r + 1;
+ end loop;
+ return result;
+ end str;
+
+ -- converts std_logic_vector into a string (binary base)
+ -- (this also takes care of the fact that the range of
+ -- a string is natural while a std_logic_vector may
+ -- have an integer range)
+
+ function str(slv: unsigned) return string is
+ variable result : string (1 to slv'length);
+ variable r : integer;
+ begin
+ r := 1;
+ for i in slv'range loop
+ result(r) := chr(slv(i));
+ r := r + 1;
+ end loop;
+ return result;
+ end str;
+
+ function str(b: boolean) return string is
+
+ begin
+ if b then
+ return "true";
+ else
+ return "false";
+ end if;
+ end str;
+
+
+ -- converts an integer into a character
+ -- for 0 to 9 the obvious mapping is used, higher
+ -- values are mapped to the characters A-Z
+ -- (this is usefull for systems with base > 10)
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+ function chr(int: integer) return character is
+ variable c: character;
+ begin
+ case int is
+ when 0 => c := '0';
+ when 1 => c := '1';
+ when 2 => c := '2';
+ when 3 => c := '3';
+ when 4 => c := '4';
+ when 5 => c := '5';
+ when 6 => c := '6';
+ when 7 => c := '7';
+ when 8 => c := '8';
+ when 9 => c := '9';
+ when 10 => c := 'A';
+ when 11 => c := 'B';
+ when 12 => c := 'C';
+ when 13 => c := 'D';
+ when 14 => c := 'E';
+ when 15 => c := 'F';
+ when 16 => c := 'G';
+ when 17 => c := 'H';
+ when 18 => c := 'I';
+ when 19 => c := 'J';
+ when 20 => c := 'K';
+ when 21 => c := 'L';
+ when 22 => c := 'M';
+ when 23 => c := 'N';
+ when 24 => c := 'O';
+ when 25 => c := 'P';
+ when 26 => c := 'Q';
+ when 27 => c := 'R';
+ when 28 => c := 'S';
+ when 29 => c := 'T';
+ when 30 => c := 'U';
+ when 31 => c := 'V';
+ when 32 => c := 'W';
+ when 33 => c := 'X';
+ when 34 => c := 'Y';
+ when 35 => c := 'Z';
+ when others => c := '?';
+ end case;
+ return c;
+ end chr;
+
+
+
+ -- convert integer to string using specified base
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+ function str(int: integer; base: integer) return string is
+
+ variable temp: string(1 to 10);
+ variable num: integer;
+ variable abs_int: integer;
+ variable len: integer := 1;
+ variable power: integer := 1;
+
+ begin
+
+ -- bug fix for negative numbers
+ abs_int := abs(int);
+
+ num := abs_int;
+
+ while num >= base loop -- Determine how many
+ len := len + 1; -- characters required
+ num := num / base; -- to represent the
+ end loop ; -- number.
+
+ for i in len downto 1 loop -- Convert the number to
+ temp(i) := chr(abs_int/power mod base); -- a string starting
+ power := power * base; -- with the right hand
+ end loop ; -- side.
+
+ -- return result and add sign if required
+ if int < 0 then
+ return '-'& temp(1 to len);
+ else
+ return temp(1 to len);
+ end if;
+
+ end str;
+
+
+ -- convert integer to string, using base 10
+ function str(int: integer) return string is
+
+ begin
+
+ return str(int, 10) ;
+
+ end str;
+
+
+
+ -- converts a std_logic_vector into a hex string.
+ function hstr(slv: std_logic_vector) return string is
+ variable hexlen: integer;
+ variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+ variable hex : string(1 to 16);
+ variable fourbit : std_logic_vector(3 downto 0);
+ begin
+ hexlen := (slv'left+1)/4;
+ if (slv'left+1) mod 4 /= 0 then
+ hexlen := hexlen + 1;
+ end if;
+ longslv(slv'left downto 0) := slv;
+ for i in (hexlen -1) downto 0 loop
+ fourbit := longslv(((i*4)+3) downto (i*4));
+ case fourbit is
+ when "0000" => hex(hexlen -I) := '0';
+ when "0001" => hex(hexlen -I) := '1';
+ when "0010" => hex(hexlen -I) := '2';
+ when "0011" => hex(hexlen -I) := '3';
+ when "0100" => hex(hexlen -I) := '4';
+ when "0101" => hex(hexlen -I) := '5';
+ when "0110" => hex(hexlen -I) := '6';
+ when "0111" => hex(hexlen -I) := '7';
+ when "1000" => hex(hexlen -I) := '8';
+ when "1001" => hex(hexlen -I) := '9';
+ when "1010" => hex(hexlen -I) := 'A';
+ when "1011" => hex(hexlen -I) := 'B';
+ when "1100" => hex(hexlen -I) := 'C';
+ when "1101" => hex(hexlen -I) := 'D';
+ when "1110" => hex(hexlen -I) := 'E';
+ when "1111" => hex(hexlen -I) := 'F';
+ when "ZZZZ" => hex(hexlen -I) := 'z';
+ when "UUUU" => hex(hexlen -I) := 'u';
+ when "XXXX" => hex(hexlen -I) := 'x';
+ when others => hex(hexlen -I) := '?';
+ end case;
+ end loop;
+ return hex(1 to hexlen);
+ end hstr;
+
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+
+ -- convert a character to upper case
+
+ function to_upper(c: character) return character is
+
+ variable u: character;
+
+ begin
+
+ case c is
+ when 'a' => u := 'A';
+ when 'b' => u := 'B';
+ when 'c' => u := 'C';
+ when 'd' => u := 'D';
+ when 'e' => u := 'E';
+ when 'f' => u := 'F';
+ when 'g' => u := 'G';
+ when 'h' => u := 'H';
+ when 'i' => u := 'I';
+ when 'j' => u := 'J';
+ when 'k' => u := 'K';
+ when 'l' => u := 'L';
+ when 'm' => u := 'M';
+ when 'n' => u := 'N';
+ when 'o' => u := 'O';
+ when 'p' => u := 'P';
+ when 'q' => u := 'Q';
+ when 'r' => u := 'R';
+ when 's' => u := 'S';
+ when 't' => u := 'T';
+ when 'u' => u := 'U';
+ when 'v' => u := 'V';
+ when 'w' => u := 'W';
+ when 'x' => u := 'X';
+ when 'y' => u := 'Y';
+ when 'z' => u := 'Z';
+ when others => u := c;
+ end case;
+
+ return u;
+
+ end to_upper;
+
+
+ -- convert a character to lower case
+
+ function to_lower(c: character) return character is
+
+ variable l: character;
+
+ begin
+
+ case c is
+ when 'A' => l := 'a';
+ when 'B' => l := 'b';
+ when 'C' => l := 'c';
+ when 'D' => l := 'd';
+ when 'E' => l := 'e';
+ when 'F' => l := 'f';
+ when 'G' => l := 'g';
+ when 'H' => l := 'h';
+ when 'I' => l := 'i';
+ when 'J' => l := 'j';
+ when 'K' => l := 'k';
+ when 'L' => l := 'l';
+ when 'M' => l := 'm';
+ when 'N' => l := 'n';
+ when 'O' => l := 'o';
+ when 'P' => l := 'p';
+ when 'Q' => l := 'q';
+ when 'R' => l := 'r';
+ when 'S' => l := 's';
+ when 'T' => l := 't';
+ when 'U' => l := 'u';
+ when 'V' => l := 'v';
+ when 'W' => l := 'w';
+ when 'X' => l := 'x';
+ when 'Y' => l := 'y';
+ when 'Z' => l := 'z';
+ when others => l := c;
+ end case;
+
+ return l;
+
+ end to_lower;
+
+
+
+ -- convert a string to upper case
+
+ function to_upper(s: string) return string is
+
+ variable uppercase: string (s'range);
+
+ begin
+
+ for i in s'range loop
+ uppercase(i):= to_upper(s(i));
+ end loop;
+ return uppercase;
+
+ end to_upper;
+
+
+
+ -- convert a string to lower case
+
+ function to_lower(s: string) return string is
+
+ variable lowercase: string (s'range);
+
+ begin
+
+ for i in s'range loop
+ lowercase(i):= to_lower(s(i));
+ end loop;
+ return lowercase;
+
+ end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is
+ variable sl: std_logic;
+ begin
+ case c is
+ when 'U' =>
+ sl := 'U';
+ when 'X' =>
+ sl := 'X';
+ when '0' =>
+ sl := '0';
+ when '1' =>
+ sl := '1';
+ when 'Z' =>
+ sl := 'Z';
+ when 'W' =>
+ sl := 'W';
+ when 'L' =>
+ sl := 'L';
+ when 'H' =>
+ sl := 'H';
+ when '-' =>
+ sl := '-';
+ when others =>
+ sl := 'X';
+ end case;
+ return sl;
+ end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is
+ variable slv: std_logic_vector(s'high-s'low downto 0);
+ variable k: integer;
+begin
+ k := s'high-s'low;
+ for i in s'range loop
+ slv(k) := to_std_logic(s(i));
+ k := k - 1;
+ end loop;
+ return slv;
+end to_std_logic_vector;
+
+
+
+
+
+
+----------------
+-- file I/O --
+----------------
+
+
+
+-- read variable length string from input file
+
+procedure str_read(file in_file: TEXT;
+ res_string: out string) is
+
+ variable l: line;
+ variable c: character;
+ variable is_string: boolean;
+
+ begin
+
+ readline(in_file, l);
+ -- clear the contents of the result string
+ for i in res_string'range loop
+ res_string(i) := ' ';
+ end loop;
+ -- read all characters of the line, up to the length
+ -- of the results string
+ for i in res_string'range loop
+ read(l, c, is_string);
+ res_string(i) := c;
+ if not is_string then -- found end of line
+ exit;
+ end if;
+ end loop;
+
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+ new_string: in string) is
+
+ variable l: line;
+
+ begin
+
+ write(l, new_string);
+ writeline(out_file, l);
+
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+ char: in character) is
+
+ variable l: line;
+
+ begin
+
+ write(l, char);
+ writeline(out_file, l);
+
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT;
+ new_string: in string) is
+ begin
+
+ for i in new_string'range loop
+ print(out_file, new_string(i));
+ if new_string(i) = LF then -- end of string
+ exit;
+ end if;
+ end loop;
+
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_reader.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_reader.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_reader.vhd (revision 16)
@@ -0,0 +1,161 @@
+-------------------------------------------------------------------------------
+-- Title : Avalon cfg reader
+-- Project :
+-------------------------------------------------------------------------------
+-- File : avalon_cfg_reader.vhd
+-- Author : kulmala3
+-- Created : 22.03.2005
+-- Last update: 2010/05/07
+-- Description: testbench block to test the config of the dma via avalon
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 22.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use work.txt_util.all;
+--use work.log2_pkg.all;
+use work.tb_n2h2_pkg.all;
+
+entity avalon_cfg_reader is
+ generic (
+ n_chans_g : integer := 0;
+ data_width_g : integer := 0;
+ conf_file_g : string := ""
+ );
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ start_in : in std_logic;
+ avalon_cfg_addr_out : out std_logic_vector(log2(n_chans_g)+conf_bits_c-1 downto 0);
+ avalon_cfg_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_re_out : out std_logic;
+ avalon_cfg_cs_out : out std_logic;
+ done_out : out std_logic
+ );
+end avalon_cfg_reader;
+
+architecture rtl of avalon_cfg_reader is
+
+ signal state_r : integer;
+ signal chan_counter_r : integer;
+begin -- rtl
+
+ -----------------------------------------------------------------------------
+ -- Go through states 0-7
+ ------------------------------------------------------------------------------
+ process (clk, rst_n)
+ file conf_file : text open read_mode is conf_file_g;
+ variable mem_addr_r : integer;
+ variable sender_r : integer;
+ variable irq_amount_r : integer;
+ variable max_amount_r : integer;
+ begin -- process
+ if rst_n = '0' then -- asynchronous reset (active low)
+ chan_counter_r <= 0;
+ avalon_cfg_addr_out <= (others => '0');
+ avalon_cfg_re_out <= '0';
+ avalon_cfg_cs_out <= '0';
+ done_out <= '0';
+ state_r <= 0;
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ case state_r is
+ when 0 =>
+ if start_in = '1' then
+ state_r <= 1;
+ done_out <= '0';
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(0, conf_bits_c);
+ avalon_cfg_re_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ else
+ state_r <= 0;
+ end if;
+
+ when 1 =>
+ read_conf_file (
+ mem_addr => mem_addr_r ,
+ sender => sender_r,
+ irq_amount => irq_amount_r,
+-- max_amount => max_amount_r,
+ file_txt => conf_file
+ );
+
+ assert avalon_cfg_readdata_in = conv_std_logic_vector(mem_addr_r, data_width_g) report "config mismatch mem addr: " & str(avalon_cfg_readdata_in) severity error;
+
+ state_r <= 2;
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(1, conf_bits_c);
+ avalon_cfg_re_out <= '1';
+ avalon_cfg_cs_out <= '1';
+
+ when 2 =>
+
+ assert avalon_cfg_readdata_in = conv_std_logic_vector(sender_r, data_width_g) report "config mismatch sender addr" severity error;
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(2, conf_bits_c);
+ avalon_cfg_re_out <= '1';
+ avalon_cfg_cs_out <= '1';
+
+ state_r <= 3;
+
+ when 3 =>
+
+ assert avalon_cfg_readdata_in = conv_std_logic_vector(irq_amount_r, data_width_g) report "config mismatch irq amount" severity error;
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(3, conf_bits_c);
+ avalon_cfg_re_out <= '1';
+ avalon_cfg_cs_out <= '1';
+
+ state_r <= 4;
+
+ when 4 =>
+ assert avalon_cfg_readdata_in = conv_std_logic_vector(mem_addr_r, data_width_g) report "config mismatch curr addr ptr" severity error;
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(5, conf_bits_c);
+ avalon_cfg_re_out <= '1';
+ avalon_cfg_cs_out <= '1';
+
+ state_r <= 5;
+
+ when 5 =>
+ assert avalon_cfg_readdata_in = conv_std_logic_vector(0, data_width_g) report "config mismatch inits not reseted" severity error;
+ avalon_cfg_re_out <= '0';
+
+ state_r <= 6;
+
+
+ when 6 =>
+ avalon_cfg_cs_out <= '0';
+ chan_counter_r <= chan_counter_r+1;
+ state_r <= 7;
+
+ when 7 =>
+ if chan_counter_r = n_chans_g then
+ state_r <= 0;
+ done_out <= '1';
+ else
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(0, conf_bits_c);
+ avalon_cfg_re_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ state_r <= 1;
+ end if;
+
+ when others => null;
+ end case;
+ end if;
+ end process;
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/fifo.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/fifo.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/fifo.vhd (revision 16)
@@ -0,0 +1,293 @@
+-------------------------------------------------------------------------------
+-- File : fifo.vhdl
+-- Description : Fifo buffer for hibi interface
+-- Author : Erno Salminen
+-- e-mail : erno.salminen@tut.fi
+-- Project : mikälie
+-- Design : Do not use term design when you mean system
+-- Date : 29.04.2002
+-- Modified : 30.04.2002 Vesa Lahtinen Optimized for synthesis
+--
+-- 15.12.04 ES: names changed
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity fifo is
+
+ generic (
+ data_width_g : integer := 32;
+ depth_g : integer := 5
+ );
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+
+ data_in : in std_logic_vector (data_width_g-1 downto 0);
+ we_in : in std_logic;
+ full_out : out std_logic;
+ one_p_out : out std_logic;
+
+ re_in : in std_logic;
+ data_out : out std_logic_vector (data_width_g-1 downto 0);
+ empty_out : out std_logic;
+ one_d_out : out std_logic
+ );
+
+end fifo;
+
+architecture behavioral of fifo is
+
+
+ -- Registers
+ signal full_r : std_logic;
+ signal empty_r : std_logic;
+ signal one_d_r : std_logic;
+ signal one_p_r : std_logic;
+ signal data_amount_r : std_logic_vector (depth_g-1 downto 0);
+
+ signal in_ptr_r : integer range 0 to depth_g-1;
+ signal out_ptr_r : integer range 0 to depth_g-1;
+
+ type data_arr_type is array (depth_g-1 downto 0) of std_logic_vector (data_width_g-1 downto 0);
+ signal fifo_buffer_r : data_arr_type;
+
+
+begin -- behavioral
+
+ -- Continuous assignments
+ -- Assigns register values to outputs
+ full_out <= full_r;
+ empty_out <= empty_r;
+ one_d_out <= one_d_r;
+ one_p_out <= one_p_r;
+ data_out <= fifo_buffer_r (out_ptr_r); -- mux at output!
+ -- Note! There is some old value in data output when fifo is empty.
+
+
+Main : process (clk, rst_n)
+begin -- process Main
+ if rst_n = '0' then -- asynchronous reset (active low)
+
+ -- Reset all registers
+ -- Fifo is empty at first
+ full_r <= '0';
+ empty_r <= '1';
+ one_d_r <= '0';
+ in_ptr_r <= 0;
+ out_ptr_r <= 0;
+ data_amount_r <= (others => '0');
+
+ if depth_g =1 then -- 30.07
+ one_p_r <= '1';
+ else
+ one_p_r <= '0';
+ end if;
+
+ for i in 0 to depth_g-1 loop
+ fifo_buffer_r (i) <= (others => '0');
+ end loop; -- i
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+
+ -- 1) Write data to fifo
+ if we_in = '1' and re_in = '0' then
+
+ if full_r = '0' then
+ empty_r <= '0';
+ if (in_ptr_r = (depth_g-1)) then
+ in_ptr_r <= 0;
+ else
+ in_ptr_r <= in_ptr_r + 1;
+ end if;
+ out_ptr_r <= out_ptr_r;
+ data_amount_r <= data_amount_r +1;
+ fifo_buffer_r (in_ptr_r) <= data_in;
+
+ -- Check if the fifo is getting full
+ if data_amount_r + 2 = depth_g then
+ full_r <= '0';
+ one_p_r <= '1';
+ elsif data_amount_r +1 = depth_g then
+ full_r <= '1';
+ one_p_r <= '0';
+ else
+ full_r <= '0';
+ one_p_r <= '0';
+ end if;
+
+ -- If fifo was empty, it has now one data
+ if empty_r = '1' then
+ one_d_r <= '1';
+ else
+ one_d_r <= '0';
+ end if;
+
+ else
+ in_ptr_r <= in_ptr_r;
+ out_ptr_r <= out_ptr_r;
+ full_r <= full_r;
+ empty_r <= empty_r;
+ fifo_buffer_r <= fifo_buffer_r;
+ data_amount_r <= data_amount_r;
+ one_d_r <= one_d_r;
+ one_p_r <= one_p_r;
+ end if;
+
+
+ -- 2) Read data from fifo
+ elsif we_in = '0' and re_in = '1' then
+
+ if empty_r = '0' then
+ in_ptr_r <= in_ptr_r;
+ if (out_ptr_r = (depth_g-1)) then
+ out_ptr_r <= 0;
+ else
+ out_ptr_r <= out_ptr_r + 1;
+ end if;
+ full_r <= '0';
+ data_amount_r <= data_amount_r -1;
+
+ -- Debug
+ -- fifo_buffer_r (out_ptr_r) <= (others => '1');
+
+ -- Check if the fifo is getting empty
+ if data_amount_r = 2 then
+ empty_r <= '0';
+ one_d_r <= '1';
+ elsif data_amount_r = 1 then
+ empty_r <= '1';
+ one_d_r <= '0';
+ else
+ empty_r <= '0';
+ one_d_r <= '0';
+ end if;
+
+ -- If fifo was full, it is no more
+ if full_r = '1' then
+ one_p_r <= '1';
+ else
+ one_p_r <= '0';
+ end if;
+
+ else
+ in_ptr_r <= in_ptr_r;
+ out_ptr_r <= out_ptr_r;
+ full_r <= full_r;
+ empty_r <= empty_r;
+ fifo_buffer_r <= fifo_buffer_r;
+ data_amount_r <= data_amount_r;
+ one_d_r <= one_d_r;
+ one_p_r <= one_p_r;
+ end if;
+
+
+ -- 3) Write and read at the same time
+ elsif we_in = '1' and re_in = '1' then
+
+
+ if full_r = '0' and empty_r = '0' then
+ if (in_ptr_r = (depth_g-1)) then
+ in_ptr_r <= 0;
+ else
+ in_ptr_r <= in_ptr_r + 1;
+ end if;
+ if (out_ptr_r = (depth_g-1)) then
+ out_ptr_r <= 0;
+ else
+ out_ptr_r <= out_ptr_r + 1;
+ end if;
+ full_r <= '0';
+ empty_r <= '0';
+ data_amount_r <= data_amount_r;
+ one_d_r <= one_d_r;
+ one_p_r <= one_p_r;
+
+ fifo_buffer_r (in_ptr_r) <= data_in;
+ -- fifo_buffer_r (out_ptr_r) <= (others => '1'); --debug
+
+
+ elsif full_r = '1' and empty_r = '0' then
+ -- Fifo is full, only reading is possible
+ in_ptr_r <= in_ptr_r;
+ if (out_ptr_r = (depth_g-1)) then
+ out_ptr_r <= 0;
+ else
+ out_ptr_r <= out_ptr_r + 1;
+ end if;
+ full_r <= '0';
+ one_p_r <= '1';
+ --fifo_buffer_r (out_ptr_r) <= (others => '1'); -- Debug
+ data_amount_r <= data_amount_r -1;
+
+ -- Check if the fifo is getting empty
+ if data_amount_r = 2 then
+ empty_r <= '0';
+ one_d_r <= '1';
+ elsif data_amount_r = 1 then
+ empty_r <= '1';
+ one_d_r <= '0';
+ else
+ empty_r <= '0';
+ one_d_r <= '0';
+ end if;
+
+
+ elsif full_r = '0' and empty_r = '1' then
+ -- Fifo is empty, only writing is possible
+ if (in_ptr_r = (depth_g-1)) then
+ in_ptr_r <= 0;
+ else
+ in_ptr_r <= in_ptr_r + 1;
+ end if;
+ out_ptr_r <= out_ptr_r;
+ empty_r <= '0';
+ one_d_r <= '1';
+ fifo_buffer_r (in_ptr_r) <= data_in;
+ data_amount_r <= data_amount_r +1;
+
+ -- Check if the fifo is getting full
+ if data_amount_r + 2 = depth_g then
+ full_r <= '0';
+ one_p_r <= '1';
+ elsif data_amount_r +1 = depth_g then
+ full_r <= '1';
+ one_p_r <= '0';
+ else
+ full_r <= '0';
+ one_p_r <= '0';
+ end if;
+
+
+ -- 4) Do nothing, fifo remains idle
+ else
+
+ in_ptr_r <= in_ptr_r;
+ out_ptr_r <= out_ptr_r;
+ full_r <= full_r;
+ empty_r <= empty_r;
+ fifo_buffer_r <= fifo_buffer_r;
+ data_amount_r <= data_amount_r;
+ one_d_r <= one_d_r;
+ one_p_r <= one_p_r;
+ end if;
+
+ else
+ -- Fifo is idle
+ in_ptr_r <= in_ptr_r;
+ out_ptr_r <= out_ptr_r;
+ full_r <= full_r;
+ empty_r <= empty_r;
+ fifo_buffer_r <= fifo_buffer_r;
+ data_amount_r <= data_amount_r;
+ one_d_r <= one_d_r;
+ one_p_r <= one_p_r;
+ end if;
+
+ end if;
+end process Main;
+
+end behavioral;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_writer.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_writer.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_writer.vhd (revision 16)
@@ -0,0 +1,218 @@
+-------------------------------------------------------------------------------
+-- Title : Avalon cfg writer
+-- Project :
+-------------------------------------------------------------------------------
+-- File : avalon_cfg_writer.vhd
+-- Author : kulmala3
+-- Created : 22.03.2005
+-- Last update: 2010/05/07
+-- Description: testbench block to config the dma via avalon
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 22.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use work.txt_util.all;
+--use work.log2_pkg.all;
+use work.tb_n2h2_pkg.all;
+
+entity avalon_cfg_writer is
+ generic (
+ n_chans_g : integer := 0;
+ data_width_g : integer := 0;
+ conf_file_g : string := ""
+ );
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ start_in : in std_logic;
+ avalon_cfg_addr_out : out std_logic_vector(log2(n_chans_g)+conf_bits_c-1 downto 0);
+ avalon_cfg_writedata_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_we_out : out std_logic;
+ avalon_cfg_cs_out : out std_logic;
+ init_in : in std_logic;
+ done_out : out std_logic
+ );
+end avalon_cfg_writer;
+
+architecture rtl of avalon_cfg_writer is
+
+ signal state_r : integer;
+ signal init_state_r : integer;
+ signal chan_counter_r : integer;
+begin -- rtl
+
+ process (clk, rst_n)
+ file conf_file : text open read_mode is conf_file_g;
+ variable mem_addr_r : integer;
+ variable sender_r : integer;
+ variable irq_amount_r : integer;
+ variable max_amount_r : integer;
+ begin -- process
+ if rst_n = '0' then -- asynchronous reset (active low)
+ chan_counter_r <= 0;
+ avalon_cfg_cs_out <= '0';
+ avalon_cfg_we_out <= '0';
+ avalon_cfg_writedata_out <= (others => '0');
+ avalon_cfg_addr_out <= (others => '0');
+ done_out <= '0';
+ state_r <= 0;
+ init_state_r <= 0;
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ case state_r is
+ when 0 =>
+ if start_in = '1' then
+ state_r <= 1;
+ done_out <= '0';
+ else
+ done_out <= '0';
+ state_r <= 0;
+ end if;
+
+ when 1 =>
+ read_conf_file (
+ mem_addr => mem_addr_r ,
+ sender => sender_r,
+ irq_amount => irq_amount_r,
+-- max_amount => max_amount_r,
+ file_txt => conf_file
+ );
+
+ assert false report "mem_addr: " & str(mem_addr_r) severity note;
+ assert false report "sender_r: " & str(sender_r) severity note;
+ assert false report "irq_amount_r: " & str(irq_amount_r) severity note;
+-- assert false report "max_amount_r: " & str(max_amount_r) severity note;
+
+ avalon_cfg_writedata_out <= conv_std_logic_vector(mem_addr_r, data_width_g);
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(0, conf_bits_c);
+ avalon_cfg_we_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ state_r <= 2;
+
+ when 2 =>
+
+ avalon_cfg_writedata_out <= conv_std_logic_vector(sender_r, data_width_g);
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(1, conf_bits_c);
+
+ avalon_cfg_we_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ state_r <= 3;
+
+ when 3 =>
+
+ avalon_cfg_writedata_out <= conv_std_logic_vector(irq_amount_r, data_width_g);
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(2, conf_bits_c);
+
+ avalon_cfg_we_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ state_r <= 5;
+
+ -- obsolete
+-- when 4 =>
+
+-- avalon_cfg_writedata_out <= conv_std_logic_vector(max_amount_r, data_width_g);
+-- avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+-- conv_std_logic_vector(0, conf_bits_c);
+-- avalon_cfg_we_out <= '1';
+-- avalon_cfg_cs_out <= '1';
+-- state_r <= 5;
+
+ when 5 =>
+ -- set init bit
+ avalon_cfg_writedata_out <= (others => '0');
+ avalon_cfg_writedata_out(chan_counter_r) <= '1';
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(5, conf_bits_c);
+ avalon_cfg_we_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ state_r <= 6;
+
+ when 6 =>
+ -- set irq_ena bit
+ avalon_cfg_writedata_out <= (others => '0');
+ avalon_cfg_writedata_out(1) <= '1';
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(4, conf_bits_c);
+ avalon_cfg_we_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ state_r <= 7;
+
+ -- obsolete
+-- when 6 =>
+-- -- reset init
+-- avalon_cfg_writedata_out <= conv_std_logic_vector(2, data_width_g);
+-- avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+-- conv_std_logic_vector(0, conf_bits_c);
+-- avalon_cfg_we_out <= '1';
+-- avalon_cfg_cs_out <= '1';
+-- state_r <= 7;
+
+ when 7 =>
+ avalon_cfg_cs_out <= '0';
+ chan_counter_r <= chan_counter_r+1;
+ state_r <= 8;
+
+ when 8 =>
+ if chan_counter_r = n_chans_g then
+ state_r <= 0;
+ chan_counter_r <= 0;
+ avalon_cfg_we_out <= '0';
+ done_out <= '1';
+ else
+ state_r <= 1;
+ end if;
+
+ when others => null;
+ end case;
+
+ if init_in = '1' then
+ init_state_r <= 1;
+ end if;
+
+ case init_state_r is
+ when 1 =>
+ -- set init bit
+ avalon_cfg_writedata_out <= (others => '0');
+ avalon_cfg_writedata_out(chan_counter_r) <= '1';
+
+ avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
+ conv_std_logic_vector(5, conf_bits_c);
+ avalon_cfg_we_out <= '1';
+ avalon_cfg_cs_out <= '1';
+ init_state_r <= 2;
+ chan_counter_r <= chan_counter_r+1;
+
+ when 2 =>
+ if chan_counter_r = n_chans_g then
+ init_state_r <= 0;
+ avalon_cfg_we_out <= '0';
+ avalon_cfg_cs_out <= '0';
+ done_out <= '1';
+ chan_counter_r <= 0;
+ else
+ avalon_cfg_we_out <= '0';
+ init_state_r <= 1;
+ end if;
+
+ when others => null;
+ end case;
+
+ end if;
+ end process;
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_fo.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_fo.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_fo.vhd (revision 16)
@@ -0,0 +1,511 @@
+------------------------------------------------------------
+-- Project : Engine
+-- Author : Ari Kulmala
+-- e-mail : ari.kulmala@tut.fi
+-- Date : 7.7.2004
+-- File : tb_n2h_tx.vhdl
+-- Design : testbench for nios to hibi transmitter
+-- Try with N2H2 TX
+------------------------------------------------------------
+-- Description : a testbench for n2h_tx individual testing.
+-- synchronous.
+------------------------------------------------------------
+-- $Log$
+-- Revision 1.1 2005/04/14 06:45:55 kulmala3
+-- First version to CVS
+--
+-- 31.08.04 AK Streaming
+-- 05.01.04 AK Interface signals naming changed.
+------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity tb_n2h2_tx is
+
+end tb_n2h2_tx;
+
+architecture rtl of tb_n2h2_tx is
+ constant PERIOD : time := 50 ns;
+
+ constant data_width_g : integer := 32;
+ constant amount_width_g : integer := 9;
+ constant addr_width_g : integer := 32;
+ constant addr_offset_c : integer := (data_width_g)/8;
+
+ constant comm_write : std_logic_vector(4 downto 0) := "00010";
+ constant comm_idle : std_logic_vector(4 downto 0) := "00000";
+ constant comm_write_msg : std_logic_vector(4 downto 0) := "00011";
+
+ constant data_start : integer := 0;
+ constant wait_req_freq_c : integer := 10;
+
+
+ type test_states is (test1, test2, test3, stop_tests);
+ signal test_control : test_states := test1;
+ type test_case_states is (assign, trigger, monitor, finish);
+ signal test_case_control : test_case_states := trigger;
+
+ signal clk : std_logic;
+ signal clk2 : std_logic;
+ signal rst_n : std_logic;
+
+
+ -- signals from n2h_tx
+ signal tx_status_from_n2h_tx : std_logic := '0';
+ signal tx_busy_from_n2h_tx : std_logic;
+
+ -- signals to n2h_tx
+ signal internal_wait_to_n2h_tx : std_logic := '0';
+ signal tx_irq_to_n2h_tx : std_logic;
+ signal Amount_to_n2h_tx : integer := 0;
+ signal Amount_vec_to_n2h_tx : std_logic_vector(amount_width_g-1 downto 0);
+ signal dpram_vec_addr_to_n2h_tx : std_logic_vector(addr_width_g-1 downto 0);
+ signal dpram_addr_to_n2h_tx : integer := 0;
+ signal comm_to_n2h_tx : std_logic_vector(4 downto 0);
+ --hibi
+ signal hibi_data_vec_from_n2h_tx : std_logic_vector(data_width_g-1 downto 0);
+ signal hibi_data_from_n2h_tx : integer := 0;
+ signal hibi_av_from_n2h_tx : std_logic := '0';
+ signal hibi_full_to_n2h_tx : std_logic := '1';
+ signal hibi_comm_from_n2h_tx : std_logic_vector(4 downto 0);
+ signal hibi_we_from_n2h_tx : std_logic;
+ -- avalon
+ signal avalon_addr_from_n2h_tx : std_logic_vector(addr_width_g-1 downto 0);
+ signal avalon_read_from_n2h_tx : std_logic;
+ signal avalon_vec_readdata_to_n2h_tx : std_logic_vector(data_width_g-1 downto 0);
+ signal avalon_readdata_to_n2h_tx : integer := 0;
+ signal avalon_waitrequest_to_n2h_tx : std_logic;
+ signal avalon_readdatavalid_to_n2h_tx : std_logic;
+ -- others
+ signal counter : integer := 0; -- temp counter, no special func
+ signal new_hibi_addr : integer := 0;
+ signal new_amount : integer := 0;
+ signal new_dpram_addr : integer := 0;
+
+ -- which address hibi should get next
+ signal global_hibi_address : integer := 0;
+ -- global number of data in next packet
+ signal global_amount : integer := 0;
+ signal global_comm : std_logic_vector(4 downto 0);
+ signal global_dpram_addr : integer := 0; -- given dpram addr
+
+ -- check avalon signals
+ signal avalon_data_counter : integer := data_start; -- data sent
+ signal avalon_addr_counter : integer := 0; -- avalon addr right?
+ signal avalon_amount : integer := 0; -- how many data
+ signal avalon_addr_sent : std_logic := '0'; -- if already gave address
+ signal avalon_last_addr : integer := 0; -- store the old addr
+-- signal avalon_gave_data : std_logic := 0; -- avalon timing
+-- signal avalon_ok : std_logic := '0'; -- all the avalon data ok
+
+ -- check hibi signals
+ signal hibi_addr_came : std_logic := '0';
+ signal hibi_data_counter : integer := data_start; -- data received
+ signal hibi_addr : integer := 0; -- right hibi addr
+ signal hibi_amount : integer := 0; -- how many datas hibi has received
+-- signal hibi_ok : std_logic := '0'; --hibi received all ok.
+begin -- rtl
+
+ hibi_data_from_n2h_tx <= conv_integer(hibi_data_vec_from_n2h_tx);
+ Amount_vec_to_n2h_tx <= conv_std_logic_vector(Amount_to_n2h_tx, amount_width_g);
+ dpram_vec_addr_to_n2h_tx <=
+ conv_std_logic_vector(dpram_addr_to_n2h_tx, addr_width_g);
+ avalon_vec_readdata_to_n2h_tx <=
+ conv_std_logic_vector(avalon_readdata_to_n2h_tx, data_width_g);
+
+
+ n2h2_tx_1 : entity work.n2h2_tx
+ generic map (
+ data_width_g => data_width_g,
+ amount_width_g => amount_width_g)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+
+ -- Avalon master read interface
+ avalon_addr_out => avalon_addr_from_n2h_tx,
+ avalon_re_out => avalon_read_from_n2h_tx,
+ avalon_readdata_in => avalon_vec_readdata_to_n2h_tx,
+ avalon_waitrequest_in => avalon_waitrequest_to_n2h_tx,
+ avalon_readdatavalid_in => avalon_readdatavalid_to_n2h_tx, -- ES 2010/05/07
+
+ -- hibi write interface
+ hibi_data_out => hibi_data_vec_from_n2h_tx,
+ hibi_av_out => hibi_av_from_n2h_tx,
+ hibi_full_in => hibi_full_to_n2h_tx,
+ hibi_comm_out => hibi_comm_from_n2h_tx,
+ hibi_we_out => hibi_we_from_n2h_tx,
+
+ -- DMA conf interface
+ tx_start_in => tx_irq_to_n2h_tx,
+ tx_status_done_out => tx_status_from_n2h_tx,
+ tx_comm_in => comm_to_n2h_tx,
+ tx_hibi_addr_in => (others => '0'),
+ tx_ram_addr_in => dpram_vec_addr_to_n2h_tx,
+ tx_amount_in => Amount_vec_to_n2h_tx
+ );
+
+
+
+-- tx : n2h_tx
+-- generic map (
+-- data_width_g => data_width_g,
+-- amount_width_g => amount_width_g,
+-- addr_width_g => addr_width_g
+-- )
+
+-- port map (
+-- clk => clk,
+-- rst_n => rst_n,
+-- tx_busy_out => tx_busy_from_n2h_tx,
+-- comm_in => comm_to_n2h_tx,
+-- Amount_in => Amount_vec_to_n2h_tx,
+-- dpram_addr_in => dpram_vec_addr_to_n2h_tx,
+-- tx_irq_in => tx_irq_to_n2h_tx,
+-- tx_status_out => tx_status_from_n2h_tx,
+-- avalon_addr_out => avalon_addr_from_n2h_tx,
+-- avalon_re_out => avalon_read_from_n2h_tx,
+-- avalon_readdata_in => avalon_vec_readdata_to_n2h_tx,
+-- avalon_readdatavalid_in => avalon_readdatavalid_to_n2h_tx,
+-- avalon_waitrequest_in => avalon_waitrequest_to_n2h_tx,
+-- internal_wait_in => internal_wait_to_n2h_tx,
+-- hibi_data_out => hibi_data_vec_from_n2h_tx,
+-- hibi_comm_out => hibi_comm_from_n2h_tx,
+-- hibi_av_out => hibi_av_from_n2h_tx,
+-- hibi_we_out => hibi_we_from_n2h_tx,
+-- hibi_full_in => hibi_full_to_n2h_tx
+-- );
+
+ -- check_avalon and check_hibi continuously monitor avalon and hibi
+ -- buses. the tests doesn't have to check whether the data came right,
+ -- those do it automatically. that's because the sent data is implemented
+ -- as a counter, so that the incoming data should be in order.
+ -- if theres too much data read from avalon, hibi gets wrong packets
+ -- and informs.
+ -- if theres too much/few data sent to hibi, hibi informs.
+
+
+ -- test is the main process that is implented as a state machine
+ -- (test1, test2 ... etc) so that new tests can be easily implemented
+ test : process (clk, rst_n)
+ begin -- process test
+ if rst_n = '0' then -- asynchronous reset (active low)
+ test_control <= test2;
+ test_case_control <= assign;
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ case test_control is
+
+ -----------------------------------------------------------------------
+ -- tests is controlled by following signals, which must be set
+ -- global_hibi_address
+ -- global_amount
+ -- global_comm
+
+ -- TEST 1 IS OBSOLETE
+ --
+ -----------------------------------------------------------------------
+ when test1 =>
+ -- basic test. tests action under hibi_full signal
+ -- and how one packet is transferred.
+ case test_case_control is
+ when trigger =>
+ -- assign and trigger irq.
+
+
+ if tx_status_from_n2h_tx = '1' then
+ global_amount <= 4;
+ Amount_to_n2h_tx <= 4;
+ global_hibi_address <= 230;
+ global_comm <= comm_write;
+ comm_to_n2h_tx <= comm_write;
+ tx_irq_to_n2h_tx <= '1';
+ dpram_addr_to_n2h_tx <= 8;
+ global_dpram_addr <= 8;
+ test_case_control <= monitor;
+ -- assert hibi full signal
+ hibi_full_to_n2h_tx <= '1';
+
+ else
+ assert false report "cannot start test, tx_status low" severity note;
+ end if;
+ when monitor =>
+ tx_irq_to_n2h_tx <= '0';
+
+ counter <= counter+1;
+ if counter < 10 then
+ test_case_control <= monitor;
+ else
+ hibi_full_to_n2h_tx <= '0';
+ test_case_control <= finish;
+ end if;
+
+-- if tx_status_from_n2h_tx = '1' then
+-- -- values read.
+-- Amount_to_n2h_tx <= 0;
+-- dpram_addr_to_n2h_tx <= 0;
+-- comm_to_n2h_tx <= comm_idle;
+-- -- lets test the full signal
+-- end if;
+
+ when finish =>
+ if tx_status_from_n2h_tx = '1' then
+ assert false report "test1 finished." severity note;
+ test_control <= test2;
+ test_case_control <= assign;
+ counter <= 0;
+ else
+ test_case_control <= finish;
+ end if;
+
+
+ when others => null;
+ end case;
+ when test2 =>
+ -- tests how multiple packets are transferred and
+ -- how max values are treated.
+
+ case test_case_control is
+ when assign =>
+ -- we always go to trigger next, unless otherwise noted.
+ test_case_control <= trigger;
+ -- assign new values
+ if counter = 0 then
+ new_amount <= 6;
+ new_hibi_addr <= 6302;
+ new_dpram_addr <= 400;
+ elsif counter = 1 then
+ new_amount <= 172;
+ new_hibi_addr <= 30;
+ new_dpram_addr <= 300;
+ elsif counter = 2 then
+ new_amount <= 1;
+ new_hibi_addr <= 21;
+ new_dpram_addr <= 323;
+ elsif counter = 3 then
+ new_amount <= 14;
+ new_hibi_addr <= 54;
+ new_dpram_addr <= 12;
+ elsif counter = 4 then
+ new_amount <= 6;
+ new_hibi_addr <= 602;
+ new_dpram_addr <= 40;
+ elsif counter = 5 then
+ new_amount <= 9;
+ new_hibi_addr <= 64510;
+ new_dpram_addr <= 511;
+ else
+ --stop the tests
+ test_control <= stop_tests;
+ test_case_control <= assign;
+ end if;
+
+ counter <= counter+1;
+
+ when trigger =>
+ -- assign and trigger irq.
+
+ if tx_status_from_n2h_tx = '1' then
+ global_amount <= new_amount;
+ Amount_to_n2h_tx <= new_amount;
+ global_hibi_address <= new_hibi_addr;
+ global_comm <= comm_write;
+ comm_to_n2h_tx <= comm_write;
+ tx_irq_to_n2h_tx <= '1';
+ dpram_addr_to_n2h_tx <= new_dpram_addr;
+ global_dpram_addr <= new_dpram_addr;
+ test_case_control <= monitor;
+ -- deassert hibi full signal, just in case
+ hibi_full_to_n2h_tx <= '0';
+
+ else
+ assert false report "cannot start test, tx_status low" severity note;
+ end if;
+
+ when monitor =>
+ tx_irq_to_n2h_tx <= '0';
+-- if tx_status_from_n2h_tx = '1' then
+-- -- values read.
+-- Amount_to_n2h_tx <= 0;
+-- dpram_addr_to_n2h_tx <= 0;
+-- comm_to_n2h_tx <= comm_idle;
+ -- lets test the full signal
+ test_case_control <= finish;
+-- end if;
+
+ when finish =>
+ if tx_status_from_n2h_tx = '1' then
+ assert false report "test2 finished." severity note;
+ test_case_control <= assign;
+ else
+ test_case_control <= finish;
+ end if;
+
+
+ when others => null;
+ end case;
+ when test3 =>
+ when stop_tests =>
+ assert false report "all tests finished." severity failure;
+ when others => null;
+ end case;
+ end if;
+ end process test;
+
+ -- checks whether incoming data to hibi is right
+ check_hibi : process (clk)
+ begin -- process check_hibi
+ if clk = '1' and clk'event then
+ if hibi_amount = 0 then
+ hibi_addr_came <= '0';
+ end if;
+
+ assert hibi_amount >= 0 report "hibi amount negative - too much data" severity warning;
+
+ if hibi_we_from_n2h_tx = '1' then
+
+ if hibi_comm_from_n2h_tx /= global_comm then
+ assert false report "hibi command failure - not as expected" severity warning;
+ end if;
+
+ -- if address valid comes before we have received all the data
+ -- we expected, thats wrong
+ if hibi_av_from_n2h_tx = '1' then
+ if hibi_amount = 0 then
+ if hibi_data_from_n2h_tx = global_hibi_address then
+ hibi_addr_came <= '1';
+ hibi_amount <= global_amount;
+ else
+ assert false report "hibi address wasn't expected" severity warning;
+ end if;
+
+ else
+ assert false report "Hibi data failure, address came but shouldn't have" severity warning;
+ end if;
+
+ else
+ -- if address has been received
+ if hibi_addr_came = '1' then
+ -- and the data is right
+ if hibi_data_from_n2h_tx = hibi_data_counter then
+ hibi_data_counter <= hibi_data_counter+1;
+ hibi_amount <= hibi_amount-1;
+ if hibi_amount = 1 then
+ hibi_addr_came <= '0';
+ end if;
+ else
+ assert false report "hibi data was wrong" severity warning;
+ end if;
+
+ else
+ assert false report "data came before an address" severity warning;
+ end if;
+ end if;
+
+ end if;
+ end if;
+
+ end process check_hibi;
+
+ check_avalon : process (clk2)
+ variable waitreq_cnt_r : integer := 0;
+ begin -- process check_avalon
+ if clk2'event and clk2 = '1' then -- rising clock edge
+
+
+ avalon_last_addr <= conv_integer(avalon_addr_from_n2h_tx);
+
+ assert avalon_amount >= 0 report "avalon amount negative - tried to read too much data" severity warning;
+
+ if avalon_read_from_n2h_tx = '1' and avalon_waitrequest_to_n2h_tx = '0' then --and
+-- avalon_readdatavalid_to_n2h_tx = '1' then
+-- avalon_readdatavalid_to_n2h_tx <= '1';
+ if (global_dpram_addr + avalon_addr_counter) /=
+ avalon_addr_from_n2h_tx then
+ assert false report "address to avalon is wrong" severity warning;
+ else
+ if (global_dpram_addr + avalon_addr_counter) = (2**addr_width_g-2) then
+ avalon_addr_counter <= 0 - global_dpram_addr;
+ elsif (global_dpram_addr + avalon_addr_counter) = (2**addr_width_g-1) then
+ -- odd number (eg. 511) overflow, add one.
+ avalon_addr_counter <= 1 - global_dpram_addr;
+ else
+ avalon_addr_counter <= avalon_addr_counter + addr_offset_c;
+ end if;
+ end if;
+
+ --avalon_waitrequest_to_n2h_tx <= '0';
+ avalon_readdatavalid_to_n2h_tx <= '1';
+ if avalon_addr_sent = '0' then
+ -- first slot contains address
+ avalon_readdata_to_n2h_tx <= global_hibi_address;
+ avalon_addr_sent <= '1';
+ avalon_amount <= global_amount;
+ else
+ -- now the data
+ if avalon_last_addr = avalon_addr_from_n2h_tx then
+ avalon_readdata_to_n2h_tx <= avalon_data_counter;
+ avalon_data_counter <= avalon_data_counter;
+ avalon_amount <= avalon_amount;
+ else
+ avalon_readdata_to_n2h_tx <= avalon_data_counter;
+ avalon_data_counter <= avalon_data_counter+1;
+ avalon_amount <= avalon_amount-1;
+ end if;
+ if avalon_amount = 1 then
+ -- next we expect that a new packet should be sent.
+ avalon_addr_sent <= '0';
+ avalon_addr_counter <= 0;
+ end if;
+ end if;
+-- elsif avalon_read_from_n2h_tx = '1' and avalon_readdatavalid_to_n2h_tx = '0' then
+-- avalon_readdatavalid_to_n2h_tx <= '1';
+-- avalon_waitrequest_to_n2h_tx <= '0';
+ else
+
+-- avalon_readdata_to_n2h_tx <= 0;
+ --avalon_waitrequest_to_n2h_tx <= '1';
+-- avalon_readdatavalid_to_n2h_tx <= '0';
+ end if;
+ avalon_waitrequest_to_n2h_tx <= '0'; -- was always
+ waitreq_cnt_r := waitreq_cnt_r +1;
+ -- generate waitreq
+ if waitreq_cnt_r = wait_req_freq_c then
+ avalon_waitrequest_to_n2h_tx <= '1';
+ waitreq_cnt_r := 0;
+ end if;
+
+
+ end if;
+ end process check_avalon;
+
+ CLOCK1 : process -- generate clock signal for design
+ variable clktmp : std_logic := '0';
+ begin
+ wait for PERIOD/2;
+ clktmp := not clktmp;
+ Clk <= clktmp;
+ end process CLOCK1;
+
+ -- different phase for the avalon bus
+ CLOCK2 : process -- generate clock signal for design
+ variable clk2tmp : std_logic := '0';
+ begin
+ clk2tmp := not clk2tmp;
+ Clk2 <= clk2tmp;
+ wait for PERIOD/2;
+ end process CLOCK2;
+
+ RESET : process
+ begin
+ Rst_n <= '0'; -- Reset the testsystem
+ wait for 6*PERIOD; -- Wait
+ Rst_n <= '1'; -- de-assert reset
+ wait;
+ end process RESET;
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_fo.do
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_fo.do (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_fo.do (revision 16)
@@ -0,0 +1,22 @@
+
+quit -sim
+
+vlib work
+
+# HW files
+
+vcom -check_synthesis -pedantic ../vhd/one_hot_mux.vhd
+vcom -check_synthesis -pedantic ../vhd/step_counter2.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_chan.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_rx_channels.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_tx_vl.vhd
+vcom -check_synthesis -pedantic ../vhd/n2h2_chan.vhd
+
+
+# TB files
+
+vcom ./blocks/sram_scalable_v3.vhd
+vcom ./blocks/tb_n2h2_tx_fo.vhd
+
+vsim -t 1ns work.tb_n2h2_tx
+do blocks/wave_tb_n2h2_tx_fo.do
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/tb/tbrx_data_file.dat
===================================================================
--- TUT/ip.hwp.communication/n2h2/tb/tbrx_data_file.dat (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/tb/tbrx_data_file.dat (revision 16)
@@ -0,0 +1,3 @@
+1111 1115 12
+1111 1116 12
+1111 1117 12
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/kci.xml
===================================================================
--- TUT/ip.hwp.communication/n2h2/kci.xml (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/kci.xml (revision 16)
@@ -0,0 +1,44 @@
+
+
+ n2h2
+ Nios to Hibi v2
+ Flags:
+-NIOS_II: Nios2 in use, not Nios1.
+-API: Use PC-to-HIBI API or similar.
+-ECOS: eCos in use. If it is not in use, libraries generated by Nios2IDE should be used. Used only when API is defined.
+
+ doc\n2h2.mdzip
+ doc\n2h2.pptx
+
+
+
+ -DNIOS_II
+
+
+ common_headers
+
+
+
+ drv/tut_n2h_regs.c
+
+
+ drv
+
+
+
+ -DAPI -DECOS
+
+
+ common_headers
+
+
+
+ drv\tut_n2h_regs.c
+
+
+ drv
+
+
+
+
+
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/cb_generator.pl
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/cb_generator.pl (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/cb_generator.pl (revision 16)
@@ -0,0 +1,1125 @@
+# | file: cb_generator.pl
+# |
+# | This SOPC Builder Generator program is provided by
+# | the Component Builder application. It is copied
+# | straight across and is data-driven from its command
+# | line arguments and the PTF files referenced.
+# |
+# | Its purpose is to construct an HDL "wrapper" for
+# | a particular instance of a particular SOPC Builder
+# | peripheral. This wrapper resolves the instance
+# | name and any HDL parameterization.
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+
+use strict;
+use format_conversion_utils;
+use ptf_parse;
+use wiz_utils;
+use europa_all;
+use run_system_command_utils;
+
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+# | first pass: include all of generator_libarary.pm RIGHT HERE.
+# | dvb04.08.02
+# | then prune down to actual functionality.
+# |
+# | TODO: Rewrite this whole file into something readable
+# | this is much more confusing than I'm comfortable with. dvb04.
+# | (though it does seem to work.)
+# |
+
+my $DEBUG_DEFAULT_GEN = 1;
+
+#This is the global hash of arguments passed in by the generator program
+
+my $generator_hr = {
+ wrapper_args => {
+ make_wrapper => 0,
+ top_module_name => "",
+ simulate_hdl => 1,
+ ports => "",
+ },
+ class_ptf_hr => "",
+ module_ptf_hr => "",
+ system_ptf_hr => "",
+ language => "",
+ external_args => "",
+ external_args_hr => "",
+ project_path_widget => "__PROJECT_DIRECTORY__",
+ generator_mode => "silent",
+ };
+
+
+sub generator_print_verbose
+{
+ my ($info) = (@_);
+
+ if($generator_hr->{generator_mode} eq "verbose"){
+ print("cb_generator.pl: ".$info);
+ }
+}
+
+sub generator_enable_mode
+{
+ my ($mode) = (@_);
+ $generator_hr->{generator_mode} = $mode;
+}
+
+sub generator_get_system_ptf_handle
+{
+ return $generator_hr->{system_ptf_hr};
+}
+
+sub generator_get_language
+{
+ return $generator_hr->{language};
+}
+
+sub generator_get_class_ptf_handle
+{
+ return $generator_hr->{class_ptf_hr};
+}
+
+sub default_ribbit
+{
+ my ($arg) = (@_);
+ &ribbit("\n\n--Error: default_gen_lib: $arg\n");
+}
+
+
+sub _copy_files
+{
+ my ($dest_dir, $source_dir, @files) = (@_);
+ my $function_name;
+
+ #validate args
+ &default_ribbit("No target dir for function copy_files!")
+ unless ($dest_dir ne "");
+
+ &default_ribbit("No source dir for function copy_files!")
+ unless ($source_dir ne "");
+
+ &default_ribbit("No files for function copy_files!")
+ unless (@files != 0);
+
+
+ #check for valid directories
+ opendir (SDIR, $source_dir) or
+ &default_ribbit("can't open $source_dir !");
+
+ opendir (DDIR, $dest_dir) or
+ &default_ribbit("can't open $dest_dir !");
+
+
+ foreach my $source_file(@files){
+ # |
+ # | Separate out the source subdir and the source filename
+ # |
+ my $source_subdir = "";
+ my $source_filename = $source_file;
+
+ if($source_filename =~ /^(.*)\/(.*)$/) # break on last slash
+ {
+ $source_subdir = "/$1"; # embed its leading slash, for concatty
+ $source_filename = $2;
+ }
+
+ my $source_fullpath = "$source_dir$source_subdir/$source_filename";
+ my $dest_fullpath = "$dest_dir/$source_filename";
+
+ &Perlcopy($source_fullpath, $dest_fullpath);
+ &generator_print_verbose("Copying file: \"$source_fullpath\""
+ . " to \"$dest_fullpath\".\n");
+ }
+
+ closedir (SDIR);
+ closedir (DDIR);
+}
+
+
+sub get_module_wrapper_arg_hash_from_system_ptf_file
+{
+ my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+ my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING");
+ my @port_list;
+ foreach my $section(@list_of_sections){
+ my $number = get_child_count($module_ptf_hr, $section);
+
+ for(my $initial=0; $initial < $number; $initial++){
+
+ my $interface_section = get_child($module_ptf_hr, $initial, $section);
+ my $interface_section_name = get_data($interface_section);
+
+ my $port_wiring_section;
+ if($section ne "PORT_WIRING"){
+ $port_wiring_section =
+ get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING");
+ }else{
+ $port_wiring_section =
+ get_child_by_path($module_ptf_hr, $section);
+ }
+ my $num_ports = get_child_count($port_wiring_section, "PORT");
+ foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){
+ my $port = get_child($port_wiring_section, $port_count, "PORT");
+
+ my %port_info_struct;
+ $port_info_struct{name} = get_data($port);
+ $port_info_struct{direction} = get_data_by_path($port, "direction");
+ $port_info_struct{width} = get_data_by_path($port, "width");
+
+ push(@port_list, \%port_info_struct);
+
+ }
+ }
+ }
+ $generator_hr->{wrapper_args}{ports} = \@port_list;
+}
+
+
+sub generator_make_module_wrapper
+{
+ my ($simulate_hdl, $top_module_name, $module_language) = (@_);
+
+ &default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n")
+ if($simulate_hdl eq '');
+
+ &default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n")
+ unless($top_module_name);
+
+ $generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl;
+ $generator_hr->{wrapper_args}{top_module_name} = $top_module_name;
+ $generator_hr->{wrapper_args}{make_wrapper} = 1;
+ $generator_hr->{wrapper_args}{module_language} = $module_language;
+
+}
+
+
+
+
+# |
+# | recognize varous number forms,
+# | return 'h0123abcd-ish.
+# |
+sub turn_anything_into_appropriate_string($$$$)
+ {
+ my ($value,$type,$editable,$module_language) = (@_);
+
+ return $value if($value =~ /^\"/); # quoted string: unscathed
+ return $value if($type eq "string"); # string: anything is ok
+
+ return $value if(!$editable); # and you know, if you can't change it, keep it!
+
+
+ # |
+ # | first, convert to a number
+ # |
+ my $base = 10;
+ my $n = $value;
+ my $width = 32;
+ my $number = 0;
+
+ $value = lc($value); # lower case
+
+ if($value =~ /^([0-9]*)\'([hbo])(.*)$/)
+ {
+ # | tick notation: AOK for verilog
+ if($module_language eq "verilog")
+ {
+ $number = $value;
+ }
+ # |
+ # | note: at this point, we could notice if the
+ # | result should be vhdl binary, and convert
+ # | to that, avoiding the precision-losing
+ # | integer intermediary
+ # |
+ # | (alternatively, we could use a binary string
+ # | always as the intermediate form, rather than
+ # | a precision-losing int.)
+ # |
+ else
+ {
+ $width = $1;
+ my $baseletter = $2;
+ my $digits = $3;
+
+ if($baseletter eq "h")
+ {
+ $base = 16;
+ }
+ elsif($baseletter eq "b")
+ {
+ $base = 2;
+ }
+ elsif($baseletter eq "o") # must be
+ {
+ $base = 8;
+ }
+
+ $digits =~ s/[ _-]//g; # crush out dividing value
+
+ while(length($digits) > 0)
+ {
+ my $digit = substr($digits,0,1);
+ $digits = substr($digits,1);
+ my $digitvalue = hex($digit); # how handy
+ $number = $number * $base + $digitvalue;
+ }
+ }
+ }
+ elsif($value =~ /^0x(.*)$/)
+ {
+ $number = hex($1);
+ }
+ else # try for decimal
+ {
+ $number = int(1 * $value);
+ }
+
+ # |
+ # | ok, we have a number. If our target type
+ # | is "std_logic_vector(this downto that)"
+ # | for tricky VHDL, we
+ # | must quote a binary string out of it.
+ # |
+
+ if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/))
+ {
+ my ($high_bit,$low_bit) = ($1,$2);
+ my $binary = "";
+ for(my $bit = $low_bit; $bit <= $high_bit; $bit++)
+ {
+ $binary = ($number % 2) . $binary;
+ $number = int($number >> 1);
+ }
+
+ $number = '"' . $binary . '"';
+ }
+
+ return $number;
+ }
+
+
+
+
+
+sub _generator_make_module_wrapper
+{
+
+ my $wrapper_args = $generator_hr->{wrapper_args};
+ my $no_black_box = $wrapper_args->{simulate_hdl};
+ my $top_module_name = $wrapper_args->{top_module_name};
+ my $language = $generator_hr->{language};
+ my @external_args = @{$generator_hr->{external_args}};
+ my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+ ### Build Module
+ my $project = e_project->new(@external_args);
+ my $top = $project->top();
+
+ # add the ports to the system module
+ my @ports;
+
+ foreach my $port_hash(@{$wrapper_args->{ports}}){
+ my $porto = e_port->new({
+ name => $port_hash->{name},
+ width => $port_hash->{width},
+ direction => $port_hash->{direction},
+ });
+ push(@ports, $porto);
+ }
+ $top->add_contents(@ports);
+
+
+
+
+
+ # +----------------------------------------
+ # | Get parameters from class.ptf
+ # | create @array of parameters, eacho
+ # | one like name=>, default=>, type=>,
+ # |
+ # | These are the definitions of parameters for
+ # | ANY instance of this module; we need to
+ # | have them in the "wrapee" module so that
+ # | when the system bus is knitted together
+ # | the parameter types can be properly used.
+ # |
+ # | (as it turns out, verilog doesnt need
+ # | them, but vhld does)
+ # |
+ # | dvb2004
+
+
+ my @e_hdl_parameters; # list of e_parameters
+
+ my $class_ptf = generator_get_class_ptf_handle();
+ my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS");
+
+ my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER");
+
+ my $module_language = $generator_hr->{wrapper_args}{module_language};
+
+
+ for(my $i = 0; $i < $hdl_parameter_count; $i++)
+ {
+ my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER");
+
+ my $boring_name = get_data($a_parameter); # legal guinevere-ized
+ my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name
+ my $default = get_data_by_path($a_parameter,"default_value");
+ my $type = get_data_by_path($a_parameter,"type");
+
+ $default = turn_anything_into_appropriate_string($default,$type,1,$module_language);
+
+ my $a_parameter = e_parameter->new
+ ({
+ name => $name,
+ default => $default,
+ type => $type
+ });
+
+ push (@e_hdl_parameters,$a_parameter);
+ }
+
+
+ # | and @e_hdl_parameters is used below in the wrappee module
+ # +--------------------------------------------
+
+ # +--------------------------------------------
+ # | Now, we build a "hdl_parameter_map", which is just
+ # | your basic hash table with keys (parameters)
+ # | and values (parameter values).
+ # |
+ # | these are the particular values for this instance.
+ # |
+
+ my %hdl_parameter_map;
+ my $module_ptf = $generator_hr->{module_ptf_hr};
+ my $hdl_parameters_ptf =
+ get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters");
+
+ my $child_count = get_child_count($hdl_parameters_ptf);
+
+ for(my $i = 0; $i < $child_count; $i++)
+ {
+ my $a_parameter = get_child($hdl_parameters_ptf,$i);
+
+ my $boring_name = get_name($a_parameter);
+ my $value = get_data($a_parameter);
+
+ # refer back to the original HDL name...
+ my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name");
+ my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name");
+ my $parameter_type = get_data_by_path($parameter_definition_ptf,"type");
+ my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable");
+
+ $value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language);
+
+ # |
+ # | our internal _dummy assignment shows up here
+ # | without a corresponding hdl entry. we
+ # | ignore it.
+ # |
+
+ if($parameter_name ne "")
+ {
+ $hdl_parameter_map{$parameter_name} = $value;
+ }
+ }
+
+ my $wrapee_module;
+ $wrapee_module = e_module->new({
+ name => $top_module_name,
+ contents => [@ports,@e_hdl_parameters],
+ do_black_box => 0,
+ do_ptf => 0,
+ _hdl_generated => 1,
+ _explicitly_empty_module => 1,
+ });
+
+ $top->add_contents (
+ e_instance->new({
+ module => $wrapee_module,
+ parameter_map => \%hdl_parameter_map
+ }),
+ );
+
+ $project->top()->do_ptf(0);
+ $project->do_write_ptf(0);
+
+
+ my $module_file = $project->_target_module_name().".v";
+ $module_file = $project->_target_module_name().".vhd"
+ if($language eq "vhdl");
+
+ $module_file = $generator_hr->{project_path_widget}."/".$module_file;
+ &generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file));
+ $project->output();
+
+
+ # if you don't want a simulation model, you don't get a simulation model
+ if($no_black_box eq "0")
+ {
+ my $black_project = e_project->new(@external_args);
+ $black_project->_target_module_name($top_module_name);
+ my $black_top = $black_project->top();
+
+
+
+ $black_top->add_contents(@ports);
+ my $black_top_instance;
+ $black_top_instance = e_module->new({
+ name => $wrapper_args->{top_module_name}."_bb",
+ contents => [@ports],
+ do_black_box => 1,
+ do_ptf => 0,
+ _hdl_generated => 0,
+ _explicitly_empty_module => 1,
+ });
+
+ $black_top->add_contents (
+ e_instance->new({
+ module => $black_top_instance,
+ }),
+ );
+
+
+
+
+ $black_project->top()->do_ptf(0);
+ $black_project->do_write_ptf(0);
+
+ my $black_module_file = $black_project->_target_module_name().".v";
+ $black_module_file = $black_project->_target_module_name().".vhd"
+ if($language eq "vhdl");
+
+
+ $black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file;
+ &generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file));
+
+# &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file);
+
+
+ $black_project->output();
+ }
+
+}
+
+####
+# Args: $file_type : "synthesis", "synthesis_only", "simulation"
+# @file_list : an array of files. This list of files is assumed to be relative to the
+# component's directory
+
+
+my $decoder_ring_hr = {
+ quartus_only => {
+ copy => 1,
+ copy_to => "project",
+ ptf_set => 0,
+ },
+ simulation_only => {
+ copy => 1,
+ copy_to => "simulation",
+ ptf_set => 1,
+ ptf_section => "Simulation_HDL_Files",
+ },
+ simulation_and_quartus => {
+ copy => 1,
+ copy_to => "project",
+ ptf_set => 1,
+ ptf_section => "Synthesis_HDL_Files",
+ },
+ precompiled_simulation_files => {
+ copy => 0,
+ ptf_set => 1,
+ ptf_section => "Precompiled_Simulation_Library_Files",
+ },
+ };
+
+
+
+
+sub generator_copy_files_and_set_system_ptf
+{
+ my ($hdl_section, @file_list) = (@_);
+
+ my $ptf_path_prefix = "";
+ my $external_args_hr = $generator_hr->{external_args_hr};
+ my @new_file_array;
+
+ #validate first
+ my $decoder_hash = $decoder_ring_hr->{$hdl_section};
+ &default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n")
+ unless($decoder_ring_hr->{$hdl_section} ne "");
+
+ &generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n");
+
+ #copy second
+ my @new_file_array;
+
+ # If we need to copy over some files, then we need to make sure we are
+ # keeping track of what files we copy over.
+ # Otherwise, we just need to keep track of the files that the user has asked to copy over
+ # and use these instead.
+ if($decoder_hash->{copy}){
+ my $copy_to_location;
+ my $copy_from_location;
+
+ if($decoder_hash->{copy_to} eq "project"){
+ $copy_to_location = $external_args_hr->{system_directory};
+ }elsif($decoder_hash->{copy_to} eq "simulation"){
+ $copy_to_location = $external_args_hr->{system_sim_dir};
+ }else{
+ &default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n");
+ }
+
+ $copy_from_location = $external_args_hr->{class_directory};
+ @new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list);
+ }else{
+ @new_file_array = @file_list;
+ }
+
+ #scribble on PTF hash last
+ if($decoder_hash->{ptf_set}){
+
+ if($decoder_hash->{copy_to} eq "project"){
+ foreach my $file(@new_file_array){
+ $file =~ s/^.*\/(.*?)$/$1/;
+ $file = $generator_hr->{project_path_widget}."/".$file;
+ }
+ }
+ &generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n");
+ if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){
+ @new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array;
+ }
+ &generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array);
+ }
+}
+
+
+
+####
+# Name: generator_set_files_in_system_ptf
+# Args: $hdl_section
+# @list_of_files
+# Returns: 1 or 0
+# Purpose: This is an internal function used to set files in the module's section in the system PTF file
+#
+sub generator_set_files_in_system_ptf
+{
+ my ($hdl_section, @list_of_files) = (@_);
+
+ my $file_list = join(",", @list_of_files);
+ my $previous_data;
+
+ &generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n");
+ my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section);
+ if($previous_data){
+ $file_list = $previous_data . ", $file_list"; # spr 132177
+ # swapping order, dvb 2003
+ }
+ &set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list);
+}
+
+####
+# Name: generator_copy_files
+# Args: $target_directory
+# $source_directory
+# @list_of_files
+# Returns: The list of files which has been copied (suitable for framing!)
+# Purpose: This is an internal function used to copy files around in the generator program.
+#
+sub generator_copy_files
+{
+ my ($target_directory, $source_directory, @list_of_files) = (@_);
+
+ my @new_file_array;
+
+ foreach my $file_name(@list_of_files){
+ $file_name =~ s|\\|\/|g;
+ if($file_name =~ /\*\.*/){
+ $file_name =~ s/\*/$1/;
+ my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name);
+ push(@new_file_array, @found_list);
+ }else{
+ &generator_print_verbose("Copying: ".$file_name."\n");
+ push(@new_file_array, $file_name);
+ }
+ }
+
+ &_copy_files($target_directory, $source_directory, @new_file_array);
+ return @new_file_array;
+}
+
+
+
+sub _find_all_dir_files_with_ext
+{
+ my ($dir,
+ $ext) = (@_);
+
+ opendir (DIR, $dir) or
+ &default_ribbit("can't open $dir !");
+
+ my @all_files = readdir(DIR);
+ my @new_file_list;
+
+
+ foreach my $file (@all_files){
+ if($file =~ /^.*($ext)$/){
+ push(@new_file_list, $file);
+ }
+ }
+
+ return @new_file_list;
+}
+
+####
+# Name: generator_begin
+# Args: Array of generator program launcher args
+# Returns: A hash reference to the module's section in the system PTF file
+# Purpose: This is the first subroutine a user should call before running the rest of their
+# generator program.
+#
+
+sub generator_begin
+{
+ my @external_args = (@_);
+
+ my ($external_args_hr,
+ $temp_user_defined,
+ $temp_db_Module,
+ $temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args);
+
+ &generator_print_verbose("generator_begin: initializing\n");
+
+ $generator_hr->{external_args_hr} = $external_args_hr;
+ $generator_hr->{external_args} = \@external_args;
+
+ # open up class.ptf and
+ $generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf");
+
+ # get the system.ptf
+ $generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf");
+ $generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}");
+ my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class");
+
+ # find the default generator section
+ $generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language");
+
+ # get some wrapper settings
+ &get_module_wrapper_arg_hash_from_system_ptf_file();
+
+ # clear system ptf's HDL section
+ &delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO");
+
+ return $generator_hr->{module_ptf_hr};
+}
+
+####
+# Name: generator_end
+# Args: none
+# Returns: nothing
+# Purpose: This is the last subroutine a user should call from their generator program.
+# Not calling this subroutine will make you very sad... =<
+#
+
+sub generator_end
+{
+ # o.k., time to make the wrapper and output it.
+ if($generator_hr->{wrapper_args}{make_wrapper}){
+ &_generator_make_module_wrapper();
+ }
+
+
+ my $external_args_hr = $generator_hr->{external_args_hr};
+ my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf";
+ &generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n");
+
+ default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n")
+ unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"));
+}
+
+sub generator_end_read_module_wrapper_string
+{
+ my $language = &generator_get_language();
+ my $ls;
+
+ if($language =~ /vhdl/){
+ $ls = ".vhd";
+ }elsif($language =~ /verilog/){
+ $ls = ".v";
+ }else{
+ &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+ }
+ my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+ my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+ my $file = $system_dir."/".$module_name.$ls;
+ &generator_print_verbose("generator library reading file into string: $file\n");
+
+ open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n";
+ my $return_string;
+ while ()
+ {
+ $return_string .= $_;
+ }
+ close (FILE);
+ return($return_string);
+}
+
+sub generator_end_write_module_wrapper_string
+{
+ my $string = shift or ribbit "no string specified\n";
+
+ my $language = &generator_get_language();
+ my $ls;
+
+ print $language;
+
+ if($language =~ /vhdl/){
+ $ls = ".vhd";
+ }elsif($language =~ /verilog/){
+ $ls = ".v";
+ }else{
+ &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+ }
+ my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+ my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+ my $file = $system_dir."/".$module_name.$ls;
+ &generator_print_verbose("generator library writing string into file: $file\n");
+
+ open (FILE,">$file") or ribbit "cannot open file ($file) ($!)\n";
+ print FILE $string;
+ close (FILE);
+}
+# end of generator_library.pm
+
+
+
+
+
+#
+#
+#
+#
+# ---------------------------------------------------------------------
+
+# +----------------------------------------------------
+# | emit_system_h
+# |
+# | if "is_cpu", attempt to emit a system.h
+# | memory map.
+# |
+
+sub emit_system_h($$$)
+ {
+ my ($sopc_directory,$master,$system_ptf) = (@_);
+
+ # |
+ # | Build a system.h file for masters.
+ # |
+
+
+# as of quartus 5.0, we prefer gtf-generate in sopc_builder directly
+
+ my $gtf_generate = "$sopc_directory/bin/gtf-generate";
+ my $gtf_filename = "$sopc_directory/bin/gtf/system.h.gtf";
+
+ if(! -f $gtf_generate)
+ {
+ # but if sopc_builder is missing it for whatever reason,
+ # try the one in sopc_kit_nios2
+
+ my $sopc_kit_nios2 = $ENV{SOPC_KIT_NIOS2};
+ if($sopc_kit_nios2 ne "")
+ {
+ $gtf_generate = "$sopc_kit_nios2/bin/gtf-generate";
+ $gtf_filename = "$sopc_kit_nios2/bin/gtf/system.h.gtf";
+ }
+ }
+
+ # |
+ # | xml template
+ # |
+
+ my $stf_template = <
+
+
+
+
+
+
+EOP
+
+ # |
+ # | THINK
+ # |
+
+ my $output_directory = "./${master}_map";
+ my $project_name = "ignored";
+ my $stf_filename = "./${master}_project.stf";
+
+ # |
+ # | build up template variables
+ # |
+
+ my %template_vars;
+ $template_vars{date} = fcu_date_time();
+ $template_vars{whoami} = $0;
+ $template_vars{project_name} = $project_name;
+ $template_vars{system_ptf} = $system_ptf;
+ $template_vars{output_directory} = $output_directory;
+ $template_vars{master} = $master;
+
+ # |
+ # | poke in the values to the template
+ # |
+
+ foreach my $key (sort(keys(%template_vars)))
+ {
+ $stf_template =~ s/--$key--/$template_vars{$key}/gs;
+ }
+
+ ## debug print $stf_template;
+
+ # |
+ # | write out the stf file, so we can soon use it
+ # |
+
+ fcu_write_file($stf_filename,$stf_template);
+
+ # |
+ # | and use it
+ # |
+
+ if(-e $gtf_generate && -e $gtf_filename)
+ {
+
+ my $generate_cmd = $gtf_generate;
+
+ $generate_cmd .= " --output-directory=$output_directory";
+ $generate_cmd .= " --gtf=$gtf_filename";
+ $generate_cmd .= " --stf=$stf_filename";
+
+ r_system($sopc_directory,$generate_cmd);
+
+ # |
+ # | done with it
+ # |
+
+ r_system($sopc_directory,"rm $stf_filename");
+
+ fcu_print_command("Generated memory map \"$output_directory/system.h\"");
+ }
+ else
+ {
+ fcu_print_command("Warning: did NOT emit system.h for $master");
+ }
+
+
+
+
+ }
+
+
+sub r_system($$)
+ {
+ my ($sopc_directory,$cmd) = (@_);
+ fcu_print_command($cmd);
+ return Run_Command_In_Unix_Like_Shell($sopc_directory,$cmd);
+ }
+
+
+
+
+
+
+
+# +------------------------------------------
+# | synthesis and simulation files are are
+# | listed in CLASS/CB_GENERATOR/HDL_FILES.
+# |
+
+sub get_synthesis_files($)
+ {
+ my ($class_ptf) = (@_);
+ my $synthesis_files = "";
+ my $simulation_files = "";
+
+ my $hdl_files = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/HDL_FILES");
+ my $child_count = get_child_count($hdl_files);
+ for(my $i = 0; $i < $child_count; $i++)
+ {
+ my $hdl_file = get_child($hdl_files,$i);
+ if(get_name($hdl_file) eq "FILE")
+ {
+ my $filename = get_data_by_path($hdl_file,"filepath");
+ my $use_in_synthesis = get_data_by_path($hdl_file,"use_in_synthesis");
+ my $use_in_simulation = get_data_by_path($hdl_file,"use_in_simulation");
+
+ if($use_in_synthesis)
+ {
+ $synthesis_files .= ", " if $synthesis_files;
+ $synthesis_files .= $filename;
+ }
+
+ if($use_in_simulation)
+ {
+ $simulation_files .= ", " if $simulation_files;
+ $simulation_files .= $filename;
+ }
+ }
+ }
+
+ return $synthesis_files;
+ }
+
+
+
+
+
+
+
+
+sub main
+ {
+
+ push(@ARGV,"--verbose=1") if 0;
+ my %args = fcu_parse_args(@ARGV);
+
+ if(0)
+ {
+ foreach my $key (sort(keys(%args)))
+ {
+ print("--$key = $args{$key} \n");
+ }
+ }
+
+ # |
+ # | get the arguments we care about
+ # |
+
+ my $class_dir = fcu_get_switch(\%args,"module_lib_dir");
+
+
+ my $target_module_name = fcu_get_switch(\%args,"target_module_name");
+ my $system_name = fcu_get_switch(\%args,"system_name");
+ my $sopc_directory = fcu_get_switch(\%args,"sopc_directory");
+
+ # |
+ # | preflight the arguments a little
+ # |
+
+ my $error_count = 0;
+
+ my $class_ptf_path = "$class_dir/class.ptf";
+ if(!-f $class_ptf_path)
+ {
+ print "error: no class.ptf at \"$class_dir\"\n";
+ $error_count++;
+ }
+
+ die "$error_count errors" if($error_count > 0);
+
+ # +-------------------------------------------
+ # | ok, let us get to work
+ # |
+
+
+ my $class_ptf = new_ptf_from_file($class_ptf_path);
+
+ # |
+ # | emit system.h for this module
+ # | TODO iff Is_CPU i guess.
+ # |
+
+ my $do_emit_system_h = get_data_by_path($class_ptf,
+ "CLASS/CB_GENERATOR/emit_system_h");
+ if($do_emit_system_h)
+ {
+ emit_system_h($sopc_directory,
+ $target_module_name,
+ "./$system_name.ptf");
+ }
+
+ my $top_module_name = get_data_by_path($class_ptf,
+ "CLASS/CB_GENERATOR/top_module_name");
+ my $file_name = "";
+
+ # | stored as file_name.v:module_name, so we break it open
+ if($top_module_name =~ /^(.*):(.*)$/)
+ {
+ $file_name = $1;
+ my $module_name = $2;
+ $top_module_name = $module_name;
+ }
+
+ # | language of this particular module...
+
+ my $module_language = "verilog";
+ if($file_name =~ /^.*\.vhd$/)
+ {
+ $module_language = "vhdl";
+ }
+
+ # |
+ # | consult the CB_GENERATOR/HDL_FILES section regarding
+ # | where our HDL files for synthesis are.
+ # |
+
+
+ my $synthesis_files = get_synthesis_files($class_ptf);
+
+
+ my $instantiate_in_system_module = get_data_by_path($class_ptf,
+ "CLASS/MODULE_DEFAULTS/SYSTEM_BUILDER_INFO/Instantiate_In_System_Module");
+
+
+
+ if($instantiate_in_system_module)
+ {
+ generator_enable_mode ("terse");
+
+
+ generator_begin (@ARGV);
+
+
+ generator_make_module_wrapper(1,$top_module_name,$module_language);
+
+ generator_copy_files_and_set_system_ptf
+ (
+ "simulation_and_quartus",
+ split(/ *, */,$synthesis_files)
+# "$synthesis_files"
+ );
+
+ generator_end ();
+ }
+
+ exit (0);
+ }
+
+$| = 1; # always polite to flush.
+main()
+
+# end of file
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_chan.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_chan.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_chan.vhd (revision 16)
@@ -0,0 +1,213 @@
+-------------------------------------------------------------------------------
+-- Title : N2H2 Top level
+-- Project :
+-------------------------------------------------------------------------------
+-- File : n2h2.vhd
+-- Author : kulmala3
+-- Created : 30.03.2005
+-- Last update: 29.06.2005
+-- Description: Wires together rx and tx
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 30.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+--use work.log2_pkg.all;
+
+entity n2h2 is
+
+ generic (
+ data_width_g : integer := 32;
+ amount_width_g : integer := 16;
+ n_chans_g : integer := 8;
+ n_chans_bits_g : integer := 3; -- how many bits to show n_chans
+ -- eg 2 for 4, 3 for 5, basically log2(n_chans_g)
+ hibi_addr_cmp_lo_g : integer := 20;
+ hibi_addr_cmp_hi_g : integer := 27
+ );
+
+ port (
+ clk_cfg : in std_logic; -- not even used...
+ clk_tx : in std_logic;
+ clk_rx : in std_logic;
+ rst_n : in std_logic; -- THIS IS ACTIVE HIGH!
+
+ -- avalon master (rx) if
+ avalon_addr_out_rx : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_we_out_rx : out std_logic;
+ avalon_writedata_out_rx : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_waitrequest_in_rx : in std_logic;
+
+ --avalon slave if (config)
+ avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0);
+ avalon_cfg_writedata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_we_in : in std_logic;
+ avalon_cfg_readdata_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_re_in : in std_logic;
+ avalon_cfg_cs_in : in std_logic;
+
+ -- Avalon master read interface (tx)
+ avalon_addr_out_tx : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_re_out_tx : out std_logic;
+ avalon_readdata_in_tx : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_waitrequest_in_tx : in std_logic;
+
+ -- hibi (rx) if
+ hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_in : in std_logic;
+ hibi_empty_in : in std_logic;
+ hibi_comm_in : in std_logic_vector(2 downto 0);
+ hibi_re_out : out std_logic;
+
+ -- hibi write interface (tx)
+ hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_out : out std_logic;
+ hibi_full_in : in std_logic;
+ hibi_comm_out : out std_logic_vector(2 downto 0);
+ hibi_we_out : out std_logic;
+
+ rx_irq_out : out std_logic
+
+ );
+
+end n2h2;
+
+architecture structural of n2h2 is
+
+ signal tx_start_from_rx : std_logic;
+ signal tx_comm_from_rx : std_logic_vector(2 downto 0);
+ signal tx_mem_addr_from_rx : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_hibi_addr_from_rx : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_amount_from_rx : std_logic_vector(amount_width_g-1 downto 0);
+ signal tx_status_done_to_rx : std_logic;
+ signal real_rst_n : std_logic;
+
+ component n2h2_rx_channels
+ generic (
+ n_chans_g : integer;
+ n_chans_bits_g : integer;
+ data_width_g : integer;
+ hibi_addr_cmp_hi_g : integer;
+ hibi_addr_cmp_lo_g : integer;
+ amount_width_g : integer);
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_we_out : out std_logic;
+ avalon_writedata_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_waitrequest_in : in std_logic;
+ hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_in : in std_logic;
+ hibi_empty_in : in std_logic;
+ hibi_comm_in : in std_logic_vector(2 downto 0);
+ hibi_re_out : out std_logic;
+ avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0);
+ avalon_cfg_writedata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_we_in : in std_logic;
+ avalon_cfg_readdata_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_re_in : in std_logic;
+ avalon_cfg_cs_in : in std_logic;
+ rx_irq_out : out std_logic;
+ tx_start_out : out std_logic;
+ tx_comm_out : out std_logic_vector(2 downto 0);
+ tx_mem_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_hibi_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_out : out std_logic_vector(amount_width_g-1 downto 0);
+ tx_status_done_in : in std_logic);
+ end component;
+
+ component n2h2_tx
+ generic (
+ data_width_g : integer;
+ amount_width_g : integer);
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_re_out : out std_logic;
+ avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_waitrequest_in : in std_logic;
+ hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_out : out std_logic;
+ hibi_full_in : in std_logic;
+ hibi_comm_out : out std_logic_vector(2 downto 0);
+ hibi_we_out : out std_logic;
+ tx_start_in : in std_logic;
+ tx_status_done_out : out std_logic;
+ tx_comm_in : in std_logic_vector(2 downto 0);
+ tx_hibi_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ tx_ram_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0));
+ end component;
+
+begin -- structural
+ -- was for compatibility with SOPC component 0.1
+ -- real_rst_n <= not rst_n;
+
+ real_rst_n <= rst_n;
+ n2h2_rx_chan_1 : n2h2_rx_channels
+ generic map (
+ n_chans_g => n_chans_g,
+ n_chans_bits_g => n_chans_bits_g,
+ data_width_g => data_width_g,
+ hibi_addr_cmp_hi_g => hibi_addr_cmp_hi_g,
+ hibi_addr_cmp_lo_g => hibi_addr_cmp_lo_g,
+ amount_width_g => amount_width_g
+ )
+ port map (
+ clk => clk_rx,
+ rst_n => real_rst_n,
+ avalon_addr_out => avalon_addr_out_rx,
+ avalon_we_out => avalon_we_out_rx,
+ avalon_writedata_out => avalon_writedata_out_rx,
+ avalon_waitrequest_in => avalon_waitrequest_in_rx,
+ hibi_data_in => hibi_data_in,
+ hibi_av_in => hibi_av_in,
+ hibi_empty_in => hibi_empty_in,
+ hibi_comm_in => hibi_comm_in,
+ hibi_re_out => hibi_re_out,
+ avalon_cfg_addr_in => avalon_cfg_addr_in,
+ avalon_cfg_writedata_in => avalon_cfg_writedata_in,
+ avalon_cfg_we_in => avalon_cfg_we_in,
+ avalon_cfg_readdata_out => avalon_cfg_readdata_out,
+ avalon_cfg_re_in => avalon_cfg_re_in,
+ avalon_cfg_cs_in => avalon_cfg_cs_in,
+ rx_irq_out => rx_irq_out,
+ tx_start_out => tx_start_from_rx,
+ tx_comm_out => tx_comm_from_rx,
+ tx_mem_addr_out => tx_mem_addr_from_rx,
+ tx_hibi_addr_out => tx_hibi_addr_from_rx,
+ tx_amount_out => tx_amount_from_rx,
+ tx_status_done_in => tx_status_done_to_rx
+ );
+
+ n2h2_tx_1 : n2h2_tx
+ generic map (
+ data_width_g => data_width_g,
+ amount_width_g => amount_width_g)
+ port map (
+ clk => clk_tx,
+ rst_n => real_rst_n,
+ avalon_addr_out => avalon_addr_out_tx,
+ avalon_re_out => avalon_re_out_tx,
+ avalon_readdata_in => avalon_readdata_in_tx,
+ avalon_waitrequest_in => avalon_waitrequest_in_tx,
+ hibi_data_out => hibi_data_out,
+ hibi_av_out => hibi_av_out,
+ hibi_full_in => hibi_full_in,
+ hibi_comm_out => hibi_comm_out,
+ hibi_we_out => hibi_we_out,
+ tx_start_in => tx_start_from_rx,
+ tx_status_done_out => tx_status_done_to_rx,
+ tx_hibi_addr_in => tx_hibi_addr_from_rx,
+ tx_comm_in => tx_comm_from_rx,
+ tx_ram_addr_in => tx_mem_addr_from_rx,
+ tx_amount_in => tx_amount_from_rx
+ );
+
+end structural;
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/one_hot_mux.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/one_hot_mux.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/one_hot_mux.vhd (revision 16)
@@ -0,0 +1,72 @@
+-------------------------------------------------------------------------------
+-- Title : one hot mux for one bit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : one_hot_mux.vhd
+-- Author : kulmala3
+-- Created : 16.06.2005
+-- Last update: 16.06.2005
+-- Description: select signal is one-hot, otherwise - a mux for one bit.
+-- Asynchronous.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 16.06.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_misc.all;
+
+entity one_hot_mux is
+
+ generic (
+ data_width_g : integer := 0);
+
+ port (
+-- clk : in std_logic;
+-- rst_n : in std_logic;
+ data_in : in std_logic_vector(data_width_g-1 downto 0);
+ sel_in : in std_logic_vector(data_width_g-1 downto 0);
+ data_out : out std_logic
+ );
+
+end one_hot_mux;
+
+architecture rtl of one_hot_mux is
+
+begin -- rtl
+
+ m: process (data_in, sel_in)
+ variable temp : std_logic_vector(data_width_g-1 downto 0);
+ variable tulos : std_logic;
+ begin -- process m
+
+ for i in 0 to data_width_g-1 loop
+ temp(i) := sel_in(i) and data_in(i);
+-- tulos := tulos or (sel_in(i) and data_in(i));
+ end loop; -- i
+
+ data_out <= or_reduce(temp);
+
+ end process m;
+
+
+-- process (data_in, sel_in)
+-- begin -- process
+
+-- for i in 0 to data_width_g-1 loop
+-- if sel_in(i) = '1' then
+-- data_out <= data_in(i);
+-- else
+
+-- end if;
+-- end loop; -- i
+
+-- end process;
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_tx.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_tx.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_tx.vhd (revision 16)
@@ -0,0 +1,168 @@
+-------------------------------------------------------------------------------
+-- Title : N2H2 TX
+-- Project :
+-------------------------------------------------------------------------------
+-- File : n2h2_tx.vhd
+-- Author : kulmala3
+-- Created : 30.03.2005
+-- Last update: 27.04.2005
+-- Description: Bufferless transmitter for N2H2.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-- Potential dead-lock (very bad luck): hibi is full, tx cant transfer,
+-- -> tx reserves avalon bus until hibi is freed.
+-- Fix needs some extra logic, done if necessary later (report!).
+-- probably done anyway at some point.
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 30.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity n2h2_tx is
+
+ generic (
+ -- legal values because of SOPC Builder £@££@ crap.
+ data_width_g : integer := 2;
+ amount_width_g : integer := 1);
+
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ -- Avalon master read interface
+ avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_re_out : out std_logic;
+ avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_waitrequest_in : in std_logic;
+ -- hibi write interface
+ hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_out : out std_logic;
+ hibi_full_in : in std_logic;
+ hibi_comm_out : out std_logic_vector(2 downto 0);
+ hibi_we_out : out std_logic;
+ -- DMA conf interface
+ tx_start_in : in std_logic;
+ tx_status_done_out : out std_logic;
+ tx_comm_in : in std_logic_vector(2 downto 0);
+ tx_hibi_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ tx_ram_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0)
+ );
+
+end n2h2_tx;
+
+architecture rtl of n2h2_tx is
+
+ constant addr_offset_c : integer := data_width_g/8;
+
+ type control_states is (idle, transmit_addr, transmit);
+ signal control_r : control_states;
+ signal start_tx_r : std_logic;
+ signal hibi_we_r : std_logic;
+ signal amount_cnt_r : std_logic_vector(amount_width_g-1 downto 0);
+ signal avalon_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal sel_data_src_r : std_logic;
+
+begin -- rtl
+
+ hibi_we_r <= (avalon_waitrequest_in nor hibi_full_in) and start_tx_r;
+ hibi_we_out <= hibi_we_r;
+-- avalon_re_out <= start_tx_r and (not hibi_full_in);
+ avalon_re_out <= start_tx_r; -- 27.4.
+ avalon_addr_out <= avalon_addr_r;
+
+ data_out : process (sel_data_src_r, avalon_readdata_in, tx_hibi_addr_in)
+ begin -- process hibi_data_out
+ if sel_data_src_r = '0' then
+ hibi_data_out <= avalon_readdata_in;
+ else
+ hibi_data_out <= tx_hibi_addr_in;
+ end if;
+ end process data_out;
+
+ main : process (clk, rst_n)
+ begin -- process main
+ if rst_n = '0' then -- asynchronous reset (active low)
+ start_tx_r <= '0';
+ control_r <= idle;
+ amount_cnt_r <= conv_std_logic_vector(0, amount_width_g);
+ avalon_addr_r <= (others => 'X');
+ tx_status_done_out <= '0';
+ hibi_av_out <= '0';
+ hibi_comm_out <= (others => '0');
+ sel_data_src_r <= '1';
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ case control_r is
+ when idle =>
+ if tx_start_in = '1' then
+ -- transfer address from register
+ control_r <= transmit_addr;
+ avalon_addr_r <= tx_ram_addr_in;
+ hibi_comm_out <= tx_comm_in;
+ hibi_av_out <= '1';
+ start_tx_r <= '1';
+ tx_status_done_out <= '0';
+ sel_data_src_r <= '1';
+ else
+ control_r <= idle;
+ avalon_addr_r <= (others => 'X');
+ hibi_comm_out <= (others => 'X');
+ hibi_av_out <= '1';
+ start_tx_r <= '0';
+ tx_status_done_out <= '1';
+
+ end if;
+
+ when transmit_addr =>
+ start_tx_r <= '1';
+
+ if hibi_we_r = '1' then
+ sel_data_src_r <= '0';
+ -- transfer address from register
+ control_r <= transmit;
+ avalon_addr_r <= tx_ram_addr_in; --+addr_offset_c;
+ hibi_av_out <= '0';
+ tx_status_done_out <= '0';
+
+ amount_cnt_r <= amount_cnt_r+1;
+ else
+ control_r <= transmit_addr;
+ avalon_addr_r <= tx_ram_addr_in;
+ hibi_av_out <= '1';
+ tx_status_done_out <= '0';
+-- hibi_data_out <= tx_hibi_addr_in;
+ sel_data_src_r <= '1';
+ end if;
+
+ when transmit =>
+ if hibi_we_r = '1' then
+ hibi_av_out <= '0';
+ amount_cnt_r <= amount_cnt_r+1;
+ avalon_addr_r <= avalon_addr_r + addr_offset_c;
+ -- start data transfer here
+ start_tx_r <= '1';
+
+ -- every data transferred
+ if amount_cnt_r >= tx_amount_in then
+ amount_cnt_r <= conv_std_logic_vector(0, amount_width_g);
+ control_r <= idle;
+ start_tx_r <= '0';
+ tx_status_done_out <= '1';
+ end if;
+ end if;
+
+ when others =>
+
+ end case;
+ end if;
+ end process main;
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_rx_ind_chan.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_rx_ind_chan.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_rx_ind_chan.vhd (revision 16)
@@ -0,0 +1,540 @@
+-------------------------------------------------------------------------------
+-- Title : Nios to HIBI version 2
+-- Project :
+-------------------------------------------------------------------------------
+-- File : n2h2_rx_channels.vhdl
+-- Author : kulmala3
+-- Created : 22.03.2005
+-- Last update: 28.06.2005
+-- Description: This version acts as a real dma.
+--
+-- THIS VERSION CONTAINS INDEPENDENT CHANNEL (DCT) AND A
+-- TX TRANSFER BUFFER
+--
+-- Currently there's no double-registers in config - the user
+-- must take care when configuring the device. (datas can go to
+-- wrong address etc, if configured while still receiving data from
+-- source)
+--
+-- Needs 2 clock cycles to propagate the IRQ (ack->irq down-> irq req)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 22.03.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+--use work.txt_util.all;
+--use work.log2_pkg.all;
+
+entity n2h2_rx_channels is
+
+ generic (
+ -- generic values for @£$ stupid SOPC builder -crap...
+ n_chans_g : integer := 3;
+ n_chans_bits_g : integer := 2; -- how many bits to represet n_chans
+ -- eg 2 for 4, 3 for 5, basically log2(n_chans_g)
+
+ data_width_g : integer := 1;
+ hibi_addr_cmp_hi_g : integer := 1; -- the highest bit used for comparing address
+ hibi_addr_cmp_lo_g : integer := 1; -- the lowest bit
+ amount_width_g : integer := 1); -- in bits, maximum amount of data
+
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ -- avalon master (rx) if
+ avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_we_out : out std_logic;
+ avalon_writedata_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_waitrequest_in : in std_logic;
+ -- hibi if
+ hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_in : in std_logic;
+ hibi_empty_in : in std_logic;
+ hibi_comm_in : in std_logic_vector(2 downto 0);
+ hibi_re_out : out std_logic;
+
+ --avalon slave if (config)
+ --conf_bits_c bits for each channel
+ avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0);
+ avalon_cfg_writedata_in : in std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_we_in : in std_logic;
+ avalon_cfg_readdata_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_cfg_re_in : in std_logic;
+ avalon_cfg_cs_in : in std_logic;
+
+ rx_irq_out : out std_logic;
+
+ -- to/from tx
+ tx_start_out : out std_logic;
+ tx_comm_out : out std_logic_vector(2 downto 0);
+ tx_mem_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_hibi_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_out : out std_logic_vector(amount_width_g-1 downto 0);
+ tx_status_done_in : in std_logic
+
+ );
+
+end n2h2_rx_channels;
+
+architecture rtl of n2h2_rx_channels is
+
+ -- NOTE!! Also have to change to interface!! avalon_cfg_addr_in !!!
+ constant conf_bits_c : integer := 4; -- number of configuration bits in CPU
+ -- side address
+ constant control_bits_c : integer := 2; -- how many bits in ctrl reg
+ constant status_bits_c : integer := 2; -- how many bits in ctrl reg
+ constant addr_offset_c : integer := data_width_g/8;
+ constant dct_hibi_addr_r : integer := 16#1100#;
+
+
+ type chan_data_array is array (n_chans_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
+ type chan_amount_array is array (n_chans_g-1 downto 0) of std_logic_vector(amount_width_g-1 downto 0);
+
+ -- registers the CPU will set
+ signal mem_addr_r : chan_data_array;
+ signal sender_addr_r : chan_data_array;
+ signal irq_amount_r : chan_amount_array;
+ signal control_r : std_logic_vector(control_bits_c-1 downto 0);
+ signal tx_mem_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_hibi_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_amount_r : std_logic_vector(amount_width_g-1 downto 0);
+ signal tx_comm_r : std_logic_vector(2 downto 0);
+
+ -- cpu sets, n2h clears
+ signal init_chan_r : std_logic_vector(n_chans_g-1 downto 0);
+
+ -- cpu clears, n2h sets
+ signal irq_chan_r : std_logic_vector(n_chans_g-1 downto 0);
+
+ -- cpu can read
+ -- tells where the next data is stored
+ signal current_mem_addr_r : chan_data_array;
+ signal status_r : std_logic_vector(status_bits_c-1 downto 0);
+
+
+ -- counter of how many datas gotten (irq nullifies)
+ signal irq_counter_r : chan_amount_array;
+ signal irq_r : std_logic;
+ signal irq_given_r : std_logic_vector(n_chans_g-1 downto 0);
+
+ -- main process signals
+-- type main_ctrl_states is (idle, read_addr, read_data, wait_avalon);
+-- signal main_ctrl_r : main_ctrl_states;
+ signal hibi_re_r : std_logic;
+ signal avalon_we_r : std_logic;
+
+ -- calc_chan signals
+ signal avalon_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal hibi_av_re_empty_r : std_logic_vector(2 downto 0);
+ signal curr_chan_avalon_we_r : std_logic; -- 0 if no channel found
+
+-- signal dirty_chan_r : std_logic_vector(n_chans_g-1 downto 0);
+-- signal not_dirty_chan_we_r : std_logic;
+-- signal one_more_data_r : std_logic_vector(n_chans_g-1 downto 0);
+
+
+ -- value n_chans_g means undefined
+-- signal curr_chan_r : integer range n_chans_g downto 0;
+
+
+ component n2h2_rx_chan
+ generic (
+ data_width_g : integer;
+ amount_width_g : integer;
+ addr_cmp_lo_g : integer;
+ addr_cmp_hi_g : integer);
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ avalon_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ irq_amount_in : in std_logic_vector(amount_width_g-1 downto 0);
+ hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_in : in std_logic;
+ hibi_empty_in : in std_logic;
+ init_in : in std_logic;
+ irq_ack_in : in std_logic;
+ avalon_waitreq_in : in std_logic;
+ avalon_we_in : in std_logic;
+ avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ avalon_we_out : out std_logic;
+ addr_match_out : out std_logic;
+ irq_out : out std_logic);
+ end component;
+
+
+-- signal irq_amount_r : chan_amount_array;
+ signal avalon_wes : std_logic_vector(n_chans_g-1 downto 0);
+ signal matches : std_logic_vector(n_chans_g-1 downto 0);
+ signal irq_ack_r : std_logic_vector(n_chans_g-1 downto 0);
+
+
+ component n2h2_ind_chan
+ generic (
+ data_width_g : integer;
+ amount_width_g : integer;
+ addr_cmp_lo_g : integer;
+ addr_cmp_hi_g : integer;
+ Tx_HIBI_addr_g : integer
+ );
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+ avalon_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_in : in std_logic;
+ hibi_empty_in : in std_logic;
+ hibi_addr_rx_in : in std_logic_vector(data_width_g-1 downto 0);
+
+ init_in : in std_logic;
+ tx_start_out : out std_logic;
+ tx_status_done_in : in std_logic;
+ tx_comm_out : out std_logic_vector(2 downto 0);
+ tx_hibi_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_ram_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_out : out std_logic_vector(amount_width_g-1 downto 0);
+ tx_reserve_out : out std_logic
+ );
+ end component;
+
+ signal avalon_addr_to_dct : std_logic_vector(data_width_g-1 downto 0);
+ signal init_to_dct : std_logic;
+ signal hibi_addr_rx_to_dct : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_start_from_dct : std_logic;
+ signal tx_status_done_to_dct : std_logic;
+ signal tx_comm_from_dct : std_logic_vector(2 downto 0);
+ signal tx_hibi_addr_from_dct : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_ram_addr_from_dct : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_amount_from_dct : std_logic_vector(amount_width_g-1 downto 0);
+ signal tx_reserve_from_dct : std_logic;
+
+ component one_hot_mux
+ generic (
+ data_width_g : integer);
+ port (
+ data_in : in std_logic_vector(data_width_g-1 downto 0);
+ sel_in : in std_logic_vector(data_width_g-1 downto 0);
+ data_out : out std_logic);
+ end component;
+
+ type chan_data_switched is array (data_width_g-1 downto 0) of std_logic_vector(n_chans_g-1 downto 0);
+
+ signal avalon_addr_temp : chan_data_switched;
+ signal tx_req_cpu_when_busy_r : std_logic;
+ signal was_not_high_r : std_logic;
+
+begin -- rtl
+ avalon_we_r <= hibi_empty_in nor hibi_av_in;
+ avalon_we_out <= avalon_we_r and curr_chan_avalon_we_r; -- and not_dirty_chan_we_r;
+
+-- hibi_re_r <= (not avalon_waitrequest_in) or hibi_av_in;
+ hibi_re_r <= '1' and (not ((avalon_waitrequest_in) and (avalon_we_r and curr_chan_avalon_we_r))); -- or hibi_av_in;
+
+ hibi_re_out <= hibi_re_r;
+ avalon_writedata_out <= hibi_data_in;
+
+ hibi_av_re_empty_r <= hibi_av_in & hibi_re_r & hibi_empty_in;
+
+ avalon_addr_out <= avalon_addr_r;
+
+ channels : for i in 0 to n_chans_g-1 generate
+
+ n2h2_rx_chan_1 : n2h2_rx_chan
+ generic map (
+ data_width_g => data_width_g,
+ amount_width_g => amount_width_g,
+ addr_cmp_lo_g => hibi_addr_cmp_lo_g,
+ addr_cmp_hi_g => hibi_addr_cmp_hi_g)
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+ avalon_addr_in => mem_addr_r(i),
+ hibi_addr_in => sender_addr_r(i),
+ irq_amount_in => irq_amount_r(i),
+ hibi_data_in => hibi_data_in,
+ hibi_av_in => hibi_av_in,
+ hibi_empty_in => hibi_empty_in,
+ init_in => init_chan_r(i),
+ irq_ack_in => irq_ack_r(i),
+ avalon_waitreq_in => avalon_waitrequest_in,
+ avalon_we_in => avalon_we_r,
+ avalon_addr_out => current_mem_addr_r(i),
+ avalon_we_out => avalon_wes(i),
+ addr_match_out => matches(i),
+ irq_out => irq_chan_r(i)
+ );
+
+ end generate channels;
+
+ one_hot_mux_1 : one_hot_mux
+ generic map (
+ data_width_g => n_chans_g)
+ port map (
+ data_in => avalon_wes,
+ sel_in => matches,
+ data_out => curr_chan_avalon_we_r
+ );
+
+ ava_temp : for i in 0 to n_chans_g-1 generate
+ j : for j in 0 to data_width_g-1 generate
+ avalon_addr_temp(j)(i) <= current_mem_addr_r(i)(j);
+ end generate j;
+ end generate ava_temp;
+
+ avalon_address : for i in 0 to data_width_g-1 generate
+ one_hot_mux_addr_i : one_hot_mux
+ generic map (
+ data_width_g => n_chans_g)
+ port map (
+ data_in => avalon_addr_temp(i),
+ sel_in => matches,
+ data_out => avalon_addr_r(i)
+ );
+
+ end generate avalon_address;
+
+ DCT_control : n2h2_ind_chan
+ generic map (
+ data_width_g => data_width_g,
+ amount_width_g => amount_width_g,
+ addr_cmp_lo_g => hibi_addr_cmp_lo_g,
+ addr_cmp_hi_g => hibi_addr_cmp_hi_g,
+ Tx_HIBI_addr_g => dct_hibi_addr_r
+ )
+ port map (
+ clk => clk,
+ rst_n => rst_n,
+ avalon_addr_in => avalon_addr_to_dct,
+ hibi_data_in => hibi_data_in,
+ hibi_av_in => hibi_av_in,
+ hibi_empty_in => hibi_empty_in,
+ hibi_addr_rx_in => hibi_addr_rx_to_dct,
+ init_in => init_to_dct,
+ tx_start_out => tx_start_from_dct,
+ tx_status_done_in => tx_status_done_to_dct,
+ tx_comm_out => tx_comm_from_dct,
+ tx_hibi_addr_out => tx_hibi_addr_from_dct,
+ tx_ram_addr_out => tx_ram_addr_from_dct,
+ tx_amount_out => tx_amount_from_dct,
+ tx_reserve_out => tx_reserve_from_dct
+ );
+
+
+
+
+
+ cpu_side : process (clk, rst_n)
+ variable legal_write : std_logic;
+ variable legal_read : std_logic;
+ variable n_chan : integer range n_chans_g-1 downto 0;
+ variable n_dest : integer range (2**conf_bits_c)-1 downto 0;
+ begin -- process cpu
+ if rst_n = '0' then -- asynchronous reset (active low)
+ for i in n_chans_g-1 downto 0 loop
+ mem_addr_r(i) <= (others => '0');
+ sender_addr_r(i) <= (others => '0');
+ irq_amount_r(i) <= (others => '1');
+ end loop; -- i
+ avalon_cfg_readdata_out <= (others => '0');
+ init_chan_r <= (others => '0');
+ control_r <= (others => '0');
+ -- status for only rx signals..
+ status_r(0) <= '0';
+ tx_mem_addr_r <= (others => '0');
+ tx_comm_r <= (others => '0');
+ tx_amount_r <= (others => '0');
+ tx_hibi_addr_r <= (others => '0');
+ rx_irq_out <= '0';
+ init_to_dct <= '0';
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ -- set the IRQ. may be changed below if some IRQ
+ -- is cleared and others are pending.
+ if irq_chan_r /= 0 then
+ -- irq ena bit...
+ rx_irq_out <= control_r(1);
+ end if;
+
+ init_to_dct <= '0';
+ irq_ack_r <= (others => '0');
+
+ legal_write := avalon_cfg_cs_in and avalon_cfg_we_in;
+ legal_read := avalon_cfg_cs_in and avalon_cfg_re_in;
+ n_chan := conv_integer(avalon_cfg_addr_in(n_chans_bits_g+conf_bits_c-1 downto conf_bits_c));
+ n_dest := conv_integer(avalon_cfg_addr_in(conf_bits_c-1 downto 0));
+
+
+ if legal_write = '1' then
+ case n_dest is
+ when 0 => -- mem_addr
+ mem_addr_r(n_chan) <= avalon_cfg_writedata_in;
+ when 1 => -- sender addr
+ sender_addr_r(n_chan) <= avalon_cfg_writedata_in;
+ when 2 => -- irq_amount
+ irq_amount_r(n_chan) <= avalon_cfg_writedata_in(amount_width_g-1 downto 0);
+ -- 3 is unwritable, curr addr ptr
+ when 4 => -- control
+ control_r <= avalon_cfg_writedata_in(control_bits_c-1 downto 0);
+ when 5 => -- init channel
+ init_chan_r <= avalon_cfg_writedata_in(n_chans_g-1 downto 0);
+ when 7 => -- IRQ chan
+ irq_ack_r <= avalon_cfg_writedata_in(n_chans_g-1 downto 0);
+ -- goes down so that generates an edge
+ -- when many interrupts are pending.
+ rx_irq_out <= '0';
+
+ -- NOW TX SIGNALS
+ when 8 =>
+ tx_mem_addr_r <= avalon_cfg_writedata_in;
+ when 9 =>
+ tx_amount_r <= avalon_cfg_writedata_in(amount_width_g-1 downto 0);
+ when 10 =>
+ tx_comm_r <= avalon_cfg_writedata_in(2 downto 0);
+ when 11 =>
+ tx_hibi_addr_r <= avalon_cfg_writedata_in;
+
+ -- NOW DCT
+ when 13 =>
+ init_to_dct <= '1';
+ when 14 =>
+ hibi_addr_rx_to_dct <= avalon_cfg_writedata_in;
+ when 15 =>
+ avalon_addr_to_dct <= avalon_cfg_writedata_in;
+ when others =>
+
+
+ -- do nothing
+
+ end case;
+ end if;
+
+ if legal_read = '1' then
+ case n_dest is
+ when 0 => -- mem_addr
+ avalon_cfg_readdata_out <= mem_addr_r(n_chan);
+ when 1 => -- sender addr
+ avalon_cfg_readdata_out <= sender_addr_r(n_chan);
+ when 2 => -- irq amount
+ avalon_cfg_readdata_out(data_width_g-1 downto amount_width_g) <= (others => '0');
+ avalon_cfg_readdata_out(amount_width_g-1 downto 0) <= irq_amount_r(n_chan);
+ when 3 => -- current addr ptr
+ avalon_cfg_readdata_out <= current_mem_addr_r(n_chan);
+ when 4 => -- control and status regs
+ avalon_cfg_readdata_out(15 downto control_bits_c) <= (others => '0');
+ avalon_cfg_readdata_out(control_bits_c-1 downto 0) <= control_r;
+ avalon_cfg_readdata_out(31 downto status_bits_c+15) <= (others => '0');
+ avalon_cfg_readdata_out(status_bits_c+15 downto 16) <= status_r;
+ when 5 => -- Init Channel
+ avalon_cfg_readdata_out(data_width_g-1 downto n_chans_g) <= (others => '0');
+ avalon_cfg_readdata_out(n_chans_g-1 downto 0) <= init_chan_r;
+ -- 6 is reserved
+ when 7 => -- IRQ chan
+ avalon_cfg_readdata_out(data_width_g-1 downto n_chans_g) <= (others => '0');
+ avalon_cfg_readdata_out(n_chans_g-1 downto 0) <= irq_chan_r;
+ when others =>
+ -- do nothing;
+ end case;
+ end if;
+
+ -- busy bit
+ status_r(0) <= avalon_we_r;
+
+ if init_chan_r /= conv_std_logic_vector(0, n_chans_g) then
+ init_chan_r <= (others => '0');
+ end if;
+
+
+ end if;
+ end process cpu_side;
+
+
+-- tx signals
+ -- done bit, start tx
+ status_r(1) <= tx_status_done_in;
+ tx_status_done_to_dct <= tx_status_done_in;
+
+ tx_start : process (clk, rst_n)
+ begin -- process sel_tx_start
+ if rst_n = '0' then -- asynchronous reset (active low)
+ was_not_high_r <= '1';
+ tx_req_cpu_when_busy_r <= '0';
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ if tx_status_done_in = '0' and control_r(0) = '1' then --and was_not_high_r = '1' then
+ tx_req_cpu_when_busy_r <= '1';
+ end if;
+
+ if tx_status_done_in = '1' and tx_req_cpu_when_busy_r = '1' and tx_start_from_dct = '0' then
+ tx_req_cpu_when_busy_r <= '0';
+ end if;
+
+-- tx_req_cpu_when_busy_r <= (d and c) or ((r and s) or ((r or s) and (d or c)));
+
+ if control_r(0) = '1' and tx_status_done_in = '1' then
+ if was_not_high_r = '1' then
+ was_not_high_r <= '1';
+-- tx_start_out <= '1';
+ else
+ was_not_high_r <= '0';
+-- tx_start_out <= '0';
+ end if;
+ else
+ was_not_high_r <= '1';
+-- tx_start_out <= '0';
+ end if;
+
+-- if tx_status_done_in = '1' then
+-- if tx_reserve_from_dct = '1' then
+-- tx_amount_out <= tx_amount_from_dct;
+-- tx_mem_addr_out <= tx_ram_addr_from_dct;
+-- tx_comm_out <= tx_comm_from_dct;
+-- tx_hibi_addr_out <= tx_hibi_addr_from_dct;
+-- tx_start_out <= tx_start_from_dct;
+-- else
+-- tx_amount_out <= tx_amount_r;
+-- tx_mem_addr_out <= tx_mem_addr_r;
+-- tx_comm_out <= tx_comm_r;
+-- tx_hibi_addr_out <= tx_hibi_addr_r;
+-- if tx_req_cpu_when_busy_r = '1' then
+-- tx_start_out <= '1';
+-- tx_req_cpu_when_busy_r <= '0';
+-- end if;
+-- end if;
+-- end if;
+
+
+
+ end if;
+
+ end process tx_start;
+
+ tx_start_out <= tx_start_from_dct or ((control_r(0) or tx_req_cpu_when_busy_r) and (tx_status_done_in));
+
+ asynch_tx: process (tx_start_from_dct, tx_amount_r, tx_mem_addr_r, tx_comm_r, tx_hibi_addr_r,
+ tx_amount_from_dct, tx_ram_addr_from_dct, tx_comm_from_dct, tx_hibi_addr_from_dct)
+ begin -- process asynch_tx_
+ if tx_start_from_dct = '1' then
+ tx_amount_out <= tx_amount_from_dct;
+ tx_mem_addr_out <= tx_ram_addr_from_dct;
+ tx_comm_out <= tx_comm_from_dct;
+ tx_hibi_addr_out <= tx_hibi_addr_from_dct;
+ else
+ tx_amount_out <= tx_amount_r;
+ tx_mem_addr_out <= tx_mem_addr_r;
+ tx_comm_out <= tx_comm_r;
+ tx_hibi_addr_out <= tx_hibi_addr_r;
+ end if;
+ end process asynch_tx;
+
+
+end rtl;
+
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/readme.txt
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/readme.txt (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/readme.txt (revision 16)
@@ -0,0 +1,3 @@
+These files are copies, do not modify. Do not use either... See other readme.txt.
+
+SOPC builder's generate needs these files to succesfully(?) complete the generation.
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_ind_chan.vhd
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_ind_chan.vhd (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/hdl/n2h2_ind_chan.vhd (revision 16)
@@ -0,0 +1,180 @@
+-------------------------------------------------------------------------------
+-- Title : N2H2 independent channel
+-- Project :
+-------------------------------------------------------------------------------
+-- File : n2h2_ind_chan.vhd
+-- Author : kulmala3
+-- Created : 20.06.2005
+-- Last update: 28.06.2005
+-- Description: An independent channel for N2H2. Sits on the RX side and can
+-- respond to requests to compile-time constant HIBI address. sends data from
+-- given address to the requesting block. HIBI address of the block is
+-- compile-time constant currently. An example of the block is DCT.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2005
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 20.06.2005 1.0 AK Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+entity n2h2_ind_chan is
+
+ generic (
+ data_width_g : integer := 0;
+ amount_width_g : integer := 0;
+ addr_cmp_lo_g : integer := 0;
+ addr_cmp_hi_g : integer := 0;
+ Tx_HIBI_addr_g : integer := 0 -- where data is sent to
+ );
+
+ port (
+ clk : in std_logic;
+ rst_n : in std_logic;
+
+ avalon_addr_in : in std_logic_vector(data_width_g-1 downto 0);
+
+ hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
+ hibi_av_in : in std_logic;
+ hibi_empty_in : in std_logic;
+ init_in : in std_logic;
+ -- keep still between transfers
+ hibi_addr_rx_in : in std_logic_vector(data_width_g-1 downto 0);
+
+ tx_start_out : out std_logic;
+ tx_status_done_in : in std_logic;
+ tx_comm_out : out std_logic_vector(2 downto 0);
+ tx_hibi_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_ram_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+ tx_amount_out : out std_logic_vector(amount_width_g-1 downto 0);
+ -- this never writes anything.
+-- avalon_waitreq_in : in std_logic;
+-- avalon_we_in : in std_logic;
+-- avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
+-- avalon_we_out : out std_logic;
+ tx_reserve_out : out std_logic
+ );
+
+end n2h2_ind_chan;
+
+architecture rtl of n2h2_ind_chan is
+ constant dont_care_c : std_logic := 'X';
+ constant addr_offset_c : integer := data_width_g/8;
+
+ type control_state is (normal, wait_tx);
+
+ signal ctrl_r : control_state;
+
+ signal addr_match_r : std_logic;
+ signal av_empty : std_logic_vector(1 downto 0);
+
+ signal amount_r : std_logic_vector(amount_width_g-1 downto 0);
+ signal ram_addr_r : std_logic_vector(data_width_g-1 downto 0);
+ signal tx_comm_r : std_logic_vector(2 downto 0);
+begin -- rtl
+
+-- tx_reserve_out <= addr_match_r;
+ tx_comm_out <= tx_comm_r;
+ tx_ram_addr_out <= ram_addr_r;
+ tx_amount_out <= amount_r;
+ tx_hibi_addr_out <= conv_std_logic_vector(Tx_HIBI_addr_g, data_width_g);
+
+ av_empty <= hibi_av_in & hibi_empty_in;
+
+ addr_matching : process (clk, rst_n)
+ begin -- process addr_matching
+ if rst_n = '0' then -- asynchronous reset (active low)
+ addr_match_r <= '0';
+ elsif clk'event and clk = '1' then -- rising clock edge
+ case av_empty is
+ when "11" | "01" =>
+ addr_match_r <= '0';
+ when "10" =>
+ if hibi_data_in(addr_cmp_hi_g downto addr_cmp_lo_g) =
+ hibi_addr_rx_in(addr_cmp_hi_g downto addr_cmp_lo_g) then
+ addr_match_r <= '1';
+ else
+ addr_match_r <= '0';
+ end if;
+ when others =>
+ -- one request per time!
+-- addr_match_r <= addr_match_r;
+ addr_match_r <= '0';
+ end case;
+
+ end if;
+ end process addr_matching;
+
+
+ ena : process (clk, rst_n)
+ begin -- process ena
+ if rst_n = '0' then -- asynchronous reset (active low)
+ ctrl_r <= normal;
+ elsif clk'event and clk = '1' then -- rising clock edge
+ tx_start_out <= '0';
+ tx_reserve_out <= '0';
+
+ tx_comm_r <= "010";
+
+ case ctrl_r is
+ when normal =>
+ if init_in = '1' then
+ ram_addr_r <= avalon_addr_in;
+ amount_r <= conv_std_logic_vector(1, amount_width_g);
+ tx_reserve_out <= tx_status_done_in;
+ tx_comm_r <= "011";
+ if tx_status_done_in = '0' then
+ ctrl_r <= wait_tx;
+ tx_start_out <= '0';
+ else
+ tx_start_out <= '1';
+ ctrl_r <= normal;
+ end if;
+ end if;
+
+ -- addr is checked in previous turn, result is seen when the
+ -- data is on the bus
+ if addr_match_r = '1' then
+ amount_r <= hibi_data_in(amount_width_g-1 downto 0);
+ -- NOTE! update multiply with shift
+ ram_addr_r <= ram_addr_r + conv_integer(amount_r)*addr_offset_c;
+ tx_comm_r <= "010";
+ if tx_status_done_in = '0' then
+ ctrl_r <= wait_tx;
+ tx_start_out <= '0';
+ else
+ tx_start_out <= '1';
+ ctrl_r <= normal;
+ end if;
+ tx_reserve_out <= tx_status_done_in;
+ end if;
+
+ when wait_tx =>
+ if tx_status_done_in = '1' then
+ tx_start_out <= '1';
+ tx_reserve_out <= '1';
+ tx_comm_r <= tx_comm_r;
+ ctrl_r <= normal;
+ else
+ tx_start_out <= '0';
+ tx_reserve_out <= '0';
+ tx_comm_r <= tx_comm_r;
+ ctrl_r <= wait_tx;
+ end if;
+ when others => null;
+ end case;
+
+
+ end if;
+ end process ena;
+
+
+
+
+end rtl;
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/inc/readme.txt
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/inc/readme.txt (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/inc/readme.txt (revision 16)
@@ -0,0 +1 @@
+See ../../drv for files tut_n2h_regs.c and tut_n2h_regs.h.
\ No newline at end of file
Index: TUT/ip.hwp.communication/n2h2/Sopc_component/class.ptf
===================================================================
--- TUT/ip.hwp.communication/n2h2/Sopc_component/class.ptf (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/Sopc_component/class.ptf (revision 16)
@@ -0,0 +1,2143 @@
+#
+# This class.ptf file built by Component Editor
+# 2005.06.29.10:05:33
+#
+# DO NOT MODIFY THIS FILE
+# If you hand-modify this file you will likely
+# interfere with Component Editor's ability to
+# read and edit it. And then Component Editor
+# will overwrite your changes anyway. So, for
+# the very best results, just relax and
+# DO NOT MODIFY THIS FILE
+#
+CLASS n2h2_str
+{
+ MODULE_DEFAULTS
+ {
+ class = "n2h2_str";
+ class_version = "0.1";
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ }
+ COMPONENT_BUILDER
+ {
+ GLS_SETTINGS
+ {
+ }
+ }
+ PORT_WIRING
+ {
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL x101
+ {
+ name = "n2h2_str/global_signals";
+ format = "Divider";
+ }
+ SIGNAL x102
+ {
+ name = "n2h2_str/avalon_slave_0";
+ format = "Divider";
+ }
+ SIGNAL x103
+ {
+ name = "clk_cfg";
+ }
+ SIGNAL x104
+ {
+ name = "rst_n";
+ }
+ SIGNAL x105
+ {
+ name = "avalon_cfg_addr_in";
+ }
+ SIGNAL x106
+ {
+ name = "avalon_cfg_writedata_in";
+ }
+ SIGNAL x107
+ {
+ name = "avalon_cfg_we_in";
+ }
+ SIGNAL x108
+ {
+ name = "avalon_cfg_readdata_out";
+ }
+ SIGNAL x109
+ {
+ name = "avalon_cfg_re_in";
+ }
+ SIGNAL x110
+ {
+ name = "avalon_cfg_cs_in";
+ }
+ SIGNAL x111
+ {
+ name = "hibi_data_in";
+ }
+ SIGNAL x112
+ {
+ name = "hibi_av_in";
+ }
+ SIGNAL x113
+ {
+ name = "hibi_empty_in";
+ }
+ SIGNAL x114
+ {
+ name = "hibi_comm_in";
+ radix = "hexadecimal";
+ }
+ SIGNAL x115
+ {
+ name = "hibi_re_out";
+ }
+ SIGNAL x116
+ {
+ name = "hibi_data_out";
+ }
+ SIGNAL x117
+ {
+ name = "hibi_av_out";
+ }
+ SIGNAL x118
+ {
+ name = "hibi_full_in";
+ }
+ SIGNAL x119
+ {
+ name = "hibi_comm_out";
+ radix = "hexadecimal";
+ }
+ SIGNAL x120
+ {
+ name = "hibi_we_out";
+ }
+ SIGNAL x121
+ {
+ name = "rx_irq_out";
+ }
+ SIGNAL x122
+ {
+ name = "n2h2_str/avalon_master_tx";
+ format = "Divider";
+ }
+ SIGNAL x123
+ {
+ name = "clk_tx";
+ }
+ SIGNAL x124
+ {
+ name = "avalon_addr_out_tx";
+ }
+ SIGNAL x125
+ {
+ name = "avalon_re_out_tx";
+ }
+ SIGNAL x126
+ {
+ name = "avalon_readdata_in_tx";
+ }
+ SIGNAL x127
+ {
+ name = "avalon_waitrequest_in_tx";
+ }
+ SIGNAL x128
+ {
+ name = "avalon_readdatavalid_in_tx";
+ }
+ SIGNAL x129
+ {
+ name = "n2h2_str/avalon_master_rx";
+ format = "Divider";
+ }
+ SIGNAL x130
+ {
+ name = "clk_rx";
+ }
+ SIGNAL x131
+ {
+ name = "avalon_addr_out_rx";
+ }
+ SIGNAL x132
+ {
+ name = "avalon_we_out_rx";
+ }
+ SIGNAL x133
+ {
+ name = "avalon_writedata_out_rx";
+ }
+ SIGNAL x134
+ {
+ name = "avalon_waitrequest_in_rx";
+ }
+ }
+ }
+ SLAVE avalon_slave_0
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Address_Width = "-1";
+ Address_Alignment = "dynamic";
+ Data_Width = "8";
+ Has_Base_Address = "1";
+ Has_IRQ = "1";
+ Setup_Time = "0cycles";
+ Hold_Time = "0cycles";
+ Read_Wait_States = "1cycles";
+ Write_Wait_States = "1cycles";
+ Read_Latency = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Is_Printable_Device = "0";
+ Is_Memory_Device = "1";
+ Is_Readable = "1";
+ Is_Writable = "1";
+ Minimum_Uninterrupted_Run_Length = "1";
+ }
+ COMPONENT_BUILDER
+ {
+ AVS_SETTINGS
+ {
+ Setup_Value = "0";
+ Read_Wait_Value = "1";
+ Write_Wait_Value = "1";
+ Hold_Value = "0";
+ Timing_Units = "cycles";
+ Read_Latency_Value = "0";
+ Max_Pending_Read_Transactions_Value = "1";
+ Address_Alignment = "dynamic";
+ Is_Printable_Device = "0";
+ interface_name = "Avalon Slave";
+ Minimum_Arbitration_Shares = "1";
+ external_wait = "0";
+ Is_Memory_Device = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT clk_cfg
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "clk";
+ is_shared = "0";
+ }
+ PORT rst_n
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "reset_n";
+ is_shared = "0";
+ }
+ PORT avalon_cfg_addr_in
+ {
+ width = "-1";
+ width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1";
+ direction = "input";
+ type = "address";
+ is_shared = "0";
+ }
+ PORT avalon_cfg_writedata_in
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "input";
+ type = "writedata";
+ is_shared = "0";
+ }
+ PORT avalon_cfg_we_in
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "write";
+ is_shared = "0";
+ }
+ PORT avalon_cfg_readdata_out
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "output";
+ type = "readdata";
+ is_shared = "0";
+ }
+ PORT avalon_cfg_re_in
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "read";
+ is_shared = "0";
+ }
+ PORT avalon_cfg_cs_in
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "chipselect";
+ is_shared = "0";
+ }
+ PORT hibi_data_in
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "input";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_av_in
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_empty_in
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_comm_in
+ {
+ width = "3";
+ width_expression = "";
+ direction = "input";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_re_out
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_data_out
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_av_out
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_full_in
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_comm_out
+ {
+ width = "3";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT hibi_we_out
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "export";
+ is_shared = "0";
+ }
+ PORT rx_irq_out
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "irq";
+ is_shared = "0";
+ }
+ }
+ }
+ MASTER avalon_master_tx
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Address_Width = "4";
+ Data_Width = "8";
+ Do_Stream_Reads = "1";
+ Do_Stream_Writes = "0";
+ Is_Asynchronous = "0";
+ Has_IRQ = "0";
+ Irq_Scheme = "none";
+ Interrupt_Range = "";
+ Is_Readable = "1";
+ Is_Writable = "0";
+ Register_Outgoing_Signals = "0";
+ }
+ COMPONENT_BUILDER
+ {
+ AVM_SETTINGS
+ {
+ stream_reads = "1";
+ stream_writes = "0";
+ irq_width = "0";
+ irq_number_width = "0";
+ irq_scheme = "none";
+ Is_Asynchronous = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT clk_tx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "clk";
+ is_shared = "0";
+ }
+ PORT avalon_addr_out_tx
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "output";
+ type = "address";
+ is_shared = "0";
+ }
+ PORT avalon_re_out_tx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "read";
+ is_shared = "0";
+ }
+ PORT avalon_readdata_in_tx
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "input";
+ type = "readdata";
+ is_shared = "0";
+ }
+ PORT avalon_waitrequest_in_tx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "waitrequest";
+ is_shared = "0";
+ }
+ PORT avalon_readdatavalid_in_tx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "readdatavalid";
+ is_shared = "0";
+ }
+ }
+ }
+ MASTER avalon_master_rx
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Address_Width = "4";
+ Data_Width = "8";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "1";
+ Is_Asynchronous = "0";
+ Has_IRQ = "0";
+ Irq_Scheme = "none";
+ Interrupt_Range = "";
+ Is_Readable = "0";
+ Is_Writable = "1";
+ Register_Outgoing_Signals = "0";
+ }
+ COMPONENT_BUILDER
+ {
+ AVM_SETTINGS
+ {
+ stream_reads = "0";
+ stream_writes = "1";
+ irq_width = "0";
+ irq_number_width = "0";
+ irq_scheme = "none";
+ Is_Asynchronous = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT clk_rx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "clk";
+ is_shared = "0";
+ }
+ PORT avalon_addr_out_rx
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "output";
+ type = "address";
+ is_shared = "0";
+ }
+ PORT avalon_we_out_rx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "output";
+ type = "write";
+ is_shared = "0";
+ }
+ PORT avalon_writedata_out_rx
+ {
+ width = "-1";
+ width_expression = "((data_width_g - 1)) - (0) + 1";
+ direction = "output";
+ type = "writedata";
+ is_shared = "0";
+ }
+ PORT avalon_waitrequest_in_rx
+ {
+ width = "1";
+ width_expression = "";
+ direction = "input";
+ type = "waitrequest";
+ is_shared = "0";
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ hdl_parameters
+ {
+ data_width_g = "32";
+ amount_width_g = "16";
+ n_chans_g = "8";
+ n_chans_bits_g = "3";
+ hibi_addr_cmp_lo_g = "0";
+ hibi_addr_cmp_hi_g = "27";
+ }
+ }
+ }
+ USER_INTERFACE
+ {
+ USER_LABELS
+ {
+ name = "n2h2_str";
+ technology = "User Logic";
+ }
+ WIZARD_UI the_wizard_ui
+ {
+ title = "n2h2_str - {{ $MOD }}";
+ CONTEXT
+ {
+ H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
+ M = "";
+ SBI_ = "SYSTEM_BUILDER_INFO";
+ SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
+ SBI_avalon_master_tx = "MASTER avalon_master_tx/SYSTEM_BUILDER_INFO";
+ SBI_avalon_master_rx = "MASTER avalon_master_rx/SYSTEM_BUILDER_INFO";
+ # The following signals have parameterized widths:
+ PORT_avalon_cfg_addr_in = "SLAVE avalon_slave_0/PORT_WIRING/PORT avalon_cfg_addr_in";
+ PORT_avalon_cfg_writedata_in = "SLAVE avalon_slave_0/PORT_WIRING/PORT avalon_cfg_writedata_in";
+ PORT_avalon_cfg_readdata_out = "SLAVE avalon_slave_0/PORT_WIRING/PORT avalon_cfg_readdata_out";
+ PORT_hibi_data_in = "SLAVE avalon_slave_0/PORT_WIRING/PORT hibi_data_in";
+ PORT_hibi_data_out = "SLAVE avalon_slave_0/PORT_WIRING/PORT hibi_data_out";
+ PORT_avalon_addr_out_tx = "MASTER avalon_master_tx/PORT_WIRING/PORT avalon_addr_out_tx";
+ PORT_avalon_readdata_in_tx = "MASTER avalon_master_tx/PORT_WIRING/PORT avalon_readdata_in_tx";
+ PORT_avalon_addr_out_rx = "MASTER avalon_master_rx/PORT_WIRING/PORT avalon_addr_out_rx";
+ PORT_avalon_writedata_out_rx = "MASTER avalon_master_rx/PORT_WIRING/PORT avalon_writedata_out_rx";
+ }
+ PAGES main
+ {
+ PAGE 1
+ {
+ align = "left";
+ title = "n2h2_str 0.1 Settings";
+ layout = "vertical";
+ TEXT
+ {
+ title = "Built on: 2005.06.29.10:05:33";
+ }
+ TEXT
+ {
+ title = "Class name: n2h2_str";
+ }
+ TEXT
+ {
+ title = "Class version: 0.1";
+ }
+ TEXT
+ {
+ title = "Component name: n2h2_str";
+ }
+ TEXT
+ {
+ title = "Component Group: User Logic";
+ }
+ GROUP parameters
+ {
+ title = "Parameters";
+ layout = "form";
+ align = "left";
+ EDIT e1
+ {
+ editable = "1";
+ title = "data_width_g:";
+ columns = "40";
+ tooltip = "default value: 32";
+ DATA
+ {
+ $H/data_width_g = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/data_width_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/data_width_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/data_width_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/data_width_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/data_width_g,'ugly_-?[0-9]+')))'data_width_g must be numeric constant, not '+$H/data_width_g; }}";
+ }
+ EDIT e2
+ {
+ editable = "1";
+ title = "amount_width_g:";
+ columns = "40";
+ tooltip = "default value: 16";
+ DATA
+ {
+ $H/amount_width_g = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/amount_width_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/amount_width_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/amount_width_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/amount_width_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/amount_width_g,'ugly_-?[0-9]+')))'amount_width_g must be numeric constant, not '+$H/amount_width_g; }}";
+ }
+ EDIT e3
+ {
+ editable = "1";
+ title = "n_chans_g:";
+ columns = "40";
+ tooltip = "default value: 8";
+ DATA
+ {
+ $H/n_chans_g = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/n_chans_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/n_chans_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/n_chans_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/n_chans_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/n_chans_g,'ugly_-?[0-9]+')))'n_chans_g must be numeric constant, not '+$H/n_chans_g; }}";
+ }
+ EDIT e4
+ {
+ editable = "1";
+ title = "n_chans_bits_g:";
+ columns = "40";
+ tooltip = "default value: 3";
+ DATA
+ {
+ $H/n_chans_bits_g = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/n_chans_bits_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/n_chans_bits_g,'ugly_-?[0-9]+')))'n_chans_bits_g must be numeric constant, not '+$H/n_chans_bits_g; }}";
+ }
+ EDIT e5
+ {
+ editable = "1";
+ title = "hibi_addr_cmp_lo_g:";
+ columns = "40";
+ tooltip = "default value: 0";
+ DATA
+ {
+ $H/hibi_addr_cmp_lo_g = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/hibi_addr_cmp_lo_g,'ugly_-?[0-9]+')))'hibi_addr_cmp_lo_g must be numeric constant, not '+$H/hibi_addr_cmp_lo_g; }}";
+ }
+ EDIT e6
+ {
+ editable = "1";
+ title = "hibi_addr_cmp_hi_g:";
+ columns = "40";
+ tooltip = "default value: 27";
+ DATA
+ {
+ $H/hibi_addr_cmp_hi_g = "$";
+ }
+ q = "'";
+ warning = "{{ if(!(regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/hibi_addr_cmp_hi_g,'ugly_-?[0-9]+')))'hibi_addr_cmp_hi_g must be numeric constant, not '+$H/hibi_addr_cmp_hi_g; }}";
+ }
+ }
+ GROUP variable_port_widths
+ {
+ # This group is for display only, to preview parameterized port widths
+ title = "Parameterized Signal Widths";
+ layout = "form";
+ align = "left";
+ EDIT avalon_cfg_addr_in_width
+ {
+ id = "avalon_cfg_addr_in_width";
+ editable = "0";
+ title = "avalon_cfg_addr_in[(((n_chans_bits_g + 4) - 1)) - (0) + 1]:";
+ tooltip = "avalon_cfg_addr_in[(((n_chans_bits_g + 4) - 1)) - (0) + 1]
direction: input
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_cfg_addr_in/width = (int(((( ( $H/n_chans_bits_g ) + 4) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_slave_0/Address_Width = $PORT_avalon_cfg_addr_in/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_cfg_addr_in/width = "$"; + } + warning = "{{ if($PORT_avalon_cfg_addr_in/width <= 0)('width of avalon_cfg_addr_in must be greater than zero' ) }}"; + } + EDIT avalon_cfg_writedata_in_width + { + id = "avalon_cfg_writedata_in_width"; + editable = "0"; + title = "avalon_cfg_writedata_in[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_cfg_writedata_in[((data_width_g - 1)) - (0) + 1]
direction: input
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_cfg_writedata_in/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_slave_0/Data_Width = 2 ^ int(log2($PORT_avalon_cfg_writedata_in/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_cfg_writedata_in/width = "$"; + } + warning = "{{ if($PORT_avalon_cfg_writedata_in/width <= 0)('width of avalon_cfg_writedata_in must be greater than zero' ) }}"; + } + EDIT avalon_cfg_readdata_out_width + { + id = "avalon_cfg_readdata_out_width"; + editable = "0"; + title = "avalon_cfg_readdata_out[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_cfg_readdata_out[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_cfg_readdata_out/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_slave_0/Data_Width = 2 ^ int(log2($PORT_avalon_cfg_readdata_out/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_cfg_readdata_out/width = "$"; + } + warning = "{{ if($PORT_avalon_cfg_readdata_out/width <= 0)('width of avalon_cfg_readdata_out must be greater than zero' ) }}"; + } + EDIT hibi_data_in_width + { + id = "hibi_data_in_width"; + editable = "0"; + title = "hibi_data_in[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "hibi_data_in[((data_width_g - 1)) - (0) + 1]
direction: input
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_hibi_data_in/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_hibi_data_in/width = "$"; + } + warning = "{{ if($PORT_hibi_data_in/width <= 0)('width of hibi_data_in must be greater than zero' ) }}"; + } + EDIT hibi_data_out_width + { + id = "hibi_data_out_width"; + editable = "0"; + title = "hibi_data_out[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "hibi_data_out[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_hibi_data_out/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_hibi_data_out/width = "$"; + } + warning = "{{ if($PORT_hibi_data_out/width <= 0)('width of hibi_data_out must be greater than zero' ) }}"; + } + EDIT avalon_addr_out_tx_width + { + id = "avalon_addr_out_tx_width"; + editable = "0"; + title = "avalon_addr_out_tx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_addr_out_tx[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_addr_out_tx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_tx/Address_Width = $PORT_avalon_addr_out_tx/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_addr_out_tx/width = "$"; + } + warning = "{{ if($PORT_avalon_addr_out_tx/width <= 0)('width of avalon_addr_out_tx must be greater than zero' ) }}"; + } + EDIT avalon_readdata_in_tx_width + { + id = "avalon_readdata_in_tx_width"; + editable = "0"; + title = "avalon_readdata_in_tx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_readdata_in_tx[((data_width_g - 1)) - (0) + 1]
direction: input
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_readdata_in_tx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_tx/Data_Width = 2 ^ int(log2($PORT_avalon_readdata_in_tx/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_readdata_in_tx/width = "$"; + } + warning = "{{ if($PORT_avalon_readdata_in_tx/width <= 0)('width of avalon_readdata_in_tx must be greater than zero' ) }}"; + } + EDIT avalon_addr_out_rx_width + { + id = "avalon_addr_out_rx_width"; + editable = "0"; + title = "avalon_addr_out_rx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_addr_out_rx[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_addr_out_rx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_rx/Address_Width = $PORT_avalon_addr_out_rx/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_addr_out_rx/width = "$"; + } + warning = "{{ if($PORT_avalon_addr_out_rx/width <= 0)('width of avalon_addr_out_rx must be greater than zero' ) }}"; + } + EDIT avalon_writedata_out_rx_width + { + id = "avalon_writedata_out_rx_width"; + editable = "0"; + title = "avalon_writedata_out_rx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_writedata_out_rx[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_writedata_out_rx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_rx/Data_Width = 2 ^ int(log2($PORT_avalon_writedata_out_rx/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_writedata_out_rx/width = "$"; + } + warning = "{{ if($PORT_avalon_writedata_out_rx/width <= 0)('width of avalon_writedata_out_rx must be greater than zero' ) }}"; + } + } + } + } + } + } + CB_GENERATOR + { + top_module_name = "n2h2_chan.vhd:n2h2"; + emit_system_h = "1"; + HDL_FILES + { + FILE + { + filepath = "hdl/n2h2_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/n2h2_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/n2h2_rx_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/n2h2_tx.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/one_hot_mux.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "5.00"; + COMPONENT_BUILDER + { + CACHED_HDL_INFO + { + # cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:123 + # used only by Component Builder + FILE n2h2_chan.vhd + { + file_mod = "Tue Jun 28 13:19:44 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:04 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:09 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2 + { + CLASS n2h2 + { + MODULE_DEFAULTS + { + class = "n2h2"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk_cfg + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT clk_tx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT clk_rx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out_rx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_we_out_rx + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_writedata_out_rx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in_rx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_addr_in + { + width = "-1"; + width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_writedata_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + } + PORT avalon_cfg_we_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_readdata_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + } + PORT avalon_cfg_re_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_cs_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out_tx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_re_out_tx + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdata_in_tx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in_tx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdatavalid_in_tx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_empty_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_in + { + width = "3"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_re_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_full_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_we_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT rx_irq_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "irq"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "16"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_g + { + parameter_name = "n_chans_g"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_bits_g + { + parameter_name = "n_chans_bits_g"; + type = "integer"; + default_value = "3"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_lo_g + { + parameter_name = "hibi_addr_cmp_lo_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_hi_g + { + parameter_name = "hibi_addr_cmp_hi_g"; + type = "integer"; + default_value = "27"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE n2h2_ind_chan.vhd + { + file_mod = "Tue Jun 28 10:08:05 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:10 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:15 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2_ind_chan + { + CLASS n2h2_ind_chan + { + MODULE_DEFAULTS + { + class = "n2h2_ind_chan"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_empty_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT init_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_addr_rx_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_start_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_status_done_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_hibi_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_ram_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_amount_out + { + width = "-1"; + width_expression = "((amount_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_reserve_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2_ind_chan"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2_ind_chan"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER addr_cmp_lo_g + { + parameter_name = "addr_cmp_lo_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER addr_cmp_hi_g + { + parameter_name = "addr_cmp_hi_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER tx_hibi_addr_g + { + parameter_name = "Tx_HIBI_addr_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE n2h2_rx_ind_chan.vhd + { + file_mod = "Tue Jun 28 11:37:13 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:15 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:19 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2_rx_channels + { + CLASS n2h2_rx_channels + { + MODULE_DEFAULTS + { + class = "n2h2_rx_channels"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_we_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_writedata_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_empty_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_in + { + width = "3"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_re_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_addr_in + { + width = "-1"; + width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_writedata_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + } + PORT avalon_cfg_we_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_readdata_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + } + PORT avalon_cfg_re_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_cs_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT rx_irq_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "irq"; + is_shared = "0"; + } + PORT tx_start_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_mem_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_hibi_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_amount_out + { + width = "-1"; + width_expression = "((amount_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_status_done_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2_rx_channels"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2_rx_channels"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_rx_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER n_chans_g + { + parameter_name = "n_chans_g"; + type = "integer"; + default_value = "3"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_bits_g + { + parameter_name = "n_chans_bits_g"; + type = "integer"; + default_value = "2"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_hi_g + { + parameter_name = "hibi_addr_cmp_hi_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_lo_g + { + parameter_name = "hibi_addr_cmp_lo_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE n2h2_tx.vhd + { + file_mod = "Wed Jun 29 08:28:14 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:19 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:24 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2_tx + { + CLASS n2h2_tx + { + MODULE_DEFAULTS + { + class = "n2h2_tx"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_re_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdata_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdatavalid_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_full_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_we_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_start_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_status_done_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_comm_in + { + width = "3"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_hibi_addr_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_ram_addr_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_amount_in + { + width = "-1"; + width_expression = "((amount_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2_tx"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2_tx"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_tx.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "2"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE one_hot_mux.vhd + { + file_mod = "Thu Jun 16 12:36:51 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:24 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:28 EEST 2005"; + #found 1 valid modules + WRAPPER one_hot_mux + { + CLASS one_hot_mux + { + MODULE_DEFAULTS + { + class = "one_hot_mux"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT sel_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT data_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "one_hot_mux"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "one_hot_mux"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/one_hot_mux.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + } + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "16"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_g + { + parameter_name = "n_chans_g"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_bits_g + { + parameter_name = "n_chans_bits_g"; + type = "integer"; + default_value = "3"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_lo_g + { + parameter_name = "hibi_addr_cmp_lo_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_hi_g + { + parameter_name = "hibi_addr_cmp_hi_g"; + type = "integer"; + default_value = "27"; + editable = "1"; + tooltip = ""; + } + } + SW_FILES + { + } + built_on = "2005.06.29.10:05:33"; + } + ASSOCIATED_FILES + { + Add_Program = "the_wizard_ui"; + Edit_Program = "the_wizard_ui"; + Generator_Program = "cb_generator.pl"; + } +} Index: TUT/ip.hwp.communication/n2h2/.sopc_builder/install.ptf =================================================================== --- TUT/ip.hwp.communication/n2h2/.sopc_builder/install.ptf (nonexistent) +++ TUT/ip.hwp.communication/n2h2/.sopc_builder/install.ptf (revision 16) @@ -0,0 +1,25 @@ +PACKAGE install +{ + version = "4.01:213"; + COMPONENT vga_lcd_latency + { + VERSION 2.0 + { + local = "D:/svn/tutwlan/trunk/hardware_lib/Platform_vhdl_lib/Vga_controller"; + } + } + COMPONENT n2h2_ver02 + { + VERSION 0.2 + { + local = "D:/svn/koski/trunk/lib/hw_lib/ips/adapters/n2h2/Sopc_64b"; + } + } + COMPONENT n2h2_str + { + VERSION 0.1 + { + local = "D:/svn/koski/trunk/lib/hw_lib/ips/adapters/n2h2/Sopc_component"; + } + } +} Index: TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.c =================================================================== --- TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.c (nonexistent) +++ TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.c (revision 16) @@ -0,0 +1,179 @@ +#include "tut_n2h_regs.h" +#include "N2H_registers_and_macros.h" + + +#if defined(API) +struct Channel_reservation { + + int mem_addr; + int amount; + +}; + +static struct Channel_reservation + channel_reservations[N2H_NUMBER_OF_CHANNELS] = {}; + + +// Common interrupt service routine. Clear IRQ and call N2H_RX_DONE. +void isr() { + + int chan = N2H_GET_IRQ_CHAN(N2H_REGISTERS_BASE_ADDRESS); + N2H_RX_DONE( chan, channel_reservations[chan].mem_addr, channel_reservations[chan].amount ); + channel_reservations[chan].mem_addr = 0; + channel_reservations[chan].amount = 0; + N2H_RX_CLEAR_IRQ(chan,N2H_REGISTERS_BASE_ADDRESS); +} + + + +// eCos specific interrupt handling +#if defined(ECOS) +#include
+#include
+#include
+
+static cyg_interrupt l_rxIrq;
+static cyg_handle_t l_rxIrqHandle;
+extern void cyg_interrupt_post_dsr(CYG_ADDRWORD intr_handle);
+
+cyg_uint32 RxIrqIsr(cyg_vector_t vector, cyg_addrword_t data) {
+ cyg_interrupt_mask(vector);
+ cyg_interrupt_post_dsr(l_rxIrqHandle);
+ return (CYG_ISR_HANDLED);
+}
+
+void RxIrqDsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
+ isr();
+ cyg_interrupt_unmask(vector);
+
+}
+
+
+// NIOSII specific interrupt handling
+#else
+void n2h_isr( void* context, int id ) {
+ isr();
+}
+#endif
+
+void N2H_INIT_ISR() {
+
+// eCos specific interrupt init
+#if defined(ECOS)
+ cyg_interrupt_create(
+ N2H_RX_IRQ,
+ N2H_RX_IRQ_PRI,
+ 0,
+ &RxIrqIsr,
+ &RxIrqDsr,
+ &l_rxIrqHandle,
+ &l_rxIrq);
+ cyg_interrupt_attach(l_rxIrqHandle);
+ cyg_interrupt_unmask(N2H_RX_IRQ);
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+
+// NIOSII specific interrupt init
+#else
+ alt_irq_register( N2H_RX_IRQ, 0, n2h_isr );
+ N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
+#endif
+}
+
+void N2H_GET_RX_BUFFER( int* dst, int src, int amount ) {
+
+ // TODO: check that src is inside RX buffer
+ // TODO: if src and dst are same, do nothing
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *(dst + i) = *((int*)src + i);
+ }
+}
+
+void N2H_PUT_TX_BUFFER( int dst, int* src, int amount ) {
+
+ // TODO: check that dst is inside TX buffer
+ // TODO: if src and dst are same, do nothing
+
+ int i;
+ for( i = 0; i < amount; ++i ) {
+
+ *((int*)dst + i) = *(src + i);
+ }
+
+}
+#endif // API
+
+/*
+* DMA engine configuration functions (Updated on 27/04/2005)
+*/
+
+// Prepare channel for receiving data.
+void N2H_CHAN_CONF(int channel, int dst_mem_addr, int rx_haddr, int amount,
+ int* base)
+{
+#ifdef API
+ channel_reservations[channel].mem_addr = dst_mem_addr;
+ channel_reservations[channel].amount = amount;
+#endif
+ N2H_CHAN_MEM_ADDR(channel, dst_mem_addr, base);
+ N2H_CHAN_HIBI_ADDR(channel, rx_haddr, base);
+ N2H_CHAN_AMOUNT(channel, amount, base);
+ N2H_CHAN_INIT(channel, base);
+}
+
+void N2H_SEND(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE(base);
+ N2H_TX_START(base);
+}
+
+// Parameter types were uint32. Int works in other places, so why not here?
+void N2H_SEND_READ(int mem_addr, int amount, int haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(haddr, base);
+ N2H_TX_COMM_READ(base);
+ N2H_TX_START(base);
+}
+
+void N2H_SEND_MSG(int src_mem_addr, int amount, int dst_haddr, int* base) {
+ while( !N2H_TX_DONE(base) );
+ N2H_TX_MEM_ADDR(src_mem_addr, base);
+ N2H_TX_AMOUNT(amount, base);
+ N2H_TX_HIBI_ADDR(dst_haddr, base);
+ N2H_TX_COMM_WRITE_MSG(base);
+ N2H_TX_START(base);
+}
+
+// Return 0 if transmission is not done yet, 1 otherwise.
+int N2H_TX_DONE(int* base) {
+ int y = 0;
+ N2H_GET_TX_DONE(y, base);
+ return y;
+}
+
+void N2H_CLEAR_IRQ(int chan, int* base) {
+ N2H_RX_CLEAR_IRQ(chan, base);
+}
+
+// Returns first channel number which has IRQ flag up.
+// If no interrupts have been received -1 is returned.
+int N2H_GET_IRQ_CHAN(int* base)
+{
+ volatile int * apu = base + 7;
+ int irq_reg = *apu;
+ int mask = 1;
+ int shift = 0;
+ for (shift = 0; shift < 32; shift++) {
+ if ((irq_reg & (mask << shift)) != 0) {
+ return shift;
+ }
+ }
+ return -1;
+}
+
Index: TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.h (revision 16)
@@ -0,0 +1,209 @@
+/*
+* History:
+* 10/08/2005 by ollil
+* + Copied minor modifications implemented by Ari.
+* This fixed a crash bug in DCT HW based system
+* 03/10/2008 by tapiok
+* fixed N2H_RX_IRQ_DIS
+* 08/2009 kojo2
+* Added following functions: N2H_INIT_ISR, N2H_RX_DONE,
+* N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER
+*/
+#ifndef __tut_n2h_regs_h_
+#define __tut_n2h_regs_h_
+
+#ifdef NIOS_II
+#include "io.h"
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)
+#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)
+#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))
+#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 | (IORD(base,4))))
+#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))
+#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)
+#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)
+#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)
+#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)
+#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)
+#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)
+#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)
+#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)
+#define N2H_TX_COMM_READ(base) IOWR(base,10,4)
+#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)
+#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)
+#define N2H_TX_START(base) IOWR(base, 4, (0x1 | (IORD(base,4))))
+#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)
+#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))
+#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))
+
+
+#else
+
+#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 1; \
+ *apu=hibi_addr; \
+ }
+
+#define N2H_CHAN_MEM_ADDR(chan, addr, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4); \
+ *apu=addr; \
+ }
+
+#define N2H_CHAN_AMOUNT(chan, amount, base) \
+ { \
+ volatile int * apu = (int*)base; \
+ apu = apu + ((chan) << 4) + 2; \
+ *apu=amount; \
+ }
+
+#define N2H_CHAN_INIT(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ *apu=1 << (chan); \
+ }
+
+#define N2H_RX_IRQ_ENA(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu | 0x2; \
+ }
+
+#define N2H_RX_IRQ_DIS(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu= *apu & 0xfffffffd; \
+ }
+
+#define N2H_GET_STAT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu >> 16; \
+ }
+
+#define N2H_GET_CONF_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ var = *apu & 0x0000ffff; \
+ }
+
+#define N2H_GET_INIT_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 5; \
+ var = *apu; \
+ }
+
+#define N2H_GET_IRQ_REG(var, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ var = *apu; \
+ }
+
+#define N2H_GET_CURR_PTR(var, chan, base) \
+ { \
+ volatile int * apu = (int*)base + 3; \
+ apu = apu + ((chan) << 4); \
+ var = *apu; \
+ }
+
+#define N2H_TX_MEM_ADDR(addr, base) \
+ { \
+ volatile int * apu = (int*)base + 8; \
+ *apu = addr; \
+ }
+
+#define N2H_TX_AMOUNT(amount, base) \
+ { \
+ volatile int * apu = (int*)base + 9; \
+ *apu = amount; \
+ }
+
+#define N2H_TX_HIBI_ADDR(haddr, base) \
+ { \
+ volatile int * apu = (int*)base + 11; \
+ *apu = haddr; \
+ }
+
+#define N2H_TX_COMM(comm, base) \
+ { \
+ volatile int * apu = (int*)base +10; \
+ *apu = comm; \
+ }
+
+#define N2H_TX_COMM_WRITE(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 2; \
+ }
+
+#define N2H_TX_COMM_READ(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 4; \
+ }
+
+#define N2H_TX_COMM_WRITE_MSG(base) \
+ { \
+ volatile int * apu = (int*)base + 10; \
+ *apu = 3; \
+ }
+
+#define N2H_TX_START(base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ *apu = *apu | 0x1; \
+ *apu = *apu & 0xfffffffe; \
+ }
+#define N2H_GET_TX_DONE(y, base) \
+ { \
+ volatile int * apu = (int*)base + 4; \
+ y = *apu >> 16; \
+ y = y & 0x1; \
+ }
+
+#define N2H_RX_CLEAR_IRQ(chan, base) \
+ { \
+ volatile int * apu = (int*)base + 7; \
+ *apu = 1 << (chan); \
+ }
+
+
+
+#endif
+
+
+#ifdef API
+extern void N2H_INIT_ISR();
+extern void N2H_RX_DONE( int chan, int mem_addr, int amount );
+extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );
+extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );
+#endif
+
+
+/*
+* DMA engine configuration
+*/
+
+extern void N2H_CHAN_CONF( int channel,
+ int mem_addr,
+ int rx_addr,
+ int amount,
+ int* base );
+
+extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);
+
+extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);
+
+extern int N2H_TX_DONE(int* base);
+
+extern void N2H_CLEAR_IRQ(int chan, int* base);
+
+extern int N2H_GET_IRQ_CHAN(int* base);
+
+#endif
Index: TUT/ip.hwp.communication/n2h2/drv/N2H_registers_and_macros.h
===================================================================
--- TUT/ip.hwp.communication/n2h2/drv/N2H_registers_and_macros.h (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/drv/N2H_registers_and_macros.h (revision 16)
@@ -0,0 +1,47 @@
+// *****************************************************************************
+// File : N2H_registers_and_macros.h
+// Author : Tero Arpinen
+// Date : 22.12.2004
+// Decription : This file contains customizable register address
+// definitions
+// for N2H interface and some needed macros
+//
+// Version history : 22.12.2004 tar Original version
+// : 06.07.2005 tar Modified to work with N2H2
+// : 02.10.2009 tko Removed unneeded macros
+// *****************************************************************************
+
+#ifndef N2H_REGISTERS_AND_MACROS_H
+#define N2H_REGISTERS_AND_MACROS_H
+
+// DEFINE FOLLOWING REGISTERS ACCORDING TO NIOS OR NIOS II HARDWARE
+// CONFIGURATION
+
+// N2H2 Avalon slave base address
+#define N2H_REGISTERS_BASE_ADDRESS ((void*) 0x00140000)
+
+// Buffer start address in cpu's memory
+#define N2H_REGISTERS_BUFFER_START (0x00300000)
+
+// Writeable registers
+// set bit 31 to 1 so that writes and reads bypass cache
+#define N2H_REGISTERS_TX_BUFFER_START (0x80300000)
+//#define N2H_REGISTERS_TX_BUFFER_START (0x00300000)
+#define N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH (0x00000600)
+#define N2H_REGISTERS_TX_BUFFER_END (N2H_REGISTERS_TX_BUFFER_START + \
+ N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH - 1)
+
+// Readable registers
+#define N2H_REGISTERS_RX_BUFFER_START (N2H_REGISTERS_TX_BUFFER_START + N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH)
+#define N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH (0x00002200)
+#define N2H_REGISTERS_RX_BUFFER_END (N2H_REGISTERS_RX_BUFFER_START + \
+ N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH \
+ - 1)
+// N2H Interrupt registers, numbers and priorities
+#define N2H_RX_IRQ (2)
+#define N2H_RX_IRQ_PRI (3)
+
+// N2H Channels
+#define N2H_NUMBER_OF_CHANNELS (8)
+
+#endif // N2H_REGISTERS_AND_MACROS_H
Index: TUT/ip.hwp.communication/n2h2/readme.txt
===================================================================
--- TUT/ip.hwp.communication/n2h2/readme.txt (nonexistent)
+++ TUT/ip.hwp.communication/n2h2/readme.txt (revision 16)
@@ -0,0 +1,50 @@
+-------------------------------------------------------------
+This is readme for compoenent Nios-to-HIBI-version2 aka. N2H2
+-------------------------------------------------------------
+
+Purpose : N2H2 connects Nios II CPU to HIBI network and acts as s DMA controller.
+
+
+
+Main idea:
+ N2H2 can copy data from Nios's local memory to HIBI.
+ N2H2 can copy data to Nios's local memory from HIBI.
+
+ SW running on Nios controls N2H2 via a couple of memory-mapped registers.
+ Each transfers needs at least 3 parameters:
+ 1. address in local memory
+ 2. address in HIBI
+ 3. number or transferred words
+
+Directory structure:
+
+ doc/ Brief documentation
+ drv/ SW driver functions
+ kci.xml Component description for Kactus integrator tool
+ readme.txt This file
+ Sopc_64b/ Files for using this in Altera's SOPC builder integrator tool
+ Sopc_component/ Files for using this in Altera's SOPC builder integrator tool
+ tb/ Testbenches for VHDL description
+ vhd/ RTL source codes
+
+
+
+History:
+ Original design by Ari Kulmala, 2005
+
+ Directory "sopc_component" copied from svn\hibi\trunk\Hibi\IP\Adapters\N2H2\V2\Sopc_component. Modifications in inc-subdirectory (bug fix), class.ptf and n2h2_chan.vhd (default for hibi_addr_cmp_lo_g changed).
+
+ Files of directory .\Sopc_component\hdl copied from svn\hibi\trunk\Hibi\IP\Adapters\N2H2\V2\Sopc_component\hdl, but only those files that are referenced in class.ptf. The SOPC component is probably out of sync with real VHDL-files, but...
+
+ Directory "vhd" copied from svn\hibi\trunk\Hibi\IP\Adapters\N2H2\V2\Ver_02
+
+
+ Modified by Lasse Lehtonen, 2011:
+
+ Added ability to receive packets that haven't been configured
+ before the packet arrives. Also added interrupt to detect lost
+ tx packets (may happen when sending "second" packet too soon
+ without polling for the completeon of the previous packet).
+
+ Those Sopc_* directories are probably useless - use the TCL
+ file in vhd/ to add the component to SOPC.
direction: input
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_cfg_addr_in/width = (int(((( ( $H/n_chans_bits_g ) + 4) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_slave_0/Address_Width = $PORT_avalon_cfg_addr_in/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_cfg_addr_in/width = "$"; + } + warning = "{{ if($PORT_avalon_cfg_addr_in/width <= 0)('width of avalon_cfg_addr_in must be greater than zero' ) }}"; + } + EDIT avalon_cfg_writedata_in_width + { + id = "avalon_cfg_writedata_in_width"; + editable = "0"; + title = "avalon_cfg_writedata_in[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_cfg_writedata_in[((data_width_g - 1)) - (0) + 1]
direction: input
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_cfg_writedata_in/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_slave_0/Data_Width = 2 ^ int(log2($PORT_avalon_cfg_writedata_in/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_cfg_writedata_in/width = "$"; + } + warning = "{{ if($PORT_avalon_cfg_writedata_in/width <= 0)('width of avalon_cfg_writedata_in must be greater than zero' ) }}"; + } + EDIT avalon_cfg_readdata_out_width + { + id = "avalon_cfg_readdata_out_width"; + editable = "0"; + title = "avalon_cfg_readdata_out[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_cfg_readdata_out[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_cfg_readdata_out/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_slave_0/Data_Width = 2 ^ int(log2($PORT_avalon_cfg_readdata_out/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_cfg_readdata_out/width = "$"; + } + warning = "{{ if($PORT_avalon_cfg_readdata_out/width <= 0)('width of avalon_cfg_readdata_out must be greater than zero' ) }}"; + } + EDIT hibi_data_in_width + { + id = "hibi_data_in_width"; + editable = "0"; + title = "hibi_data_in[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "hibi_data_in[((data_width_g - 1)) - (0) + 1]
direction: input
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_hibi_data_in/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_hibi_data_in/width = "$"; + } + warning = "{{ if($PORT_hibi_data_in/width <= 0)('width of hibi_data_in must be greater than zero' ) }}"; + } + EDIT hibi_data_out_width + { + id = "hibi_data_out_width"; + editable = "0"; + title = "hibi_data_out[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "hibi_data_out[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: export"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_hibi_data_out/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_hibi_data_out/width = "$"; + } + warning = "{{ if($PORT_hibi_data_out/width <= 0)('width of hibi_data_out must be greater than zero' ) }}"; + } + EDIT avalon_addr_out_tx_width + { + id = "avalon_addr_out_tx_width"; + editable = "0"; + title = "avalon_addr_out_tx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_addr_out_tx[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_addr_out_tx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_tx/Address_Width = $PORT_avalon_addr_out_tx/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_addr_out_tx/width = "$"; + } + warning = "{{ if($PORT_avalon_addr_out_tx/width <= 0)('width of avalon_addr_out_tx must be greater than zero' ) }}"; + } + EDIT avalon_readdata_in_tx_width + { + id = "avalon_readdata_in_tx_width"; + editable = "0"; + title = "avalon_readdata_in_tx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_readdata_in_tx[((data_width_g - 1)) - (0) + 1]
direction: input
signal type: readdata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_readdata_in_tx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_tx/Data_Width = 2 ^ int(log2($PORT_avalon_readdata_in_tx/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_readdata_in_tx/width = "$"; + } + warning = "{{ if($PORT_avalon_readdata_in_tx/width <= 0)('width of avalon_readdata_in_tx must be greater than zero' ) }}"; + } + EDIT avalon_addr_out_rx_width + { + id = "avalon_addr_out_rx_width"; + editable = "0"; + title = "avalon_addr_out_rx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_addr_out_rx[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: address"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_addr_out_rx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_rx/Address_Width = $PORT_avalon_addr_out_rx/width; }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_addr_out_rx/width = "$"; + } + warning = "{{ if($PORT_avalon_addr_out_rx/width <= 0)('width of avalon_addr_out_rx must be greater than zero' ) }}"; + } + EDIT avalon_writedata_out_rx_width + { + id = "avalon_writedata_out_rx_width"; + editable = "0"; + title = "avalon_writedata_out_rx[((data_width_g - 1)) - (0) + 1]:"; + tooltip = "avalon_writedata_out_rx[((data_width_g - 1)) - (0) + 1]
direction: output
signal type: writedata"; + # This expression should emulate the HDL, and assign the port width + dummy = "{{ $PORT_avalon_writedata_out_rx/width = (int((( ( $H/data_width_g ) - 1)) - (0) + 1-1) - int(0) + 1); }}"; + dummy_dummy = "{{ $SBI_avalon_master_rx/Data_Width = 2 ^ int(log2($PORT_avalon_writedata_out_rx/width - 1) + 1); }}"; + DATA + { + # The EDIT field is noneditable, so this just reads the current width. + $PORT_avalon_writedata_out_rx/width = "$"; + } + warning = "{{ if($PORT_avalon_writedata_out_rx/width <= 0)('width of avalon_writedata_out_rx must be greater than zero' ) }}"; + } + } + } + } + } + } + CB_GENERATOR + { + top_module_name = "n2h2_chan.vhd:n2h2"; + emit_system_h = "1"; + HDL_FILES + { + FILE + { + filepath = "hdl/n2h2_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/n2h2_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/n2h2_rx_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/n2h2_tx.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + FILE + { + filepath = "hdl/one_hot_mux.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "5.00"; + COMPONENT_BUILDER + { + CACHED_HDL_INFO + { + # cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:123 + # used only by Component Builder + FILE n2h2_chan.vhd + { + file_mod = "Tue Jun 28 13:19:44 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:04 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:09 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2 + { + CLASS n2h2 + { + MODULE_DEFAULTS + { + class = "n2h2"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk_cfg + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT clk_tx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT clk_rx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out_rx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_we_out_rx + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_writedata_out_rx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in_rx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_addr_in + { + width = "-1"; + width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_writedata_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + } + PORT avalon_cfg_we_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_readdata_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + } + PORT avalon_cfg_re_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_cs_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out_tx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_re_out_tx + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdata_in_tx + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in_tx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdatavalid_in_tx + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_empty_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_in + { + width = "3"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_re_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_full_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_we_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT rx_irq_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "irq"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "16"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_g + { + parameter_name = "n_chans_g"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_bits_g + { + parameter_name = "n_chans_bits_g"; + type = "integer"; + default_value = "3"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_lo_g + { + parameter_name = "hibi_addr_cmp_lo_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_hi_g + { + parameter_name = "hibi_addr_cmp_hi_g"; + type = "integer"; + default_value = "27"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE n2h2_ind_chan.vhd + { + file_mod = "Tue Jun 28 10:08:05 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:10 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:15 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2_ind_chan + { + CLASS n2h2_ind_chan + { + MODULE_DEFAULTS + { + class = "n2h2_ind_chan"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_empty_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT init_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_addr_rx_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_start_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_status_done_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_hibi_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_ram_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_amount_out + { + width = "-1"; + width_expression = "((amount_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_reserve_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2_ind_chan"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2_ind_chan"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER addr_cmp_lo_g + { + parameter_name = "addr_cmp_lo_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER addr_cmp_hi_g + { + parameter_name = "addr_cmp_hi_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER tx_hibi_addr_g + { + parameter_name = "Tx_HIBI_addr_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE n2h2_rx_ind_chan.vhd + { + file_mod = "Tue Jun 28 11:37:13 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:15 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:19 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2_rx_channels + { + CLASS n2h2_rx_channels + { + MODULE_DEFAULTS + { + class = "n2h2_rx_channels"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_we_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_writedata_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_empty_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_in + { + width = "3"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_re_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_addr_in + { + width = "-1"; + width_expression = "(((n_chans_bits_g + 4) - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_writedata_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "writedata"; + is_shared = "0"; + } + PORT avalon_cfg_we_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_readdata_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "readdata"; + is_shared = "0"; + } + PORT avalon_cfg_re_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_cfg_cs_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT rx_irq_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "irq"; + is_shared = "0"; + } + PORT tx_start_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_mem_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_hibi_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_amount_out + { + width = "-1"; + width_expression = "((amount_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_status_done_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2_rx_channels"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2_rx_channels"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_rx_ind_chan.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER n_chans_g + { + parameter_name = "n_chans_g"; + type = "integer"; + default_value = "3"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_bits_g + { + parameter_name = "n_chans_bits_g"; + type = "integer"; + default_value = "2"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_hi_g + { + parameter_name = "hibi_addr_cmp_hi_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_lo_g + { + parameter_name = "hibi_addr_cmp_lo_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE n2h2_tx.vhd + { + file_mod = "Wed Jun 29 08:28:14 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:19 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:24 EEST 2005"; + #found 1 valid modules + WRAPPER n2h2_tx + { + CLASS n2h2_tx + { + MODULE_DEFAULTS + { + class = "n2h2_tx"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT clk + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "clk"; + is_shared = "0"; + } + PORT rst_n + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_addr_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_re_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdata_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_waitrequest_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT avalon_readdatavalid_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_data_out + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_av_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_full_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT hibi_comm_out + { + width = "3"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT hibi_we_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_start_in + { + width = "1"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_status_done_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + PORT tx_comm_in + { + width = "3"; + width_expression = ""; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_hibi_addr_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_ram_addr_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT tx_amount_in + { + width = "-1"; + width_expression = "((amount_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "n2h2_tx"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "n2h2_tx"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/N2H2_ind_chans/n2h2_tx.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "2"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "1"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + FILE one_hot_mux.vhd + { + file_mod = "Thu Jun 16 12:36:51 EEST 2005"; + quartus_map_start = "Wed Jun 29 10:01:24 EEST 2005"; + quartus_map_finished = "Wed Jun 29 10:01:28 EEST 2005"; + #found 1 valid modules + WRAPPER one_hot_mux + { + CLASS one_hot_mux + { + MODULE_DEFAULTS + { + class = "one_hot_mux"; + class_version = "1.0"; + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + } + SLAVE avalon_slave_0 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + } + PORT_WIRING + { + PORT data_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT sel_in + { + width = "-1"; + width_expression = "((data_width_g - 1)) - (0) + 1"; + direction = "input"; + type = "export"; + is_shared = "0"; + } + PORT data_out + { + width = "1"; + width_expression = ""; + direction = "output"; + type = "export"; + is_shared = "0"; + } + } + } + } + USER_INTERFACE + { + USER_LABELS + { + name = "one_hot_mux"; + technology = "imported components"; + } + } + CB_GENERATOR + { + top_module_name = "one_hot_mux"; + emit_system_h = "0"; + HDL_FILES + { + FILE + { + filepath = "D:/tyohakemisto/Vhdl/N2H2/Vhdl/one_hot_mux.vhd"; + use_in_simulation = "1"; + use_in_synthesis = "1"; + } + } + } + SOPC_Builder_Version = "0.0"; + COMPONENT_BUILDER + { + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + } + } + } + } + } + } + HDL_PARAMETERS + { + # generated by cbDocument.CBDocument.getParameterContainer:385 + # used only by Component Editor + HDL_PARAMETER data_width_g + { + parameter_name = "data_width_g"; + type = "integer"; + default_value = "32"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER amount_width_g + { + parameter_name = "amount_width_g"; + type = "integer"; + default_value = "16"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_g + { + parameter_name = "n_chans_g"; + type = "integer"; + default_value = "8"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER n_chans_bits_g + { + parameter_name = "n_chans_bits_g"; + type = "integer"; + default_value = "3"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_lo_g + { + parameter_name = "hibi_addr_cmp_lo_g"; + type = "integer"; + default_value = "0"; + editable = "1"; + tooltip = ""; + } + HDL_PARAMETER hibi_addr_cmp_hi_g + { + parameter_name = "hibi_addr_cmp_hi_g"; + type = "integer"; + default_value = "27"; + editable = "1"; + tooltip = ""; + } + } + SW_FILES + { + } + built_on = "2005.06.29.10:05:33"; + } + ASSOCIATED_FILES + { + Add_Program = "the_wizard_ui"; + Edit_Program = "the_wizard_ui"; + Generator_Program = "cb_generator.pl"; + } +} Index: TUT/ip.hwp.communication/n2h2/.sopc_builder/install.ptf =================================================================== --- TUT/ip.hwp.communication/n2h2/.sopc_builder/install.ptf (nonexistent) +++ TUT/ip.hwp.communication/n2h2/.sopc_builder/install.ptf (revision 16) @@ -0,0 +1,25 @@ +PACKAGE install +{ + version = "4.01:213"; + COMPONENT vga_lcd_latency + { + VERSION 2.0 + { + local = "D:/svn/tutwlan/trunk/hardware_lib/Platform_vhdl_lib/Vga_controller"; + } + } + COMPONENT n2h2_ver02 + { + VERSION 0.2 + { + local = "D:/svn/koski/trunk/lib/hw_lib/ips/adapters/n2h2/Sopc_64b"; + } + } + COMPONENT n2h2_str + { + VERSION 0.1 + { + local = "D:/svn/koski/trunk/lib/hw_lib/ips/adapters/n2h2/Sopc_component"; + } + } +} Index: TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.c =================================================================== --- TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.c (nonexistent) +++ TUT/ip.hwp.communication/n2h2/drv/tut_n2h_regs.c (revision 16) @@ -0,0 +1,179 @@ +#include "tut_n2h_regs.h" +#include "N2H_registers_and_macros.h" + + +#if defined(API) +struct Channel_reservation { + + int mem_addr; + int amount; + +}; + +static struct Channel_reservation + channel_reservations[N2H_NUMBER_OF_CHANNELS] = {}; + + +// Common interrupt service routine. Clear IRQ and call N2H_RX_DONE. +void isr() { + + int chan = N2H_GET_IRQ_CHAN(N2H_REGISTERS_BASE_ADDRESS); + N2H_RX_DONE( chan, channel_reservations[chan].mem_addr, channel_reservations[chan].amount ); + channel_reservations[chan].mem_addr = 0; + channel_reservations[chan].amount = 0; + N2H_RX_CLEAR_IRQ(chan,N2H_REGISTERS_BASE_ADDRESS); +} + + + +// eCos specific interrupt handling +#if defined(ECOS) +#include