URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
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- This comparison shows the changes necessary to convert path
/funbase_ip_library/trunk
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/TUT/ip.hwp.accelerator/port_blinker/1.0/port_blinker.1.0.xml
0,0 → 1,216
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 10:48:51 pe loka 21 2011--> |
<spirit:component> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.accelerator</spirit:library> |
<spirit:name>port_blinker</spirit:name> |
<spirit:version>1.0</spirit:version> |
<spirit:busInterfaces> |
<spirit:busInterface> |
<spirit:name>clk</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>clk</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>port_out</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="toggle_in" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="toggle_in.absDef" spirit:version="1.0"/> |
<spirit:master/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TOGGLE_TO_SIG_GEN</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>port_out</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>rst_n</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RESETn</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rst_n</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>signal_gen_if</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="sig_gen" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="sig_gen.absDef" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ENABLE_FROM_GEN</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>ena_in</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>SIGNAL_FROM_GEN</spirit:name> |
<spirit:vector> |
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>val_in</spirit:name> |
<spirit:vector> |
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:model> |
<spirit:ports> |
<spirit:port> |
<spirit:name>clk</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>ena_in</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>port_out</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>out</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>rst_n</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>val_in</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |
<spirit:modelParameters> |
<spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped"> |
<spirit:name>SIGNAL_WIDTH</spirit:name> |
<spirit:value>32</spirit:value> |
</spirit:modelParameter> |
</spirit:modelParameters> |
</spirit:model> |
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>hdlSources</spirit:name> |
<spirit:file> |
<spirit:name>src/port_blinker.vhd</spirit:name> |
<spirit:fileType>vhdlSource</spirit:fileType> |
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile> |
<spirit:buildCommand> |
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags> |
</spirit:buildCommand> |
</spirit:file> |
</spirit:fileSet> |
</spirit:fileSets> |
<spirit:vendorExtensions> |
<kactus2:extensions> |
<kactus2:kts_attributes> |
<kactus2:kts_productHier>IP</kactus2:kts_productHier> |
<kactus2:kts_implementation>HW</kactus2:kts_implementation> |
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness> |
</kactus2:kts_attributes> |
</kactus2:extensions> |
</spirit:vendorExtensions> |
</spirit:component> |
/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd
0,0 → 1,99
------------------------------------------------------------------------------- |
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
------------------------------------------------------------------------------- |
-- Title : Port blinker |
-- Project : Funbase |
------------------------------------------------------------------------------- |
-- File : port_blinker.vhd |
-- Author : Juha Arvio |
-- Company : TUT |
-- Last update: 20.10.2011 |
-- Version : 0.1 |
-- Platform : |
------------------------------------------------------------------------------- |
-- Description: |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 20.10.2011 0.1 arvio Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity port_blinker is |
generic ( SIGNAL_WIDTH : integer := 32 ); |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
|
ena_in : in std_logic; |
val_in : in std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
port_out : out std_logic ); |
|
end port_blinker; |
|
architecture rtl of port_blinker is |
function i2s(value : integer; width : integer) return std_logic_vector is |
begin |
return conv_std_logic_vector(value, width); |
end; |
|
function s2i(value : std_logic_vector) return integer is |
begin |
return conv_integer(value); |
end; |
|
signal port_level_r : std_logic; |
signal val_cnt_r : std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
begin |
|
port_out <= port_level_r; |
|
process (clk, rst_n) |
begin |
if (rst_n = '0') then |
port_level_r <= '0'; |
val_cnt_r <= (others => '0'); |
|
elsif (clk'event and clk = '1') then |
|
if (ena_in = '0') then |
val_cnt_r <= (others => '0'); |
else |
if (val_cnt_r = val_in) then |
port_level_r <= not(port_level_r); |
val_cnt_r <= (others => '0'); |
else |
val_cnt_r <= val_cnt_r + 1; |
end if; |
end if; |
|
end if; |
end process; |
|
end rtl; |
/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd.bak
0,0 → 1,94
------------------------------------------------------------------------------- |
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
------------------------------------------------------------------------------- |
-- Title : Signal generator |
-- Project : Funbase |
------------------------------------------------------------------------------- |
-- File : sig_gen.vhd |
-- Author : Juha Arvio |
-- Company : TUT |
-- Last update: 20.10.2011 |
-- Version : 0.1 |
-- Platform : |
------------------------------------------------------------------------------- |
-- Description: |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 20.10.2011 0.1 arvio Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity sig_gen is |
generic ( SIGNAL_VAL : integer := 100000000; |
SIGNAL_WIDTH : integer := 32 ); |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
|
toggle_in : in std_logic; |
sig_out : out std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
ena_out : out std_logic ); |
|
end sig_gen; |
|
architecture rtl of sig_gen is |
function i2s(value : integer; width : integer) return std_logic_vector is |
begin |
return conv_std_logic_vector(value, width); |
end; |
|
function s2i(value : std_logic_vector) return integer is |
begin |
return conv_integer(value); |
end; |
|
signal toggle_d1_r : std_logic; |
signal toggle_r : std_logic; |
begin |
|
sig_out <= i2s(SIGNAL_VAL, SIGNAL_WIDTH); |
ena_out <= toggle_r; |
|
process (clk, rst_n) |
begin |
if (rst_n = '0') then |
toggle_d1_r <= '0'; |
toggle_r <= '0'; |
|
elsif (clk'event and clk = '1') then |
toggle_d1_r <= toggle_in; |
|
if ((toggle_in = '1') and (toggle_d1_r = '0') then |
toggle_r <= not(toggle_r); |
end if; |
end if; |
end process; |
|
end rtl; |
/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd
0,0 → 1,94
------------------------------------------------------------------------------- |
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems |
-- |
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
-- |
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
-- |
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml |
------------------------------------------------------------------------------- |
-- Title : Signal generator |
-- Project : Funbase |
------------------------------------------------------------------------------- |
-- File : sig_gen.vhd |
-- Author : Juha Arvio |
-- Company : TUT |
-- Last update: 20.10.2011 |
-- Version : 0.1 |
-- Platform : |
------------------------------------------------------------------------------- |
-- Description: |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 20.10.2011 0.1 arvio Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity sig_gen is |
generic ( SIGNAL_VAL : integer := 100000000; |
SIGNAL_WIDTH : integer := 32 ); |
|
port ( |
clk : in std_logic; |
rst_n : in std_logic; |
|
toggle_in : in std_logic; |
sig_out : out std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
ena_out : out std_logic ); |
|
end sig_gen; |
|
architecture rtl of sig_gen is |
function i2s(value : integer; width : integer) return std_logic_vector is |
begin |
return conv_std_logic_vector(value, width); |
end; |
|
function s2i(value : std_logic_vector) return integer is |
begin |
return conv_integer(value); |
end; |
|
signal toggle_d1_r : std_logic; |
signal toggle_r : std_logic; |
begin |
|
sig_out <= i2s(SIGNAL_VAL, SIGNAL_WIDTH); |
ena_out <= toggle_r; |
|
process (clk, rst_n) |
begin |
if (rst_n = '0') then |
toggle_d1_r <= '0'; |
toggle_r <= '0'; |
|
elsif (clk'event and clk = '1') then |
toggle_d1_r <= toggle_in; |
|
if ((toggle_in = '1') and (toggle_d1_r = '0')) then |
toggle_r <= not(toggle_r); |
end if; |
end if; |
end process; |
|
end rtl; |
/TUT/ip.hwp.accelerator/sig_gen/1.0/sig_gen.1.0.xml
0,0 → 1,220
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 15:26:11 pe loka 21 2011--> |
<spirit:component> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.accelerator</spirit:library> |
<spirit:name>sig_gen</spirit:name> |
<spirit:version>1.0</spirit:version> |
<spirit:busInterfaces> |
<spirit:busInterface> |
<spirit:name>clk</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>CLK</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>clk</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>rst_n</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>RESETn</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>rst_n</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>signal_gen_if</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="sig_gen" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="sig_gen.absDef" spirit:version="1.0"/> |
<spirit:master/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>ENABLE_FROM_GEN</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>ena_out</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>SIGNAL_FROM_GEN</spirit:name> |
<spirit:vector> |
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>sig_out</spirit:name> |
<spirit:vector> |
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
<spirit:busInterface> |
<spirit:name>toggle_in</spirit:name> |
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="toggle_in" spirit:version="1.0"/> |
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="toggle_in.absDef" spirit:version="1.0"/> |
<spirit:slave/> |
<spirit:connectionRequired>false</spirit:connectionRequired> |
<spirit:portMaps> |
<spirit:portMap> |
<spirit:logicalPort> |
<spirit:name>TOGGLE_TO_SIG_GEN</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:logicalPort> |
<spirit:physicalPort> |
<spirit:name>toggle_in</spirit:name> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:physicalPort> |
</spirit:portMap> |
</spirit:portMaps> |
<spirit:bitsInLau>8</spirit:bitsInLau> |
<spirit:endianness>little</spirit:endianness> |
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:model> |
<spirit:ports> |
<spirit:port> |
<spirit:name>clk</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>ena_out</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>out</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>rst_n</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>sig_out</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>out</spirit:direction> |
<spirit:vector> |
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
<spirit:name>toggle_in</spirit:name> |
<spirit:wire spirit:allLogicalDirectionsAllowed="false"> |
<spirit:direction>in</spirit:direction> |
<spirit:vector> |
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |
<spirit:modelParameters> |
<spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped"> |
<spirit:name>SIGNAL_VAL</spirit:name> |
<spirit:value>100000000</spirit:value> |
</spirit:modelParameter> |
<spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped"> |
<spirit:name>SIGNAL_WIDTH</spirit:name> |
<spirit:value>32</spirit:value> |
</spirit:modelParameter> |
</spirit:modelParameters> |
</spirit:model> |
<spirit:fileSets> |
<spirit:fileSet> |
<spirit:name>hdlSources</spirit:name> |
<spirit:file> |
<spirit:name>src/sig_gen.vhd</spirit:name> |
<spirit:fileType>vhdlSource</spirit:fileType> |
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile> |
<spirit:buildCommand> |
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags> |
</spirit:buildCommand> |
</spirit:file> |
</spirit:fileSet> |
</spirit:fileSets> |
<spirit:vendorExtensions> |
<kactus2:extensions> |
<kactus2:kts_attributes> |
<kactus2:kts_productHier>IP</kactus2:kts_productHier> |
<kactus2:kts_implementation>HW</kactus2:kts_implementation> |
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness> |
</kactus2:kts_attributes> |
</kactus2:extensions> |
</spirit:vendorExtensions> |
</spirit:component> |