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/TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.hierarchical.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.hierarchical.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.hierarchical.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.hierarchical.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.hierarchical.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.pc_board.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.pc_board.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.pc_board.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.pc_board.1.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.pc_board.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.arria_ii.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.arria_ii.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.arria_ii.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.arria_ii.1.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.arria_ii.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png (revision 24)

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This document was generated by Kactus2 on 07.11.2011 13:55:21 by user matilail

+

+ Table of contents
+ 1. Component TUT - product - pc_arria_ii_gx - 1.0
+    1.1. Kactus2 attributes
+    1.2. Views
+ 2. Component TUT - board - arria_ii_board - 1.0
+    2.1. Kactus2 attributes
+    2.2. Ports
+    2.3. Bus interfaces
+    2.4. Views
+ 3. Component TUT - chip - ddr2_memory - 1.0
+    3.1. Kactus2 attributes
+    3.2. Bus interfaces
+    3.3. Views
+ 4. Component TUT - chip - arria_ii - 1.0
+    4.1. Kactus2 attributes
+    4.2. Ports
+    4.3. Bus interfaces
+    4.4. Views
+ 5. Component TUT - soc - arria_ii_gx_demo_soc - 1.0
+    5.1. Kactus2 attributes
+    5.2. Ports
+    5.3. Bus interfaces
+    5.4. Views
+ 6. Component TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0
+    6.1. Model parameters
+    6.2. Kactus2 attributes
+    6.3. Ports
+    6.4. Bus interfaces
+    6.5. File sets
+    6.6. Views
+ 7. Component TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0
+    7.1. Kactus2 attributes
+    7.2. Ports
+    7.3. Bus interfaces
+    7.4. File sets
+    7.5. Views
+ 8. Component TUT - ip.hwp.storage - hibi_mem_dma - 2.0
+    8.1. Kactus2 attributes
+    8.2. Ports
+    8.3. Bus interfaces
+    8.4. File sets
+    8.5. Views
+ 9. Component TUT - ip.hwp.accelerator - picture_manip - 1.0
+    9.1. Kactus2 attributes
+    9.2. Ports
+    9.3. Bus interfaces
+    9.4. File sets
+    9.5. Views
+ 10. Component TUT - ip.hwp.communication - hibi_segment_small - 2.0
+    10.1. Kactus2 attributes
+    10.2. Ports
+    10.3. Bus interfaces
+    10.4. File sets
+    10.5. Views
+ 11. Component TUT - board - pc_board - 1.0
+    11.1. Kactus2 attributes
+    11.2. Bus interfaces
+    11.3. Views
+

+

1. Component TUT - product - pc_arria_ii_gx - 1.0

+

+
+ Description: Example Kactus2 product which includes Linux_PC and ArriaII_GX development board connected together with PCIe.
+ IP-Xact file: pc_arria_ii_gx.1.0.xml
+

+

1.1 Kactus2 attributes

+

+    Product hierarchy: Product
+    Component implementation: HW
+    Component firmness: Mutable
+

+

1.2 Views

+

1.2.1 View: hierachical

+

+
+    Type: hierarchical
+ Description: Hierarchical view for lower abstraction level (board).
+

+

1.2.1.1 Configuration TUT - product - pc_arria_ii_gx.designcfg - 1.0

+

+    IP-Xact file: pc_arria_ii_gx.designcfg.1.0.xml
+
+

+

1.2.1.2 Design TUT - product - pc_arria_ii_gx.design - 1.0

+

+    IP-Xact file: pc_arria_ii_gx.design.1.0.xml
+
+

+ + + + + + + + + + + + + + + + + + + + + +

Instance name	Component type	Configurable values	Active view	Description
ArriaII_GX_Board	TUT - board - arria_ii_board - 1.0	+	hierarchical
Linux_PC	TUT - board - pc_board - 1.0	+	flat

+

1.2.2 View: flat

+

+    Type: non-hierarchical
+ Description: Flat view for pc_arria_II_gx product.
+

2. Component TUT - board - arria_ii_board - 1.0

+

+
+ Description: Arria II GX development board.
+ IP-Xact file: arria_ii_board.1.0.xml
+

+

2.1 Kactus2 attributes

+

+    Product hierarchy: Board
+    Component implementation: HW
+    Component firmness: Mutable
+

+

2.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
pcie_4x_p_REF_CLK_FROM_PCIE	in	1	0	0
pcie_4x_p_RST_N_FROM_PCIE	in	1	0	0
pcie_4x_p_RX_FROM_PCIE	in	4	3	0
pcie_4x_p_TX_TO_PCIE	out	4	3	0

+

2.3 Bus interfaces

+

2.3.1 pcie_4x_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• pcie_4x_p_RST_N_FROM_PCIE
+
• pcie_4x_p_REF_CLK_FROM_PCIE
+
• pcie_4x_p_RX_FROM_PCIE
+
• pcie_4x_p_TX_TO_PCIE
+

+

2.4 Views

+

2.4.1 View: hierarchical

+

+
+    Type: hierarchical
+

+

2.4.1.1 Configuration TUT - board - arria_ii_board.designcfg - 1.0

+

+    IP-Xact file: arria_ii_board.designcfg.1.0.xml
+
+

+

2.4.1.2 Design TUT - board - arria_ii_board.design - 1.0

+

+    IP-Xact file: arria_ii_board.design.1.0.xml
+
+

+ + + + + + + + + + + + + + + + + + + + + +

Instance name	Component type	Configurable values	Active view	Description
ddr2_memory	TUT - chip - ddr2_memory - 1.0	+	flat
arria_ii_gx_chip	TUT - chip - arria_ii - 1.0	+	hierarchical

+

2.4.2 View: flat

+

+    Type: non-hierarchical
+

3. Component TUT - chip - ddr2_memory - 1.0

+

+
+ Description: Dummy DDR2 memory block.
+ IP-Xact file: ddr2_memory.1.0.xml
+

+

3.1 Kactus2 attributes

+

+    Product hierarchy: Chip
+    Component implementation: HW
+    Component firmness: Mutable
+

+

3.2 Bus interfaces

+

3.2.1 ddr2_p

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+

+

3.3 Views

+

3.3.1 View: flat

+

+    Type: non-hierarchical
+

4. Component TUT - chip - arria_ii - 1.0

+

+
+ Description: Arria II GX EP2AGX125EF35C4ES FPGA chip.
+ IP-Xact file: arria_ii.1.0.xml
+

+

4.1 Kactus2 attributes

+

+    Product hierarchy: Chip
+    Component implementation: HW
+    Component firmness: Mutable
+

+

4.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clkin_bot_p	in	1	0	0
ddr2_p_ADDR_TO_DDR2	out	16	15	0
ddr2_p_BA_TO_DDR2	out	3	2	0
ddr2_p_CAS_N_TO_DDR2	out	1	0	0
ddr2_p_CKE_TO_DDR2	out	1	0	0
ddr2_p_CLK_N_TO_AND_FROM_DDR2	inout	2	1	0
ddr2_p_CLK_TO_AND_FROM_DDR2	inout	2	1	0
ddr2_p_CS_N_TO_DDR2	out	1	0	0
ddr2_p_DQS_N_TO_AND_FROM_DDR2	inout	8	7	0
ddr2_p_DQS_TO_AND_FROM_DDR2	inout	8	7	0
ddr2_p_DQ_M_TO_DDR2	out	8	7	0
ddr2_p_DQ_TO_AND_FROM_DDR2	inout	64	63	0
ddr2_p_ODT_TO_DDR2	out	1	0	0
ddr2_p_RAS_N_TO_DDR2	out	1	0	0
ddr2_p_WE_N_TO_DDR2	out	1	0	0
pcie_4x_p_REF_CLK_FROM_PCIE	in	1	0	0
pcie_4x_p_RST_N_FROM_PCIE	in	2	1	0
pcie_4x_p_RX_FROM_PCIE	in	4	3	0
pcie_4x_p_TX_TO_PCIE	out	4	3	0
user_pb	in	1	0	0

+

4.3 Bus interfaces

+

4.3.1 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clkin_bot_p
+

+

4.3.2 ddr2_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• ddr2_p_ADDR_TO_DDR2
+
• ddr2_p_BA_TO_DDR2
+
• ddr2_p_CAS_N_TO_DDR2
+
• ddr2_p_CKE_TO_DDR2
+
• ddr2_p_CLK_N_TO_AND_FROM_DDR2
+
• ddr2_p_CLK_TO_AND_FROM_DDR2
+
• ddr2_p_CS_N_TO_DDR2
+
• ddr2_p_DQS_N_TO_AND_FROM_DDR2
+
• ddr2_p_DQS_TO_AND_FROM_DDR2
+
• ddr2_p_DQ_M_TO_DDR2
+
• ddr2_p_DQ_TO_AND_FROM_DDR2
+
• ddr2_p_ODT_TO_DDR2
+
• ddr2_p_RAS_N_TO_DDR2
+
• ddr2_p_WE_N_TO_DDR2
+

+

4.3.3 pcie_4x_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• pcie_4x_p_TX_TO_PCIE
+
• pcie_4x_p_RX_FROM_PCIE
+
• pcie_4x_p_REF_CLK_FROM_PCIE
+
• pcie_4x_p_RST_N_FROM_PCIE
+

+

4.3.4 push_button_0

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• user_pb
+

+

4.4 Views

+

4.4.1 View: hierarchical

+

+
+    Type: hierarchical
+

+

4.4.1.1 Configuration TUT - chip - arria_ii.designcfg - 1.0

+

+    IP-Xact file: arria_ii.designcfg.1.0.xml
+
+

+

4.4.1.2 Design TUT - chip - arria_ii.design - 1.0

+

+    IP-Xact file: arria_ii.design.1.0.xml
+
+

+ + + + + + + + + + + + + + +

Instance name	Component type	Configurable values	Active view	Description
arria_ii_gx_demo_soc_1	TUT - soc - arria_ii_gx_demo_soc - 1.0	+	structural

+

4.4.2 View: flat

+

+    Type: non-hierarchical
+

5. Component TUT - soc - arria_ii_gx_demo_soc - 1.0

+

+
+ IP-Xact file: arria_ii_gx_demo_soc.1.0.xml
+

+

5.1 Kactus2 attributes

+

+    Product hierarchy: SoC
+    Component implementation: HW
+    Component firmness: Mutable
+

+

5.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clkin_bot_p	in	1	0	0
ddr2_dimm_addr	out	16	15	0
ddr2_dimm_ba	out	3	2	0
ddr2_dimm_cas_n	out	1	0	0
ddr2_dimm_cke	out	1	0	0
ddr2_dimm_clk	inout	2	1	0
ddr2_dimm_clk_n	inout	2	1	0
ddr2_dimm_cs_n	out	1	0	0
ddr2_dimm_dm	out	8	7	0
ddr2_dimm_dq	inout	64	63	0
ddr2_dimm_dqs	inout	8	7	0
ddr2_dimm_dqs_n	inout	8	7	0
ddr2_dimm_odt	out	1	0	0
ddr2_dimm_ras_n	out	1	0	0
ddr2_dimm_we_n	out	1	0	0
pcie_refclk_p	in	1	0	0
pcie_rx_p	in	4	3	0
pcie_tx_p	out	4	3	0
rst_n_RESETn	in	1	0	0
user_pb	in	3	2	0

+

5.3 Bus interfaces

+

5.3.1 clk_in

+

+    Description: Clock input for demo design
+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clkin_bot_p
+

+

5.3.2 ddr2_p

+

+    Description: DDR2 interface to DDR2 memory
+    Interface mode: master
+    Ports used in this interface: +

+

+
• ddr2_dimm_addr
+
• ddr2_dimm_ba
+
• ddr2_dimm_cas_n
+
• ddr2_dimm_cke
+
• ddr2_dimm_clk_n
+
• ddr2_dimm_clk
+
• ddr2_dimm_cs_n
+
• ddr2_dimm_dqs_n
+
• ddr2_dimm_dqs
+
• ddr2_dimm_dm
+
• ddr2_dimm_dq
+
• ddr2_dimm_odt
+
• ddr2_dimm_ras_n
+
• ddr2_dimm_we_n
+

+

5.3.3 pcie_4x_p

+

+    Description: PCIe 4x interface
+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• pcie_tx_p
+
• pcie_rx_p
+
• pcie_refclk_p
+
• user_pb
+

+

5.3.4 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• user_pb
+

+

5.4 Views

+

5.4.1 View: structural

+

+
+    Type: hierarchical
+

+

5.4.1.1 Configuration TUT - soc - arria_ii_gx_demo_soc.designcfg - 1.0

+

+    IP-Xact file: arria_ii_gx_demo_soc.designcfg.1.0.xml
+
+

+

5.4.1.2 Design TUT - soc - arria_ii_gx_demo_soc.design - 1.0

+

+    IP-Xact file: arria_ii_gx_demo_soc.design.1.0.xml
+
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Instance name	Component type	Configurable values	Active view	Description
pcie_to_hibi_4x_1	TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0	+	rtl
a2_ddr2_dimm_1GB_1	TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0	+	rtl
hibi_mem_dma_1	TUT - ip.hwp.storage - hibi_mem_dma - 2.0	+	rtl
picture_manip_1	TUT - ip.hwp.accelerator - picture_manip - 1.0	+	rtl
hibi_segment_small_1	TUT - ip.hwp.communication - hibi_segment_small - 2.0	+	rtl

+

5.4.2 View: rtl

+

+    Type: non-hierarchical
+

6. Component TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0

+

+
+ Description: Adapter to connect HIBI based FPGA subsystem to PCIe bus.
+ IP-Xact file: pcie_to_hibi_4x.1.0.xml
+

+

6.1 Model parameters

+ + + + + + + + + + +

Name	Data type	Default value
HIBI_DATA_WIDTH	integer	32

+

6.2 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Parameterizable
+

+

6.3 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clk_in	in	1	0	0
hibi_av_in	in	1	0	0
hibi_av_out	out	1	0	0
hibi_comm_in	in	5	4	0
hibi_comm_out	out	5	4	0
hibi_data_in	in	32	31	0
hibi_data_out	out	32	31	0
hibi_empty_in	in	1	0	0
hibi_full_in	in	1	0	0
hibi_one_d_in	in	1	0	0
hibi_one_p_in	in	1	0	0
hibi_re_out	out	1	0	0
hibi_we_out	out	1	0	0
pcie_ref_clk	in	1	0	0
pcie_rst_n	in	1	0	0
pcie_rx	in	4	3	0
pcie_tx	out	4	3	0
rst_n	in	1	0	0

+

6.4 Bus interfaces

+

6.4.1 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk_in
+

+

6.4.2 hibi_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• hibi_av_out
+
• hibi_one_d_in
+
• hibi_data_in
+
• hibi_data_out
+
• hibi_av_in
+
• hibi_full_in
+
• hibi_comm_out
+
• hibi_we_out
+
• hibi_comm_in
+
• hibi_empty_in
+
• hibi_re_out
+
• hibi_one_p_in
+

+

6.4.3 pcie_4x_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• pcie_tx
+
• pcie_rx
+
• pcie_rst_n
+
• pcie_ref_clk
+

+

6.4.4 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

6.5 File sets

+

6.5.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
verilogSource	vlog	-quiet -work pcie_to_hibi_4x	false
vhdlSource	vcom	-quiet -check_synthesis -work pcie_to_hibi_4x	false

+

   6.5.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
pcie_to_hibi_4x.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_0.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_1.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_2.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_3.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_4.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_5.vhd	pcie_to_hibi_4x			vhdlSource
pcie.vhd	pcie_to_hibi_4x			vhdlSource
dma.vhd	pcie_to_hibi_4x			vhdlSource
pcie_core.vhd	pcie_to_hibi_4x			vhdlSource
pcie_serdes.vhd	pcie_to_hibi_4x			vhdlSource
a2h.v	pcie_to_hibi_4x			verilogSource
altpcie_64b_x4_pipen1b.v	pcie_to_hibi_4x			verilogSource
altpcie_hip_pipen1b.v	pcie_to_hibi_4x			verilogSource
altpcie_pclk_align.v	pcie_to_hibi_4x			verilogSource
altpcie_pclk_pll.v	pcie_to_hibi_4x			verilogSource
altpcie_phasefifo.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_100_125.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_100_250.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_125_250.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_15625_125.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_250_100.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy0.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy1_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy2.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy3_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy4_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy5_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_serdes_2agx_x4d_gen1_08p.v	pcie_to_hibi_4x			verilogSource
altpcie_serdes_2agx_x4d_gen1_16p.v	pcie_to_hibi_4x			verilogSource
pciexp64_dlink.v	pcie_to_hibi_4x			verilogSource
pciexp64_trans.v	pcie_to_hibi_4x			verilogSource
pciexp_dcram.v	pcie_to_hibi_4x			verilogSource
pciexpx8f_confctrl.v	pcie_to_hibi_4x			verilogSource
avalon_to_hibi.v	pcie_to_hibi_4x			verilogSource

+

6.5.2 Documentation

+

+    Description: pcie_to_hibi IP documentations.
+    Identifiers:
+

+

   6.5.2.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
PCI-E_to_hibi.docx				documentation	pcie_to_hibi IP block documentation in word document.
PCI-E_to_hibi.pptx				documentation	pcie_to_hibi IP block documentation in powerpoint presentation.

+

6.5.3 fpga_settings

+

+    Identifiers:
+

+

   6.5.3.1 Files

+ + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
pcie.sdc				quartusSDCFile	pcie_to_hibi timing and area constraints.

+

6.5.4 sopc_files

+

+    Identifiers:
+

+

   6.5.4.1 Files

+ + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
pcie_to_hibi_4x_sopc.sopc				quartusSOPCFILE	SOPC project file

+

6.6 Views

+

6.6.1 View: rtl

+

+    Type: non-hierarchical
+    File sets contained in this view: +

+

+
• hdlSources
+

+

7. Component TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0

+

+
+ Description: Altera ddr2 memory controller
+ IP-Xact file: alt_ddr2_a2.comp.1.0.xml
+

+

7.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Mutable
+

+

7.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
aux_full_rate_clk	out	1	0	0
aux_half_rate_clk	out	1	0	0
dll_reference_clk	out	1	0	0
dqs_delay_ctrl_export	out	6	5	0
global_reset_n	in	1	0	0
local_address	in	25	24	0
local_be	in	32	31	0
local_burstbegin	in	1	0	0
local_init_done	out	1	0	0
local_rdata	out	256	255	0
local_rdata_valid	out	1	0	0
local_read_req	in	1	0	0
local_ready	out	1	0	0
local_refresh_ack	out	1	0	0
local_size	in	3	2	0
local_wdata	in	256	255	0
local_write_req	in	1	0	0
mem_addr	out	14	13	0
mem_ba	out	3	2	0
mem_cas_n	out	1	0	0
mem_cke	out	1	0	0
mem_clk	inout	2	1	0
mem_clk_n	inout	2	1	0
mem_cs_n	out	1	0	0
mem_dm	out	8	7	0
mem_dq	inout	64	63	0
mem_dqs	inout	8	7	0
mem_dqsn	inout	8	7	0
mem_odt	out	1	0	0
mem_ras_n	out	1	0	0
mem_we_n	out	1	0	0
phy_clk	out	1	0	0
pll_ref_clk	in	1	0	0
reset_phy_clk_n	out	1	0	0
reset_request_n	out	1	0	0
soft_reset_n	in	1	0	0

+

7.3 Bus interfaces

+

7.3.1 alt_ddr2_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• local_init_done
+
• local_write_req
+
• local_read_req
+
• local_address
+
• local_ready
+
• local_rdata_valid
+
• local_wdata
+
• local_rdata
+
• local_be
+
• local_burstbegin
+
• local_size
+

+

7.3.2 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• pll_ref_clk
+

+

7.3.3 ddr2_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• mem_clk
+
• mem_clk_n
+
• mem_cke
+
• mem_cs_n
+
• mem_cas_n
+
• mem_ras_n
+
• mem_odt
+
• mem_we_n
+
• mem_ba
+
• mem_addr
+
• mem_dm
+
• mem_dqs
+
• mem_dqsn
+
• mem_dq
+

+

7.3.4 phy_clk_out

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• phy_clk
+

+

7.3.5 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• global_reset_n
+

+

7.3.6 soft_rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• soft_reset_n
+

+

7.4 File sets

+

7.4.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
verilogSource	vlog	-quiet -work alt_ddr2_a2	false
vhdlSource	vcom	-quiet -check_synthesis -work alt_ddr2_a2	false

+

   7.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
a2_ddr2_dimm_1GB.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_alt_ddrx_controller_wrapper.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_controller_phy.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_dq_dqs.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_pll.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_seq.vhd	alt_ddr2_a2			vhdlSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_seq_wrapper.v	alt_ddr2_a2		+incdir+D:/user/matilail/funbase/svn/release_2/lib/TUT/ip.hwp/stor.alt_ddr2_a2/1.0/hdl	verilogSource
alt_ddrx_addr_cmd.v	alt_ddr2_a2			verilogSource
alt_ddrx_afi_block.v	alt_ddr2_a2			verilogSource
alt_ddrx_avalon_if.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_timer.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_timer_info.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_timer_wrapper.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_tracking.v	alt_ddr2_a2			verilogSource
alt_ddrx_bypass.v	alt_ddr2_a2			verilogSource
alt_ddrx_cache.v	alt_ddr2_a2			verilogSource
alt_ddrx_clock_and_reset.v	alt_ddr2_a2			verilogSource
alt_ddrx_cmd_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_cmd_queue.v	alt_ddr2_a2			verilogSource
alt_ddrx_controller.v	alt_ddr2_a2			verilogSource
alt_ddrx_csr.v	alt_ddr2_a2			verilogSource
alt_ddrx_ddr2_odt_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_ddr3_odt_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_decoder.v	alt_ddr2_a2			verilogSource
alt_ddrx_decoder_40.v	alt_ddr2_a2			verilogSource
alt_ddrx_decoder_72.v	alt_ddr2_a2			verilogSource
alt_ddrx_ecc.v	alt_ddr2_a2			verilogSource
alt_ddrx_encoder.v	alt_ddr2_a2			verilogSource
alt_ddrx_encoder_40.v	alt_ddr2_a2			verilogSource
alt_ddrx_encoder_72.v	alt_ddr2_a2			verilogSource
alt_ddrx_input_if.v	alt_ddr2_a2			verilogSource
alt_ddrx_odt_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_rank_monitor.v	alt_ddr2_a2			verilogSource
alt_ddrx_state_machine.v	alt_ddr2_a2			verilogSource
alt_ddrx_timers.v	alt_ddr2_a2			verilogSource
alt_ddrx_timers_fsm.v	alt_ddr2_a2			verilogSource
alt_ddrx_timing_param.v	alt_ddr2_a2			verilogSource
alt_ddrx_wdata_fifo.v	alt_ddr2_a2			verilogSource
alt_mem_phy_defines.v	alt_ddr2_a2			verilogSource
altera_avalon_half_rate_bridge.v	alt_ddr2_a2			verilogSource

+

7.5 Views

+

7.5.1 View: rtl

+

+    Type: non-hierarchical
+

8. Component TUT - ip.hwp.storage - hibi_mem_dma - 2.0

+

+
+ Description: HIBI memory DMA access IP.
+ IP-Xact file: hibi_mem_dma.comp.xml
+

+

8.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Mutable
+

+

8.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clk	in	1	0	0
hibi_addr_in	in	32	31	0
hibi_addr_out	out	32	31	0
hibi_av_out	out	1	0	0
hibi_comm_in	in	3	2	0
hibi_comm_out	out	3	2	0
hibi_data_in	in	32	31	0
hibi_data_out	out	32	31	0
hibi_empty_in	in	1	0	0
hibi_full_in	in	1	0	0
hibi_msg_addr_out	out	32	31	0
hibi_msg_av_out	out	1	0	0
hibi_msg_comm_in	in	3	2	0
hibi_msg_comm_out	out	3	2	0
hibi_msg_data_in	in	32	31	0
hibi_msg_data_out	out	32	31	0
hibi_msg_empty_in	in	1	0	0
hibi_msg_full_in	in	1	0	0
hibi_msg_re_out	out	1	0	0
hibi_msg_we_out	out	1	0	0
hibi_re_out	out	1	0	0
hibi_we_out	out	1	0	0
mem_addr_out	out	25	24	0
mem_be_out	out	32	31	0
mem_burst_begin_out	out	1	0	0
mem_burst_size_out	out	3	2	0
mem_init_done_in	in	1	0	0
mem_rd_req_out	out	1	0	0
mem_rdata_in	in	256	255	0
mem_rdata_valid_in	in	1	0	0
mem_ready_in	in	1	0	0
mem_wdata_out	out	256	255	0
mem_wr_req_out	out	1	0	0
rst_n	in	1	0	0

+

8.3 Bus interfaces

+

8.3.1 alt_ddr2_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• mem_init_done_in
+
• mem_wr_req_out
+
• mem_rd_req_out
+
• mem_addr_out
+
• mem_ready_in
+
• mem_rdata_valid_in
+
• mem_wdata_out
+
• mem_rdata_in
+
• mem_be_out
+
• mem_burst_begin_out
+
• mem_burst_size_out
+

+

8.3.2 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk
+

+

8.3.3 hibi_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• hibi_addr_out
+
• hibi_data_in
+
• hibi_data_out
+
• hibi_full_in
+
• hibi_comm_out
+
• hibi_we_out
+
• hibi_comm_in
+
• hibi_empty_in
+
• hibi_re_out
+
• hibi_msg_addr_out
+
• hibi_msg_data_in
+
• hibi_msg_data_out
+
• hibi_msg_full_in
+
• hibi_msg_comm_out
+
• hibi_msg_we_out
+
• hibi_msg_comm_in
+
• hibi_msg_empty_in
+
• hibi_msg_re_out
+
• hibi_addr_in
+

+

8.3.4 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

8.4 File sets

+

8.4.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
vhdlSource	vcom	-quiet -check_synthesis -work hibi_mem_dma	false

+

   8.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
fifo_ram.vhd	hibi_mem_dma			vhdlSource
fifo_u.vhd	hibi_mem_dma			vhdlSource
dual_port_ram_u.vhd	hibi_mem_dma			vhdlSource
onchip_ram_u.vhd	hibi_mem_dma			vhdlSource
dual_ram_async_read.vhd	hibi_mem_dma			vhdlSource
hibi_mem_dma.vhd	hibi_mem_dma			vhdlSource

+

8.4.2 Documentation

+

+    Identifiers:
+

+

   8.4.2.1 Files

+ + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
HIBI_MEM_DMA.docx				documentation	hibi_mem_dma IP block datasheet.

+

8.5 Views

+

8.5.1 View: rtl

+

+    Type: non-hierarchical
+ Description: HIBI_MEM_DMA vhdl source view
+    File sets contained in this view: +

+

+
• hdlSources
+

+

9. Component TUT - ip.hwp.accelerator - picture_manip - 1.0

+

+
+ Description: Simple picture manipulator IP to rotate 8-bit grayscale picture 90 degrees clockwise.
+ IP-Xact file: picture_manip.1.0.xml
+

+

9.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Mutable
+

+

9.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clk	in	1	0	0
hibi_av_in	in	1	0	0
hibi_av_out	out	1	0	0
hibi_comm_in	in	5	4	0
hibi_comm_out	out	5	4	0
hibi_data_in	in	32	31	0
hibi_data_out	out	32	31	0
hibi_empty_in	in	1	0	0
hibi_full_in	in	1	0	0
hibi_one_d_in	in	1	0	0
hibi_one_p_in	in	1	0	0
hibi_re_out	out	1	0	0
hibi_we_out	out	1	0	0
rst_n	in	1	0	0

+

9.3 Bus interfaces

+

9.3.1 clk

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk
+

+

9.3.2 hibi_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• hibi_av_out
+
• hibi_one_d_in
+
• hibi_data_in
+
• hibi_data_out
+
• hibi_av_in
+
• hibi_full_in
+
• hibi_comm_out
+
• hibi_we_out
+
• hibi_comm_in
+
• hibi_empty_in
+
• hibi_re_out
+
• hibi_one_p_in
+

+

9.3.3 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

9.4 File sets

+

9.4.1 hdlSources

+

+    Identifiers:
+

+

   9.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
manip_memory.vhd	picture_manip			vhdlSource
picture_manip_pkg.vhd	picture_manip			vhdlSource
picture_manip.vhd	pciture_manip			vhdlSource

+

9.5 Views

+

9.5.1 View: rtl

+

+    Type: non-hierarchical
+    File sets contained in this view: +

+

+
• hdlSources
+

+

10. Component TUT - ip.hwp.communication - hibi_segment_small - 2.0

+

+
+ Description: HIBI segment block including two r4_wrapper and one r3_wrapper interfaces.
+ IP-Xact file: hibi_segment_small.2.0.xml
+

+

10.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Parameterizable
+

+

10.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
agent_addr_in_17	in	32	31	0
agent_addr_out_17	out	32	31	0
agent_av_in_1	in	1	0	0
agent_av_in_2	in	1	0	0
agent_av_in_3	in	1	0	0
agent_av_in_4	in	1	0	0
agent_av_in_5	in	1	0	0
agent_av_in_6	in	1	0	0
agent_av_in_7	in	1	0	0
agent_av_in_8	in	1	0	0
agent_av_out_1	out	1	0	0
agent_av_out_2	out	1	0	0
agent_av_out_3	out	1	0	0
agent_av_out_4	out	1	0	0
agent_av_out_5	out	1	0	0
agent_av_out_6	out	1	0	0
agent_av_out_7	out	1	0	0
agent_av_out_8	out	1	0	0
agent_comm_in_1	in	3	2	0
agent_comm_in_17	in	3	2	0
agent_comm_in_2	in	3	2	0
agent_comm_in_3	in	3	2	0
agent_comm_in_4	in	3	2	0
agent_comm_in_5	in	3	2	0
agent_comm_in_6	in	3	2	0
agent_comm_in_7	in	3	2	0
agent_comm_in_8	in	3	2	0
agent_comm_out_1	out	3	2	0
agent_comm_out_17	out	3	2	0
agent_comm_out_2	out	3	2	0
agent_comm_out_3	out	3	2	0
agent_comm_out_4	out	3	2	0
agent_comm_out_5	out	3	2	0
agent_comm_out_6	out	3	2	0
agent_comm_out_7	out	3	2	0
agent_comm_out_8	out	3	2	0
agent_data_in_1	in	32	31	0
agent_data_in_17	in	32	31	0
agent_data_in_2	in	32	31	0
agent_data_in_3	in	32	31	0
agent_data_in_4	in	32	31	0
agent_data_in_5	in	32	31	0
agent_data_in_6	in	32	31	0
agent_data_in_7	in	32	31	0
agent_data_in_8	in	32	31	0
agent_data_out_1	out	32	31	0
agent_data_out_17	out	32	31	0
agent_data_out_2	out	32	31	0
agent_data_out_3	out	32	31	0
agent_data_out_4	out	32	31	0
agent_data_out_5	out	32	31	0
agent_data_out_6	out	32	31	0
agent_data_out_7	out	32	31	0
agent_data_out_8	out	32	31	0
agent_empty_out_1	out	1	0	0
agent_empty_out_17	out	1	0	0
agent_empty_out_2	out	1	0	0
agent_empty_out_3	out	1	0	0
agent_empty_out_4	out	1	0	0
agent_empty_out_5	out	1	0	0
agent_empty_out_6	out	1	0	0
agent_empty_out_7	out	1	0	0
agent_empty_out_8	out	1	0	0
agent_full_out_1	out	1	0	0
agent_full_out_17	out	1	0	0
agent_full_out_2	out	1	0	0
agent_full_out_3	out	1	0	0
agent_full_out_4	out	1	0	0
agent_full_out_5	out	1	0	0
agent_full_out_6	out	1	0	0
agent_full_out_7	out	1	0	0
agent_full_out_8	out	1	0	0
agent_msg_addr_in_17	in	32	31	0
agent_msg_addr_out_17	out	32	31	0
agent_msg_comm_in_17	in	3	2	0
agent_msg_comm_out_17	out	3	2	0
agent_msg_data_in_17	in	32	31	0
agent_msg_data_out_17	out	32	31	0
agent_msg_empty_out_17	out	1	0	0
agent_msg_full_out_17	out	1	0	0
agent_msg_one_p_out_17	out	1	0	0
agent_msg_re_in_17	in	1	0	0
agent_msg_we_in_17	in	1	0	0
agent_one_d_out_1	out	1	0	0
agent_one_d_out_2	out	1	0	0
agent_one_d_out_3	out	1	0	0
agent_one_d_out_4	out	1	0	0
agent_one_d_out_5	out	1	0	0
agent_one_d_out_6	out	1	0	0
agent_one_d_out_7	out	1	0	0
agent_one_d_out_8	out	1	0	0
agent_one_p_out_1	out	1	0	0
agent_one_p_out_17	out	1	0	0
agent_one_p_out_2	out	1	0	0
agent_one_p_out_3	out	1	0	0
agent_one_p_out_4	out	1	0	0
agent_one_p_out_5	out	1	0	0
agent_one_p_out_6	out	1	0	0
agent_one_p_out_7	out	1	0	0
agent_one_p_out_8	out	1	0	0
agent_re_in_1	in	1	0	0
agent_re_in_17	in	1	0	0
agent_re_in_2	in	1	0	0
agent_re_in_3	in	1	0	0
agent_re_in_4	in	1	0	0
agent_re_in_5	in	1	0	0
agent_re_in_6	in	1	0	0
agent_re_in_7	in	1	0	0
agent_re_in_8	in	1	0	0
agent_we_in_1	in	1	0	0
agent_we_in_17	in	1	0	0
agent_we_in_2	in	1	0	0
agent_we_in_3	in	1	0	0
agent_we_in_4	in	1	0	0
agent_we_in_5	in	1	0	0
agent_we_in_6	in	1	0	0
agent_we_in_7	in	1	0	0
agent_we_in_8	in	1	0	0
clk	in	1	0	0
rst_n	in	1	0	0

+

10.3 Bus interfaces

+

10.3.1 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk
+

+

10.3.2 ddr2_ctrl_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• agent_comm_in_17
+
• agent_data_in_17
+
• agent_addr_in_17
+
• agent_we_in_17
+
• agent_re_in_17
+
• agent_comm_out_17
+
• agent_data_out_17
+
• agent_addr_out_17
+
• agent_full_out_17
+
• agent_one_p_out_17
+
• agent_empty_out_17
+
• agent_msg_re_in_17
+
• agent_msg_we_in_17
+
• agent_msg_addr_in_17
+
• agent_msg_data_in_17
+
• agent_msg_comm_in_17
+
• agent_msg_full_out_17
+
• agent_msg_one_p_out_17
+
• agent_msg_addr_out_17
+
• agent_msg_data_out_17
+
• agent_msg_comm_out_17
+
• agent_msg_empty_out_17
+

+

10.3.3 hibi_p1

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• agent_comm_in_1
+
• agent_data_in_1
+
• agent_av_in_1
+
• agent_we_in_1
+
• agent_re_in_1
+
• agent_comm_out_1
+
• agent_data_out_1
+
• agent_av_out_1
+
• agent_full_out_1
+
• agent_one_p_out_1
+
• agent_empty_out_1
+
• agent_one_d_out_1
+

+

10.3.4 hibi_p2

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• agent_comm_in_2
+
• agent_data_in_2
+
• agent_av_in_2
+
• agent_we_in_2
+
• agent_re_in_2
+
• agent_comm_out_2
+
• agent_data_out_2
+
• agent_av_out_2
+
• agent_full_out_2
+
• agent_one_p_out_2
+
• agent_empty_out_2
+
• agent_one_d_out_2
+

+

10.3.5 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

10.4 File sets

+

10.4.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
vhdlSource	vcom	-quiet -check_synthesis -work hibi_mem_dma	false

+

   10.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
hibiv2_pkg.vhd	hibi			vhdlSource
Hibi_segment.vhd	hibi			vhdlSource
addr_data_demuxes.vhd	hibi			vhdlSource
addr_data_muxes.vhd	hibi			vhdlSource
addr_decoder.vhd	hibi			vhdlSource
cfg_init_pkg.vhd	hibi			vhdlSource
cfg_mem.vhd	hibi			vhdlSource
copy_of_multiclk_fifo.vhd	hibi			vhdlSource
double_fifo_demux_wr.vhd	hibi			vhdlSource
double_fifo_mux_rd.vhd	hibi			vhdlSource
dyn_arb.vhd	hibi			vhdlSource
fifo.vhd	hibi			vhdlSource
fifo_muxes.vhd	hibi			vhdlSource
hibi_wrapper_r1.vhd	hibi			vhdlSource
hibi_wrapper_r3.vhd	hibi			vhdlSource
hibi_wrapper_r4.vhd	hibi			vhdlSource
lfsr.vhd	hibi			vhdlSource
receiver.vhd	hibi			vhdlSource
rx_ctrl.vhd	hibi			vhdlSource
transmitter.vhd	hibi			vhdlSource
tx_ctrl.vhd	hibi			vhdlSource

+

10.5 Views

+

10.5.1 View: rtl

+

+    Type: non-hierarchical
+    File sets contained in this view: +

+

+
• hdlSources
+

+

11. Component TUT - board - pc_board - 1.0

+

+
+ IP-Xact file: pc_board.1.0.xml
+

+

11.1 Kactus2 attributes

+

+    Product hierarchy: Board
+    Component implementation: HW
+    Component firmness: Parameterizable
+

+

11.2 Bus interfaces

+

11.2.1 pcie_4x

+

+    Interface mode: master
+    Ports used in this interface: +

+

+

+

11.3 Views

+

11.3.1 View: flat

+

+    Type: non-hierarchical
+

+ + + +

+ + + Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.ddr2_memory.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.ddr2_memory.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.ddr2_memory.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.ddr2_memory.1.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.chip.ddr2_memory.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.product.pc_arria_ii_gx.1.0.hierachical.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.product.pc_arria_ii_gx.1.0.hierachical.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.product.pc_arria_ii_gx.1.0.hierachical.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.product.pc_arria_ii_gx.1.0.hierachical.png (revision 24)

TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.product.pc_arria_ii_gx.1.0.hierachical.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.png =================================================================== --- TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.png (nonexistent) +++ TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.board.arria_ii_board.1.0.png (revision 24)

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TUT/product/pc_arria_ii_gx/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.structural.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/chip/support/clock_oscillator/1.0/clock_oscillator.1.0.xml =================================================================== --- TUT/chip/support/clock_oscillator/1.0/clock_oscillator.1.0.xml (nonexistent) +++ TUT/chip/support/clock_oscillator/1.0/clock_oscillator.1.0.xml (revision 24) @@ -0,0 +1,29 @@ + + + + TUT + chip + clock_oscillator + 1.0 + + + clk_out + + + + false + 8 + little + + + + + + + Chip + HW + Template + + + + Index: TUT/chip/support/push_buttons/1.0/push_buttons.1.0.xml =================================================================== --- TUT/chip/support/push_buttons/1.0/push_buttons.1.0.xml (nonexistent) +++ TUT/chip/support/push_buttons/1.0/push_buttons.1.0.xml (revision 24) @@ -0,0 +1,29 @@ + + + + TUT + chip + push_buttons + 1.0 + + + button_0 + + + + false + 8 + little + + + + + + + Chip + HW + Mutable + + + + Index: TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd =================================================================== --- TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd (revision 24) @@ -0,0 +1,77 @@ +-- **************************************************** +-- ** File: altera_de_II_demo.vhd +-- ** Date: 27.10.2011 15:33:01 +-- ** Description: +-- ** +-- ** This file was generated by Kactus2 vhdl generator +-- ** +-- **************************************************** + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.all; + +entity altera_de_II_demo is + + port ( + clk : in std_logic; + port_out : out std_logic; + rst_n : in std_logic; + toggle_in : in std_logic); + +end altera_de_II_demo; + +architecture structural of altera_de_II_demo is + + signal port_blinker_1_ena_in_sig_gen_1_ena_out : std_logic; + signal port_blinker_1_val_in_sig_gen_1_sig_out : std_logic_vector(31 downto 0); + + component port_blinker + generic ( + SIGNAL_WIDTH : integer := 32); + port ( + clk : in std_logic; + ena_in : in std_logic; + port_out : out std_logic; + rst_n : in std_logic; + val_in : in std_logic_vector(31 downto 0)); + end component; + + component sig_gen + generic ( + SIGNAL_VAL : integer := 100000000; + SIGNAL_WIDTH : integer := 32); + port ( + clk : in std_logic; + ena_out : out std_logic; + rst_n : in std_logic; + sig_out : out std_logic_vector(31 downto 0); + toggle_in : in std_logic); + end component; + + + +begin + + + port_blinker_1 : port_blinker + port map ( + rst_n => rst_n, + val_in(31 downto 0) => port_blinker_1_val_in_sig_gen_1_sig_out(31 downto 0), + port_out => port_out, + ena_in => port_blinker_1_ena_in_sig_gen_1_ena_out, + clk => clk); + + sig_gen_1 : sig_gen + port map ( + sig_out(31 downto 0) => port_blinker_1_val_in_sig_gen_1_sig_out(31 downto 0), + ena_out => port_blinker_1_ena_in_sig_gen_1_ena_out, + clk => clk, + toggle_in => toggle_in, + rst_n => rst_n); + +end structural; + Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.flow.rpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.flow.rpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.flow.rpt (revision 24) @@ -0,0 +1,117 @@ +Flow report for altera_de_II_demo +Fri Oct 28 11:32:49 2011 +Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2011 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+------------------------------------------------+ +; Flow Status ; Successful - Fri Oct 28 11:32:49 2011 ; +; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ; +; Revision Name ; altera_de_II_demo ; +; Top-level Entity Name ; altera_de_II_demo ; +; Family ; Cyclone II ; +; Device ; EP2C35F672C6 ; +; Timing Models ; Final ; +; Total logic elements ; 46 / 33,216 ( < 1 % ) ; +; Total combinational functions ; 45 / 33,216 ( < 1 % ) ; +; Dedicated logic registers ; 35 / 33,216 ( < 1 % ) ; +; Total registers ; 35 ; +; Total pins ; 4 / 475 ( < 1 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 483,840 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 10/28/2011 11:32:29 ; +; Main task ; Compilation ; +; Revision Name ; altera_de_II_demo ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 146449710050.131979074904228 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; ++-------------------------------------+------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 250 MB ; 00:00:01 ; +; Fitter ; 00:00:08 ; 1.2 ; 344 MB ; 00:00:06 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 236 MB ; 00:00:01 ; +; Assembler ; 00:00:03 ; 1.0 ; 271 MB ; 00:00:02 ; +; Total ; 00:00:18 ; -- ; -- ; 00:00:10 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; platy ; Windows XP ; 5.1 ; i686 ; +; Fitter ; platy ; Windows XP ; 5.1 ; i686 ; +; TimeQuest Timing Analyzer ; platy ; Windows XP ; 5.1 ; i686 ; +; Assembler ; platy ; Windows XP ; 5.1 ; i686 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo +quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo +quartus_sta altera_de_II_demo -c altera_de_II_demo +quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo + + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.summary =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.summary (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.summary (revision 24) @@ -0,0 +1,16 @@ +Fitter Status : Successful - Fri Oct 28 11:32:43 2011 +Quartus II Version : 11.0 Build 208 07/03/2011 SP 1 SJ Full Version +Revision Name : altera_de_II_demo +Top-level Entity Name : altera_de_II_demo +Family : Cyclone II +Device : EP2C35F672C6 +Timing Models : Final +Total logic elements : 46 / 33,216 ( < 1 % ) + Total combinational functions : 45 / 33,216 ( < 1 % ) + Dedicated logic registers : 35 / 33,216 ( < 1 % ) +Total registers : 35 +Total pins : 4 / 475 ( < 1 % ) +Total virtual pins : 0 +Total memory bits : 0 / 483,840 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cbx.xml =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cbx.xml (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cbx.xml (revision 24) @@ -0,0 +1,5 @@ + + + + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.kpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.kpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.kpt (revision 24)

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TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(1).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.html =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.html (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.html (revision 24) @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Hierarchy	Input	Constant Input	Unused Input	Floating Input	Output	Constant Output	Unused Output	Floating Output	Bidir	Constant Bidir	Unused Bidir	Input only Bidir	Output only Bidir
sig_gen_1	3	32	0	32	33	32	32	32	0	0	0	0	0
port_blinker_1	35	0	0	0	1	0	0	0	0	0	0	0	0

Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tmw_info =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tmw_info (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tmw_info (revision 24) @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:26 +start_analysis_synthesis:s:00:00:10-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:10-start_full_compilation +start_assembler:s:00:00:04-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(1).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(1).cnf.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(1).cnf.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(1).cnf.hdb (revision 24)

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TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.rdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.rdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.rdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.qmsg =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.qmsg (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.qmsg (revision 24) @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:46 2011 " "Info: Processing started: Fri Oct 28 11:32:46 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "271 " "Info: Peak virtual memory: 271 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:49 2011 " "Info: Processing ended: Fri Oct 28 11:32:49 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp0.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp0.ddb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp0.ddb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp0.ddb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp0.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.fit.qmsg =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.fit.qmsg (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.fit.qmsg (revision 24) @@ -0,0 +1,39 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:35 2011 " "Info: Processing started: Fri Oct 28 11:32:35 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "altera_de_II_demo EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"altera_de_II_demo\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 576 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 577 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 578 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "altera_de_II_demo.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "Info: No user constrained base clocks found in the design" { } { } 0 0 "No user constrained %1!s! found in the design" 0 0 "" 0 -1} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { clk } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 20 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 5 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { rst_n } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 22 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 7 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Warning: Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Warning: Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Warning: Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Warning: Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Warning: Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Warning: Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27 " "Warning: Node \"CLOCK_27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Warning: Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Warning: Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Warning: Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Warning: Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Warning: Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Warning: Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Warning: Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Warning: Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Warning: Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Warning: Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Warning: Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Warning: Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_0 " "Warning: Node \"DRAM_BA_0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_1 " "Warning: Node \"DRAM_BA_1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Warning: Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Warning: Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Warning: Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Warning: Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Warning: Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Warning: Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Warning: Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Warning: Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Warning: Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Warning: Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Warning: Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Warning: Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Warning: Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Warning: Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Warning: Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Warning: Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Warning: Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Warning: Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Warning: Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Warning: Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Warning: Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Warning: Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Warning: Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Warning: Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CLK " "Warning: Node \"ENET_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CMD " "Warning: Node \"ENET_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CMD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CS_N " "Warning: Node \"ENET_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Node \"ENET_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[10\] " "Warning: Node \"ENET_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[11\] " "Warning: Node \"ENET_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[12\] " "Warning: Node \"ENET_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[13\] " "Warning: Node \"ENET_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[14\] " "Warning: Node \"ENET_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[15\] " "Warning: Node \"ENET_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[1\] " "Warning: Node \"ENET_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[2\] " "Warning: Node \"ENET_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[3\] " "Warning: Node \"ENET_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[4\] " "Warning: Node \"ENET_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[5\] " "Warning: Node \"ENET_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[6\] " "Warning: Node \"ENET_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[7\] " "Warning: Node \"ENET_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[8\] " "Warning: Node \"ENET_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[9\] " "Warning: Node \"ENET_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_INT " "Warning: Node \"ENET_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_INT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RD_N " "Warning: Node \"ENET_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_RD_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RST_N " "Warning: Node \"ENET_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_WR_N " "Warning: Node \"ENET_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_WR_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EXT_CLOCK " "Warning: Node \"EXT_CLOCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EXT_CLOCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Warning: Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Warning: Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Warning: Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Warning: Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Warning: Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Warning: Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Warning: Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Warning: Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Warning: Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Warning: Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Warning: Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Warning: Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Warning: Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Warning: Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Warning: Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Warning: Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Warning: Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Warning: Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Warning: Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Warning: Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Warning: Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Warning: Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Warning: Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Warning: Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Warning: Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Warning: Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Warning: Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Warning: Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Warning: Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Warning: Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Warning: Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Warning: Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Warning: Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Warning: Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Warning: Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Warning: Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Warning: Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Warning: Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Warning: Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Warning: Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Warning: Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Warning: Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Warning: Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Warning: Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Warning: Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Warning: Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Warning: Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Warning: Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Warning: Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Warning: Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Warning: Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Warning: Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Warning: Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Warning: Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Warning: Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Warning: Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Warning: Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Warning: Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Warning: Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Warning: Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Warning: Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[34\] " "Warning: Node \"GPIO_0\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[35\] " "Warning: Node \"GPIO_0\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Warning: Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Warning: Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Warning: Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Warning: Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Warning: Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Warning: Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Warning: Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Warning: Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Warning: Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Warning: Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Warning: Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Warning: Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Warning: Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Warning: Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Warning: Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Warning: Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Warning: Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Warning: Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Warning: Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Warning: Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Warning: Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Warning: Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Warning: Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Warning: Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Warning: Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Warning: Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Warning: Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Warning: Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Warning: Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Warning: Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Warning: Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Warning: Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Warning: Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Warning: Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[34\] " "Warning: Node \"GPIO_1\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[35\] " "Warning: Node \"GPIO_1\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Warning: Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Warning: Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Warning: Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Warning: Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Warning: Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Warning: Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Warning: Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Warning: Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Warning: Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Warning: Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Warning: Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Warning: Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Warning: Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Warning: Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Warning: Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Warning: Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Warning: Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Warning: Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Warning: Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Warning: Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Warning: Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Warning: Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Warning: Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Warning: Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Warning: Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Warning: Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Warning: Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Warning: Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Warning: Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Warning: Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Warning: Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Warning: Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Warning: Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Warning: Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Warning: Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Warning: Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Warning: Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Warning: Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Warning: Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Warning: Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Warning: Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Warning: Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Warning: Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Warning: Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Warning: Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Warning: Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Warning: Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Warning: Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Warning: Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Warning: Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Warning: Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Warning: Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Warning: Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Warning: Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Warning: Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Warning: Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Warning: Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Warning: Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Warning: Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Warning: Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Warning: Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Warning: Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Warning: Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Warning: Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Warning: Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Warning: Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_TXD " "Warning: Node \"IRDA_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "IRDA_TXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Warning: Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Warning: Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Warning: Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Warning: Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Warning: Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Warning: Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Warning: Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Warning: Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Warning: Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Warning: Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Warning: Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Warning: Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Warning: Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Warning: Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Warning: Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Warning: Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Warning: Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Warning: Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Warning: Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Warning: Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Warning: Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Warning: Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Warning: Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Warning: Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Warning: Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Warning: Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Warning: Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Warning: Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Warning: Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Warning: Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Warning: Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Warning: Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Warning: Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Warning: Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Warning: Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Warning: Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Warning: Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Warning: Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Warning: Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Warning: Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Warning: Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Warning: Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Warning: Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Warning: Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Warning: Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK0_N " "Warning: Node \"OTG_DACK0_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DACK0_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK1_N " "Warning: Node \"OTG_DACK1_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DACK1_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Warning: Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Warning: Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Warning: Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Warning: Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Warning: Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Warning: Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Warning: Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Warning: Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Warning: Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Warning: Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Warning: Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Warning: Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Warning: Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Warning: Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Warning: Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Warning: Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ0 " "Warning: Node \"OTG_DREQ0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DREQ0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ1 " "Warning: Node \"OTG_DREQ1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DREQ1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Warning: Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT0 " "Warning: Node \"OTG_INT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_INT0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT1 " "Warning: Node \"OTG_INT1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_INT1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Warning: Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Warning: Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Warning: Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Warning: Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Warning: Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Warning: Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Warning: Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Warning: Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT " "Warning: Node \"SD_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_DAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT3 " "Warning: Node \"SD_DAT3\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Warning: Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Warning: Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Warning: Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Warning: Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Warning: Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Warning: Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Warning: Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Warning: Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Warning: Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Warning: Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Warning: Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Warning: Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Warning: Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Warning: Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Warning: Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Warning: Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Warning: Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Warning: Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Warning: Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Warning: Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Warning: Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Warning: Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Warning: Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Warning: Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Warning: Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Warning: Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Warning: Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Warning: Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Warning: Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Warning: Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Warning: Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Warning: Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Warning: Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Warning: Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Warning: Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Warning: Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Warning: Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Warning: Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Warning: Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Warning: Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Warning: Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Warning: Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Warning: Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Warning: Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Warning: Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Warning: Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Warning: Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Warning: Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Warning: Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Warning: Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Warning: Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Warning: Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Warning: Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Warning: Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Warning: Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Warning: Node \"TCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCS " "Warning: Node \"TCS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Warning: Node \"TDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDI" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Warning: Node \"TDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Warning: Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Warning: Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Warning: Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Warning: Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Warning: Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Warning: Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Warning: Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Warning: Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Warning: Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET " "Warning: Node \"TD_RESET\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Warning: Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Warning: Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Warning: Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK " "Warning: Node \"VGA_BLANK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_BLANK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Warning: Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Warning: Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Warning: Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Warning: Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Warning: Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Warning: Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Warning: Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Warning: Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[8\] " "Warning: Node \"VGA_B\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[9\] " "Warning: Node \"VGA_B\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Warning: Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Warning: Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Warning: Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Warning: Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Warning: Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Warning: Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Warning: Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Warning: Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Warning: Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[8\] " "Warning: Node \"VGA_G\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[9\] " "Warning: Node \"VGA_G\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Warning: Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Warning: Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Warning: Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Warning: Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Warning: Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Warning: Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Warning: Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Warning: Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Warning: Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[8\] " "Warning: Node \"VGA_R\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[9\] " "Warning: Node \"VGA_R\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC " "Warning: Node \"VGA_SYNC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_SYNC" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Warning: Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X55_Y24 X65_Y36 " "Info: Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36" { } { } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "port_out 0 " "Info: Pin \"port_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg " "Info: Generated suppressed messages file D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 424 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 424 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Info: Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:43 2011 " "Info: Processing ended: Fri Oct 28 11:32:43 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp1.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp1.ddb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp1.ddb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp1.ddb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp1.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.syn_hier_info =================================================================== Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp_merge.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp_merge.kpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp_merge.kpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp_merge.kpt (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp_merge.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.qmsg =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.qmsg (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.qmsg (revision 24) @@ -0,0 +1,30 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:45 2011 " "Info: Processing started: Fri Oct 28 11:32:45 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_sta altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "altera_de_II_demo.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 0 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Info: Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "Info: create_clock -period 1.000 -name clk clk" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "%1!s!" 0 0 "" 0 -1} +{ "Info" "0" "" "Info: Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" { } { } 1 0 "Timing requirements not met" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.010 " "Info: Worst-case setup slack is -3.010" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.010 -94.090 clk " "Info: -3.010 -94.090 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.391 " "Info: Worst-case hold slack is 0.391" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 clk " "Info: 0.391 0.000 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "Info: No Recovery paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "Info: No Removal paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Info: Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -36.380 clk " "Info: -1.380 -36.380 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." { } { } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1} +{ "Info" "0" "" "Info: Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "port_out 0 " "Info: Pin \"port_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" { } { } 1 0 "Timing requirements not met" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.845 " "Info: Worst-case setup slack is -0.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.845 -25.749 clk " "Info: -0.845 -25.749 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Info: Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " "Info: 0.215 0.000 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "Info: No Recovery paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "Info: No Removal paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Info: Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -36.380 clk " "Info: -1.380 -36.380 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." { } { } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" { } { } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" { } { } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:47 2011 " "Info: Processing ended: Fri Oct 28 11:32:47 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.rdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.rdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.rdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.db_info =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.db_info (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.db_info (revision 24) @@ -0,0 +1,3 @@ +Quartus_Version = Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version +Version_Index = 234934273 +Creation_Time = Thu Oct 27 15:34:11 2011 Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg_swap.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg_swap.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg_swap.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg_swap.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg_swap.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.amm.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.amm.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.amm.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.amm.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.amm.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hier_info =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hier_info (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hier_info (revision 24) @@ -0,0 +1,151 @@ +|altera_de_II_demo +clk => port_blinker:port_blinker_1.clk +clk => sig_gen:sig_gen_1.clk +rst_n => port_blinker:port_blinker_1.rst_n +rst_n => sig_gen:sig_gen_1.rst_n +toggle_in => sig_gen:sig_gen_1.toggle_in + + +|altera_de_II_demo|port_blinker:port_blinker_1 +clk => val_cnt_r[0].CLK +clk => val_cnt_r[1].CLK +clk => val_cnt_r[2].CLK +clk => val_cnt_r[3].CLK +clk => val_cnt_r[4].CLK +clk => val_cnt_r[5].CLK +clk => val_cnt_r[6].CLK +clk => val_cnt_r[7].CLK +clk => val_cnt_r[8].CLK +clk => val_cnt_r[9].CLK +clk => val_cnt_r[10].CLK +clk => val_cnt_r[11].CLK +clk => val_cnt_r[12].CLK +clk => val_cnt_r[13].CLK +clk => val_cnt_r[14].CLK +clk => val_cnt_r[15].CLK +clk => val_cnt_r[16].CLK +clk => val_cnt_r[17].CLK +clk => val_cnt_r[18].CLK +clk => val_cnt_r[19].CLK +clk => val_cnt_r[20].CLK +clk => val_cnt_r[21].CLK +clk => val_cnt_r[22].CLK +clk => val_cnt_r[23].CLK +clk => val_cnt_r[24].CLK +clk => val_cnt_r[25].CLK +clk => val_cnt_r[26].CLK +clk => val_cnt_r[27].CLK +clk => val_cnt_r[28].CLK +clk => val_cnt_r[29].CLK +clk => val_cnt_r[30].CLK +clk => val_cnt_r[31].CLK +clk => port_level_r.CLK +rst_n => val_cnt_r[0].ACLR +rst_n => val_cnt_r[1].ACLR +rst_n => val_cnt_r[2].ACLR +rst_n => val_cnt_r[3].ACLR +rst_n => val_cnt_r[4].ACLR +rst_n => val_cnt_r[5].ACLR +rst_n => val_cnt_r[6].ACLR +rst_n => val_cnt_r[7].ACLR +rst_n => val_cnt_r[8].ACLR +rst_n => val_cnt_r[9].ACLR +rst_n => val_cnt_r[10].ACLR +rst_n => val_cnt_r[11].ACLR +rst_n => val_cnt_r[12].ACLR +rst_n => val_cnt_r[13].ACLR +rst_n => val_cnt_r[14].ACLR +rst_n => val_cnt_r[15].ACLR +rst_n => val_cnt_r[16].ACLR +rst_n => val_cnt_r[17].ACLR +rst_n => val_cnt_r[18].ACLR +rst_n => val_cnt_r[19].ACLR +rst_n => val_cnt_r[20].ACLR +rst_n => val_cnt_r[21].ACLR +rst_n => val_cnt_r[22].ACLR +rst_n => val_cnt_r[23].ACLR +rst_n => val_cnt_r[24].ACLR +rst_n => val_cnt_r[25].ACLR +rst_n => val_cnt_r[26].ACLR +rst_n => val_cnt_r[27].ACLR +rst_n => val_cnt_r[28].ACLR +rst_n => val_cnt_r[29].ACLR +rst_n => val_cnt_r[30].ACLR +rst_n => val_cnt_r[31].ACLR +rst_n => port_level_r.ACLR +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => val_cnt_r.OUTPUTSELECT +ena_in => port_level_r.ENA +val_in[0] => Equal0.IN31 +val_in[1] => Equal0.IN30 +val_in[2] => Equal0.IN29 +val_in[3] => Equal0.IN28 +val_in[4] => Equal0.IN27 +val_in[5] => Equal0.IN26 +val_in[6] => Equal0.IN25 +val_in[7] => Equal0.IN24 +val_in[8] => Equal0.IN23 +val_in[9] => Equal0.IN22 +val_in[10] => Equal0.IN21 +val_in[11] => Equal0.IN20 +val_in[12] => Equal0.IN19 +val_in[13] => Equal0.IN18 +val_in[14] => Equal0.IN17 +val_in[15] => Equal0.IN16 +val_in[16] => Equal0.IN15 +val_in[17] => Equal0.IN14 +val_in[18] => Equal0.IN13 +val_in[19] => Equal0.IN12 +val_in[20] => Equal0.IN11 +val_in[21] => Equal0.IN10 +val_in[22] => Equal0.IN9 +val_in[23] => Equal0.IN8 +val_in[24] => Equal0.IN7 +val_in[25] => Equal0.IN6 +val_in[26] => Equal0.IN5 +val_in[27] => Equal0.IN4 +val_in[28] => Equal0.IN3 +val_in[29] => Equal0.IN2 +val_in[30] => Equal0.IN1 +val_in[31] => Equal0.IN0 + + +|altera_de_II_demo|sig_gen:sig_gen_1 +clk => toggle_r.CLK +clk => toggle_d1_r.CLK +rst_n => toggle_r.ACLR +rst_n => toggle_d1_r.ACLR +toggle_in => process_0.IN1 +toggle_in => toggle_d1_r.DATAIN + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.logdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.logdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.logdb (revision 24) @@ -0,0 +1 @@ +v1 Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.logdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.logdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.logdb (revision 24) @@ -0,0 +1 @@ +v1 Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta_cmp.6_slow.tdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta_cmp.6_slow.tdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta_cmp.6_slow.tdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta_cmp.6_slow.tdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta_cmp.6_slow.tdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry.sci =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry.sci (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry.sci (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry.sci Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/logic_util_heursitic.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/logic_util_heursitic.dat =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/logic_util_heursitic.dat (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/logic_util_heursitic.dat (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/logic_util_heursitic.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(0).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.(2).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.qmsg =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.qmsg (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.qmsg (revision 24) @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:28 2011 " "Info: Processing started: Fri Oct 28 11:32:28 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sig_gen-rtl " "Info: Found design unit 1: sig_gen-rtl" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 61 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 sig_gen " "Info: Found entity 1: sig_gen" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 port_blinker-rtl " "Info: Found design unit 1: port_blinker-rtl" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 60 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 port_blinker " "Info: Found entity 1: port_blinker" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altera_de_II_demo-structural " "Info: Found design unit 1: altera_de_II_demo-structural" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 27 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 altera_de_II_demo " "Info: Found entity 1: altera_de_II_demo" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 17 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "altera_de_II_demo " "Info: Elaborating entity \"altera_de_II_demo\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "port_blinker port_blinker:port_blinker_1 " "Info: Elaborating entity \"port_blinker\" for hierarchy \"port_blinker:port_blinker_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "port_blinker_1" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 60 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sig_gen sig_gen:sig_gen_1 " "Info: Elaborating entity \"sig_gen\" for hierarchy \"sig_gen:sig_gen_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "sig_gen_1" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 68 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { } { } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:34 2011 " "Info: Processing ended: Fri Oct 28 11:32:34 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.idb.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.idb.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.idb.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.idb.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.idb.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.rdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.rdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.rdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.rdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.rdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.rdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tis_db_list.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tis_db_list.ddb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tis_db_list.ddb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tis_db_list.ddb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.tis_db_list.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.bpm =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.bpm (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.bpm (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.bpm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.txt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.txt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.lpc.txt (revision 24) @@ -0,0 +1,8 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; sig_gen_1 ; 3 ; 32 ; 0 ; 32 ; 33 ; 32 ; 32 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; port_blinker_1 ; 35 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.bpm =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.bpm (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.bpm (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.bpm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.smart_action.txt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.smart_action.txt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.smart_action.txt (revision 24) @@ -0,0 +1 @@ +DONE Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry_dsc.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry_dsc.sci =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry_dsc.sci (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry_dsc.sci (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sld_design_entry_dsc.sci Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/prev_cmp_altera_de_II_demo.qmsg =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/prev_cmp_altera_de_II_demo.qmsg (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/prev_cmp_altera_de_II_demo.qmsg (revision 24) @@ -0,0 +1,90 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 27 15:34:16 2011 " "Info: Processing started: Thu Oct 27 15:34:16 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sig_gen-rtl " "Info: Found design unit 1: sig_gen-rtl" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 61 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 sig_gen " "Info: Found entity 1: sig_gen" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 port_blinker-rtl " "Info: Found design unit 1: port_blinker-rtl" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 60 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 port_blinker " "Info: Found entity 1: port_blinker" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altera_de_II_demo-structural " "Info: Found design unit 1: altera_de_II_demo-structural" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 27 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 altera_de_II_demo " "Info: Found entity 1: altera_de_II_demo" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 17 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "altera_de_II_demo " "Info: Elaborating entity \"altera_de_II_demo\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "port_blinker port_blinker:port_blinker_1 " "Info: Elaborating entity \"port_blinker\" for hierarchy \"port_blinker:port_blinker_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "port_blinker_1" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 60 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sig_gen sig_gen:sig_gen_1 " "Info: Elaborating entity \"sig_gen\" for hierarchy \"sig_gen:sig_gen_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "sig_gen_1" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 68 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { } { } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "252 " "Info: Peak virtual memory: 252 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 27 15:34:19 2011 " "Info: Processing ended: Thu Oct 27 15:34:19 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 27 15:34:21 2011 " "Info: Processing started: Thu Oct 27 15:34:21 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "altera_de_II_demo EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"altera_de_II_demo\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 576 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 577 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 578 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "altera_de_II_demo.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "Info: No user constrained base clocks found in the design" { } { } 0 0 "No user constrained %1!s! found in the design" 0 0 "" 0 -1} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { clk } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 20 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 5 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { rst_n } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 22 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 7 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Warning: Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Warning: Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Warning: Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Warning: Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Warning: Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Warning: Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27 " "Warning: Node \"CLOCK_27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Warning: Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Warning: Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Warning: Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Warning: Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Warning: Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Warning: Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Warning: Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Warning: Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Warning: Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Warning: Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Warning: Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Warning: Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_0 " "Warning: Node \"DRAM_BA_0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_1 " "Warning: Node \"DRAM_BA_1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Warning: Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Warning: Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Warning: Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Warning: Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Warning: Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Warning: Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Warning: Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Warning: Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Warning: Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Warning: Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Warning: Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Warning: Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Warning: Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Warning: Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Warning: Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Warning: Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Warning: Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Warning: Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Warning: Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Warning: Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Warning: Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Warning: Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Warning: Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Warning: Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CLK " "Warning: Node \"ENET_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CMD " "Warning: Node \"ENET_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CMD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CS_N " "Warning: Node \"ENET_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Node \"ENET_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[10\] " "Warning: Node \"ENET_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[11\] " "Warning: Node \"ENET_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[12\] " "Warning: Node \"ENET_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[13\] " "Warning: Node \"ENET_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[14\] " "Warning: Node \"ENET_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[15\] " "Warning: Node \"ENET_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[1\] " "Warning: Node \"ENET_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[2\] " "Warning: Node \"ENET_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[3\] " "Warning: Node \"ENET_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[4\] " "Warning: Node \"ENET_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[5\] " "Warning: Node \"ENET_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[6\] " "Warning: Node \"ENET_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[7\] " "Warning: Node \"ENET_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[8\] " "Warning: Node \"ENET_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[9\] " "Warning: Node \"ENET_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_INT " "Warning: Node \"ENET_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_INT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RD_N " "Warning: Node \"ENET_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_RD_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RST_N " "Warning: Node \"ENET_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_WR_N " "Warning: Node \"ENET_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_WR_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EXT_CLOCK " "Warning: Node \"EXT_CLOCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "EXT_CLOCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Warning: Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Warning: Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Warning: Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Warning: Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Warning: Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Warning: Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Warning: Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Warning: Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Warning: Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Warning: Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Warning: Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Warning: Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Warning: Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Warning: Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Warning: Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Warning: Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Warning: Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Warning: Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Warning: Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Warning: Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Warning: Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Warning: Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Warning: Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Warning: Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Warning: Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Warning: Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Warning: Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Warning: Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Warning: Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Warning: Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Warning: Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Warning: Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Warning: Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Warning: Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Warning: Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Warning: Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Warning: Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Warning: Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Warning: Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Warning: Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Warning: Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Warning: Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Warning: Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Warning: Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Warning: Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Warning: Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Warning: Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Warning: Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Warning: Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Warning: Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Warning: Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Warning: Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Warning: Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Warning: Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Warning: Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Warning: Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Warning: Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Warning: Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Warning: Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Warning: Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Warning: Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[34\] " "Warning: Node \"GPIO_0\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[35\] " "Warning: Node \"GPIO_0\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Warning: Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Warning: Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Warning: Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Warning: Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Warning: Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Warning: Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Warning: Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Warning: Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Warning: Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Warning: Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Warning: Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Warning: Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Warning: Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Warning: Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Warning: Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Warning: Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Warning: Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Warning: Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Warning: Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Warning: Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Warning: Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Warning: Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Warning: Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Warning: Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Warning: Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Warning: Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Warning: Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Warning: Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Warning: Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Warning: Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Warning: Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Warning: Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Warning: Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Warning: Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[34\] " "Warning: Node \"GPIO_1\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[35\] " "Warning: Node \"GPIO_1\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Warning: Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Warning: Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Warning: Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Warning: Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Warning: Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Warning: Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Warning: Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Warning: Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Warning: Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Warning: Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Warning: Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Warning: Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Warning: Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Warning: Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Warning: Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Warning: Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Warning: Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Warning: Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Warning: Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Warning: Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Warning: Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Warning: Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Warning: Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Warning: Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Warning: Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Warning: Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Warning: Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Warning: Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Warning: Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Warning: Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Warning: Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Warning: Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Warning: Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Warning: Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Warning: Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Warning: Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Warning: Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Warning: Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Warning: Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Warning: Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Warning: Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Warning: Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Warning: Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Warning: Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Warning: Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Warning: Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Warning: Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Warning: Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Warning: Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Warning: Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Warning: Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Warning: Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Warning: Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Warning: Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Warning: Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Warning: Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Warning: Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Warning: Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Warning: Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Warning: Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Warning: Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Warning: Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Warning: Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Warning: Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Warning: Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Warning: Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_TXD " "Warning: Node \"IRDA_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "IRDA_TXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Warning: Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Warning: Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Warning: Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Warning: Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Warning: Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Warning: Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Warning: Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Warning: Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Warning: Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Warning: Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Warning: Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Warning: Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Warning: Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Warning: Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Warning: Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Warning: Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Warning: Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Warning: Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Warning: Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Warning: Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Warning: Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Warning: Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Warning: Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Warning: Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Warning: Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Warning: Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Warning: Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Warning: Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Warning: Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Warning: Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Warning: Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Warning: Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Warning: Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Warning: Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Warning: Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Warning: Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Warning: Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Warning: Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Warning: Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Warning: Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Warning: Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Warning: Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Warning: Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Warning: Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Warning: Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK0_N " "Warning: Node \"OTG_DACK0_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DACK0_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK1_N " "Warning: Node \"OTG_DACK1_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DACK1_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Warning: Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Warning: Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Warning: Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Warning: Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Warning: Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Warning: Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Warning: Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Warning: Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Warning: Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Warning: Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Warning: Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Warning: Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Warning: Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Warning: Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Warning: Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Warning: Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ0 " "Warning: Node \"OTG_DREQ0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DREQ0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ1 " "Warning: Node \"OTG_DREQ1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DREQ1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Warning: Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT0 " "Warning: Node \"OTG_INT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_INT0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT1 " "Warning: Node \"OTG_INT1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_INT1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Warning: Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Warning: Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Warning: Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Warning: Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Warning: Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Warning: Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Warning: Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Warning: Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT " "Warning: Node \"SD_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_DAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT3 " "Warning: Node \"SD_DAT3\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Warning: Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Warning: Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Warning: Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Warning: Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Warning: Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Warning: Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Warning: Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Warning: Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Warning: Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Warning: Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Warning: Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Warning: Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Warning: Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Warning: Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Warning: Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Warning: Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Warning: Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Warning: Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Warning: Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Warning: Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Warning: Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Warning: Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Warning: Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Warning: Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Warning: Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Warning: Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Warning: Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Warning: Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Warning: Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Warning: Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Warning: Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Warning: Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Warning: Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Warning: Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Warning: Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Warning: Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Warning: Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Warning: Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Warning: Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Warning: Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Warning: Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Warning: Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Warning: Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Warning: Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Warning: Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Warning: Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Warning: Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Warning: Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Warning: Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Warning: Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Warning: Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Warning: Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Warning: Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Warning: Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Warning: Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Warning: Node \"TCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCS " "Warning: Node \"TCS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Warning: Node \"TDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDI" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Warning: Node \"TDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Warning: Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Warning: Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Warning: Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Warning: Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Warning: Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Warning: Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Warning: Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Warning: Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Warning: Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET " "Warning: Node \"TD_RESET\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Warning: Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Warning: Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Warning: Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK " "Warning: Node \"VGA_BLANK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_BLANK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Warning: Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Warning: Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Warning: Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Warning: Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Warning: Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Warning: Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Warning: Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Warning: Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[8\] " "Warning: Node \"VGA_B\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[9\] " "Warning: Node \"VGA_B\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Warning: Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Warning: Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Warning: Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Warning: Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Warning: Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Warning: Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Warning: Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Warning: Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Warning: Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[8\] " "Warning: Node \"VGA_G\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[9\] " "Warning: Node \"VGA_G\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Warning: Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Warning: Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Warning: Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Warning: Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Warning: Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Warning: Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Warning: Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Warning: Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Warning: Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[8\] " "Warning: Node \"VGA_R\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[9\] " "Warning: Node \"VGA_R\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC " "Warning: Node \"VGA_SYNC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_SYNC" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Warning: Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X55_Y24 X65_Y36 " "Info: Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36" { } { } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "port_out 0 " "Info: Pin \"port_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg " "Info: Generated suppressed messages file D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 424 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 424 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Info: Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 27 15:34:29 2011 " "Info: Processing ended: Thu Oct 27 15:34:29 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 27 15:34:30 2011 " "Info: Processing started: Thu Oct 27 15:34:30 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_sta altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1} +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 27 15:34:32 2011 " "Info: Processing started: Thu Oct 27 15:34:32 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "altera_de_II_demo.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 0 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Info: Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "Info: create_clock -period 1.000 -name clk clk" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "%1!s!" 0 0 "" 0 -1} +{ "Info" "0" "" "Info: Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" { } { } 1 0 "Timing requirements not met" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.010 " "Info: Worst-case setup slack is -3.010" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.010 -94.090 clk " "Info: -3.010 -94.090 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.391 " "Info: Worst-case hold slack is 0.391" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 clk " "Info: 0.391 0.000 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "Info: No Recovery paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "Info: No Removal paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Info: Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -36.380 clk " "Info: -1.380 -36.380 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." { } { } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1} +{ "Info" "0" "" "Info: Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "port_out 0 " "Info: Pin \"port_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Critical Warning: Timing requirements not met" { } { } 1 0 "Timing requirements not met" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.845 " "Info: Worst-case setup slack is -0.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.845 -25.749 clk " "Info: -0.845 -25.749 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Info: Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " "Info: 0.215 0.000 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "Info: No Recovery paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "Info: No Removal paths to report" { } { } 0 0 "No %1!s! paths to report" 0 0 "" 0 -1} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Info: Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " "Info: Slack End Point TNS Clock " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -36.380 clk " "Info: -1.380 -36.380 clk " { } { } 0 0 "%1!s!" 0 0 "" 0 -1} } { } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." { } { } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" { } { } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" { } { } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 27 15:34:34 2011 " "Info: Processing ended: Thu Oct 27 15:34:34 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "271 " "Info: Peak virtual memory: 271 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 27 15:34:36 2011 " "Info: Processing ended: Thu Oct 27 15:34:36 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Warning" "WFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 0 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "" 0 -1} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 429 s " "Info: Quartus II Full Compilation was successful. 0 errors, 429 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.logdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.logdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.logdb (revision 24) @@ -0,0 +1 @@ +v1 Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hif =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hif (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hif (revision 24) @@ -0,0 +1,143 @@ +Quartus II +Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version +14 +1076 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +altera_de_II_demo +# storage +db|altera_de_II_demo.(0).cnf +db|altera_de_II_demo.(0).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +|user|matilail|funbase|opencores_lib|trunk|tut|soc|altera_de_ii_demo|1.0|vhd|altera_de_ii_demo.vhd +d82f1bd0599de6894c099ad6416a991 +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# include_file { +|user|matilail|funbase|opencores_lib|trunk|tut|ip.hwp.accelerator|port_blinker|1.0|src|port_blinker.vhd +6ad6d680d0e2cd2c32135b7829ff2d0 +|user|matilail|funbase|opencores_lib|trunk|tut|ip.hwp.accelerator|sig_gen|1.0|src|sig_gen.vhd +d3cb4f38966ab5c1efe7799a8a75aa52 +} +# hierarchies { +| +} +# macro_sequence + +# end +# entity +port_blinker +# storage +db|altera_de_II_demo.(1).cnf +db|altera_de_II_demo.(1).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +|user|matilail|funbase|opencores_lib|trunk|tut|ip.hwp.accelerator|port_blinker|1.0|src|port_blinker.vhd +6ad6d680d0e2cd2c32135b7829ff2d0 +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# user_parameter { +signal_width +32 +PARAMETER_SIGNED_DEC +USR + constraint(val_in) +31 downto 0 +PARAMETER_STRING +USR +} +# hierarchies { +port_blinker:port_blinker_1 +} +# macro_sequence + +# end +# entity +sig_gen +# storage +db|altera_de_II_demo.(2).cnf +db|altera_de_II_demo.(2).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +|user|matilail|funbase|opencores_lib|trunk|tut|ip.hwp.accelerator|sig_gen|1.0|src|sig_gen.vhd +d3cb4f38966ab5c1efe7799a8a75aa52 +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# user_parameter { +signal_val +100000000 +PARAMETER_SIGNED_DEC +USR +signal_width +32 +PARAMETER_SIGNED_DEC +USR + constraint(sig_out) +31 downto 0 +PARAMETER_STRING +USR +} +# hierarchies { +sig_gen:sig_gen_1 +} +# macro_sequence + +# end +# complete + Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm_labs.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm_labs.ddb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm_labs.ddb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm_labs.ddb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm_labs.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.kpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.kpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.kpt (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.rpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.rpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.rpt (revision 24) @@ -0,0 +1,301 @@ +Analysis & Synthesis report for altera_de_II_demo +Fri Oct 28 11:32:34 2011 +Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Multiplexer Restructuring Statistics (Restructuring Performed) + 10. Parameter Settings for User Entity Instance: port_blinker:port_blinker_1 + 11. Parameter Settings for User Entity Instance: sig_gen:sig_gen_1 + 12. Elapsed Time Per Partition + 13. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2011 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Fri Oct 28 11:32:34 2011 ; +; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ; +; Revision Name ; altera_de_II_demo ; +; Top-level Entity Name ; altera_de_II_demo ; +; Family ; Cyclone II ; +; Total logic elements ; 46 ; +; Total combinational functions ; 45 ; +; Dedicated logic registers ; 35 ; +; Total registers ; 35 ; +; Total pins ; 4 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C35F672C6 ; ; +; Top-level entity name ; altera_de_II_demo ; altera_de_II_demo ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 0.0% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------+ +; ../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd ; +; ../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd ; +; ../vhd/altera_de_II_demo.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd ; ++----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 46 ; +; ; ; +; Total combinational functions ; 45 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 11 ; +; -- 3 input functions ; 2 ; +; -- <=2 input functions ; 32 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 14 ; +; -- arithmetic mode ; 31 ; +; ; ; +; Total registers ; 35 ; +; -- Dedicated logic registers ; 35 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 4 ; +; Maximum fan-out node ; clk ; +; Maximum fan-out ; 35 ; +; Total fan-out ; 251 ; +; Average fan-out ; 2.99 ; ++---------------------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------+--------------+ +; |altera_de_II_demo ; 45 (0) ; 35 (0) ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; |altera_de_II_demo ; ; +; |port_blinker:port_blinker_1| ; 44 (44) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |altera_de_II_demo|port_blinker:port_blinker_1 ; ; +; |sig_gen:sig_gen_1| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |altera_de_II_demo|sig_gen:sig_gen_1 ; ; ++----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 35 ; +; Number of registers using Synchronous Clear ; 32 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 35 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+-------------------------------------------------------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+-------------------------------------------------------------+----------------------------+ +; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; |altera_de_II_demo|port_blinker:port_blinker_1|val_cnt_r[0] ; ; ++--------------------+-----------+---------------+----------------------+------------------------+-------------------------------------------------------------+----------------------------+ + + ++--------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: port_blinker:port_blinker_1 ; ++----------------+-------+-------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------+ +; signal_width ; 32 ; Signed Integer ; ++----------------+-------+-------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: sig_gen:sig_gen_1 ; ++----------------+-----------+-----------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-----------+-----------------------------------+ +; signal_val ; 100000000 ; Signed Integer ; +; signal_width ; 32 ; Signed Integer ; ++----------------+-----------+-----------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + Info: Processing started: Fri Oct 28 11:32:28 2011 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd + Info: Found design unit 1: sig_gen-rtl + Info: Found entity 1: sig_gen +Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd + Info: Found design unit 1: port_blinker-rtl + Info: Found entity 1: port_blinker +Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd + Info: Found design unit 1: altera_de_II_demo-structural + Info: Found entity 1: altera_de_II_demo +Info: Elaborating entity "altera_de_II_demo" for the top level hierarchy +Info: Elaborating entity "port_blinker" for hierarchy "port_blinker:port_blinker_1" +Info: Elaborating entity "sig_gen" for hierarchy "sig_gen:sig_gen_1" +Info: Generating hard_block partition "hard_block:auto_generated_inst" +Info: Implemented 50 device resources after synthesis - the final resource count might be different + Info: Implemented 3 input pins + Info: Implemented 1 output pins + Info: Implemented 46 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 250 megabytes + Info: Processing ended: Fri Oct 28 11:32:34 2011 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:02 + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.summary =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.summary (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.summary (revision 24) @@ -0,0 +1,29 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow Model Setup 'clk' +Slack : -3.010 +TNS : -94.090 + +Type : Slow Model Hold 'clk' +Slack : 0.391 +TNS : 0.000 + +Type : Slow Model Minimum Pulse Width 'clk' +Slack : -1.380 +TNS : -36.380 + +Type : Fast Model Setup 'clk' +Slack : -0.845 +TNS : -25.749 + +Type : Fast Model Hold 'clk' +Slack : 0.215 +TNS : 0.000 + +Type : Fast Model Minimum Pulse Width 'clk' +Slack : -1.380 +TNS : -36.380 + +------------------------------------------------------------ Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.asm.rpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.asm.rpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.asm.rpt (revision 24) @@ -0,0 +1,130 @@ +Assembler report for altera_de_II_demo +Fri Oct 28 11:32:49 2011 +Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof + 6. Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2011 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Fri Oct 28 11:32:49 2011 ; +; Revision Name ; altera_de_II_demo ; +; Top-level Entity Name ; altera_de_II_demo ; +; Family ; Cyclone II ; +; Device ; EP2C35F672C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++----------------------------------------------------------------------------------------------------------+ +; File Name ; ++----------------------------------------------------------------------------------------------------------+ +; D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof ; +; D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof ; ++----------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof ; ++----------------+-------------------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-------------------------------------------------------------------------------------------------------------------+ +; Device ; EP2C35F672C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x002E88AB ; ++----------------+-------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof ; ++--------------------+---------------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+---------------------------------------------------------------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1C7755AE ; +; Compression Ratio ; 3 ; ++--------------------+---------------------------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + Info: Processing started: Fri Oct 28 11:32:46 2011 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 271 megabytes + Info: Processing ended: Fri Oct 28 11:32:49 2011 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.done =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.done (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.done (revision 24) @@ -0,0 +1 @@ +Fri Oct 28 11:32:50 2011 Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pin =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pin (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pin (revision 24) @@ -0,0 +1,742 @@ + -- Copyright (C) 1991-2011 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version +CHIP "altera_de_II_demo" ASSIGNED TO AN: EP2C35F672C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A2 : gnd : : : : +VCCIO3 : A3 : power : : 3.3V : 3 : +RESERVED_INPUT : A4 : : : : 3 : +RESERVED_INPUT : A5 : : : : 3 : +RESERVED_INPUT : A6 : : : : 3 : +RESERVED_INPUT : A7 : : : : 3 : +RESERVED_INPUT : A8 : : : : 3 : +RESERVED_INPUT : A9 : : : : 3 : +RESERVED_INPUT : A10 : : : : 3 : +VCCIO3 : A11 : power : : 3.3V : 3 : +GND : A12 : gnd : : : : +GND+ : A13 : : : : 4 : +RESERVED_INPUT : A14 : : : : 4 : +GND : A15 : gnd : : : : +VCCIO4 : A16 : power : : 3.3V : 4 : +RESERVED_INPUT : A17 : : : : 4 : +RESERVED_INPUT : A18 : : : : 4 : +RESERVED_INPUT : A19 : : : : 4 : +RESERVED_INPUT : A20 : : : : 4 : +RESERVED_INPUT : A21 : : : : 4 : +RESERVED_INPUT : A22 : : : : 4 : +RESERVED_INPUT : A23 : : : : 4 : +VCCIO4 : A24 : power : : 3.3V : 4 : +GND : A25 : gnd : : : : +RESERVED_INPUT : AA1 : : : : 1 : +RESERVED_INPUT : AA2 : : : : 1 : +RESERVED_INPUT : AA3 : : : : 1 : +RESERVED_INPUT : AA4 : : : : 1 : +RESERVED_INPUT : AA5 : : : : 1 : +RESERVED_INPUT : AA6 : : : : 1 : +RESERVED_INPUT : AA7 : : : : 1 : +VCCA_PLL1 : AA8 : power : : 1.2V : : +RESERVED_INPUT : AA9 : : : : 8 : +RESERVED_INPUT : AA10 : : : : 8 : +RESERVED_INPUT : AA11 : : : : 8 : +RESERVED_INPUT : AA12 : : : : 8 : +RESERVED_INPUT : AA13 : : : : 7 : +RESERVED_INPUT : AA14 : : : : 7 : +RESERVED_INPUT : AA15 : : : : 7 : +RESERVED_INPUT : AA16 : : : : 7 : +RESERVED_INPUT : AA17 : : : : 7 : +RESERVED_INPUT : AA18 : : : : 7 : +VCCA_PLL4 : AA19 : power : : 1.2V : : +RESERVED_INPUT : AA20 : : : : 7 : +GND_PLL4 : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +RESERVED_INPUT : AA23 : : : : 6 : +RESERVED_INPUT : AA24 : : : : 6 : +RESERVED_INPUT : AA25 : : : : 6 : +RESERVED_INPUT : AA26 : : : : 6 : +RESERVED_INPUT : AB1 : : : : 1 : +RESERVED_INPUT : AB2 : : : : 1 : +RESERVED_INPUT : AB3 : : : : 1 : +RESERVED_INPUT : AB4 : : : : 1 : +VCCIO1 : AB5 : power : : 3.3V : 1 : +VCCIO8 : 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: input : : : 2 : +TDO : M7 : output : : : 2 : +TDI : M8 : input : : : 2 : +VCCIO2 : M9 : power : : 3.3V : 2 : +VCCINT : M10 : power : : 1.2V : : +VCCINT : M11 : power : : 1.2V : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +GND : M14 : gnd : : : : +GND : M15 : gnd : : : : +VCCINT : M16 : power : : 1.2V : : +VCCINT : M17 : power : : 1.2V : : +VCCIO5 : M18 : power : : 3.3V : 5 : +RESERVED_INPUT : M19 : : : : 5 : +RESERVED_INPUT : M20 : : : : 5 : +RESERVED_INPUT : M21 : : : : 5 : +RESERVED_INPUT : M22 : : : : 5 : +RESERVED_INPUT : M23 : : : : 5 : +RESERVED_INPUT : M24 : : : : 5 : +RESERVED_INPUT : M25 : : : : 5 : +GND : M26 : gnd : : : : +GND+ : N1 : : : : 2 : +clk : N2 : input : 3.3-V LVTTL : : 2 : Y +DATA0 : N3 : input : : : 2 : +nCE : N4 : : : : 2 : +VCCIO2 : N5 : power : : 3.3V : 2 : +DCLK : N6 : : : : 2 : +nCONFIG : N7 : : : : 2 : +GND : N8 : gnd : : : : +RESERVED_INPUT : N9 : : : : 2 : +VCCINT : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +GND : N14 : gnd : : : : +GND : N15 : gnd : : : : +GND : N16 : gnd : : : : +VCCINT : N17 : power : : 1.2V : : +RESERVED_INPUT : N18 : : : : 5 : +GND : N19 : gnd : : : : +RESERVED_INPUT : N20 : : : : 5 : +NC : N21 : : : : : +VCCIO5 : N22 : power : : 3.3V : 5 : +RESERVED_INPUT : N23 : : : : 5 : +RESERVED_INPUT : N24 : : : : 5 : +rst_n : N25 : input : 3.3-V LVTTL : : 5 : Y +GND+ : N26 : : : : 5 : +GND+ : P1 : : : : 1 : +GND+ : P2 : : : : 1 : +RESERVED_INPUT : P3 : : : : 1 : +RESERVED_INPUT : P4 : : : : 1 : +VCCIO1 : P5 : power : : 3.3V : 1 : +RESERVED_INPUT : P6 : : : : 1 : +RESERVED_INPUT : P7 : : : : 1 : +GND : P8 : gnd : : : : +RESERVED_INPUT : P9 : : : : 2 : +VCCINT : P10 : power : : 1.2V : : +GND : P11 : gnd : : : : +GND : P12 : gnd : : : : +GND : P13 : gnd : : : : +GND : P14 : gnd : : : : +GND : P15 : gnd : : : : +GND : P16 : gnd : : : : +RESERVED_INPUT : P17 : : : : 6 : +RESERVED_INPUT : P18 : : : : 5 : +GND : P19 : gnd : : : : +MSEL0 : P20 : : : : 6 : +MSEL1 : P21 : : : : 6 : +VCCIO6 : P22 : power : : 3.3V : 6 : +RESERVED_INPUT : P23 : : : : 6 : +RESERVED_INPUT : P24 : : : : 6 : +GND+ : P25 : : : : 6 : +GND+ : P26 : : : : 6 : +GND : R1 : gnd : : : : +RESERVED_INPUT : R2 : : : : 1 : +RESERVED_INPUT : R3 : : : : 1 : +RESERVED_INPUT : R4 : : : : 1 : +RESERVED_INPUT : R5 : : : : 1 : +RESERVED_INPUT : R6 : : : : 1 : +RESERVED_INPUT : R7 : : : : 1 : +RESERVED_INPUT : R8 : : : : 1 : +VCCIO1 : R9 : power : : 3.3V : 1 : +VCCINT : R10 : power : : 1.2V : : +VCCINT : R11 : power : : 1.2V : : +GND : R12 : gnd : : : : +GND : R13 : gnd : : : : +GND : R14 : gnd : : : : +GND : R15 : gnd : : : : +VCCINT : R16 : power : : 1.2V : : +RESERVED_INPUT : R17 : : : : 6 : +VCCIO6 : R18 : power : : 3.3V : 6 : +RESERVED_INPUT : R19 : : : : 6 : +RESERVED_INPUT : R20 : : : : 6 : +GND : R21 : gnd : : : : +nSTATUS : R22 : : : : 6 : +CONF_DONE : R23 : : : : 6 : +RESERVED_INPUT : R24 : : : : 6 : +RESERVED_INPUT : R25 : : : : 6 : +GND : R26 : gnd : : : : +VCCIO1 : T1 : power : : 3.3V : 1 : +RESERVED_INPUT : T2 : : : : 1 : +RESERVED_INPUT : T3 : : : : 1 : +RESERVED_INPUT : T4 : : : : 1 : +GND : T5 : gnd : : : : +RESERVED_INPUT : T6 : : : : 1 : +RESERVED_INPUT : T7 : : : : 1 : +RESERVED_INPUT : T8 : : : : 1 : +RESERVED_INPUT : T9 : : : : 1 : +RESERVED_INPUT : T10 : : : : 1 : +VCCINT : T11 : power : : 1.2V : : +GND : T12 : gnd : : : : +GND : T13 : gnd : : : : +GND : T14 : gnd : : : : +GND : T15 : gnd : : : : +VCCINT : T16 : power : : 1.2V : : +RESERVED_INPUT : T17 : : : : 6 : +RESERVED_INPUT : T18 : : : : 6 : +RESERVED_INPUT : T19 : : : : 6 : +RESERVED_INPUT : T20 : : : : 6 : +RESERVED_INPUT : T21 : : : : 6 : +RESERVED_INPUT : T22 : : : : 6 : +RESERVED_INPUT : T23 : : : : 6 : +RESERVED_INPUT : T24 : : : : 6 : +RESERVED_INPUT : T25 : : : : 6 : +VCCIO6 : T26 : power : : 3.3V : 6 : +RESERVED_INPUT : U1 : : : : 1 : +RESERVED_INPUT : U2 : : : : 1 : +RESERVED_INPUT : U3 : : : : 1 : +RESERVED_INPUT : U4 : : : : 1 : +RESERVED_INPUT : U5 : : : : 1 : +RESERVED_INPUT : U6 : : : : 1 : +RESERVED_INPUT : U7 : : : : 1 : +GND : U8 : gnd : : : : +RESERVED_INPUT : U9 : : : : 1 : +RESERVED_INPUT : U10 : : : : 1 : +VCCINT : U11 : power : : 1.2V : : +RESERVED_INPUT : U12 : : : : 8 : +VCCINT : U13 : power : : 1.2V : : +VCCINT : U14 : power : : 1.2V : : +VCCINT : U15 : power : : 1.2V : : +VCCINT : U16 : power : : 1.2V : : +RESERVED_INPUT : U17 : : : : 7 : +RESERVED_INPUT : U18 : : : : 7 : +GND : U19 : gnd : : : : +RESERVED_INPUT : U20 : : : : 6 : +RESERVED_INPUT : U21 : : : : 6 : +RESERVED_INPUT : U22 : : : : 6 : +RESERVED_INPUT : U23 : : : : 6 : +RESERVED_INPUT : U24 : : : : 6 : +RESERVED_INPUT : U25 : : : : 6 : +RESERVED_INPUT : U26 : : : : 6 : +RESERVED_INPUT : V1 : : : : 1 : +toggle_in : V2 : input : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT : V3 : : : : 1 : +RESERVED_INPUT : V4 : : : : 1 : +RESERVED_INPUT : V5 : : : : 1 : +RESERVED_INPUT : V6 : : : : 1 : +RESERVED_INPUT : V7 : : : : 1 : +VCCIO1 : V8 : power : : 3.3V : 1 : +RESERVED_INPUT : V9 : : : : 8 : +RESERVED_INPUT : V10 : : : : 8 : +RESERVED_INPUT : V11 : : : : 8 : +VCCIO8 : V12 : power : : 3.3V : 8 : +RESERVED_INPUT : V13 : : : : 8 : +RESERVED_INPUT : V14 : : : : 8 : +VCCIO7 : V15 : power : : 3.3V : 7 : +VCCINT : V16 : power : : 1.2V : : +RESERVED_INPUT : V17 : : : : 7 : +RESERVED_INPUT : V18 : : : : 7 : +VCCIO6 : V19 : power : : 3.3V : 6 : +RESERVED_INPUT : V20 : : : : 6 : +RESERVED_INPUT : V21 : : : : 6 : +RESERVED_INPUT : V22 : : : : 6 : +RESERVED_INPUT : V23 : : : : 6 : +RESERVED_INPUT : V24 : : : : 6 : +RESERVED_INPUT : V25 : : : : 6 : +RESERVED_INPUT : V26 : : : : 6 : +RESERVED_INPUT : W1 : : : : 1 : +RESERVED_INPUT : W2 : : : : 1 : +RESERVED_INPUT : W3 : : : : 1 : +RESERVED_INPUT : W4 : : : : 1 : +GND : W5 : gnd : : : : +RESERVED_INPUT : W6 : : : : 1 : +GND_PLL1 : W7 : gnd : : : : +RESERVED_INPUT : W8 : : : : 8 : +VCCIO8 : W9 : power : : 3.3V : 8 : +RESERVED_INPUT : W10 : : : : 8 : +RESERVED_INPUT : W11 : : : : 8 : +RESERVED_INPUT : W12 : : : : 8 : +GND : W13 : gnd : : : : +GND : W14 : gnd : : : : +RESERVED_INPUT : W15 : : : : 7 : +RESERVED_INPUT : W16 : : : : 7 : +RESERVED_INPUT : W17 : : : : 7 : +VCCIO7 : W18 : power : : 3.3V : 7 : +RESERVED_INPUT : W19 : : : : 7 : +GND_PLL4 : W20 : gnd : : : : +RESERVED_INPUT : W21 : : : : 6 : +GND : W22 : gnd : : : : +RESERVED_INPUT : W23 : : : : 6 : +RESERVED_INPUT : W24 : : : : 6 : +RESERVED_INPUT : W25 : : : : 6 : +RESERVED_INPUT : W26 : : : : 6 : +RESERVED_INPUT : Y1 : : : : 1 : +NC : Y2 : : : : : +RESERVED_INPUT : Y3 : : : : 1 : +RESERVED_INPUT : Y4 : : : : 1 : +RESERVED_INPUT : Y5 : : : : 1 : +GND_PLL1 : Y6 : gnd : : : : +VCCD_PLL1 : Y7 : power : : 1.2V : : +GNDA_PLL1 : Y8 : gnd : : : : +GND : Y9 : gnd : : : : +RESERVED_INPUT : Y10 : : : : 8 : +RESERVED_INPUT : Y11 : : : : 8 : +RESERVED_INPUT : Y12 : : : : 8 : +RESERVED_INPUT : Y13 : : : : 7 : +RESERVED_INPUT : Y14 : : : : 7 : +RESERVED_INPUT : Y15 : : : : 7 : +RESERVED_INPUT : Y16 : : : : 7 : +GND : Y17 : gnd : : : : +RESERVED_INPUT : Y18 : : : : 7 : +GNDA_PLL4 : Y19 : gnd : : : : +VCCD_PLL4 : Y20 : power : : 1.2V : : +RESERVED_INPUT : Y21 : : : : 6 : +RESERVED_INPUT : Y22 : : : : 6 : +RESERVED_INPUT : Y23 : : : : 6 : +RESERVED_INPUT : Y24 : : : : 6 : +RESERVED_INPUT : Y25 : : : : 6 : +RESERVED_INPUT : Y26 : : : : 6 : Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qpf =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qpf (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qpf (revision 24) @@ -0,0 +1,12 @@ +# ----------------------------------------------------------- # + +# Quartus project generated by Kactus2 +# Date created 15:33:10 27.10.2011 + +# ----------------------------------------------------------- # + +QUARTUS_VERSION = "10.0" + +# Revisions + +PROJECT_REVISION = "altera_de_II_demo" Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.rpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.rpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.rpt (revision 24) @@ -0,0 +1,2341 @@ +Fitter report for altera_de_II_demo +Fri Oct 28 11:32:43 2011 +Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. Output Pin Default Load For Reported TCO + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Control Signals + 21. Global & Other Fast Signals + 22. Non-Global High Fan-Out Signals + 23. Interconnect Usage Summary + 24. LAB Logic Elements + 25. LAB-wide Signals + 26. LAB Signals Sourced + 27. LAB Signals Sourced Out + 28. LAB Distinct Inputs + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2011 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+------------------------------------------------+ +; Fitter Status ; Successful - Fri Oct 28 11:32:43 2011 ; +; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ; +; Revision Name ; altera_de_II_demo ; +; Top-level Entity Name ; altera_de_II_demo ; +; Family ; Cyclone II ; +; Device ; EP2C35F672C6 ; +; Timing Models ; Final ; +; Total logic elements ; 46 / 33,216 ( < 1 % ) ; +; Total combinational functions ; 45 / 33,216 ( < 1 % ) ; +; Dedicated logic registers ; 35 / 33,216 ( < 1 % ) ; +; Total registers ; 35 ; +; Total pins ; 4 / 475 ( < 1 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 483,840 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C35F672C6 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.22 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; 12.5% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+---------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+---------------+---------------+----------------+ +; Location ; ; ; AUD_ADCDAT ; PIN_B5 ; QSF Assignment ; +; Location ; ; ; AUD_ADCLRCK ; PIN_C5 ; QSF Assignment ; +; Location ; ; ; AUD_BCLK ; PIN_B4 ; QSF Assignment ; +; Location ; ; ; AUD_DACDAT ; PIN_A4 ; QSF Assignment ; +; Location ; ; ; AUD_DACLRCK ; PIN_C6 ; QSF Assignment ; +; Location ; ; ; AUD_XCK ; PIN_A5 ; QSF Assignment ; +; Location ; ; ; CLOCK_27 ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[0] ; PIN_T6 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[10] ; PIN_Y1 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[11] ; PIN_V5 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[1] ; PIN_V4 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[2] ; PIN_V3 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[3] ; PIN_W2 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[4] ; PIN_W1 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[5] ; PIN_U6 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[6] ; PIN_U7 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[7] ; PIN_U5 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[8] ; PIN_W4 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[9] ; PIN_W3 ; QSF Assignment ; +; Location ; ; ; DRAM_BA_0 ; PIN_AE2 ; QSF Assignment ; +; Location ; ; ; DRAM_BA_1 ; PIN_AE3 ; QSF Assignment ; +; Location ; ; ; DRAM_CAS_N ; PIN_AB3 ; QSF Assignment ; +; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ; +; Location ; ; ; DRAM_CLK ; PIN_AA7 ; QSF Assignment ; +; Location ; ; ; DRAM_CS_N ; PIN_AC3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[0] ; PIN_V6 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[11] ; PIN_AA4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[12] ; PIN_AA3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[13] ; PIN_AC2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[14] ; PIN_AC1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[15] ; PIN_AA5 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[1] ; PIN_AA2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[2] ; PIN_AA1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[3] ; PIN_Y3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[4] ; PIN_Y4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[5] ; PIN_R8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[6] ; PIN_T8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[7] ; PIN_V7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[8] ; PIN_W6 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[9] ; PIN_AB2 ; QSF Assignment ; +; Location ; ; ; DRAM_LDQM ; PIN_AD2 ; QSF Assignment ; +; Location ; ; ; DRAM_RAS_N ; PIN_AB4 ; QSF Assignment ; +; Location ; ; ; DRAM_UDQM ; PIN_Y5 ; QSF Assignment ; +; Location ; ; ; DRAM_WE_N ; PIN_AD3 ; QSF Assignment ; +; Location ; ; ; ENET_CLK ; PIN_B24 ; QSF Assignment ; +; Location ; ; ; ENET_CMD ; PIN_A21 ; QSF Assignment ; +; Location ; ; ; ENET_CS_N ; PIN_A23 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[0] ; PIN_D17 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[10] ; PIN_C19 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[11] ; PIN_D19 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[12] ; PIN_B19 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[13] ; PIN_A19 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[14] ; PIN_E18 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[15] ; PIN_D18 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[1] ; PIN_C17 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[2] ; PIN_B18 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[3] ; PIN_A18 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[4] ; PIN_B17 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[5] ; PIN_A17 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[6] ; PIN_B16 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[7] ; PIN_B15 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[8] ; PIN_B20 ; QSF Assignment ; +; Location ; ; ; ENET_DATA[9] ; PIN_A20 ; QSF Assignment ; +; Location ; ; ; ENET_INT ; PIN_B21 ; QSF Assignment ; +; Location ; ; ; ENET_RD_N ; PIN_A22 ; QSF Assignment ; +; Location ; ; ; ENET_RST_N ; PIN_B23 ; QSF Assignment ; +; Location ; ; ; ENET_WR_N ; PIN_B22 ; QSF Assignment ; +; Location ; ; ; EXT_CLOCK ; PIN_P26 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[0] ; PIN_AC18 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[10] ; PIN_AE17 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[11] ; PIN_AF17 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[12] ; PIN_W16 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[13] ; PIN_W15 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[14] ; PIN_AC16 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[15] ; PIN_AD16 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[16] ; PIN_AE16 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[17] ; PIN_AC15 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[18] ; PIN_AB15 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[19] ; PIN_AA15 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[1] ; PIN_AB18 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[20] ; PIN_Y15 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[21] ; PIN_Y14 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[2] ; PIN_AE19 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[3] ; PIN_AF19 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[4] ; PIN_AE18 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[5] ; PIN_AF18 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[6] ; PIN_Y16 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[7] ; PIN_AA16 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[8] ; PIN_AD17 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[9] ; PIN_AC17 ; QSF Assignment ; +; Location ; ; ; FL_CE_N ; PIN_V17 ; QSF Assignment ; +; Location ; ; ; FL_DQ[0] ; PIN_AD19 ; QSF Assignment ; +; Location ; ; ; FL_DQ[1] ; PIN_AC19 ; QSF Assignment ; +; Location ; ; ; FL_DQ[2] ; PIN_AF20 ; QSF Assignment ; +; Location ; ; ; FL_DQ[3] ; PIN_AE20 ; QSF Assignment ; +; Location ; ; ; FL_DQ[4] ; PIN_AB20 ; QSF Assignment ; +; Location ; ; ; FL_DQ[5] ; PIN_AC20 ; QSF Assignment ; +; Location ; ; ; FL_DQ[6] ; PIN_AF21 ; QSF Assignment ; +; Location ; ; ; FL_DQ[7] ; PIN_AE21 ; QSF Assignment ; +; Location ; ; ; FL_OE_N ; PIN_W17 ; QSF Assignment ; +; Location ; ; ; FL_RST_N ; PIN_AA18 ; QSF Assignment ; +; Location ; ; ; FL_WE_N ; PIN_AA17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[0] ; PIN_D25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[10] ; PIN_N18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[11] ; PIN_P18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[12] ; PIN_G23 ; QSF Assignment ; +; Location ; ; ; GPIO_0[13] ; PIN_G24 ; QSF Assignment ; +; Location ; ; ; GPIO_0[14] ; PIN_K22 ; QSF Assignment ; +; Location ; ; ; GPIO_0[15] ; PIN_G25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[16] ; PIN_H23 ; QSF Assignment ; +; Location ; ; ; GPIO_0[17] ; PIN_H24 ; QSF Assignment ; +; Location ; ; ; GPIO_0[18] ; PIN_J23 ; QSF Assignment ; +; Location ; ; ; GPIO_0[19] ; PIN_J24 ; QSF Assignment ; +; Location ; ; ; GPIO_0[1] ; PIN_J22 ; QSF Assignment ; +; Location ; ; ; GPIO_0[20] ; PIN_H25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[21] ; PIN_H26 ; QSF Assignment ; +; Location ; ; ; GPIO_0[22] ; PIN_H19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[23] ; PIN_K18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[24] ; PIN_K19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[25] ; PIN_K21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[26] ; PIN_K23 ; QSF Assignment ; +; Location ; ; ; GPIO_0[27] ; PIN_K24 ; QSF Assignment ; +; Location ; ; ; GPIO_0[28] ; PIN_L21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[29] ; PIN_L20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[2] ; PIN_E26 ; QSF Assignment ; +; Location ; ; ; GPIO_0[30] ; PIN_J25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[31] ; PIN_J26 ; QSF Assignment ; +; Location ; ; ; GPIO_0[32] ; PIN_L23 ; QSF Assignment ; +; Location ; ; ; GPIO_0[33] ; PIN_L24 ; QSF Assignment ; +; Location ; ; ; GPIO_0[34] ; PIN_L25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[35] ; PIN_L19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[3] ; PIN_E25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[4] ; PIN_F24 ; QSF Assignment ; +; Location ; ; ; GPIO_0[5] ; PIN_F23 ; QSF Assignment ; +; Location ; ; ; GPIO_0[6] ; PIN_J21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[7] ; PIN_J20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[8] ; PIN_F25 ; QSF Assignment ; +; Location ; ; ; GPIO_0[9] ; PIN_F26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[0] ; PIN_K25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[10] ; PIN_N24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[11] ; PIN_P24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[12] ; PIN_R25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[13] ; PIN_R24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[14] ; PIN_R20 ; QSF Assignment ; +; Location ; ; ; GPIO_1[15] ; PIN_T22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[16] ; PIN_T23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[17] ; PIN_T24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[18] ; PIN_T25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[19] ; PIN_T18 ; QSF Assignment ; +; Location ; ; ; GPIO_1[1] ; PIN_K26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[20] ; PIN_T21 ; QSF Assignment ; +; Location ; ; ; GPIO_1[21] ; PIN_T20 ; QSF Assignment ; +; Location ; ; ; GPIO_1[22] ; PIN_U26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[23] ; PIN_U25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[24] ; PIN_U23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[25] ; PIN_U24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[26] ; PIN_R19 ; QSF Assignment ; +; Location ; ; ; GPIO_1[27] ; PIN_T19 ; QSF Assignment ; +; Location ; ; ; GPIO_1[28] ; PIN_U20 ; QSF Assignment ; +; Location ; ; ; GPIO_1[29] ; PIN_U21 ; QSF Assignment ; +; Location ; ; ; GPIO_1[2] ; PIN_M22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[30] ; PIN_V26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[31] ; PIN_V25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[32] ; PIN_V24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[33] ; PIN_V23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[34] ; PIN_W25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[35] ; PIN_W23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[3] ; PIN_M23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[4] ; PIN_M19 ; QSF Assignment ; +; Location ; ; ; GPIO_1[5] ; PIN_M20 ; QSF Assignment ; +; Location ; ; ; GPIO_1[6] ; PIN_N20 ; QSF Assignment ; +; Location ; ; ; GPIO_1[7] ; PIN_M21 ; QSF Assignment ; +; Location ; ; ; GPIO_1[8] ; PIN_M24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[9] ; PIN_M25 ; QSF Assignment ; +; Location ; ; ; HEX0[0] ; PIN_AF10 ; QSF Assignment ; +; Location ; ; ; HEX0[1] ; PIN_AB12 ; QSF Assignment ; +; Location ; ; ; HEX0[2] ; PIN_AC12 ; QSF Assignment ; +; Location ; ; ; HEX0[3] ; PIN_AD11 ; QSF Assignment ; +; Location ; ; ; HEX0[4] ; PIN_AE11 ; QSF Assignment ; +; Location ; ; ; HEX0[5] ; PIN_V14 ; QSF Assignment ; +; Location ; ; ; HEX0[6] ; PIN_V13 ; QSF Assignment ; +; Location ; ; ; HEX1[0] ; PIN_V20 ; QSF Assignment ; +; Location ; ; ; HEX1[1] ; PIN_V21 ; QSF Assignment ; +; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ; +; Location ; ; ; HEX1[3] ; PIN_Y22 ; QSF Assignment ; +; Location ; ; ; HEX1[4] ; PIN_AA24 ; QSF Assignment ; +; Location ; ; ; HEX1[5] ; PIN_AA23 ; QSF Assignment ; +; Location ; ; ; HEX1[6] ; PIN_AB24 ; QSF Assignment ; +; Location ; ; ; HEX2[0] ; PIN_AB23 ; QSF Assignment ; +; Location ; ; ; HEX2[1] ; PIN_V22 ; QSF Assignment ; +; Location ; ; ; HEX2[2] ; PIN_AC25 ; QSF Assignment ; +; Location ; ; ; HEX2[3] ; PIN_AC26 ; QSF Assignment ; +; Location ; ; ; HEX2[4] ; PIN_AB26 ; QSF Assignment ; +; Location ; ; ; HEX2[5] ; PIN_AB25 ; QSF Assignment ; +; Location ; ; ; HEX2[6] ; PIN_Y24 ; QSF Assignment ; +; Location ; ; ; HEX3[0] ; PIN_Y23 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_AA25 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_AA26 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_Y26 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_Y25 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_U22 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_W24 ; QSF Assignment ; +; Location ; ; ; HEX4[0] ; PIN_U9 ; QSF Assignment ; +; Location ; ; ; HEX4[1] ; PIN_U1 ; QSF Assignment ; +; Location ; ; ; HEX4[2] ; PIN_U2 ; QSF Assignment ; +; Location ; ; ; HEX4[3] ; PIN_T4 ; QSF Assignment ; +; Location ; ; ; HEX4[4] ; PIN_R7 ; QSF Assignment ; +; Location ; ; ; HEX4[5] ; PIN_R6 ; QSF Assignment ; +; Location ; ; ; HEX4[6] ; PIN_T3 ; QSF Assignment ; +; Location ; ; ; HEX5[0] ; PIN_T2 ; QSF Assignment ; +; Location ; ; ; HEX5[1] ; PIN_P6 ; QSF Assignment ; +; Location ; ; ; HEX5[2] ; PIN_P7 ; QSF Assignment ; +; Location ; ; ; HEX5[3] ; PIN_T9 ; QSF Assignment ; +; Location ; ; ; HEX5[4] ; PIN_R5 ; QSF Assignment ; +; Location ; ; ; HEX5[5] ; PIN_R4 ; QSF Assignment ; +; Location ; ; ; HEX5[6] ; PIN_R3 ; QSF Assignment ; +; Location ; ; ; HEX6[0] ; PIN_R2 ; QSF Assignment ; +; Location ; ; ; HEX6[1] ; PIN_P4 ; QSF Assignment ; +; Location ; ; ; HEX6[2] ; PIN_P3 ; QSF Assignment ; +; Location ; ; ; HEX6[3] ; PIN_M2 ; QSF Assignment ; +; Location ; ; ; HEX6[4] ; PIN_M3 ; QSF Assignment ; +; Location ; ; ; HEX6[5] ; PIN_M5 ; QSF Assignment ; +; Location ; ; ; HEX6[6] ; PIN_M4 ; QSF Assignment ; +; Location ; ; ; HEX7[0] ; PIN_L3 ; QSF Assignment ; +; Location ; ; ; HEX7[1] ; PIN_L2 ; QSF Assignment ; +; Location ; ; ; HEX7[2] ; PIN_L9 ; QSF Assignment ; +; Location ; ; ; HEX7[3] ; PIN_L6 ; QSF Assignment ; +; Location ; ; ; HEX7[4] ; PIN_L7 ; QSF Assignment ; +; Location ; ; ; HEX7[5] ; PIN_P9 ; QSF Assignment ; +; Location ; ; ; HEX7[6] ; PIN_N9 ; QSF Assignment ; +; Location ; ; ; I2C_SCLK ; PIN_A6 ; QSF Assignment ; +; Location ; ; ; I2C_SDAT ; PIN_B6 ; QSF Assignment ; +; Location ; ; ; IRDA_RXD ; PIN_AE25 ; QSF Assignment ; +; Location ; ; ; IRDA_TXD ; PIN_AE24 ; QSF Assignment ; +; Location ; ; ; KEY[0] ; PIN_G26 ; QSF Assignment ; +; Location ; ; ; KEY[1] ; PIN_N23 ; QSF Assignment ; +; Location ; ; ; KEY[2] ; PIN_P23 ; QSF Assignment ; +; Location ; ; ; KEY[3] ; PIN_W26 ; QSF Assignment ; +; Location ; ; ; LCD_BLON ; PIN_K2 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[0] ; PIN_J1 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[1] ; PIN_J2 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[2] ; PIN_H1 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[3] ; PIN_H2 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[4] ; PIN_J4 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[5] ; PIN_J3 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[6] ; PIN_H4 ; QSF Assignment ; +; Location ; ; ; LCD_DATA[7] ; PIN_H3 ; QSF Assignment ; +; Location ; ; ; LCD_EN ; PIN_K3 ; QSF Assignment ; +; Location ; ; ; LCD_ON ; PIN_L4 ; QSF Assignment ; +; Location ; ; ; LCD_RS ; PIN_K1 ; QSF Assignment ; +; Location ; ; ; LCD_RW ; PIN_K4 ; QSF Assignment ; +; Location ; ; ; LEDG[1] ; PIN_AF22 ; QSF Assignment ; +; Location ; ; ; LEDG[2] ; PIN_W19 ; QSF Assignment ; +; Location ; ; ; LEDG[3] ; PIN_V18 ; QSF Assignment ; +; Location ; ; ; LEDG[4] ; PIN_U18 ; QSF Assignment ; +; Location ; ; ; LEDG[5] ; PIN_U17 ; QSF Assignment ; +; Location ; ; ; LEDG[6] ; PIN_AA20 ; QSF Assignment ; +; Location ; ; ; LEDG[7] ; PIN_Y18 ; QSF Assignment ; +; Location ; ; ; LEDG[8] ; PIN_Y12 ; QSF Assignment ; +; Location ; ; ; LEDR[10] ; PIN_AA13 ; QSF Assignment ; +; Location ; ; ; LEDR[11] ; PIN_AC14 ; QSF Assignment ; +; Location ; ; ; LEDR[12] ; PIN_AD15 ; QSF Assignment ; +; Location ; ; ; LEDR[13] ; PIN_AE15 ; QSF Assignment ; +; Location ; ; ; LEDR[14] ; PIN_AF13 ; QSF Assignment ; +; Location ; ; ; LEDR[15] ; PIN_AE13 ; QSF Assignment ; +; Location ; ; ; LEDR[16] ; PIN_AE12 ; QSF Assignment ; +; Location ; ; ; LEDR[17] ; PIN_AD12 ; QSF Assignment ; +; Location ; ; ; LEDR[1] ; PIN_AF23 ; QSF Assignment ; +; Location ; ; ; LEDR[2] ; PIN_AB21 ; QSF Assignment ; +; Location ; ; ; LEDR[3] ; PIN_AC22 ; QSF Assignment ; +; Location ; ; ; LEDR[4] ; PIN_AD22 ; QSF Assignment ; +; Location ; ; ; LEDR[5] ; PIN_AD23 ; QSF Assignment ; +; Location ; ; ; LEDR[6] ; PIN_AD21 ; QSF Assignment ; +; Location ; ; ; LEDR[7] ; PIN_AC21 ; QSF Assignment ; +; Location ; ; ; LEDR[8] ; PIN_AA14 ; QSF Assignment ; +; Location ; ; ; LEDR[9] ; PIN_Y13 ; QSF Assignment ; +; Location ; ; ; OTG_ADDR[0] ; PIN_K7 ; QSF Assignment ; +; Location ; ; ; OTG_ADDR[1] ; PIN_F2 ; QSF Assignment ; +; Location ; ; ; OTG_CS_N ; PIN_F1 ; QSF Assignment ; +; Location ; ; ; OTG_DACK0_N ; PIN_C2 ; QSF Assignment ; +; Location ; ; ; OTG_DACK1_N ; PIN_B2 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[0] ; PIN_F4 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[10] ; PIN_K6 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[11] ; PIN_K5 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[12] ; PIN_G4 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[13] ; PIN_G3 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[14] ; PIN_J6 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[15] ; PIN_K8 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[1] ; PIN_D2 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[2] ; PIN_D1 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[3] ; PIN_F7 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[4] ; PIN_J5 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[5] ; PIN_J8 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[8] ; PIN_E2 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[9] ; PIN_E1 ; QSF Assignment ; +; Location ; ; ; OTG_DREQ0 ; PIN_F6 ; QSF Assignment ; +; Location ; ; ; OTG_DREQ1 ; PIN_E5 ; QSF Assignment ; +; Location ; ; ; OTG_FSPEED ; PIN_F3 ; QSF Assignment ; +; Location ; ; ; OTG_INT0 ; PIN_B3 ; QSF Assignment ; +; Location ; ; ; OTG_INT1 ; PIN_C3 ; QSF Assignment ; +; Location ; ; ; OTG_LSPEED ; PIN_G6 ; QSF Assignment ; +; Location ; ; ; OTG_RD_N ; PIN_G2 ; QSF Assignment ; +; Location ; ; ; OTG_RST_N ; PIN_G5 ; QSF Assignment ; +; Location ; ; ; OTG_WR_N ; PIN_G1 ; QSF Assignment ; +; Location ; ; ; PS2_CLK ; PIN_D26 ; QSF Assignment ; +; Location ; ; ; PS2_DAT ; PIN_C24 ; QSF Assignment ; +; Location ; ; ; SD_CLK ; PIN_AD25 ; QSF Assignment ; +; Location ; ; ; SD_CMD ; PIN_Y21 ; QSF Assignment ; +; Location ; ; ; SD_DAT ; PIN_AD24 ; QSF Assignment ; +; Location ; ; ; SD_DAT3 ; PIN_AC23 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[0] ; PIN_AE4 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[10] ; PIN_V10 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[11] ; PIN_V9 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[12] ; PIN_AC7 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[13] ; PIN_W8 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[14] ; PIN_W10 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[15] ; PIN_Y10 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[16] ; PIN_AB8 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[17] ; PIN_AC8 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[1] ; PIN_AF4 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[2] ; PIN_AC5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[3] ; PIN_AC6 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[4] ; PIN_AD4 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[5] ; PIN_AD5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[6] ; PIN_AE5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[7] ; PIN_AF5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[8] ; PIN_AD6 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[9] ; PIN_AD7 ; QSF Assignment ; +; Location ; ; ; SRAM_CE_N ; PIN_AC11 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[0] ; PIN_AD8 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[10] ; PIN_AE8 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[11] ; PIN_AF8 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[12] ; PIN_W11 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[13] ; PIN_W12 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[14] ; PIN_AC9 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[15] ; PIN_AC10 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[1] ; PIN_AE6 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[2] ; PIN_AF6 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[3] ; PIN_AA9 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[4] ; PIN_AA10 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[5] ; PIN_AB10 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[6] ; PIN_AA11 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[7] ; PIN_Y11 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[8] ; PIN_AE7 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[9] ; PIN_AF7 ; QSF Assignment ; +; Location ; ; ; SRAM_LB_N ; PIN_AE9 ; QSF Assignment ; +; Location ; ; ; SRAM_OE_N ; PIN_AD10 ; QSF Assignment ; +; Location ; ; ; SRAM_UB_N ; PIN_AF9 ; QSF Assignment ; +; Location ; ; ; SRAM_WE_N ; PIN_AE10 ; QSF Assignment ; +; Location ; ; ; SW[10] ; PIN_N1 ; QSF Assignment ; +; Location ; ; ; SW[11] ; PIN_P1 ; QSF Assignment ; +; Location ; ; ; SW[12] ; PIN_P2 ; QSF Assignment ; +; Location ; ; ; SW[13] ; PIN_T7 ; QSF Assignment ; +; Location ; ; ; SW[14] ; PIN_U3 ; QSF Assignment ; +; Location ; ; ; SW[15] ; PIN_U4 ; QSF Assignment ; +; Location ; ; ; SW[16] ; PIN_V1 ; QSF Assignment ; +; Location ; ; ; SW[1] ; PIN_N26 ; QSF Assignment ; +; Location ; ; ; SW[2] ; PIN_P25 ; QSF Assignment ; +; Location ; ; ; SW[3] ; PIN_AE14 ; QSF Assignment ; +; Location ; ; ; SW[4] ; PIN_AF14 ; QSF Assignment ; +; Location ; ; ; SW[5] ; PIN_AD13 ; QSF Assignment ; +; Location ; ; ; SW[6] ; PIN_AC13 ; QSF Assignment ; +; Location ; ; ; SW[7] ; PIN_C13 ; QSF Assignment ; +; Location ; ; ; SW[8] ; PIN_B13 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_A13 ; QSF Assignment ; +; Location ; ; ; TCK ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; TCS ; PIN_A14 ; QSF Assignment ; +; Location ; ; ; TDI ; PIN_B14 ; QSF Assignment ; +; Location ; ; ; TDO ; PIN_F14 ; QSF Assignment ; +; Location ; ; ; TD_DATA[0] ; PIN_J9 ; QSF Assignment ; +; Location ; ; ; TD_DATA[1] ; PIN_E8 ; QSF Assignment ; +; Location ; ; ; TD_DATA[2] ; PIN_H8 ; QSF Assignment ; +; Location ; ; ; TD_DATA[3] ; PIN_H10 ; QSF Assignment ; +; Location ; ; ; TD_DATA[4] ; PIN_G9 ; QSF Assignment ; +; Location ; ; ; TD_DATA[5] ; PIN_F9 ; QSF Assignment ; +; Location ; ; ; TD_DATA[6] ; PIN_D7 ; QSF Assignment ; +; Location ; ; ; TD_DATA[7] ; PIN_C7 ; QSF Assignment ; +; Location ; ; ; TD_HS ; PIN_D5 ; QSF Assignment ; +; Location ; ; ; TD_RESET ; PIN_C4 ; QSF Assignment ; +; Location ; ; ; TD_VS ; PIN_K9 ; QSF Assignment ; +; Location ; ; ; UART_RXD ; PIN_C25 ; QSF Assignment ; +; Location ; ; ; UART_TXD ; PIN_B25 ; QSF Assignment ; +; Location ; ; ; VGA_BLANK ; PIN_D6 ; QSF Assignment ; +; Location ; ; ; VGA_B[0] ; PIN_J13 ; QSF Assignment ; +; Location ; ; ; VGA_B[1] ; PIN_J14 ; QSF Assignment ; +; Location ; ; ; VGA_B[2] ; PIN_F12 ; QSF Assignment ; +; Location ; ; ; VGA_B[3] ; PIN_G12 ; QSF Assignment ; +; Location ; ; ; VGA_B[4] ; PIN_J10 ; QSF Assignment ; +; Location ; ; ; VGA_B[5] ; PIN_J11 ; QSF Assignment ; +; Location ; ; ; VGA_B[6] ; PIN_C11 ; QSF Assignment ; +; Location ; ; ; VGA_B[7] ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; VGA_B[8] ; PIN_C12 ; QSF Assignment ; +; Location ; ; ; VGA_B[9] ; PIN_B12 ; QSF Assignment ; +; Location ; ; ; VGA_CLK ; PIN_B8 ; QSF Assignment ; +; Location ; ; ; VGA_G[0] ; PIN_B9 ; QSF Assignment ; +; Location ; ; ; VGA_G[1] ; PIN_A9 ; QSF Assignment ; +; Location ; ; ; VGA_G[2] ; PIN_C10 ; QSF Assignment ; +; Location ; ; ; VGA_G[3] ; PIN_D10 ; QSF Assignment ; +; Location ; ; ; VGA_G[4] ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; VGA_G[5] ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; VGA_G[6] ; PIN_G11 ; QSF Assignment ; +; Location ; ; ; VGA_G[7] ; PIN_D11 ; QSF Assignment ; +; Location ; ; ; VGA_G[8] ; PIN_E12 ; QSF Assignment ; +; Location ; ; ; VGA_G[9] ; PIN_D12 ; QSF Assignment ; +; Location ; ; ; VGA_HS ; PIN_A7 ; QSF Assignment ; +; Location ; ; ; VGA_R[0] ; PIN_C8 ; QSF Assignment ; +; Location ; ; ; VGA_R[1] ; PIN_F10 ; QSF Assignment ; +; Location ; ; ; VGA_R[2] ; PIN_G10 ; QSF Assignment ; +; Location ; ; ; VGA_R[3] ; PIN_D9 ; QSF Assignment ; +; Location ; ; ; VGA_R[4] ; PIN_C9 ; QSF Assignment ; +; Location ; ; ; VGA_R[5] ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; VGA_R[6] ; PIN_H11 ; QSF Assignment ; +; Location ; ; ; VGA_R[7] ; PIN_H12 ; QSF Assignment ; +; Location ; ; ; VGA_R[8] ; PIN_F11 ; QSF Assignment ; +; Location ; ; ; VGA_R[9] ; PIN_E10 ; QSF Assignment ; +; Location ; ; ; VGA_SYNC ; PIN_B7 ; QSF Assignment ; +; Location ; ; ; VGA_VS ; PIN_D8 ; QSF Assignment ; ++----------+----------------+--------------+---------------+---------------+----------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 90 ( 0.00 % ) ; +; -- Achieved ; 0 / 90 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 87 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pin. + + ++-------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------------------------------+ +; Total logic elements ; 46 / 33,216 ( < 1 % ) ; +; -- Combinational with no register ; 11 ; +; -- Register only ; 1 ; +; -- Combinational with a register ; 34 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 11 ; +; -- 3 input functions ; 2 ; +; -- <=2 input functions ; 32 ; +; -- Register only ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 14 ; +; -- arithmetic mode ; 31 ; +; ; ; +; Total registers* ; 35 / 34,593 ( < 1 % ) ; +; -- Dedicated logic registers ; 35 / 33,216 ( < 1 % ) ; +; -- I/O registers ; 0 / 1,377 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 5 / 2,076 ( < 1 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 4 / 475 ( < 1 % ) ; +; -- Clock pins ; 2 / 8 ( 25 % ) ; +; Global signals ; 2 ; +; M4Ks ; 0 / 105 ( 0 % ) ; +; Total block memory bits ; 0 / 483,840 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 483,840 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out node ; clk~clkctrl ; +; Maximum fan-out ; 35 ; +; Highest non-global fan-out signal ; port_blinker:port_blinker_1|val_cnt_r[0]~34 ; +; Highest non-global fan-out ; 32 ; +; Total fan-out ; 253 ; +; Average fan-out ; 2.84 ; ++---------------------------------------------+---------------------------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 46 / 33216 ( < 1 % ) ; 0 / 33216 ( 0 % ) ; +; -- Combinational with no register ; 11 ; 0 ; +; -- Register only ; 1 ; 0 ; +; -- Combinational with a register ; 34 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 11 ; 0 ; +; -- 3 input functions ; 2 ; 0 ; +; -- <=2 input functions ; 32 ; 0 ; +; -- Register only ; 1 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 14 ; 0 ; +; -- arithmetic mode ; 31 ; 0 ; +; ; ; ; +; Total registers ; 35 ; 0 ; +; -- Dedicated logic registers ; 35 / 33216 ( < 1 % ) ; 0 / 33216 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 5 / 2076 ( < 1 % ) ; 0 / 2076 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 4 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ; 0 / 70 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 2 / 20 ( 10 % ) ; 0 / 20 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 253 ; 0 ; +; -- Registered Connections ; 70 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 3 ; 0 ; +; -- Output Ports ; 1 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clk ; N2 ; 2 ; 0 ; 18 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; rst_n ; N25 ; 5 ; 65 ; 19 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; toggle_in ; V2 ; 1 ; 0 ; 12 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ++-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; port_out ; AE23 ; 7 ; 63 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; - ; - ; ++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+----------------+---------------+--------------+ +; 1 ; 1 / 64 ( 2 % ) ; 3.3V ; -- ; +; 2 ; 3 / 59 ( 5 % ) ; 3.3V ; -- ; +; 3 ; 0 / 56 ( 0 % ) ; 3.3V ; -- ; +; 4 ; 0 / 58 ( 0 % ) ; 3.3V ; -- ; +; 5 ; 1 / 65 ( 2 % ) ; 3.3V ; -- ; +; 6 ; 1 / 59 ( 2 % ) ; 3.3V ; -- ; +; 7 ; 1 / 58 ( 2 % ) ; 3.3V ; -- ; +; 8 ; 0 / 56 ( 0 % ) ; 3.3V ; -- ; ++----------+----------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A3 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A4 ; 484 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 482 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 479 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 465 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 457 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 451 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 447 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A13 ; 430 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A14 ; 427 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A17 ; 412 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 406 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 394 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 390 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; 382 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A22 ; 379 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A23 ; 378 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; A24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 107 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA2 ; 106 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA3 ; 117 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA4 ; 116 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA5 ; 120 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA6 ; 130 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA7 ; 129 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA8 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; AA9 ; 152 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 153 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 155 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 179 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 192 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 194 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 197 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 209 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 219 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 220 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; AA20 ; 230 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA23 ; 256 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA24 ; 255 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA25 ; 266 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AA26 ; 267 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB1 ; 115 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB2 ; 114 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB3 ; 126 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB4 ; 127 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB8 ; 147 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB10 ; 154 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB12 ; 171 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB15 ; 198 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB18 ; 215 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB20 ; 225 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; 242 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AB22 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB23 ; 258 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB24 ; 257 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB25 ; 263 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AB26 ; 262 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AC1 ; 119 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AC2 ; 118 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AC3 ; 128 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC5 ; 133 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC6 ; 134 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC7 ; 143 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC8 ; 148 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC9 ; 163 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC10 ; 164 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC11 ; 168 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC12 ; 172 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC13 ; 185 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AC14 ; 191 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC15 ; 199 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC16 ; 202 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC17 ; 207 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC18 ; 216 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC19 ; 222 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC20 ; 226 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC21 ; 237 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC22 ; 241 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AC23 ; 245 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AC24 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AC25 ; 260 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AC26 ; 261 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AD1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD2 ; 122 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AD3 ; 123 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AD4 ; 135 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD5 ; 136 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD6 ; 139 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD7 ; 140 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD8 ; 149 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD10 ; 167 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD11 ; 173 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD12 ; 181 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD13 ; 186 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD15 ; 190 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD16 ; 201 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD17 ; 208 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD19 ; 221 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD20 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD21 ; 238 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD22 ; 240 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD23 ; 239 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AD24 ; 249 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AD25 ; 248 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AD26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; 124 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AE3 ; 125 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AE4 ; 131 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE5 ; 137 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE6 ; 150 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE7 ; 157 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE8 ; 159 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE9 ; 165 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE10 ; 169 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE11 ; 174 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE12 ; 182 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE13 ; 183 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE14 ; 188 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AE15 ; 189 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE16 ; 200 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE17 ; 206 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE18 ; 212 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE19 ; 214 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE20 ; 224 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE21 ; 228 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE22 ; 236 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AE23 ; 244 ; 7 ; port_out ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE24 ; 247 ; 6 ; ~LVDS150p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; AE25 ; 246 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; AE26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF4 ; 132 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF5 ; 138 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF6 ; 151 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF7 ; 158 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF8 ; 160 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF9 ; 166 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF10 ; 170 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF13 ; 184 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF14 ; 187 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AF15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF17 ; 205 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF18 ; 211 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF19 ; 213 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF20 ; 223 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF21 ; 227 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF22 ; 235 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF23 ; 243 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; AF24 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B2 ; 2 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; B3 ; 3 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; B4 ; 483 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 481 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 480 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 466 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 458 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 452 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 448 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 435 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 433 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B13 ; 429 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B14 ; 428 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B15 ; 420 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 419 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 411 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 405 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 393 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 389 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; 381 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B22 ; 380 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B23 ; 377 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; B24 ; 363 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; B25 ; 362 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; B26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C2 ; 6 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; 7 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; C4 ; 478 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C5 ; 486 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C6 ; 485 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C7 ; 468 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C8 ; 463 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C9 ; 459 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 450 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C11 ; 436 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C12 ; 434 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C13 ; 431 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 421 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C16 ; 418 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C17 ; 404 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 391 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C21 ; 375 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C22 ; 374 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C23 ; 373 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; C24 ; 360 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; C25 ; 361 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; C26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D1 ; 13 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 12 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; D3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 477 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D6 ; 467 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D7 ; 469 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 464 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 460 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; 449 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D11 ; 445 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 443 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D13 ; 432 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D14 ; 426 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 417 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 415 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; 403 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D18 ; 396 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D19 ; 392 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D20 ; 387 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D21 ; 376 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; D22 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D23 ; 369 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; D24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D25 ; 358 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; D26 ; 359 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 19 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; E4 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; 4 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; 474 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E10 ; 453 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; E11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E12 ; 444 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; E13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E15 ; 416 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E18 ; 395 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; E19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E20 ; 388 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; E21 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E22 ; 370 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E23 ; 365 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E24 ; 364 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E25 ; 355 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; E26 ; 356 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 29 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 28 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 10 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F4 ; 11 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; F6 ; 5 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F7 ; 14 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F8 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F9 ; 470 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 462 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 454 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 440 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 423 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 425 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 409 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; 408 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F17 ; 401 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F18 ; 398 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; F19 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 372 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 371 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; F23 ; 353 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F24 ; 354 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F25 ; 350 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; F26 ; 349 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; 30 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G2 ; 31 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G3 ; 24 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; 23 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G5 ; 8 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 9 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; 471 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G10 ; 461 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G11 ; 446 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 439 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; 422 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G14 ; 424 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G15 ; 410 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 407 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 402 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G18 ; 397 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; G19 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 368 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 367 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G23 ; 346 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G24 ; 345 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G25 ; 343 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; G26 ; 342 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 37 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 36 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 32 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H4 ; 33 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; 18 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H8 ; 473 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H10 ; 472 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 456 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 455 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H15 ; 414 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H16 ; 413 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H17 ; 400 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; H18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H19 ; 335 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H21 ; 366 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H23 ; 341 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H24 ; 340 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H25 ; 337 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; H26 ; 336 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J1 ; 39 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 38 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; 34 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J4 ; 35 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; 15 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J6 ; 25 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J7 ; 17 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J8 ; 16 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J9 ; 475 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J10 ; 438 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J11 ; 437 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J13 ; 442 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J14 ; 441 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J16 ; 385 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J17 ; 399 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J18 ; 383 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; J19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J20 ; 351 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 352 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 357 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J23 ; 339 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J24 ; 338 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J25 ; 327 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; J26 ; 326 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 42 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K2 ; 43 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K3 ; 41 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K4 ; 40 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K5 ; 22 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K6 ; 21 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K7 ; 27 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K8 ; 26 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K9 ; 476 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K16 ; 386 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; K17 ; 384 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; K18 ; 334 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K19 ; 333 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 332 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 344 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K23 ; 331 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K24 ; 330 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K25 ; 321 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; K26 ; 320 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L2 ; 50 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L3 ; 51 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L4 ; 44 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; 48 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L7 ; 47 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L8 ; 59 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L9 ; 49 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L10 ; 52 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L19 ; 322 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; 328 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L21 ; 329 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L23 ; 325 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L24 ; 324 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L25 ; 323 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; L26 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; 56 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M3 ; 55 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M4 ; 53 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M5 ; 54 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 58 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; M7 ; 60 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; M8 ; 57 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; M9 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M19 ; 317 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; 316 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M21 ; 314 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M22 ; 319 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M23 ; 318 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M24 ; 313 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M25 ; 312 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; M26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N1 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N2 ; 64 ; 2 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N3 ; 62 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; N4 ; 63 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; N5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N6 ; 61 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; N7 ; 66 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; 45 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N18 ; 348 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 315 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; N21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N23 ; 311 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; N24 ; 310 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; N25 ; 309 ; 5 ; rst_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N26 ; 308 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; P1 ; 68 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; P2 ; 67 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; P3 ; 69 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P4 ; 70 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P6 ; 78 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; 77 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; 46 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; 293 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 347 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 301 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; P21 ; 300 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P23 ; 305 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P24 ; 304 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; P25 ; 307 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; P26 ; 306 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; 71 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; 72 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R4 ; 73 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R5 ; 74 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R6 ; 81 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R7 ; 82 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R8 ; 110 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R17 ; 294 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R19 ; 282 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 297 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R22 ; 298 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; R23 ; 299 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; R24 ; 302 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R25 ; 303 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; R26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T2 ; 79 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 80 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T4 ; 83 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; 93 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T7 ; 92 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T8 ; 111 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T9 ; 76 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T10 ; 75 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T17 ; 289 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T18 ; 290 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; 281 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T20 ; 287 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T21 ; 288 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 296 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T23 ; 295 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T24 ; 292 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T25 ; 291 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; T26 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U1 ; 85 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U2 ; 84 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U3 ; 88 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U4 ; 89 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U5 ; 100 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U6 ; 98 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U7 ; 99 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U9 ; 86 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U10 ; 87 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U12 ; 178 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; U13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; 231 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; U18 ; 232 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U20 ; 280 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U21 ; 279 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 270 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U23 ; 284 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U24 ; 283 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U25 ; 285 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; U26 ; 286 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 90 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 91 ; 1 ; toggle_in ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V3 ; 95 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V4 ; 94 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; 104 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V6 ; 105 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V7 ; 112 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V8 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V9 ; 142 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V10 ; 141 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V11 ; 177 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V13 ; 176 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V14 ; 175 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V17 ; 218 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V18 ; 233 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; V19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V20 ; 251 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 252 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 259 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V23 ; 275 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V24 ; 276 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V25 ; 277 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; V26 ; 278 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 97 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W2 ; 96 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 102 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 101 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W6 ; 113 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W7 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; W8 ; 144 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W10 ; 145 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W11 ; 161 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 162 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W15 ; 203 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 204 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; 217 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W19 ; 234 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; W20 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; W21 ; 253 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W23 ; 272 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W24 ; 271 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W25 ; 273 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; W26 ; 274 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 103 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; Y3 ; 108 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y4 ; 109 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y5 ; 121 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y6 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; Y7 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; Y8 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 146 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y11 ; 156 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y12 ; 180 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y13 ; 193 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y14 ; 195 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; 196 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y16 ; 210 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y18 ; 229 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; Y19 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; Y21 ; 250 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 254 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y23 ; 265 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y24 ; 264 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y25 ; 269 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; Y26 ; 268 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------+--------------+ +; |altera_de_II_demo ; 46 (0) ; 35 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 11 (0) ; 1 (0) ; 34 (0) ; |altera_de_II_demo ; ; +; |port_blinker:port_blinker_1| ; 44 (44) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 33 (33) ; |altera_de_II_demo|port_blinker:port_blinker_1 ; ; +; |sig_gen:sig_gen_1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |altera_de_II_demo|sig_gen:sig_gen_1 ; ; ++----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-----------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++-----------+----------+---------------+---------------+-----------------------+-----+ +; port_out ; Output ; -- ; -- ; -- ; -- ; +; clk ; Input ; (0) 299 ps ; (0) 299 ps ; -- ; -- ; +; rst_n ; Input ; (0) 299 ps ; (0) 299 ps ; -- ; -- ; +; toggle_in ; Input ; (6) 4075 ps ; (6) 4075 ps ; -- ; -- ; ++-----------+----------+---------------+---------------+-----------------------+-----+ + + ++--------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------+-------------------+---------+ +; clk ; ; ; +; rst_n ; ; ; +; toggle_in ; ; ; +; - sig_gen:sig_gen_1|toggle_d1_r ; 1 ; 6 ; +; - sig_gen:sig_gen_1|toggle_r~0 ; 1 ; 6 ; ++--------------------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_N2 ; 35 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; port_blinker:port_blinker_1|val_cnt_r[0]~34 ; LCCOMB_X63_Y29_N28 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ; +; rst_n ; PIN_N25 ; 35 ; Async. clear ; yes ; Global Clock ; GCLK6 ; -- ; ++---------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; clk ; PIN_N2 ; 35 ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_N25 ; 35 ; Global Clock ; GCLK6 ; -- ; ++-------+----------+---------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------------------+---------+ +; port_blinker:port_blinker_1|val_cnt_r[0]~34 ; 32 ; +; sig_gen:sig_gen_1|toggle_r ; 3 ; +; toggle_in ; 2 ; +; port_blinker:port_blinker_1|Equal0~9 ; 2 ; +; port_blinker:port_blinker_1|Equal0~4 ; 2 ; +; port_blinker:port_blinker_1|port_level_r ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[31] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[30] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[29] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[28] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[26] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[24] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[27] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[25] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[23] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[22] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[21] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[20] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[18] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[16] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[19] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[17] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[15] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[14] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[13] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[12] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[8] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[11] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[10] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[9] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[7] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[6] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[5] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[4] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[3] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[2] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[1] ; 2 ; +; port_blinker:port_blinker_1|val_cnt_r[0] ; 2 ; +; sig_gen:sig_gen_1|toggle_r~0 ; 1 ; +; sig_gen:sig_gen_1|toggle_d1_r ; 1 ; +; port_blinker:port_blinker_1|port_level_r~0 ; 1 ; +; port_blinker:port_blinker_1|Equal0~8 ; 1 ; +; port_blinker:port_blinker_1|Equal0~7 ; 1 ; +; port_blinker:port_blinker_1|Equal0~6 ; 1 ; +; port_blinker:port_blinker_1|Equal0~5 ; 1 ; +; port_blinker:port_blinker_1|Equal0~3 ; 1 ; +; port_blinker:port_blinker_1|Equal0~2 ; 1 ; +; port_blinker:port_blinker_1|Equal0~1 ; 1 ; +; port_blinker:port_blinker_1|Equal0~0 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[31]~95 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[30]~94 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[30]~93 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[29]~92 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[29]~91 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[28]~90 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[28]~89 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[27]~88 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[27]~87 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[26]~86 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[26]~85 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[25]~84 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[25]~83 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[24]~82 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[24]~81 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[23]~80 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[23]~79 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[22]~78 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[22]~77 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[21]~76 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[21]~75 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[20]~74 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[20]~73 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[19]~72 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[19]~71 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[18]~70 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[18]~69 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[17]~68 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[17]~67 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[16]~66 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[16]~65 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[15]~64 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[15]~63 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[14]~62 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[14]~61 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[13]~60 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[13]~59 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[12]~58 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[12]~57 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[11]~56 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[11]~55 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[10]~54 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[10]~53 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[9]~52 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[9]~51 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[8]~50 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[8]~49 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[7]~48 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[7]~47 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[6]~46 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[6]~45 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[5]~44 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[5]~43 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[4]~42 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[4]~41 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[3]~40 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[3]~39 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[2]~38 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[2]~37 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[1]~36 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[1]~35 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[0]~33 ; 1 ; +; port_blinker:port_blinker_1|val_cnt_r[0]~32 ; 1 ; ++----------------------------------------------+---------+ + + ++----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+-----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+-----------------------+ +; Block interconnects ; 38 / 94,460 ( < 1 % ) ; +; C16 interconnects ; 1 / 3,315 ( < 1 % ) ; +; C4 interconnects ; 23 / 60,840 ( < 1 % ) ; +; Direct links ; 12 / 94,460 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Local interconnects ; 42 / 33,216 ( < 1 % ) ; +; R24 interconnects ; 3 / 3,091 ( < 1 % ) ; +; R4 interconnects ; 20 / 81,294 ( < 1 % ) ; ++----------------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 9.20) ; Number of LABs (Total = 5) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 2 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 5) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 4 ; +; 1 Clock ; 4 ; +; 1 Sync. clear ; 2 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 5) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 2 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 7.20) ; Number of LABs (Total = 5) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 2 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 9.20) ; Number of LABs (Total = 5) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 2 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As input tri-stated ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + Info: Processing started: Fri Oct 28 11:32:35 2011 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Info: Selected device EP2C35F672C6 for design "altera_de_II_demo" +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C50F672C6 is compatible + Info: Device EP2C70F672C6 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location E3 + Info: Pin ~nCSO~ is reserved at location D3 + Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24 +Info: Timing-driven compilation is using the TimeQuest Timing Analyzer +Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info: No user constrained base clocks found in the design +Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info: Automatically promoted node clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info: Automatically promoted node rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6 +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Warning: Ignored locations or region assignments to the following nodes + Warning: Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design + Warning: Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design + Warning: Node "AUD_BCLK" is assigned to location or region, but does not exist in design + Warning: Node "AUD_DACDAT" is assigned to location or region, but does not exist in design + Warning: Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design + Warning: Node "AUD_XCK" is assigned to location or region, but does not exist in design + Warning: Node "CLOCK_27" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_BA_0" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_BA_1" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_CKE" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_CLK" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_CS_N" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_LDQM" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_UDQM" is assigned to location or region, but does not exist in design + Warning: Node "DRAM_WE_N" is assigned to location or region, but does not exist in design + Warning: Node "ENET_CLK" is assigned to location or region, but does not exist in design + Warning: Node "ENET_CMD" is assigned to location or region, but does not exist in design + Warning: Node "ENET_CS_N" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[0]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[10]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[11]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[12]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[13]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[14]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[15]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[1]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[2]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[3]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[4]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[5]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[6]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[7]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[8]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_DATA[9]" is assigned to location or region, but does not exist in design + Warning: Node "ENET_INT" is assigned to location or region, but does not exist in design + Warning: Node "ENET_RD_N" is assigned to location or region, but does not exist in design + Warning: Node "ENET_RST_N" is assigned to location or region, but does not exist in design + Warning: Node "ENET_WR_N" is assigned to location or region, but does not exist in design + Warning: Node "EXT_CLOCK" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design + Warning: Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design + Warning: Node "FL_CE_N" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[0]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[1]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[2]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[3]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[4]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[5]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[6]" is assigned to location or region, but does not exist in design + Warning: Node "FL_DQ[7]" is assigned to location or region, but does not exist in design + Warning: Node "FL_OE_N" is assigned to location or region, but does not exist in design + Warning: Node "FL_RST_N" is assigned to location or region, but does not exist in design + Warning: Node "FL_WE_N" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[0]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[10]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[11]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[12]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[13]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[14]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[15]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[16]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[17]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[18]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[19]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[1]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[20]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[21]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[22]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[23]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[24]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[25]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[26]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[27]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[28]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[29]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[2]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[30]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[31]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[32]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[33]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[34]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[35]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[3]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[4]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[5]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[6]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[7]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[8]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_0[9]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[0]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[10]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[11]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[12]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[13]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[14]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[15]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[16]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[17]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[18]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[19]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[1]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[20]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[21]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[22]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[23]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[24]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[25]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[26]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[27]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[28]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[29]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[2]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[30]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[31]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[32]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[33]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[34]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[35]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[3]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[4]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[5]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[6]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[7]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[8]" is assigned to location or region, but does not exist in design + Warning: Node "GPIO_1[9]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX0[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX1[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX2[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX4[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX5[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX6[6]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[0]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[1]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[2]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[3]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[4]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[5]" is assigned to location or region, but does not exist in design + Warning: Node "HEX7[6]" is assigned to location or region, but does not exist in design + Warning: Node "I2C_SCLK" is assigned to location or region, but does not exist in design + Warning: Node "I2C_SDAT" is assigned to location or region, but does not exist in design + Warning: Node "IRDA_RXD" is assigned to location or region, but does not exist in design + Warning: Node "IRDA_TXD" is assigned to location or region, but does not exist in design + Warning: Node "KEY[0]" is assigned to location or region, but does not exist in design + Warning: Node "KEY[1]" is assigned to location or region, but does not exist in design + Warning: Node "KEY[2]" is assigned to location or region, but does not exist in design + Warning: Node "KEY[3]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_BLON" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design + Warning: Node "LCD_EN" is assigned to location or region, but does not exist in design + Warning: Node "LCD_ON" is assigned to location or region, but does not exist in design + Warning: Node "LCD_RS" is assigned to location or region, but does not exist in design + Warning: Node "LCD_RW" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[1]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[2]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[3]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[4]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[5]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[6]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[7]" is assigned to location or region, but does not exist in design + Warning: Node "LEDG[8]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[10]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[11]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[12]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[13]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[14]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[15]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[16]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[17]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[1]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[2]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[3]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[4]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[5]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[6]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[7]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[8]" is assigned to location or region, but does not exist in design + Warning: Node "LEDR[9]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_CS_N" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DACK0_N" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DACK1_N" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DREQ0" is assigned to location or region, but does not exist in design + Warning: Node "OTG_DREQ1" is assigned to location or region, but does not exist in design + Warning: Node "OTG_FSPEED" is assigned to location or region, but does not exist in design + Warning: Node "OTG_INT0" is assigned to location or region, but does not exist in design + Warning: Node "OTG_INT1" is assigned to location or region, but does not exist in design + Warning: Node "OTG_LSPEED" is assigned to location or region, but does not exist in design + Warning: Node "OTG_RD_N" is assigned to location or region, but does not exist in design + Warning: Node "OTG_RST_N" is assigned to location or region, but does not exist in design + Warning: Node "OTG_WR_N" is assigned to location or region, but does not exist in design + Warning: Node "PS2_CLK" is assigned to location or region, but does not exist in design + Warning: Node "PS2_DAT" is assigned to location or region, but does not exist in design + Warning: Node "SD_CLK" is assigned to location or region, but does not exist in design + Warning: Node "SD_CMD" is assigned to location or region, but does not exist in design + Warning: Node "SD_DAT" is assigned to location or region, but does not exist in design + Warning: Node "SD_DAT3" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_CE_N" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_LB_N" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_OE_N" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_UB_N" is assigned to location or region, but does not exist in design + Warning: Node "SRAM_WE_N" is assigned to location or region, but does not exist in design + Warning: Node "SW[10]" is assigned to location or region, but does not exist in design + Warning: Node "SW[11]" is assigned to location or region, but does not exist in design + Warning: Node "SW[12]" is assigned to location or region, but does not exist in design + Warning: Node "SW[13]" is assigned to location or region, but does not exist in design + Warning: Node "SW[14]" is assigned to location or region, but does not exist in design + Warning: Node "SW[15]" is assigned to location or region, but does not exist in design + Warning: Node "SW[16]" is assigned to location or region, but does not exist in design + Warning: Node "SW[1]" is assigned to location or region, but does not exist in design + Warning: Node "SW[2]" is assigned to location or region, but does not exist in design + Warning: Node "SW[3]" is assigned to location or region, but does not exist in design + Warning: Node "SW[4]" is assigned to location or region, but does not exist in design + Warning: Node "SW[5]" is assigned to location or region, but does not exist in design + Warning: Node "SW[6]" is assigned to location or region, but does not exist in design + Warning: Node "SW[7]" is assigned to location or region, but does not exist in design + Warning: Node "SW[8]" is assigned to location or region, but does not exist in design + Warning: Node "SW[9]" is assigned to location or region, but does not exist in design + Warning: Node "TCK" is assigned to location or region, but does not exist in design + Warning: Node "TCS" is assigned to location or region, but does not exist in design + Warning: Node "TDI" is assigned to location or region, but does not exist in design + Warning: Node "TDO" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[0]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[1]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[2]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[3]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[4]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[5]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[6]" is assigned to location or region, but does not exist in design + Warning: Node "TD_DATA[7]" is assigned to location or region, but does not exist in design + Warning: Node "TD_HS" is assigned to location or region, but does not exist in design + Warning: Node "TD_RESET" is assigned to location or region, but does not exist in design + Warning: Node "TD_VS" is assigned to location or region, but does not exist in design + Warning: Node "UART_RXD" is assigned to location or region, but does not exist in design + Warning: Node "UART_TXD" is assigned to location or region, but does not exist in design + Warning: Node "VGA_BLANK" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[0]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[1]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[2]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[3]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[4]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[5]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[6]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[7]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[8]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_B[9]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_CLK" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[0]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[1]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[2]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[3]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[4]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[5]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[6]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[7]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[8]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_G[9]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_HS" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[0]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[1]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[2]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[3]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[4]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[5]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[6]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[7]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[8]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_R[9]" is assigned to location or region, but does not exist in design + Warning: Node "VGA_SYNC" is assigned to location or region, but does not exist in design + Warning: Node "VGA_VS" is assigned to location or region, but does not exist in design +Info: Fitter preparation operations ending: elapsed time is 00:00:01 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Router estimated average interconnect usage is 0% of the available device resources + Info: Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 1 output pins without output pin load capacitance assignment + Info: Pin "port_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info: Generated suppressed messages file D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 424 warnings + Info: Peak virtual memory: 344 megabytes + Info: Processing ended: Fri Oct 28 11:32:43 2011 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg. + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qsf =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qsf (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qsf (revision 24) @@ -0,0 +1,446 @@ +# ----------------------------------------------------------- # + +# Quartus project generated by Kactus2 +# Date created 15:33:10 27.10.2011 + +# ----------------------------------------------------------- # + +set_global_assignment -name TOP_LEVEL_ENTITY altera_de_II_demo +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1" +set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd +set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd +set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd +set_location_assignment PIN_N26 -to SW[1] +set_location_assignment PIN_P25 -to SW[2] +set_location_assignment PIN_AE14 -to SW[3] +set_location_assignment PIN_AF14 -to SW[4] +set_location_assignment PIN_AD13 -to SW[5] +set_location_assignment PIN_AC13 -to SW[6] +set_location_assignment PIN_C13 -to SW[7] +set_location_assignment PIN_B13 -to SW[8] +set_location_assignment PIN_A13 -to SW[9] +set_location_assignment PIN_N1 -to SW[10] +set_location_assignment PIN_P1 -to SW[11] +set_location_assignment PIN_P2 -to SW[12] +set_location_assignment PIN_T7 -to SW[13] +set_location_assignment PIN_U3 -to SW[14] +set_location_assignment PIN_U4 -to SW[15] +set_location_assignment PIN_V1 -to SW[16] +set_location_assignment PIN_T6 -to DRAM_ADDR[0] +set_location_assignment PIN_V4 -to DRAM_ADDR[1] +set_location_assignment PIN_V3 -to DRAM_ADDR[2] +set_location_assignment PIN_W2 -to DRAM_ADDR[3] +set_location_assignment PIN_W1 -to DRAM_ADDR[4] +set_location_assignment PIN_U6 -to DRAM_ADDR[5] +set_location_assignment PIN_U7 -to DRAM_ADDR[6] +set_location_assignment PIN_U5 -to DRAM_ADDR[7] +set_location_assignment PIN_W4 -to DRAM_ADDR[8] +set_location_assignment PIN_W3 -to DRAM_ADDR[9] +set_location_assignment PIN_Y1 -to DRAM_ADDR[10] +set_location_assignment PIN_V5 -to DRAM_ADDR[11] +set_location_assignment PIN_AE2 -to DRAM_BA_0 +set_location_assignment PIN_AE3 -to DRAM_BA_1 +set_location_assignment PIN_AB3 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_AA7 -to DRAM_CLK +set_location_assignment PIN_AC3 -to DRAM_CS_N +set_location_assignment PIN_V6 -to DRAM_DQ[0] +set_location_assignment PIN_AA2 -to DRAM_DQ[1] +set_location_assignment PIN_AA1 -to DRAM_DQ[2] +set_location_assignment PIN_Y3 -to DRAM_DQ[3] +set_location_assignment PIN_Y4 -to DRAM_DQ[4] +set_location_assignment PIN_R8 -to DRAM_DQ[5] +set_location_assignment PIN_T8 -to DRAM_DQ[6] +set_location_assignment PIN_V7 -to DRAM_DQ[7] +set_location_assignment PIN_W6 -to DRAM_DQ[8] +set_location_assignment PIN_AB2 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA4 -to DRAM_DQ[11] +set_location_assignment PIN_AA3 -to DRAM_DQ[12] +set_location_assignment PIN_AC2 -to DRAM_DQ[13] +set_location_assignment PIN_AC1 -to DRAM_DQ[14] +set_location_assignment PIN_AA5 -to DRAM_DQ[15] +set_location_assignment PIN_AD2 -to DRAM_LDQM +set_location_assignment PIN_Y5 -to DRAM_UDQM +set_location_assignment PIN_AB4 -to DRAM_RAS_N +set_location_assignment PIN_AD3 -to DRAM_WE_N +set_location_assignment PIN_AC18 -to FL_ADDR[0] +set_location_assignment PIN_AB18 -to FL_ADDR[1] +set_location_assignment PIN_AE19 -to FL_ADDR[2] +set_location_assignment PIN_AF19 -to FL_ADDR[3] +set_location_assignment PIN_AE18 -to FL_ADDR[4] +set_location_assignment PIN_AF18 -to FL_ADDR[5] +set_location_assignment PIN_Y16 -to FL_ADDR[6] +set_location_assignment PIN_AA16 -to FL_ADDR[7] +set_location_assignment PIN_AD17 -to FL_ADDR[8] +set_location_assignment PIN_AC17 -to FL_ADDR[9] +set_location_assignment PIN_AE17 -to FL_ADDR[10] +set_location_assignment PIN_AF17 -to FL_ADDR[11] +set_location_assignment PIN_W16 -to FL_ADDR[12] +set_location_assignment PIN_W15 -to FL_ADDR[13] +set_location_assignment PIN_AC16 -to FL_ADDR[14] +set_location_assignment PIN_AD16 -to FL_ADDR[15] +set_location_assignment PIN_AE16 -to FL_ADDR[16] +set_location_assignment PIN_AC15 -to FL_ADDR[17] +set_location_assignment PIN_AB15 -to FL_ADDR[18] +set_location_assignment PIN_AA15 -to FL_ADDR[19] +set_location_assignment PIN_Y15 -to FL_ADDR[20] +set_location_assignment PIN_Y14 -to FL_ADDR[21] +set_location_assignment PIN_V17 -to FL_CE_N +set_location_assignment PIN_W17 -to FL_OE_N +set_location_assignment PIN_AD19 -to FL_DQ[0] +set_location_assignment PIN_AC19 -to FL_DQ[1] +set_location_assignment PIN_AF20 -to FL_DQ[2] +set_location_assignment PIN_AE20 -to FL_DQ[3] +set_location_assignment PIN_AB20 -to FL_DQ[4] +set_location_assignment PIN_AC20 -to FL_DQ[5] +set_location_assignment PIN_AF21 -to FL_DQ[6] +set_location_assignment PIN_AE21 -to FL_DQ[7] +set_location_assignment PIN_AA18 -to FL_RST_N +set_location_assignment PIN_AA17 -to FL_WE_N +set_location_assignment PIN_AF10 -to HEX0[0] +set_location_assignment PIN_AB12 -to HEX0[1] +set_location_assignment PIN_AC12 -to HEX0[2] +set_location_assignment PIN_AD11 -to HEX0[3] +set_location_assignment PIN_AE11 -to HEX0[4] +set_location_assignment PIN_V14 -to HEX0[5] +set_location_assignment PIN_V13 -to HEX0[6] +set_location_assignment PIN_V20 -to HEX1[0] +set_location_assignment PIN_V21 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_Y22 -to HEX1[3] +set_location_assignment PIN_AA24 -to HEX1[4] +set_location_assignment PIN_AA23 -to HEX1[5] +set_location_assignment PIN_AB24 -to HEX1[6] +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_V22 -to HEX2[1] +set_location_assignment PIN_AC25 -to HEX2[2] +set_location_assignment PIN_AC26 -to HEX2[3] +set_location_assignment PIN_AB26 -to HEX2[4] +set_location_assignment PIN_AB25 -to HEX2[5] +set_location_assignment PIN_Y24 -to HEX2[6] +set_location_assignment PIN_Y23 -to HEX3[0] +set_location_assignment PIN_AA25 -to HEX3[1] +set_location_assignment PIN_AA26 -to HEX3[2] +set_location_assignment PIN_Y26 -to HEX3[3] +set_location_assignment PIN_Y25 -to HEX3[4] +set_location_assignment PIN_U22 -to HEX3[5] +set_location_assignment PIN_W24 -to HEX3[6] +set_location_assignment PIN_U9 -to HEX4[0] +set_location_assignment PIN_U1 -to HEX4[1] +set_location_assignment PIN_U2 -to HEX4[2] +set_location_assignment PIN_T4 -to HEX4[3] +set_location_assignment PIN_R7 -to HEX4[4] +set_location_assignment PIN_R6 -to HEX4[5] +set_location_assignment PIN_T3 -to HEX4[6] +set_location_assignment PIN_T2 -to HEX5[0] +set_location_assignment PIN_P6 -to HEX5[1] +set_location_assignment PIN_P7 -to HEX5[2] +set_location_assignment PIN_T9 -to HEX5[3] +set_location_assignment PIN_R5 -to HEX5[4] +set_location_assignment PIN_R4 -to HEX5[5] +set_location_assignment PIN_R3 -to HEX5[6] +set_location_assignment PIN_R2 -to HEX6[0] +set_location_assignment PIN_P4 -to HEX6[1] +set_location_assignment PIN_P3 -to HEX6[2] +set_location_assignment PIN_M2 -to HEX6[3] +set_location_assignment PIN_M3 -to HEX6[4] +set_location_assignment PIN_M5 -to HEX6[5] +set_location_assignment PIN_M4 -to HEX6[6] +set_location_assignment PIN_L3 -to HEX7[0] +set_location_assignment PIN_L2 -to HEX7[1] +set_location_assignment PIN_L9 -to HEX7[2] +set_location_assignment PIN_L6 -to HEX7[3] +set_location_assignment PIN_L7 -to HEX7[4] +set_location_assignment PIN_P9 -to HEX7[5] +set_location_assignment PIN_N9 -to HEX7[6] +set_location_assignment PIN_G26 -to KEY[0] +set_location_assignment PIN_N23 -to KEY[1] +set_location_assignment PIN_P23 -to KEY[2] +set_location_assignment PIN_W26 -to KEY[3] +set_location_assignment PIN_AF23 -to LEDR[1] +set_location_assignment PIN_AB21 -to LEDR[2] +set_location_assignment PIN_AC22 -to LEDR[3] +set_location_assignment PIN_AD22 -to LEDR[4] +set_location_assignment PIN_AD23 -to LEDR[5] +set_location_assignment PIN_AD21 -to LEDR[6] +set_location_assignment PIN_AC21 -to LEDR[7] +set_location_assignment PIN_AA14 -to LEDR[8] +set_location_assignment PIN_Y13 -to LEDR[9] +set_location_assignment PIN_AA13 -to LEDR[10] +set_location_assignment PIN_AC14 -to LEDR[11] +set_location_assignment PIN_AD15 -to LEDR[12] +set_location_assignment PIN_AE15 -to LEDR[13] +set_location_assignment PIN_AF13 -to LEDR[14] +set_location_assignment PIN_AE13 -to LEDR[15] +set_location_assignment PIN_AE12 -to LEDR[16] +set_location_assignment PIN_AD12 -to LEDR[17] +set_location_assignment PIN_AF22 -to LEDG[1] +set_location_assignment PIN_W19 -to LEDG[2] +set_location_assignment PIN_V18 -to LEDG[3] +set_location_assignment PIN_U18 -to LEDG[4] +set_location_assignment PIN_U17 -to LEDG[5] +set_location_assignment PIN_AA20 -to LEDG[6] +set_location_assignment PIN_Y18 -to LEDG[7] +set_location_assignment PIN_Y12 -to LEDG[8] +set_location_assignment PIN_D13 -to CLOCK_27 +set_location_assignment PIN_P26 -to EXT_CLOCK +set_location_assignment PIN_D26 -to PS2_CLK +set_location_assignment PIN_C24 -to PS2_DAT +set_location_assignment PIN_C25 -to UART_RXD +set_location_assignment PIN_B25 -to UART_TXD +set_location_assignment PIN_K4 -to LCD_RW +set_location_assignment PIN_K3 -to LCD_EN +set_location_assignment PIN_K1 -to LCD_RS +set_location_assignment PIN_J1 -to LCD_DATA[0] +set_location_assignment PIN_J2 -to LCD_DATA[1] +set_location_assignment PIN_H1 -to LCD_DATA[2] +set_location_assignment PIN_H2 -to LCD_DATA[3] +set_location_assignment PIN_J4 -to LCD_DATA[4] +set_location_assignment PIN_J3 -to LCD_DATA[5] +set_location_assignment PIN_H4 -to LCD_DATA[6] +set_location_assignment PIN_H3 -to LCD_DATA[7] +set_location_assignment PIN_L4 -to LCD_ON +set_location_assignment PIN_K2 -to LCD_BLON +set_location_assignment PIN_AE4 -to SRAM_ADDR[0] +set_location_assignment PIN_AF4 -to SRAM_ADDR[1] +set_location_assignment PIN_AC5 -to SRAM_ADDR[2] +set_location_assignment PIN_AC6 -to SRAM_ADDR[3] +set_location_assignment PIN_AD4 -to SRAM_ADDR[4] +set_location_assignment PIN_AD5 -to SRAM_ADDR[5] +set_location_assignment PIN_AE5 -to SRAM_ADDR[6] +set_location_assignment PIN_AF5 -to SRAM_ADDR[7] +set_location_assignment PIN_AD6 -to SRAM_ADDR[8] +set_location_assignment PIN_AD7 -to SRAM_ADDR[9] +set_location_assignment PIN_V10 -to SRAM_ADDR[10] +set_location_assignment PIN_V9 -to SRAM_ADDR[11] +set_location_assignment PIN_AC7 -to SRAM_ADDR[12] +set_location_assignment PIN_W8 -to SRAM_ADDR[13] +set_location_assignment PIN_W10 -to SRAM_ADDR[14] +set_location_assignment PIN_Y10 -to SRAM_ADDR[15] +set_location_assignment PIN_AB8 -to SRAM_ADDR[16] +set_location_assignment PIN_AC8 -to SRAM_ADDR[17] +set_location_assignment PIN_AD8 -to SRAM_DQ[0] +set_location_assignment PIN_AE6 -to SRAM_DQ[1] +set_location_assignment PIN_AF6 -to SRAM_DQ[2] +set_location_assignment PIN_AA9 -to SRAM_DQ[3] +set_location_assignment PIN_AA10 -to SRAM_DQ[4] +set_location_assignment PIN_AB10 -to SRAM_DQ[5] +set_location_assignment PIN_AA11 -to SRAM_DQ[6] +set_location_assignment PIN_Y11 -to SRAM_DQ[7] +set_location_assignment PIN_AE7 -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[9] +set_location_assignment PIN_AE8 -to SRAM_DQ[10] +set_location_assignment PIN_AF8 -to SRAM_DQ[11] +set_location_assignment PIN_W11 -to SRAM_DQ[12] +set_location_assignment PIN_W12 -to SRAM_DQ[13] +set_location_assignment PIN_AC9 -to SRAM_DQ[14] +set_location_assignment PIN_AC10 -to SRAM_DQ[15] +set_location_assignment PIN_AE10 -to SRAM_WE_N +set_location_assignment PIN_AD10 -to SRAM_OE_N +set_location_assignment PIN_AF9 -to SRAM_UB_N +set_location_assignment PIN_AE9 -to SRAM_LB_N +set_location_assignment PIN_AC11 -to SRAM_CE_N +set_location_assignment PIN_K7 -to OTG_ADDR[0] +set_location_assignment PIN_F2 -to OTG_ADDR[1] +set_location_assignment PIN_F1 -to OTG_CS_N +set_location_assignment PIN_G2 -to OTG_RD_N +set_location_assignment PIN_G1 -to OTG_WR_N +set_location_assignment PIN_G5 -to OTG_RST_N +set_location_assignment PIN_F4 -to OTG_DATA[0] +set_location_assignment PIN_D2 -to OTG_DATA[1] +set_location_assignment PIN_D1 -to OTG_DATA[2] +set_location_assignment PIN_F7 -to OTG_DATA[3] +set_location_assignment PIN_J5 -to OTG_DATA[4] +set_location_assignment PIN_J8 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_E2 -to OTG_DATA[8] +set_location_assignment PIN_E1 -to OTG_DATA[9] +set_location_assignment PIN_K6 -to OTG_DATA[10] +set_location_assignment PIN_K5 -to OTG_DATA[11] +set_location_assignment PIN_G4 -to OTG_DATA[12] +set_location_assignment PIN_G3 -to OTG_DATA[13] +set_location_assignment PIN_J6 -to OTG_DATA[14] +set_location_assignment PIN_K8 -to OTG_DATA[15] +set_location_assignment PIN_B3 -to OTG_INT0 +set_location_assignment PIN_C3 -to OTG_INT1 +set_location_assignment PIN_C2 -to OTG_DACK0_N +set_location_assignment PIN_B2 -to OTG_DACK1_N +set_location_assignment PIN_F6 -to OTG_DREQ0 +set_location_assignment PIN_E5 -to OTG_DREQ1 +set_location_assignment PIN_F3 -to OTG_FSPEED +set_location_assignment PIN_G6 -to OTG_LSPEED +set_location_assignment PIN_B14 -to TDI +set_location_assignment PIN_A14 -to TCS +set_location_assignment PIN_D14 -to TCK +set_location_assignment PIN_F14 -to TDO +set_location_assignment PIN_C4 -to TD_RESET +set_location_assignment PIN_C8 -to VGA_R[0] +set_location_assignment PIN_F10 -to VGA_R[1] +set_location_assignment PIN_G10 -to VGA_R[2] +set_location_assignment PIN_D9 -to VGA_R[3] +set_location_assignment PIN_C9 -to VGA_R[4] +set_location_assignment PIN_A8 -to VGA_R[5] +set_location_assignment PIN_H11 -to VGA_R[6] +set_location_assignment PIN_H12 -to VGA_R[7] +set_location_assignment PIN_F11 -to VGA_R[8] +set_location_assignment PIN_E10 -to VGA_R[9] +set_location_assignment PIN_B9 -to VGA_G[0] +set_location_assignment PIN_A9 -to VGA_G[1] +set_location_assignment PIN_C10 -to VGA_G[2] +set_location_assignment PIN_D10 -to VGA_G[3] +set_location_assignment PIN_B10 -to VGA_G[4] +set_location_assignment PIN_A10 -to VGA_G[5] +set_location_assignment PIN_G11 -to VGA_G[6] +set_location_assignment PIN_D11 -to VGA_G[7] +set_location_assignment PIN_E12 -to VGA_G[8] +set_location_assignment PIN_D12 -to VGA_G[9] +set_location_assignment PIN_J13 -to VGA_B[0] +set_location_assignment PIN_J14 -to VGA_B[1] +set_location_assignment PIN_F12 -to VGA_B[2] +set_location_assignment PIN_G12 -to VGA_B[3] +set_location_assignment PIN_J10 -to VGA_B[4] +set_location_assignment PIN_J11 -to VGA_B[5] +set_location_assignment PIN_C11 -to VGA_B[6] +set_location_assignment PIN_B11 -to VGA_B[7] +set_location_assignment PIN_C12 -to VGA_B[8] +set_location_assignment PIN_B12 -to VGA_B[9] +set_location_assignment PIN_B8 -to VGA_CLK +set_location_assignment PIN_D6 -to VGA_BLANK +set_location_assignment PIN_A7 -to VGA_HS +set_location_assignment PIN_D8 -to VGA_VS +set_location_assignment PIN_B7 -to VGA_SYNC +set_location_assignment PIN_A6 -to I2C_SCLK +set_location_assignment PIN_B6 -to I2C_SDAT +set_location_assignment PIN_J9 -to TD_DATA[0] +set_location_assignment PIN_E8 -to TD_DATA[1] +set_location_assignment PIN_H8 -to TD_DATA[2] +set_location_assignment PIN_H10 -to TD_DATA[3] +set_location_assignment PIN_G9 -to TD_DATA[4] +set_location_assignment PIN_F9 -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[6] +set_location_assignment PIN_C7 -to TD_DATA[7] +set_location_assignment PIN_D5 -to TD_HS +set_location_assignment PIN_K9 -to TD_VS +set_location_assignment PIN_C5 -to AUD_ADCLRCK +set_location_assignment PIN_B5 -to AUD_ADCDAT +set_location_assignment PIN_C6 -to AUD_DACLRCK +set_location_assignment PIN_A4 -to AUD_DACDAT +set_location_assignment PIN_A5 -to AUD_XCK +set_location_assignment PIN_B4 -to AUD_BCLK +set_location_assignment PIN_D17 -to ENET_DATA[0] +set_location_assignment PIN_C17 -to ENET_DATA[1] +set_location_assignment PIN_B18 -to ENET_DATA[2] +set_location_assignment PIN_A18 -to ENET_DATA[3] +set_location_assignment PIN_B17 -to ENET_DATA[4] +set_location_assignment PIN_A17 -to ENET_DATA[5] +set_location_assignment PIN_B16 -to ENET_DATA[6] +set_location_assignment PIN_B15 -to ENET_DATA[7] +set_location_assignment PIN_B20 -to ENET_DATA[8] +set_location_assignment PIN_A20 -to ENET_DATA[9] +set_location_assignment PIN_C19 -to ENET_DATA[10] +set_location_assignment PIN_D19 -to ENET_DATA[11] +set_location_assignment PIN_B19 -to ENET_DATA[12] +set_location_assignment PIN_A19 -to ENET_DATA[13] +set_location_assignment PIN_E18 -to ENET_DATA[14] +set_location_assignment PIN_D18 -to ENET_DATA[15] +set_location_assignment PIN_B24 -to ENET_CLK +set_location_assignment PIN_A21 -to ENET_CMD +set_location_assignment PIN_A23 -to ENET_CS_N +set_location_assignment PIN_B21 -to ENET_INT +set_location_assignment PIN_A22 -to ENET_RD_N +set_location_assignment PIN_B22 -to ENET_WR_N +set_location_assignment PIN_B23 -to ENET_RST_N +set_location_assignment PIN_AE24 -to IRDA_TXD +set_location_assignment PIN_AE25 -to IRDA_RXD +set_location_assignment PIN_AD24 -to SD_DAT +set_location_assignment PIN_AC23 -to SD_DAT3 +set_location_assignment PIN_Y21 -to SD_CMD +set_location_assignment PIN_AD25 -to SD_CLK +set_location_assignment PIN_D25 -to GPIO_0[0] +set_location_assignment PIN_J22 -to GPIO_0[1] +set_location_assignment PIN_E26 -to GPIO_0[2] +set_location_assignment PIN_E25 -to GPIO_0[3] +set_location_assignment PIN_F24 -to GPIO_0[4] +set_location_assignment PIN_F23 -to GPIO_0[5] +set_location_assignment PIN_J21 -to GPIO_0[6] +set_location_assignment PIN_J20 -to GPIO_0[7] +set_location_assignment PIN_F25 -to GPIO_0[8] +set_location_assignment PIN_F26 -to GPIO_0[9] +set_location_assignment PIN_N18 -to GPIO_0[10] +set_location_assignment PIN_P18 -to GPIO_0[11] +set_location_assignment PIN_G23 -to GPIO_0[12] +set_location_assignment PIN_G24 -to GPIO_0[13] +set_location_assignment PIN_K22 -to GPIO_0[14] +set_location_assignment PIN_G25 -to GPIO_0[15] +set_location_assignment PIN_H23 -to GPIO_0[16] +set_location_assignment PIN_H24 -to GPIO_0[17] +set_location_assignment PIN_J23 -to GPIO_0[18] +set_location_assignment PIN_J24 -to GPIO_0[19] +set_location_assignment PIN_H25 -to GPIO_0[20] +set_location_assignment PIN_H26 -to GPIO_0[21] +set_location_assignment PIN_H19 -to GPIO_0[22] +set_location_assignment PIN_K18 -to GPIO_0[23] +set_location_assignment PIN_K19 -to GPIO_0[24] +set_location_assignment PIN_K21 -to GPIO_0[25] +set_location_assignment PIN_K23 -to GPIO_0[26] +set_location_assignment PIN_K24 -to GPIO_0[27] +set_location_assignment PIN_L21 -to GPIO_0[28] +set_location_assignment PIN_L20 -to GPIO_0[29] +set_location_assignment PIN_J25 -to GPIO_0[30] +set_location_assignment PIN_J26 -to GPIO_0[31] +set_location_assignment PIN_L23 -to GPIO_0[32] +set_location_assignment PIN_L24 -to GPIO_0[33] +set_location_assignment PIN_L25 -to GPIO_0[34] +set_location_assignment PIN_L19 -to GPIO_0[35] +set_location_assignment PIN_K25 -to GPIO_1[0] +set_location_assignment PIN_K26 -to GPIO_1[1] +set_location_assignment PIN_M22 -to GPIO_1[2] +set_location_assignment PIN_M23 -to GPIO_1[3] +set_location_assignment PIN_M19 -to GPIO_1[4] +set_location_assignment PIN_M20 -to GPIO_1[5] +set_location_assignment PIN_N20 -to GPIO_1[6] +set_location_assignment PIN_M21 -to GPIO_1[7] +set_location_assignment PIN_M24 -to GPIO_1[8] +set_location_assignment PIN_M25 -to GPIO_1[9] +set_location_assignment PIN_N24 -to GPIO_1[10] +set_location_assignment PIN_P24 -to GPIO_1[11] +set_location_assignment PIN_R25 -to GPIO_1[12] +set_location_assignment PIN_R24 -to GPIO_1[13] +set_location_assignment PIN_R20 -to GPIO_1[14] +set_location_assignment PIN_T22 -to GPIO_1[15] +set_location_assignment PIN_T23 -to GPIO_1[16] +set_location_assignment PIN_T24 -to GPIO_1[17] +set_location_assignment PIN_T25 -to GPIO_1[18] +set_location_assignment PIN_T18 -to GPIO_1[19] +set_location_assignment PIN_T21 -to GPIO_1[20] +set_location_assignment PIN_T20 -to GPIO_1[21] +set_location_assignment PIN_U26 -to GPIO_1[22] +set_location_assignment PIN_U25 -to GPIO_1[23] +set_location_assignment PIN_U23 -to GPIO_1[24] +set_location_assignment PIN_U24 -to GPIO_1[25] +set_location_assignment PIN_R19 -to GPIO_1[26] +set_location_assignment PIN_T19 -to GPIO_1[27] +set_location_assignment PIN_U20 -to GPIO_1[28] +set_location_assignment PIN_U21 -to GPIO_1[29] +set_location_assignment PIN_V26 -to GPIO_1[30] +set_location_assignment PIN_V25 -to GPIO_1[31] +set_location_assignment PIN_V24 -to GPIO_1[32] +set_location_assignment PIN_V23 -to GPIO_1[33] +set_location_assignment PIN_W25 -to GPIO_1[34] +set_location_assignment PIN_W23 -to GPIO_1[35] +set_location_assignment PIN_N25 -to rst_n +set_location_assignment PIN_V2 -to toggle_in +set_location_assignment PIN_AE23 -to port_out +set_location_assignment PIN_N2 -to clk +set_global_assignment -name DEVICE EP2C35F672C6 +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + +set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg (revision 24) @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.rpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.rpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.rpt (revision 24) @@ -0,0 +1,1072 @@ +TimeQuest Timing Analyzer report for altera_de_II_demo +Fri Oct 28 11:32:47 2011 +Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow Model Fmax Summary + 6. Slow Model Setup Summary + 7. Slow Model Hold Summary + 8. Slow Model Recovery Summary + 9. Slow Model Removal Summary + 10. Slow Model Minimum Pulse Width Summary + 11. Slow Model Setup: 'clk' + 12. Slow Model Hold: 'clk' + 13. Slow Model Minimum Pulse Width: 'clk' + 14. Setup Times + 15. Hold Times + 16. Clock to Output Times + 17. Minimum Clock to Output Times + 18. Fast Model Setup Summary + 19. Fast Model Hold Summary + 20. Fast Model Recovery Summary + 21. Fast Model Removal Summary + 22. Fast Model Minimum Pulse Width Summary + 23. Fast Model Setup: 'clk' + 24. Fast Model Hold: 'clk' + 25. Fast Model Minimum Pulse Width: 'clk' + 26. Setup Times + 27. Hold Times + 28. Clock to Output Times + 29. Minimum Clock to Output Times + 30. Multicorner Timing Analysis Summary + 31. Setup Times + 32. Hold Times + 33. Clock to Output Times + 34. Minimum Clock to Output Times + 35. Setup Transfers + 36. Hold Transfers + 37. Report TCCS + 38. Report RSKM + 39. Unconstrained Paths + 40. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2011 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+------------------------------------------------------------------+ +; Quartus II Version ; Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version ; +; Revision Name ; altera_de_II_demo ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C35F672C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+------------------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 2 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ + + ++--------------------------------------------------+ +; Slow Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 249.38 MHz ; 249.38 MHz ; clk ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++--------------------------------+ +; Slow Model Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; clk ; -3.010 ; -94.090 ; ++-------+--------+---------------+ + + ++-------------------------------+ +; Slow Model Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clk ; 0.391 ; 0.000 ; ++-------+-------+---------------+ + + +------------------------------- +; Slow Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Slow Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Slow Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clk ; -1.380 ; -36.380 ; ++-------+--------+-----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Setup: 'clk' ; ++--------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -3.010 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 4.046 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.995 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.007 ; 4.038 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.951 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 3.987 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.934 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 3.970 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.922 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 3.958 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.917 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.007 ; 3.960 ; +; -2.890 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 3.926 ; +; -2.890 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 3.926 ; +; -2.890 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 3.926 ; +; -2.890 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 3.926 ; ++--------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Hold: 'clk' ; ++-------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.391 ; sig_gen:sig_gen_1|toggle_r ; sig_gen:sig_gen_1|toggle_r ; clk ; clk ; 0.000 ; 0.000 ; 0.657 ; +; 0.391 ; port_blinker:port_blinker_1|port_level_r ; port_blinker:port_blinker_1|port_level_r ; clk ; clk ; 0.000 ; 0.000 ; 0.657 ; +; 0.519 ; sig_gen:sig_gen_1|toggle_d1_r ; sig_gen:sig_gen_1|toggle_r ; clk ; clk ; 0.000 ; 0.000 ; 0.785 ; +; 0.531 ; port_blinker:port_blinker_1|val_cnt_r[31] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 0.000 ; 0.000 ; 0.797 ; +; 0.795 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.061 ; +; 0.799 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[16] ; clk ; clk ; 0.000 ; 0.000 ; 1.065 ; +; 0.805 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[17] ; clk ; clk ; 0.000 ; 0.000 ; 1.071 ; +; 0.805 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.071 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[29] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[30] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[18] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[20] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[23] ; port_blinker:port_blinker_1|val_cnt_r[23] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[25] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[27] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[14] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[13] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[7] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.806 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 0.000 ; 0.000 ; 1.072 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[28] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[19] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[24] ; port_blinker:port_blinker_1|val_cnt_r[24] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[26] ; port_blinker:port_blinker_1|val_cnt_r[26] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[12] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.838 ; port_blinker:port_blinker_1|val_cnt_r[3] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.104 ; +; 0.839 ; port_blinker:port_blinker_1|val_cnt_r[22] ; port_blinker:port_blinker_1|val_cnt_r[22] ; clk ; clk ; 0.000 ; 0.000 ; 1.105 ; +; 0.839 ; port_blinker:port_blinker_1|val_cnt_r[21] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 1.105 ; +; 0.839 ; port_blinker:port_blinker_1|val_cnt_r[6] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 0.000 ; 0.000 ; 1.105 ; +; 0.839 ; port_blinker:port_blinker_1|val_cnt_r[5] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 1.105 ; +; 0.995 ; sig_gen:sig_gen_1|toggle_r ; port_blinker:port_blinker_1|port_level_r ; clk ; clk ; 0.000 ; 0.000 ; 1.261 ; +; 1.178 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.444 ; +; 1.182 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[17] ; clk ; clk ; 0.000 ; 0.000 ; 1.448 ; +; 1.188 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[18] ; clk ; clk ; 0.000 ; 0.000 ; 1.454 ; +; 1.188 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 0.000 ; 0.000 ; 1.454 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[30] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[14] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[13] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[26] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[20] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.189 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 1.455 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[28] ; port_blinker:port_blinker_1|val_cnt_r[29] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[19] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[24] ; port_blinker:port_blinker_1|val_cnt_r[25] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[26] ; port_blinker:port_blinker_1|val_cnt_r[27] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[12] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.224 ; port_blinker:port_blinker_1|val_cnt_r[3] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 1.490 ; +; 1.225 ; port_blinker:port_blinker_1|val_cnt_r[22] ; port_blinker:port_blinker_1|val_cnt_r[23] ; clk ; clk ; 0.000 ; 0.000 ; 1.491 ; +; 1.225 ; port_blinker:port_blinker_1|val_cnt_r[6] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 0.000 ; 0.000 ; 1.491 ; +; 1.225 ; port_blinker:port_blinker_1|val_cnt_r[21] ; port_blinker:port_blinker_1|val_cnt_r[22] ; clk ; clk ; 0.000 ; 0.000 ; 1.491 ; +; 1.225 ; port_blinker:port_blinker_1|val_cnt_r[5] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 0.000 ; 0.000 ; 1.491 ; +; 1.249 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 0.000 ; 0.000 ; 1.515 ; +; 1.253 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[18] ; clk ; clk ; 0.000 ; 0.000 ; 1.519 ; +; 1.259 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 1.525 ; +; 1.259 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.525 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[13] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[29] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[27] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[20] ; port_blinker:port_blinker_1|val_cnt_r[22] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.260 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 0.000 ; 0.000 ; 1.526 ; +; 1.281 ; port_blinker:port_blinker_1|val_cnt_r[23] ; port_blinker:port_blinker_1|val_cnt_r[24] ; clk ; clk ; 0.000 ; 0.000 ; 1.547 ; +; 1.281 ; port_blinker:port_blinker_1|val_cnt_r[7] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 0.000 ; 0.000 ; 1.547 ; +; 1.288 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[16] ; clk ; clk ; 0.000 ; -0.007 ; 1.547 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[28] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[12] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[26] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[24] ; port_blinker:port_blinker_1|val_cnt_r[26] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[19] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.295 ; port_blinker:port_blinker_1|val_cnt_r[3] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 1.561 ; +; 1.296 ; port_blinker:port_blinker_1|val_cnt_r[21] ; port_blinker:port_blinker_1|val_cnt_r[23] ; clk ; clk ; 0.000 ; 0.000 ; 1.562 ; +; 1.296 ; port_blinker:port_blinker_1|val_cnt_r[5] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 0.000 ; 0.000 ; 1.562 ; +; 1.320 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.586 ; +; 1.324 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 1.590 ; +; 1.330 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 1.596 ; +; 1.330 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 1.596 ; +; 1.331 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 1.597 ; +; 1.331 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 1.597 ; +; 1.331 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 1.597 ; +; 1.331 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 1.597 ; +; 1.331 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 1.597 ; ++-------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Minimum Pulse Width: 'clk' ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------------------------+ +; -1.380 ; 1.000 ; 2.380 ; Port Rate ; clk ; Rise ; clk ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|port_level_r ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|port_level_r ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[0] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[0] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[10] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[10] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[11] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[11] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[12] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[12] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[13] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[13] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[14] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[14] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[15] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[15] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[16] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[16] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[17] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[17] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[18] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[18] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[19] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[19] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[1] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[1] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[20] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[20] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[21] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[21] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[22] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[22] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[23] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[23] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[24] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[24] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[25] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[25] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[26] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[26] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[27] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[27] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[28] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[28] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[29] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[29] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[2] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[2] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[30] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[30] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[31] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[31] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[3] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[3] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[4] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[4] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[5] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[5] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[6] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[6] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[7] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[7] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[8] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[8] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[9] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[9] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_d1_r ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_d1_r ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_r ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_r ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|port_level_r|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|port_level_r|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[10]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[10]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[11]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[11]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[12]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[12]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[13]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[13]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[14]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[14]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[15]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[15]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[16]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[16]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[17]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[17]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[18]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[18]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[19]|clk ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; toggle_in ; clk ; 5.557 ; 5.557 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; toggle_in ; clk ; -5.163 ; -5.163 ; Rise ; clk ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; port_out ; clk ; 8.556 ; 8.556 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; port_out ; clk ; 8.556 ; 8.556 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++--------------------------------+ +; Fast Model Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; clk ; -0.845 ; -25.749 ; ++-------+--------+---------------+ + + ++-------------------------------+ +; Fast Model Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clk ; 0.215 ; 0.000 ; ++-------+-------+---------------+ + + +------------------------------- +; Fast Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Fast Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Fast Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clk ; -1.380 ; -36.380 ; ++-------+--------+-----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Setup: 'clk' ; ++--------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.845 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.877 ; +; -0.839 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 1.000 ; -0.006 ; 1.865 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.815 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.847 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.006 ; 1.846 ; +; -0.808 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 1.000 ; -0.006 ; 1.834 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.806 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.838 ; +; -0.804 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 1.000 ; -0.006 ; 1.830 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.797 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.829 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.787 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.819 ; +; -0.777 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 1.000 ; 0.006 ; 1.815 ; ++--------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Hold: 'clk' ; ++-------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.215 ; sig_gen:sig_gen_1|toggle_r ; sig_gen:sig_gen_1|toggle_r ; clk ; clk ; 0.000 ; 0.000 ; 0.367 ; +; 0.215 ; port_blinker:port_blinker_1|port_level_r ; port_blinker:port_blinker_1|port_level_r ; clk ; clk ; 0.000 ; 0.000 ; 0.367 ; +; 0.239 ; sig_gen:sig_gen_1|toggle_d1_r ; sig_gen:sig_gen_1|toggle_r ; clk ; clk ; 0.000 ; 0.000 ; 0.391 ; +; 0.243 ; port_blinker:port_blinker_1|val_cnt_r[31] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 0.000 ; 0.000 ; 0.395 ; +; 0.355 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.507 ; +; 0.357 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[16] ; clk ; clk ; 0.000 ; 0.000 ; 0.509 ; +; 0.359 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[17] ; clk ; clk ; 0.000 ; 0.000 ; 0.511 ; +; 0.359 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.511 ; +; 0.360 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[18] ; clk ; clk ; 0.000 ; 0.000 ; 0.512 ; +; 0.360 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[25] ; clk ; clk ; 0.000 ; 0.000 ; 0.512 ; +; 0.360 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[27] ; clk ; clk ; 0.000 ; 0.000 ; 0.512 ; +; 0.360 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 0.000 ; 0.000 ; 0.512 ; +; 0.360 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 0.000 ; 0.000 ; 0.512 ; +; 0.360 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 0.000 ; 0.000 ; 0.512 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[29] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[30] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[20] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[23] ; port_blinker:port_blinker_1|val_cnt_r[23] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[14] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[13] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.361 ; port_blinker:port_blinker_1|val_cnt_r[7] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 0.000 ; 0.000 ; 0.513 ; +; 0.371 ; port_blinker:port_blinker_1|val_cnt_r[19] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 0.523 ; +; 0.371 ; port_blinker:port_blinker_1|val_cnt_r[24] ; port_blinker:port_blinker_1|val_cnt_r[24] ; clk ; clk ; 0.000 ; 0.000 ; 0.523 ; +; 0.371 ; port_blinker:port_blinker_1|val_cnt_r[26] ; port_blinker:port_blinker_1|val_cnt_r[26] ; clk ; clk ; 0.000 ; 0.000 ; 0.523 ; +; 0.371 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 0.000 ; 0.000 ; 0.523 ; +; 0.371 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 0.000 ; 0.000 ; 0.523 ; +; 0.371 ; port_blinker:port_blinker_1|val_cnt_r[3] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 0.523 ; +; 0.372 ; port_blinker:port_blinker_1|val_cnt_r[28] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 0.524 ; +; 0.372 ; port_blinker:port_blinker_1|val_cnt_r[22] ; port_blinker:port_blinker_1|val_cnt_r[22] ; clk ; clk ; 0.000 ; 0.000 ; 0.524 ; +; 0.372 ; port_blinker:port_blinker_1|val_cnt_r[21] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 0.524 ; +; 0.372 ; port_blinker:port_blinker_1|val_cnt_r[12] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 0.524 ; +; 0.372 ; port_blinker:port_blinker_1|val_cnt_r[6] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 0.000 ; 0.000 ; 0.524 ; +; 0.372 ; port_blinker:port_blinker_1|val_cnt_r[5] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 0.524 ; +; 0.447 ; sig_gen:sig_gen_1|toggle_r ; port_blinker:port_blinker_1|port_level_r ; clk ; clk ; 0.000 ; 0.000 ; 0.599 ; +; 0.493 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.645 ; +; 0.495 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[17] ; clk ; clk ; 0.000 ; 0.000 ; 0.647 ; +; 0.497 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[18] ; clk ; clk ; 0.000 ; 0.000 ; 0.649 ; +; 0.497 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 0.000 ; 0.000 ; 0.649 ; +; 0.498 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 0.650 ; +; 0.498 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[26] ; clk ; clk ; 0.000 ; 0.000 ; 0.650 ; +; 0.498 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 0.000 ; 0.000 ; 0.650 ; +; 0.498 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 0.650 ; +; 0.498 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 0.650 ; +; 0.498 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 0.650 ; +; 0.499 ; port_blinker:port_blinker_1|val_cnt_r[30] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 0.000 ; 0.000 ; 0.651 ; +; 0.499 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 0.651 ; +; 0.499 ; port_blinker:port_blinker_1|val_cnt_r[14] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 0.000 ; 0.000 ; 0.651 ; +; 0.499 ; port_blinker:port_blinker_1|val_cnt_r[13] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 0.651 ; +; 0.499 ; port_blinker:port_blinker_1|val_cnt_r[20] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 0.651 ; +; 0.499 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 0.651 ; +; 0.511 ; port_blinker:port_blinker_1|val_cnt_r[24] ; port_blinker:port_blinker_1|val_cnt_r[25] ; clk ; clk ; 0.000 ; 0.000 ; 0.663 ; +; 0.511 ; port_blinker:port_blinker_1|val_cnt_r[26] ; port_blinker:port_blinker_1|val_cnt_r[27] ; clk ; clk ; 0.000 ; 0.000 ; 0.663 ; +; 0.511 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[9] ; clk ; clk ; 0.000 ; 0.000 ; 0.663 ; +; 0.511 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 0.000 ; 0.000 ; 0.663 ; +; 0.511 ; port_blinker:port_blinker_1|val_cnt_r[19] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 0.663 ; +; 0.511 ; port_blinker:port_blinker_1|val_cnt_r[3] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 0.663 ; +; 0.512 ; port_blinker:port_blinker_1|val_cnt_r[28] ; port_blinker:port_blinker_1|val_cnt_r[29] ; clk ; clk ; 0.000 ; 0.000 ; 0.664 ; +; 0.512 ; port_blinker:port_blinker_1|val_cnt_r[22] ; port_blinker:port_blinker_1|val_cnt_r[23] ; clk ; clk ; 0.000 ; 0.000 ; 0.664 ; +; 0.512 ; port_blinker:port_blinker_1|val_cnt_r[12] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 0.000 ; 0.000 ; 0.664 ; +; 0.512 ; port_blinker:port_blinker_1|val_cnt_r[6] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 0.000 ; 0.000 ; 0.664 ; +; 0.512 ; port_blinker:port_blinker_1|val_cnt_r[21] ; port_blinker:port_blinker_1|val_cnt_r[22] ; clk ; clk ; 0.000 ; 0.000 ; 0.664 ; +; 0.512 ; port_blinker:port_blinker_1|val_cnt_r[5] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 0.000 ; 0.000 ; 0.664 ; +; 0.528 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[2] ; clk ; clk ; 0.000 ; 0.000 ; 0.680 ; +; 0.530 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[18] ; clk ; clk ; 0.000 ; 0.000 ; 0.682 ; +; 0.532 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 0.684 ; +; 0.532 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 0.684 ; +; 0.533 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[27] ; clk ; clk ; 0.000 ; 0.000 ; 0.685 ; +; 0.533 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[11] ; clk ; clk ; 0.000 ; 0.000 ; 0.685 ; +; 0.533 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 0.685 ; +; 0.533 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 0.685 ; +; 0.533 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[29] ; clk ; clk ; 0.000 ; 0.000 ; 0.685 ; +; 0.533 ; port_blinker:port_blinker_1|val_cnt_r[11] ; port_blinker:port_blinker_1|val_cnt_r[13] ; clk ; clk ; 0.000 ; 0.000 ; 0.685 ; +; 0.534 ; port_blinker:port_blinker_1|val_cnt_r[29] ; port_blinker:port_blinker_1|val_cnt_r[31] ; clk ; clk ; 0.000 ; 0.000 ; 0.686 ; +; 0.534 ; port_blinker:port_blinker_1|val_cnt_r[13] ; port_blinker:port_blinker_1|val_cnt_r[15] ; clk ; clk ; 0.000 ; 0.000 ; 0.686 ; +; 0.534 ; port_blinker:port_blinker_1|val_cnt_r[20] ; port_blinker:port_blinker_1|val_cnt_r[22] ; clk ; clk ; 0.000 ; 0.000 ; 0.686 ; +; 0.534 ; port_blinker:port_blinker_1|val_cnt_r[4] ; port_blinker:port_blinker_1|val_cnt_r[6] ; clk ; clk ; 0.000 ; 0.000 ; 0.686 ; +; 0.546 ; port_blinker:port_blinker_1|val_cnt_r[24] ; port_blinker:port_blinker_1|val_cnt_r[26] ; clk ; clk ; 0.000 ; 0.000 ; 0.698 ; +; 0.546 ; port_blinker:port_blinker_1|val_cnt_r[8] ; port_blinker:port_blinker_1|val_cnt_r[10] ; clk ; clk ; 0.000 ; 0.000 ; 0.698 ; +; 0.546 ; port_blinker:port_blinker_1|val_cnt_r[26] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 0.698 ; +; 0.546 ; port_blinker:port_blinker_1|val_cnt_r[10] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 0.698 ; +; 0.546 ; port_blinker:port_blinker_1|val_cnt_r[19] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 0.698 ; +; 0.546 ; port_blinker:port_blinker_1|val_cnt_r[3] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 0.698 ; +; 0.547 ; port_blinker:port_blinker_1|val_cnt_r[28] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 0.699 ; +; 0.547 ; port_blinker:port_blinker_1|val_cnt_r[12] ; port_blinker:port_blinker_1|val_cnt_r[14] ; clk ; clk ; 0.000 ; 0.000 ; 0.699 ; +; 0.547 ; port_blinker:port_blinker_1|val_cnt_r[21] ; port_blinker:port_blinker_1|val_cnt_r[23] ; clk ; clk ; 0.000 ; 0.000 ; 0.699 ; +; 0.547 ; port_blinker:port_blinker_1|val_cnt_r[5] ; port_blinker:port_blinker_1|val_cnt_r[7] ; clk ; clk ; 0.000 ; 0.000 ; 0.699 ; +; 0.552 ; port_blinker:port_blinker_1|val_cnt_r[15] ; port_blinker:port_blinker_1|val_cnt_r[16] ; clk ; clk ; 0.000 ; -0.006 ; 0.698 ; +; 0.554 ; port_blinker:port_blinker_1|val_cnt_r[23] ; port_blinker:port_blinker_1|val_cnt_r[24] ; clk ; clk ; 0.000 ; 0.000 ; 0.706 ; +; 0.554 ; port_blinker:port_blinker_1|val_cnt_r[7] ; port_blinker:port_blinker_1|val_cnt_r[8] ; clk ; clk ; 0.000 ; 0.000 ; 0.706 ; +; 0.563 ; port_blinker:port_blinker_1|val_cnt_r[0] ; port_blinker:port_blinker_1|val_cnt_r[3] ; clk ; clk ; 0.000 ; 0.000 ; 0.715 ; +; 0.565 ; port_blinker:port_blinker_1|val_cnt_r[16] ; port_blinker:port_blinker_1|val_cnt_r[19] ; clk ; clk ; 0.000 ; 0.000 ; 0.717 ; +; 0.567 ; port_blinker:port_blinker_1|val_cnt_r[17] ; port_blinker:port_blinker_1|val_cnt_r[20] ; clk ; clk ; 0.000 ; 0.000 ; 0.719 ; +; 0.567 ; port_blinker:port_blinker_1|val_cnt_r[1] ; port_blinker:port_blinker_1|val_cnt_r[4] ; clk ; clk ; 0.000 ; 0.000 ; 0.719 ; +; 0.568 ; port_blinker:port_blinker_1|val_cnt_r[25] ; port_blinker:port_blinker_1|val_cnt_r[28] ; clk ; clk ; 0.000 ; 0.000 ; 0.720 ; +; 0.568 ; port_blinker:port_blinker_1|val_cnt_r[9] ; port_blinker:port_blinker_1|val_cnt_r[12] ; clk ; clk ; 0.000 ; 0.000 ; 0.720 ; +; 0.568 ; port_blinker:port_blinker_1|val_cnt_r[18] ; port_blinker:port_blinker_1|val_cnt_r[21] ; clk ; clk ; 0.000 ; 0.000 ; 0.720 ; +; 0.568 ; port_blinker:port_blinker_1|val_cnt_r[2] ; port_blinker:port_blinker_1|val_cnt_r[5] ; clk ; clk ; 0.000 ; 0.000 ; 0.720 ; +; 0.568 ; port_blinker:port_blinker_1|val_cnt_r[27] ; port_blinker:port_blinker_1|val_cnt_r[30] ; clk ; clk ; 0.000 ; 0.000 ; 0.720 ; ++-------+-------------------------------------------+-------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Minimum Pulse Width: 'clk' ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------------------------+ +; -1.380 ; 1.000 ; 2.380 ; Port Rate ; clk ; Rise ; clk ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|port_level_r ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|port_level_r ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[0] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[0] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[10] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[10] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[11] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[11] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[12] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[12] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[13] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[13] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[14] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[14] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[15] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[15] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[16] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[16] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[17] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[17] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[18] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[18] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[19] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[19] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[1] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[1] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[20] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[20] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[21] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[21] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[22] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[22] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[23] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[23] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[24] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[24] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[25] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[25] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[26] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[26] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[27] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[27] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[28] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[28] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[29] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[29] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[2] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[2] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[30] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[30] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[31] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[31] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[3] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[3] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[4] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[4] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[5] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[5] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[6] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[6] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[7] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[7] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[8] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[8] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[9] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; port_blinker:port_blinker_1|val_cnt_r[9] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_d1_r ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_d1_r ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_r ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; sig_gen:sig_gen_1|toggle_r ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|port_level_r|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|port_level_r|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[10]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[10]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[11]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[11]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[12]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[12]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[13]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[13]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[14]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[14]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[15]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[15]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[16]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[16]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[17]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[17]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[18]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[18]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; port_blinker_1|val_cnt_r[19]|clk ; ++--------+--------------+----------------+------------------+-------+------------+-------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; toggle_in ; clk ; 2.989 ; 2.989 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; toggle_in ; clk ; -2.830 ; -2.830 ; Rise ; clk ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; port_out ; clk ; 4.700 ; 4.700 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; port_out ; clk ; 4.700 ; 4.700 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+---------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+---------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -3.010 ; 0.215 ; N/A ; N/A ; -1.380 ; +; clk ; -3.010 ; 0.215 ; N/A ; N/A ; -1.380 ; +; Design-wide TNS ; -94.09 ; 0.0 ; 0.0 ; 0.0 ; -36.38 ; +; clk ; -94.090 ; 0.000 ; N/A ; N/A ; -36.380 ; ++------------------+---------+-------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; toggle_in ; clk ; 5.557 ; 5.557 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; toggle_in ; clk ; -2.830 ; -2.830 ; Rise ; clk ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; port_out ; clk ; 8.556 ; 8.556 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; port_out ; clk ; 4.700 ; 4.700 ; Rise ; clk ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 1620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 1620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 2 ; 2 ; +; Unconstrained Input Port Paths ; 37 ; 37 ; +; Unconstrained Output Ports ; 1 ; 1 ; +; Unconstrained Output Port Paths ; 1 ; 1 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II TimeQuest Timing Analyzer + Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version + Info: Processing started: Fri Oct 28 11:32:45 2011 +Info: Command: quartus_sta altera_de_II_demo -c altera_de_II_demo +Info: qsta_default_script.tcl version: #1 +Info: Parallel compilation is enabled and will use 2 of the 2 processors detected +Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info: Deriving Clocks + Info: create_clock -period 1.000 -name clk clk +Info: Analyzing Slow Model +Critical Warning: Timing requirements not met +Info: Worst-case setup slack is -3.010 + Info: Slack End Point TNS Clock + Info: ========= ============= ===================== + Info: -3.010 -94.090 clk +Info: Worst-case hold slack is 0.391 + Info: Slack End Point TNS Clock + Info: ========= ============= ===================== + Info: 0.391 0.000 clk +Info: No Recovery paths to report +Info: No Removal paths to report +Info: Worst-case minimum pulse width slack is -1.380 + Info: Slack End Point TNS Clock + Info: ========= ============= ===================== + Info: -1.380 -36.380 clk +Info: The selected device family is not supported by the report_metastability command. +Info: Analyzing Fast Model +Info: Started post-fitting delay annotation +Warning: Found 1 output pins without output pin load capacitance assignment + Info: Pin "port_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Critical Warning: Timing requirements not met +Info: Worst-case setup slack is -0.845 + Info: Slack End Point TNS Clock + Info: ========= ============= ===================== + Info: -0.845 -25.749 clk +Info: Worst-case hold slack is 0.215 + Info: Slack End Point TNS Clock + Info: ========= ============= ===================== + Info: 0.215 0.000 clk +Info: No Recovery paths to report +Info: No Removal paths to report +Info: Worst-case minimum pulse width slack is -1.380 + Info: Slack End Point TNS Clock + Info: ========= ============= ===================== + Info: -1.380 -36.380 clk +Info: The selected device family is not supported by the report_metastability command. +Info: Design is not fully constrained for setup requirements +Info: Design is not fully constrained for hold requirements +Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 236 megabytes + Info: Processing ended: Fri Oct 28 11:32:47 2011 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.db_info =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.db_info (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.db_info (revision 24) @@ -0,0 +1,3 @@ +Quartus_Version = Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version +Version_Index = 234934273 +Creation_Time = Thu Oct 27 15:34:18 2011 Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.logdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.logdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.logdb (revision 24) @@ -0,0 +1 @@ +v1 Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.cdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.cdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.cdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.dfp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.dfp =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.dfp (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.dfp (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.dfp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.dpi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.dpi =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.dpi (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.dpi (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.dpi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.kpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.kpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.kpt (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.hdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.hdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.hdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.kpt =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.kpt (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.kpt (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.sig =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.sig (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.sig (revision 24) @@ -0,0 +1 @@ +9a9b3e9d6db0b9dc3feca87af856c \ No newline at end of file Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.rcfdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.rcfdb =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.rcfdb (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.rcfdb (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.rcfdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hb_info =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hb_info =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hb_info (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hb_info (revision 24)

TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hb_info Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/README =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/README (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/README (revision 24) @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + Index: TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.summary =================================================================== --- TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.summary (nonexistent) +++ TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.summary (revision 24) @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Fri Oct 28 11:32:34 2011 +Quartus II Version : 11.0 Build 208 07/03/2011 SP 1 SJ Full Version +Revision Name : altera_de_II_demo +Top-level Entity Name : altera_de_II_demo +Family : Cyclone II +Total logic elements : 46 + Total combinational functions : 45 + Dedicated logic registers : 35 +Total registers : 35 +Total pins : 4 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 Index: TUT/soc/arria_ii_gx_demo_soc/1.0/vhd/arria_ii_gx_demo_soc.vhd =================================================================== --- TUT/soc/arria_ii_gx_demo_soc/1.0/vhd/arria_ii_gx_demo_soc.vhd (nonexistent) +++ TUT/soc/arria_ii_gx_demo_soc/1.0/vhd/arria_ii_gx_demo_soc.vhd (revision 24) @@ -0,0 +1,430 @@ +-- **************************************************** +-- ** File: arria_ii_gx_demo_soc.vhd +-- ** Date: 07.11.2011 14:06:37 +-- ** Description: +-- ** +-- ** This file was generated by Kactus2 vhdl generator +-- ** +-- **************************************************** + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +library pcie_to_hibi_4x; +use pcie_to_hibi_4x.all; +library hibi_mem_dma; +use hibi_mem_dma.all; +library picture_manip; +use picture_manip.all; +library pciture_manip; +use pciture_manip.all; +library hibi; +use hibi.all; + +entity arria_ii_gx_demo_soc is + + port ( + clkin_bot_p : in std_logic; + ddr2_dimm_addr : out std_logic_vector(15 downto 0); + ddr2_dimm_ba : out std_logic_vector(2 downto 0); + ddr2_dimm_cas_n : out std_logic; + ddr2_dimm_cke : out std_logic; + ddr2_dimm_clk : inout std_logic_vector(1 downto 0); + ddr2_dimm_clk_n : inout std_logic_vector(1 downto 0); + ddr2_dimm_cs_n : out std_logic; + ddr2_dimm_dm : out std_logic_vector(7 downto 0); + ddr2_dimm_dq : inout std_logic_vector(63 downto 0); + ddr2_dimm_dqs : inout std_logic_vector(7 downto 0); + ddr2_dimm_dqs_n : inout std_logic_vector(7 downto 0); + ddr2_dimm_odt : out std_logic; + ddr2_dimm_ras_n : out std_logic; + ddr2_dimm_we_n : out std_logic; + pcie_refclk_p : in std_logic; + pcie_rx_p : in std_logic_vector(3 downto 0); + pcie_tx_p : out std_logic_vector(3 downto 0); + user_pb : in std_logic_vector(2 downto 0)); + +end arria_ii_gx_demo_soc; + +architecture structural of arria_ii_gx_demo_soc is + + signal a2_ddr2_dimm_1GB_1_local_address_hibi_mem_dma_1_mem_addr_out : std_logic_vector(24 downto 0); + signal a2_ddr2_dimm_1GB_1_local_be_hibi_mem_dma_1_mem_be_out : std_logic_vector(31 downto 0); + signal a2_ddr2_dimm_1GB_1_local_burstbegin_hibi_mem_dma_1_mem_burst_begin_out : std_logic; + signal a2_ddr2_dimm_1GB_1_local_init_done_hibi_mem_dma_1_mem_init_done_in : std_logic; + signal a2_ddr2_dimm_1GB_1_local_rdata_hibi_mem_dma_1_mem_rdata_in : std_logic_vector(255 downto 0); + signal a2_ddr2_dimm_1GB_1_local_rdata_valid_hibi_mem_dma_1_mem_rdata_valid_in : std_logic; + signal a2_ddr2_dimm_1GB_1_local_read_req_hibi_mem_dma_1_mem_rd_req_out : std_logic; + signal a2_ddr2_dimm_1GB_1_local_ready_hibi_mem_dma_1_mem_ready_in : std_logic; + signal a2_ddr2_dimm_1GB_1_local_size_hibi_mem_dma_1_mem_burst_size_out : std_logic_vector(2 downto 0); + signal a2_ddr2_dimm_1GB_1_local_wdata_hibi_mem_dma_1_mem_wdata_out : std_logic_vector(255 downto 0); + signal a2_ddr2_dimm_1GB_1_local_write_req_hibi_mem_dma_1_mem_wr_req_out : std_logic; + signal a2_ddr2_dimm_1GB_1_phy_clk_pcie_to_hibi_4x_1_clk_in : std_logic; + signal hibi_segment_small_1_agent_addr_out_17_hibi_mem_dma_1_hibi_addr_in : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_addr_in_17_hibi_mem_dma_1_hibi_addr_out : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_comm_out_17_hibi_mem_dma_1_hibi_comm_in : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_comm_in_17_hibi_mem_dma_1_hibi_comm_out : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_data_out_17_hibi_mem_dma_1_hibi_data_in : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_data_in_17_hibi_mem_dma_1_hibi_data_out : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_empty_out_17_hibi_mem_dma_1_hibi_empty_in : std_logic; + signal hibi_segment_small_1_agent_full_out_17_hibi_mem_dma_1_hibi_full_in : std_logic; + signal hibi_segment_small_1_agent_msg_addr_in_17_hibi_mem_dma_1_hibi_msg_addr_out : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_msg_comm_out_17_hibi_mem_dma_1_hibi_msg_comm_in : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_msg_comm_in_17_hibi_mem_dma_1_hibi_msg_comm_out : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_msg_data_out_17_hibi_mem_dma_1_hibi_msg_data_in : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_msg_data_in_17_hibi_mem_dma_1_hibi_msg_data_out : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_msg_empty_out_17_hibi_mem_dma_1_hibi_msg_empty_in : std_logic; + signal hibi_segment_small_1_agent_msg_full_out_17_hibi_mem_dma_1_hibi_msg_full_in : std_logic; + signal hibi_segment_small_1_agent_msg_re_in_17_hibi_mem_dma_1_hibi_msg_re_out : std_logic; + signal hibi_segment_small_1_agent_msg_we_in_17_hibi_mem_dma_1_hibi_msg_we_out : std_logic; + signal hibi_segment_small_1_agent_re_in_17_hibi_mem_dma_1_hibi_re_out : std_logic; + signal hibi_segment_small_1_agent_we_in_17_hibi_mem_dma_1_hibi_we_out : std_logic; + signal hibi_segment_small_1_agent_av_in_1_pcie_to_hibi_4x_1_hibi_av_out : std_logic; + signal hibi_segment_small_1_agent_av_in_2_picture_manip_1_hibi_av_out : std_logic; + signal hibi_segment_small_1_agent_av_out_1_pcie_to_hibi_4x_1_hibi_av_in : std_logic; + signal hibi_segment_small_1_agent_av_out_2_picture_manip_1_hibi_av_in : std_logic; + signal hibi_segment_small_1_agent_comm_in_1_pcie_to_hibi_4x_1_hibi_comm_out : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_comm_in_2_picture_manip_1_hibi_comm_out : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_comm_out_1_pcie_to_hibi_4x_1_hibi_comm_in : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_comm_out_2_picture_manip_1_hibi_comm_in : std_logic_vector(2 downto 0); + signal hibi_segment_small_1_agent_data_in_1_pcie_to_hibi_4x_1_hibi_data_out : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_data_in_2_picture_manip_1_hibi_data_out : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_data_out_1_pcie_to_hibi_4x_1_hibi_data_in : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_data_out_2_picture_manip_1_hibi_data_in : std_logic_vector(31 downto 0); + signal hibi_segment_small_1_agent_empty_out_1_pcie_to_hibi_4x_1_hibi_empty_in : std_logic; + signal hibi_segment_small_1_agent_empty_out_2_picture_manip_1_hibi_empty_in : std_logic; + signal hibi_segment_small_1_agent_full_out_1_pcie_to_hibi_4x_1_hibi_full_in : std_logic; + signal hibi_segment_small_1_agent_full_out_2_picture_manip_1_hibi_full_in : std_logic; + signal hibi_segment_small_1_agent_one_d_out_1_pcie_to_hibi_4x_1_hibi_one_d_in : std_logic; + signal hibi_segment_small_1_agent_one_d_out_2_picture_manip_1_hibi_one_d_in : std_logic; + signal hibi_segment_small_1_agent_one_p_out_1_pcie_to_hibi_4x_1_hibi_one_p_in : std_logic; + signal hibi_segment_small_1_agent_one_p_out_2_picture_manip_1_hibi_one_p_in : std_logic; + signal hibi_segment_small_1_agent_re_in_1_pcie_to_hibi_4x_1_hibi_re_out : std_logic; + signal hibi_segment_small_1_agent_re_in_2_picture_manip_1_hibi_re_out : std_logic; + signal hibi_segment_small_1_agent_we_in_1_pcie_to_hibi_4x_1_hibi_we_out : std_logic; + signal hibi_segment_small_1_agent_we_in_2_picture_manip_1_hibi_we_out : std_logic; + + -- Altera ddr2 memory controller + component a2_ddr2_dimm_1GB + port ( + global_reset_n : in std_logic; + local_address : in std_logic_vector(24 downto 0); + local_be : in std_logic_vector(31 downto 0); + local_burstbegin : in std_logic; + local_init_done : out std_logic; + local_rdata : out std_logic_vector(255 downto 0); + local_rdata_valid : out std_logic; + local_read_req : in std_logic; + local_ready : out std_logic; + local_size : in std_logic_vector(2 downto 0); + local_wdata : in std_logic_vector(255 downto 0); + local_write_req : in std_logic; + mem_addr : out std_logic_vector(13 downto 0); + mem_ba : out std_logic_vector(2 downto 0); + mem_cas_n : out std_logic; + mem_cke : out std_logic; + mem_clk : inout std_logic_vector(1 downto 0); + mem_clk_n : inout std_logic_vector(1 downto 0); + mem_cs_n : out std_logic; + mem_dm : out std_logic_vector(7 downto 0); + mem_dq : inout std_logic_vector(63 downto 0); + mem_dqs : inout std_logic_vector(7 downto 0); + mem_dqsn : inout std_logic_vector(7 downto 0); + mem_odt : out std_logic; + mem_ras_n : out std_logic; + mem_we_n : out std_logic; + phy_clk : out std_logic; + pll_ref_clk : in std_logic); + end component; + + -- HIBI memory DMA access IP. + component hibi_mem_dma + port ( + clk : in std_logic; + hibi_addr_in : in std_logic_vector(31 downto 0); + hibi_addr_out : out std_logic_vector(31 downto 0); + hibi_comm_in : in std_logic_vector(2 downto 0); + hibi_comm_out : out std_logic_vector(2 downto 0); + hibi_data_in : in std_logic_vector(31 downto 0); + hibi_data_out : out std_logic_vector(31 downto 0); + hibi_empty_in : in std_logic; + hibi_full_in : in std_logic; + hibi_msg_addr_out : out std_logic_vector(31 downto 0); + hibi_msg_comm_in : in std_logic_vector(2 downto 0); + hibi_msg_comm_out : out std_logic_vector(2 downto 0); + hibi_msg_data_in : in std_logic_vector(31 downto 0); + hibi_msg_data_out : out std_logic_vector(31 downto 0); + hibi_msg_empty_in : in std_logic; + hibi_msg_full_in : in std_logic; + hibi_msg_re_out : out std_logic; + hibi_msg_we_out : out std_logic; + hibi_re_out : out std_logic; + hibi_we_out : out std_logic; + mem_addr_out : out std_logic_vector(24 downto 0); + mem_be_out : out std_logic_vector(31 downto 0); + mem_burst_begin_out : out std_logic; + mem_burst_size_out : out std_logic_vector(2 downto 0); + mem_init_done_in : in std_logic; + mem_rd_req_out : out std_logic; + mem_rdata_in : in std_logic_vector(255 downto 0); + mem_rdata_valid_in : in std_logic; + mem_ready_in : in std_logic; + mem_wdata_out : out std_logic_vector(255 downto 0); + mem_wr_req_out : out std_logic; + rst_n : in std_logic); + end component; + + -- HIBI segment block including two r4_wrapper and one r3_wrapper interfaces. + component hibi_segment_small + port ( + agent_addr_in_17 : in std_logic_vector(31 downto 0); + agent_addr_out_17 : out std_logic_vector(31 downto 0); + agent_av_in_1 : in std_logic; + agent_av_in_2 : in std_logic; + agent_av_out_1 : out std_logic; + agent_av_out_2 : out std_logic; + agent_comm_in_1 : in std_logic_vector(2 downto 0); + agent_comm_in_17 : in std_logic_vector(2 downto 0); + agent_comm_in_2 : in std_logic_vector(2 downto 0); + agent_comm_out_1 : out std_logic_vector(2 downto 0); + agent_comm_out_17 : out std_logic_vector(2 downto 0); + agent_comm_out_2 : out std_logic_vector(2 downto 0); + agent_data_in_1 : in std_logic_vector(31 downto 0); + agent_data_in_17 : in std_logic_vector(31 downto 0); + agent_data_in_2 : in std_logic_vector(31 downto 0); + agent_data_out_1 : out std_logic_vector(31 downto 0); + agent_data_out_17 : out std_logic_vector(31 downto 0); + agent_data_out_2 : out std_logic_vector(31 downto 0); + agent_empty_out_1 : out std_logic; + agent_empty_out_17 : out std_logic; + agent_empty_out_2 : out std_logic; + agent_full_out_1 : out std_logic; + agent_full_out_17 : out std_logic; + agent_full_out_2 : out std_logic; + agent_msg_addr_in_17 : in std_logic_vector(31 downto 0); + agent_msg_comm_in_17 : in std_logic_vector(2 downto 0); + agent_msg_comm_out_17 : out std_logic_vector(2 downto 0); + agent_msg_data_in_17 : in std_logic_vector(31 downto 0); + agent_msg_data_out_17 : out std_logic_vector(31 downto 0); + agent_msg_empty_out_17 : out std_logic; + agent_msg_full_out_17 : out std_logic; + agent_msg_re_in_17 : in std_logic; + agent_msg_we_in_17 : in std_logic; + agent_one_d_out_1 : out std_logic; + agent_one_d_out_2 : out std_logic; + agent_one_p_out_1 : out std_logic; + agent_one_p_out_2 : out std_logic; + agent_re_in_1 : in std_logic; + agent_re_in_17 : in std_logic; + agent_re_in_2 : in std_logic; + agent_we_in_1 : in std_logic; + agent_we_in_17 : in std_logic; + agent_we_in_2 : in std_logic; + clk : in std_logic; + rst_n : in std_logic); + end component; + + -- Adapter to connect HIBI based FPGA subsystem to PCIe bus. + component pcie_to_hibi_4x + generic ( + HIBI_DATA_WIDTH : integer := 32); + port ( + clk_in : in std_logic; + hibi_av_in : in std_logic; + hibi_av_out : out std_logic; + hibi_comm_in : in std_logic_vector(4 downto 0); + hibi_comm_out : out std_logic_vector(4 downto 0); + hibi_data_in : in std_logic_vector(31 downto 0); + hibi_data_out : out std_logic_vector(31 downto 0); + hibi_empty_in : in std_logic; + hibi_full_in : in std_logic; + hibi_one_d_in : in std_logic; + hibi_one_p_in : in std_logic; + hibi_re_out : out std_logic; + hibi_we_out : out std_logic; + pcie_ref_clk : in std_logic; + pcie_rst_n : in std_logic; + pcie_rx : in std_logic_vector(3 downto 0); + pcie_tx : out std_logic_vector(3 downto 0); + rst_n : in std_logic); + end component; + + -- Simple picture manipulator IP to rotate 8-bit grayscale picture 90 degrees clockwise. + component picture_manip + port ( + clk : in std_logic; + hibi_av_in : in std_logic; + hibi_av_out : out std_logic; + hibi_comm_in : in std_logic_vector(4 downto 0); + hibi_comm_out : out std_logic_vector(4 downto 0); + hibi_data_in : in std_logic_vector(31 downto 0); + hibi_data_out : out std_logic_vector(31 downto 0); + hibi_empty_in : in std_logic; + hibi_full_in : in std_logic; + hibi_one_d_in : in std_logic; + hibi_one_p_in : in std_logic; + hibi_re_out : out std_logic; + hibi_we_out : out std_logic; + rst_n : in std_logic); + end component; + + + +begin + + + a2_ddr2_dimm_1GB_1 : a2_ddr2_dimm_1GB + port map ( + mem_dq => ddr2_dimm_dq, + mem_clk => ddr2_dimm_clk, + mem_clk_n => ddr2_dimm_clk_n, + local_wdata => a2_ddr2_dimm_1GB_1_local_wdata_hibi_mem_dma_1_mem_wdata_out, + mem_odt => ddr2_dimm_odt, + mem_dqs => ddr2_dimm_dqs, + mem_dqsn => ddr2_dimm_dqs_n, + local_read_req => a2_ddr2_dimm_1GB_1_local_read_req_hibi_mem_dma_1_mem_rd_req_out, + mem_cke => ddr2_dimm_cke, + pll_ref_clk => clkin_bot_p, + local_address => a2_ddr2_dimm_1GB_1_local_address_hibi_mem_dma_1_mem_addr_out, + local_be => a2_ddr2_dimm_1GB_1_local_be_hibi_mem_dma_1_mem_be_out, + mem_cs_n => ddr2_dimm_cs_n, + mem_dm => ddr2_dimm_dm, + mem_ras_n => ddr2_dimm_ras_n, + mem_we_n => ddr2_dimm_we_n, + local_ready => a2_ddr2_dimm_1GB_1_local_ready_hibi_mem_dma_1_mem_ready_in, + local_size => a2_ddr2_dimm_1GB_1_local_size_hibi_mem_dma_1_mem_burst_size_out, + global_reset_n => user_pb, + local_burstbegin => a2_ddr2_dimm_1GB_1_local_burstbegin_hibi_mem_dma_1_mem_burst_begin_out, + mem_addr => ddr2_dimm_addr, + local_write_req => a2_ddr2_dimm_1GB_1_local_write_req_hibi_mem_dma_1_mem_wr_req_out, + phy_clk => a2_ddr2_dimm_1GB_1_phy_clk_pcie_to_hibi_4x_1_clk_in, + mem_ba => ddr2_dimm_ba, + mem_cas_n => ddr2_dimm_cas_n, + local_rdata_valid => a2_ddr2_dimm_1GB_1_local_rdata_valid_hibi_mem_dma_1_mem_rdata_valid_in, + local_init_done => a2_ddr2_dimm_1GB_1_local_init_done_hibi_mem_dma_1_mem_init_done_in, + local_rdata => a2_ddr2_dimm_1GB_1_local_rdata_hibi_mem_dma_1_mem_rdata_in); + + hibi_mem_dma_1 : hibi_mem_dma + port map ( + hibi_msg_comm_in => hibi_segment_small_1_agent_msg_comm_out_17_hibi_mem_dma_1_hibi_msg_comm_in, + hibi_msg_comm_out => hibi_segment_small_1_agent_msg_comm_in_17_hibi_mem_dma_1_hibi_msg_comm_out, + mem_rdata_in => a2_ddr2_dimm_1GB_1_local_rdata_hibi_mem_dma_1_mem_rdata_in, + clk => a2_ddr2_dimm_1GB_1_phy_clk_pcie_to_hibi_4x_1_clk_in, + hibi_we_out => hibi_segment_small_1_agent_we_in_17_hibi_mem_dma_1_hibi_we_out, + mem_burst_size_out => a2_ddr2_dimm_1GB_1_local_size_hibi_mem_dma_1_mem_burst_size_out, + mem_wdata_out => a2_ddr2_dimm_1GB_1_local_wdata_hibi_mem_dma_1_mem_wdata_out, + hibi_msg_data_in => hibi_segment_small_1_agent_msg_data_out_17_hibi_mem_dma_1_hibi_msg_data_in, + hibi_data_out => hibi_segment_small_1_agent_data_in_17_hibi_mem_dma_1_hibi_data_out, + hibi_empty_in => hibi_segment_small_1_agent_empty_out_17_hibi_mem_dma_1_hibi_empty_in, + hibi_data_in => hibi_segment_small_1_agent_data_out_17_hibi_mem_dma_1_hibi_data_in, + hibi_addr_in(31 downto 0) => hibi_segment_small_1_agent_addr_out_17_hibi_mem_dma_1_hibi_addr_in(31 downto 0), + mem_wr_req_out => a2_ddr2_dimm_1GB_1_local_write_req_hibi_mem_dma_1_mem_wr_req_out, + hibi_msg_re_out => hibi_segment_small_1_agent_msg_re_in_17_hibi_mem_dma_1_hibi_msg_re_out, + mem_rdata_valid_in => a2_ddr2_dimm_1GB_1_local_rdata_valid_hibi_mem_dma_1_mem_rdata_valid_in, + mem_ready_in => a2_ddr2_dimm_1GB_1_local_ready_hibi_mem_dma_1_mem_ready_in, + mem_addr_out => a2_ddr2_dimm_1GB_1_local_address_hibi_mem_dma_1_mem_addr_out, + mem_be_out => a2_ddr2_dimm_1GB_1_local_be_hibi_mem_dma_1_mem_be_out, + hibi_msg_full_in => hibi_segment_small_1_agent_msg_full_out_17_hibi_mem_dma_1_hibi_msg_full_in, + mem_init_done_in => a2_ddr2_dimm_1GB_1_local_init_done_hibi_mem_dma_1_mem_init_done_in, + mem_rd_req_out => a2_ddr2_dimm_1GB_1_local_read_req_hibi_mem_dma_1_mem_rd_req_out, + hibi_msg_data_out => hibi_segment_small_1_agent_msg_data_in_17_hibi_mem_dma_1_hibi_msg_data_out, + hibi_msg_empty_in => hibi_segment_small_1_agent_msg_empty_out_17_hibi_mem_dma_1_hibi_msg_empty_in, + hibi_msg_we_out => hibi_segment_small_1_agent_msg_we_in_17_hibi_mem_dma_1_hibi_msg_we_out, + hibi_re_out => hibi_segment_small_1_agent_re_in_17_hibi_mem_dma_1_hibi_re_out, + hibi_comm_out => hibi_segment_small_1_agent_comm_in_17_hibi_mem_dma_1_hibi_comm_out, + rst_n => user_pb, + hibi_full_in => hibi_segment_small_1_agent_full_out_17_hibi_mem_dma_1_hibi_full_in, + hibi_addr_out => hibi_segment_small_1_agent_addr_in_17_hibi_mem_dma_1_hibi_addr_out, + hibi_comm_in => hibi_segment_small_1_agent_comm_out_17_hibi_mem_dma_1_hibi_comm_in, + hibi_msg_addr_out => hibi_segment_small_1_agent_msg_addr_in_17_hibi_mem_dma_1_hibi_msg_addr_out, + mem_burst_begin_out => a2_ddr2_dimm_1GB_1_local_burstbegin_hibi_mem_dma_1_mem_burst_begin_out); + + hibi_segment_small_1 : hibi_segment_small + port map ( + agent_msg_re_in_17 => hibi_segment_small_1_agent_msg_re_in_17_hibi_mem_dma_1_hibi_msg_re_out, + agent_msg_we_in_17 => hibi_segment_small_1_agent_msg_we_in_17_hibi_mem_dma_1_hibi_msg_we_out, + agent_full_out_1 => hibi_segment_small_1_agent_full_out_1_pcie_to_hibi_4x_1_hibi_full_in, + agent_full_out_17 => hibi_segment_small_1_agent_full_out_17_hibi_mem_dma_1_hibi_full_in, + agent_comm_out_2 => hibi_segment_small_1_agent_comm_out_2_picture_manip_1_hibi_comm_in, + agent_data_in_1 => hibi_segment_small_1_agent_data_in_1_pcie_to_hibi_4x_1_hibi_data_out, + agent_one_d_out_1 => hibi_segment_small_1_agent_one_d_out_1_pcie_to_hibi_4x_1_hibi_one_d_in, + agent_av_in_2 => hibi_segment_small_1_agent_av_in_2_picture_manip_1_hibi_av_out, + agent_we_in_1 => hibi_segment_small_1_agent_we_in_1_pcie_to_hibi_4x_1_hibi_we_out, + agent_we_in_17 => hibi_segment_small_1_agent_we_in_17_hibi_mem_dma_1_hibi_we_out, + clk => a2_ddr2_dimm_1GB_1_phy_clk_pcie_to_hibi_4x_1_clk_in, + agent_comm_out_1 => hibi_segment_small_1_agent_comm_out_1_pcie_to_hibi_4x_1_hibi_comm_in, + agent_comm_in_17 => hibi_segment_small_1_agent_comm_in_17_hibi_mem_dma_1_hibi_comm_out, + agent_comm_in_2 => hibi_segment_small_1_agent_comm_in_2_picture_manip_1_hibi_comm_out, + agent_empty_out_2 => hibi_segment_small_1_agent_empty_out_2_picture_manip_1_hibi_empty_in, + agent_msg_empty_out_17 => hibi_segment_small_1_agent_msg_empty_out_17_hibi_mem_dma_1_hibi_msg_empty_in, + agent_data_in_17 => hibi_segment_small_1_agent_data_in_17_hibi_mem_dma_1_hibi_data_out, + agent_data_in_2 => hibi_segment_small_1_agent_data_in_2_picture_manip_1_hibi_data_out, + agent_one_d_out_2 => hibi_segment_small_1_agent_one_d_out_2_picture_manip_1_hibi_one_d_in, + agent_one_p_out_1 => hibi_segment_small_1_agent_one_p_out_1_pcie_to_hibi_4x_1_hibi_one_p_in, + agent_re_in_2 => hibi_segment_small_1_agent_re_in_2_picture_manip_1_hibi_re_out, + agent_full_out_2 => hibi_segment_small_1_agent_full_out_2_picture_manip_1_hibi_full_in, + agent_data_out_2 => hibi_segment_small_1_agent_data_out_2_picture_manip_1_hibi_data_in, + agent_empty_out_1 => hibi_segment_small_1_agent_empty_out_1_pcie_to_hibi_4x_1_hibi_empty_in, + agent_av_out_1 => hibi_segment_small_1_agent_av_out_1_pcie_to_hibi_4x_1_hibi_av_in, + agent_av_out_2 => hibi_segment_small_1_agent_av_out_2_picture_manip_1_hibi_av_in, + agent_one_p_out_2 => hibi_segment_small_1_agent_one_p_out_2_picture_manip_1_hibi_one_p_in, + agent_msg_data_in_17 => hibi_segment_small_1_agent_msg_data_in_17_hibi_mem_dma_1_hibi_msg_data_out, + agent_msg_data_out_17 => hibi_segment_small_1_agent_msg_data_out_17_hibi_mem_dma_1_hibi_msg_data_in, + agent_msg_full_out_17 => hibi_segment_small_1_agent_msg_full_out_17_hibi_mem_dma_1_hibi_msg_full_in, + agent_data_out_1 => hibi_segment_small_1_agent_data_out_1_pcie_to_hibi_4x_1_hibi_data_in, + rst_n => user_pb, + agent_re_in_1 => hibi_segment_small_1_agent_re_in_1_pcie_to_hibi_4x_1_hibi_re_out, + agent_re_in_17 => hibi_segment_small_1_agent_re_in_17_hibi_mem_dma_1_hibi_re_out, + agent_comm_out_17 => hibi_segment_small_1_agent_comm_out_17_hibi_mem_dma_1_hibi_comm_in, + agent_data_out_17 => hibi_segment_small_1_agent_data_out_17_hibi_mem_dma_1_hibi_data_in, + agent_msg_addr_in_17 => hibi_segment_small_1_agent_msg_addr_in_17_hibi_mem_dma_1_hibi_msg_addr_out, + agent_msg_comm_in_17 => hibi_segment_small_1_agent_msg_comm_in_17_hibi_mem_dma_1_hibi_msg_comm_out, + agent_msg_comm_out_17 => hibi_segment_small_1_agent_msg_comm_out_17_hibi_mem_dma_1_hibi_msg_comm_in, + agent_addr_in_17 => hibi_segment_small_1_agent_addr_in_17_hibi_mem_dma_1_hibi_addr_out, + agent_we_in_2 => hibi_segment_small_1_agent_we_in_2_picture_manip_1_hibi_we_out, + agent_empty_out_17 => hibi_segment_small_1_agent_empty_out_17_hibi_mem_dma_1_hibi_empty_in, + agent_addr_out_17 => hibi_segment_small_1_agent_addr_out_17_hibi_mem_dma_1_hibi_addr_in, + agent_av_in_1 => hibi_segment_small_1_agent_av_in_1_pcie_to_hibi_4x_1_hibi_av_out, + agent_comm_in_1 => hibi_segment_small_1_agent_comm_in_1_pcie_to_hibi_4x_1_hibi_comm_out); + + pcie_to_hibi_4x_1 : pcie_to_hibi_4x + port map ( + hibi_data_in => hibi_segment_small_1_agent_data_out_1_pcie_to_hibi_4x_1_hibi_data_in, + hibi_we_out => hibi_segment_small_1_agent_we_in_1_pcie_to_hibi_4x_1_hibi_we_out, + hibi_data_out => hibi_segment_small_1_agent_data_in_1_pcie_to_hibi_4x_1_hibi_data_out, + hibi_empty_in => hibi_segment_small_1_agent_empty_out_1_pcie_to_hibi_4x_1_hibi_empty_in, + hibi_av_in => hibi_segment_small_1_agent_av_out_1_pcie_to_hibi_4x_1_hibi_av_in, + hibi_full_in => hibi_segment_small_1_agent_full_out_1_pcie_to_hibi_4x_1_hibi_full_in, + rst_n => user_pb, + clk_in => a2_ddr2_dimm_1GB_1_phy_clk_pcie_to_hibi_4x_1_clk_in, + pcie_rst_n => user_pb, + pcie_rx(3 downto 0) => pcie_rx_p(3 downto 0), + hibi_av_out => hibi_segment_small_1_agent_av_in_1_pcie_to_hibi_4x_1_hibi_av_out, + pcie_ref_clk => pcie_refclk_p, + pcie_tx(3 downto 0) => pcie_tx_p(3 downto 0), + hibi_comm_in => hibi_segment_small_1_agent_comm_out_1_pcie_to_hibi_4x_1_hibi_comm_in, + hibi_comm_out => hibi_segment_small_1_agent_comm_in_1_pcie_to_hibi_4x_1_hibi_comm_out, + hibi_one_d_in => hibi_segment_small_1_agent_one_d_out_1_pcie_to_hibi_4x_1_hibi_one_d_in, + hibi_one_p_in => hibi_segment_small_1_agent_one_p_out_1_pcie_to_hibi_4x_1_hibi_one_p_in, + hibi_re_out => hibi_segment_small_1_agent_re_in_1_pcie_to_hibi_4x_1_hibi_re_out); + + picture_manip_1 : picture_manip + port map ( + hibi_av_in => hibi_segment_small_1_agent_av_out_2_picture_manip_1_hibi_av_in, + hibi_empty_in => hibi_segment_small_1_agent_empty_out_2_picture_manip_1_hibi_empty_in, + clk => a2_ddr2_dimm_1GB_1_phy_clk_pcie_to_hibi_4x_1_clk_in, + rst_n => user_pb, + hibi_one_p_in => hibi_segment_small_1_agent_one_p_out_2_picture_manip_1_hibi_one_p_in, + hibi_full_in => hibi_segment_small_1_agent_full_out_2_picture_manip_1_hibi_full_in, + hibi_one_d_in => hibi_segment_small_1_agent_one_d_out_2_picture_manip_1_hibi_one_d_in, + hibi_re_out => hibi_segment_small_1_agent_re_in_2_picture_manip_1_hibi_re_out, + hibi_we_out => hibi_segment_small_1_agent_we_in_2_picture_manip_1_hibi_we_out, + hibi_data_in => hibi_segment_small_1_agent_data_out_2_picture_manip_1_hibi_data_in, + hibi_data_out => hibi_segment_small_1_agent_data_in_2_picture_manip_1_hibi_data_out, + hibi_comm_out => hibi_segment_small_1_agent_comm_in_2_picture_manip_1_hibi_comm_out, + hibi_av_out => hibi_segment_small_1_agent_av_in_2_picture_manip_1_hibi_av_out, + hibi_comm_in => hibi_segment_small_1_agent_comm_out_2_picture_manip_1_hibi_comm_in); + +end structural; + Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png =================================================================== --- TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png (nonexistent) +++ TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png (revision 24)

TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png =================================================================== --- TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png (nonexistent) +++ TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png (revision 24)

TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/arria_ii_gx_demo_soc_report.html =================================================================== --- TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/arria_ii_gx_demo_soc_report.html (nonexistent) +++ TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/arria_ii_gx_demo_soc_report.html (revision 24) @@ -0,0 +1,3698 @@ + + + + + + + +

This document was generated by Kactus2 on 07.11.2011 14:06:01 by user matilail

+

+ Table of contents
+ 1. Component TUT - soc - arria_ii_gx_demo_soc - 1.0
+    1.1. Kactus2 attributes
+    1.2. Ports
+    1.3. Bus interfaces
+    1.4. Views
+ 2. Component TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0
+    2.1. Model parameters
+    2.2. Kactus2 attributes
+    2.3. Ports
+    2.4. Bus interfaces
+    2.5. File sets
+    2.6. Views
+ 3. Component TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0
+    3.1. Kactus2 attributes
+    3.2. Ports
+    3.3. Bus interfaces
+    3.4. File sets
+    3.5. Views
+ 4. Component TUT - ip.hwp.storage - hibi_mem_dma - 2.0
+    4.1. Kactus2 attributes
+    4.2. Ports
+    4.3. Bus interfaces
+    4.4. File sets
+    4.5. Views
+ 5. Component TUT - ip.hwp.accelerator - picture_manip - 1.0
+    5.1. Kactus2 attributes
+    5.2. Ports
+    5.3. Bus interfaces
+    5.4. File sets
+    5.5. Views
+ 6. Component TUT - ip.hwp.communication - hibi_segment_small - 2.0
+    6.1. Kactus2 attributes
+    6.2. Ports
+    6.3. Bus interfaces
+    6.4. File sets
+    6.5. Views
+

+

1. Component TUT - soc - arria_ii_gx_demo_soc - 1.0

+

+
+ IP-Xact file: arria_ii_gx_demo_soc.1.0.xml
+

+

1.1 Kactus2 attributes

+

+    Product hierarchy: SoC
+    Component implementation: HW
+    Component firmness: Mutable
+

+

1.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clkin_bot_p	in	1	0	0
ddr2_dimm_addr	out	16	15	0
ddr2_dimm_ba	out	3	2	0
ddr2_dimm_cas_n	out	1	0	0
ddr2_dimm_cke	out	1	0	0
ddr2_dimm_clk	inout	2	1	0
ddr2_dimm_clk_n	inout	2	1	0
ddr2_dimm_cs_n	out	1	0	0
ddr2_dimm_dm	out	8	7	0
ddr2_dimm_dq	inout	64	63	0
ddr2_dimm_dqs	inout	8	7	0
ddr2_dimm_dqs_n	inout	8	7	0
ddr2_dimm_odt	out	1	0	0
ddr2_dimm_ras_n	out	1	0	0
ddr2_dimm_we_n	out	1	0	0
pcie_refclk_p	in	1	0	0
pcie_rx_p	in	4	3	0
pcie_tx_p	out	4	3	0
rst_n_RESETn	in	1	0	0
user_pb	in	3	2	0

+

1.3 Bus interfaces

+

1.3.1 clk_in

+

+    Description: Clock input for demo design
+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clkin_bot_p
+

+

1.3.2 ddr2_p

+

+    Description: DDR2 interface to DDR2 memory
+    Interface mode: master
+    Ports used in this interface: +

+

+
• ddr2_dimm_addr
+
• ddr2_dimm_ba
+
• ddr2_dimm_cas_n
+
• ddr2_dimm_cke
+
• ddr2_dimm_clk_n
+
• ddr2_dimm_clk
+
• ddr2_dimm_cs_n
+
• ddr2_dimm_dqs_n
+
• ddr2_dimm_dqs
+
• ddr2_dimm_dm
+
• ddr2_dimm_dq
+
• ddr2_dimm_odt
+
• ddr2_dimm_ras_n
+
• ddr2_dimm_we_n
+

+

1.3.3 pcie_4x_p

+

+    Description: PCIe 4x interface
+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• pcie_tx_p
+
• pcie_rx_p
+
• pcie_refclk_p
+
• user_pb
+

+

1.3.4 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• user_pb
+

+

1.4 Views

+

1.4.1 View: structural

+

+
+    Type: hierarchical
+

+

1.4.1.1 Configuration TUT - soc - arria_ii_gx_demo_soc.designcfg - 1.0

+

+    IP-Xact file: arria_ii_gx_demo_soc.designcfg.1.0.xml
+
+

+

1.4.1.2 Design TUT - soc - arria_ii_gx_demo_soc.design - 1.0

+

+    IP-Xact file: arria_ii_gx_demo_soc.design.1.0.xml
+
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Instance name	Component type	Configurable values	Active view	Description
pcie_to_hibi_4x_1	TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0	+	rtl
a2_ddr2_dimm_1GB_1	TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0	+	rtl
hibi_mem_dma_1	TUT - ip.hwp.storage - hibi_mem_dma - 2.0	+	rtl
picture_manip_1	TUT - ip.hwp.accelerator - picture_manip - 1.0	+	rtl
hibi_segment_small_1	TUT - ip.hwp.communication - hibi_segment_small - 2.0	+	rtl

+

1.4.2 View: rtl

+

+    Type: non-hierarchical
+

2. Component TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0

+

+
+ Description: Adapter to connect HIBI based FPGA subsystem to PCIe bus.
+ IP-Xact file: pcie_to_hibi_4x.1.0.xml
+

+

2.1 Model parameters

+ + + + + + + + + + +

Name	Data type	Default value
HIBI_DATA_WIDTH	integer	32

+

2.2 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Parameterizable
+

+

2.3 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clk_in	in	1	0	0
hibi_av_in	in	1	0	0
hibi_av_out	out	1	0	0
hibi_comm_in	in	5	4	0
hibi_comm_out	out	5	4	0
hibi_data_in	in	32	31	0
hibi_data_out	out	32	31	0
hibi_empty_in	in	1	0	0
hibi_full_in	in	1	0	0
hibi_one_d_in	in	1	0	0
hibi_one_p_in	in	1	0	0
hibi_re_out	out	1	0	0
hibi_we_out	out	1	0	0
pcie_ref_clk	in	1	0	0
pcie_rst_n	in	1	0	0
pcie_rx	in	4	3	0
pcie_tx	out	4	3	0
rst_n	in	1	0	0

+

2.4 Bus interfaces

+

2.4.1 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk_in
+

+

2.4.2 hibi_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• hibi_av_out
+
• hibi_one_d_in
+
• hibi_data_in
+
• hibi_data_out
+
• hibi_av_in
+
• hibi_full_in
+
• hibi_comm_out
+
• hibi_we_out
+
• hibi_comm_in
+
• hibi_empty_in
+
• hibi_re_out
+
• hibi_one_p_in
+

+

2.4.3 pcie_4x_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• pcie_tx
+
• pcie_rx
+
• pcie_rst_n
+
• pcie_ref_clk
+

+

2.4.4 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

2.5 File sets

+

2.5.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
verilogSource	vlog	-quiet -work pcie_to_hibi_4x	false
vhdlSource	vcom	-quiet -check_synthesis -work pcie_to_hibi_4x	false

+

   2.5.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
pcie_to_hibi_4x.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_0.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_1.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_2.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_3.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_4.vhd	pcie_to_hibi_4x			vhdlSource
pcie_to_hibi_4x_sopc_burst_5.vhd	pcie_to_hibi_4x			vhdlSource
pcie.vhd	pcie_to_hibi_4x			vhdlSource
dma.vhd	pcie_to_hibi_4x			vhdlSource
pcie_core.vhd	pcie_to_hibi_4x			vhdlSource
pcie_serdes.vhd	pcie_to_hibi_4x			vhdlSource
a2h.v	pcie_to_hibi_4x			verilogSource
altpcie_64b_x4_pipen1b.v	pcie_to_hibi_4x			verilogSource
altpcie_hip_pipen1b.v	pcie_to_hibi_4x			verilogSource
altpcie_pclk_align.v	pcie_to_hibi_4x			verilogSource
altpcie_pclk_pll.v	pcie_to_hibi_4x			verilogSource
altpcie_phasefifo.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_100_125.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_100_250.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_125_250.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_15625_125.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_250_100.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy0.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy1_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy2.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy3_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy4_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_pll_phy5_62p5.v	pcie_to_hibi_4x			verilogSource
altpcie_serdes_2agx_x4d_gen1_08p.v	pcie_to_hibi_4x			verilogSource
altpcie_serdes_2agx_x4d_gen1_16p.v	pcie_to_hibi_4x			verilogSource
pciexp64_dlink.v	pcie_to_hibi_4x			verilogSource
pciexp64_trans.v	pcie_to_hibi_4x			verilogSource
pciexp_dcram.v	pcie_to_hibi_4x			verilogSource
pciexpx8f_confctrl.v	pcie_to_hibi_4x			verilogSource
avalon_to_hibi.v	pcie_to_hibi_4x			verilogSource

+

2.5.2 Documentation

+

+    Description: pcie_to_hibi IP documentations.
+    Identifiers:
+

+

   2.5.2.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
PCI-E_to_hibi.docx				documentation	pcie_to_hibi IP block documentation in word document.
PCI-E_to_hibi.pptx				documentation	pcie_to_hibi IP block documentation in powerpoint presentation.

+

2.5.3 fpga_settings

+

+    Identifiers:
+

+

   2.5.3.1 Files

+ + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
pcie.sdc				quartusSDCFile	pcie_to_hibi timing and area constraints.

+

2.5.4 sopc_files

+

+    Identifiers:
+

+

   2.5.4.1 Files

+ + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
pcie_to_hibi_4x_sopc.sopc				quartusSOPCFILE	SOPC project file

+

2.6 Views

+

2.6.1 View: rtl

+

+    Type: non-hierarchical
+    File sets contained in this view: +

+

+
• hdlSources
+

+

3. Component TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0

+

+
+ Description: Altera ddr2 memory controller
+ IP-Xact file: alt_ddr2_a2.comp.1.0.xml
+

+

3.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Mutable
+

+

3.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
aux_full_rate_clk	out	1	0	0
aux_half_rate_clk	out	1	0	0
dll_reference_clk	out	1	0	0
dqs_delay_ctrl_export	out	6	5	0
global_reset_n	in	1	0	0
local_address	in	25	24	0
local_be	in	32	31	0
local_burstbegin	in	1	0	0
local_init_done	out	1	0	0
local_rdata	out	256	255	0
local_rdata_valid	out	1	0	0
local_read_req	in	1	0	0
local_ready	out	1	0	0
local_refresh_ack	out	1	0	0
local_size	in	3	2	0
local_wdata	in	256	255	0
local_write_req	in	1	0	0
mem_addr	out	14	13	0
mem_ba	out	3	2	0
mem_cas_n	out	1	0	0
mem_cke	out	1	0	0
mem_clk	inout	2	1	0
mem_clk_n	inout	2	1	0
mem_cs_n	out	1	0	0
mem_dm	out	8	7	0
mem_dq	inout	64	63	0
mem_dqs	inout	8	7	0
mem_dqsn	inout	8	7	0
mem_odt	out	1	0	0
mem_ras_n	out	1	0	0
mem_we_n	out	1	0	0
phy_clk	out	1	0	0
pll_ref_clk	in	1	0	0
reset_phy_clk_n	out	1	0	0
reset_request_n	out	1	0	0
soft_reset_n	in	1	0	0

+

3.3 Bus interfaces

+

3.3.1 alt_ddr2_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• local_init_done
+
• local_write_req
+
• local_read_req
+
• local_address
+
• local_ready
+
• local_rdata_valid
+
• local_wdata
+
• local_rdata
+
• local_be
+
• local_burstbegin
+
• local_size
+

+

3.3.2 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• pll_ref_clk
+

+

3.3.3 ddr2_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• mem_clk
+
• mem_clk_n
+
• mem_cke
+
• mem_cs_n
+
• mem_cas_n
+
• mem_ras_n
+
• mem_odt
+
• mem_we_n
+
• mem_ba
+
• mem_addr
+
• mem_dm
+
• mem_dqs
+
• mem_dqsn
+
• mem_dq
+

+

3.3.4 phy_clk_out

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• phy_clk
+

+

3.3.5 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• global_reset_n
+

+

3.3.6 soft_rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• soft_reset_n
+

+

3.4 File sets

+

3.4.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
verilogSource	vlog	-quiet -work alt_ddr2_a2	false
vhdlSource	vcom	-quiet -check_synthesis -work alt_ddr2_a2	false

+

   3.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
a2_ddr2_dimm_1GB.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_alt_ddrx_controller_wrapper.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_controller_phy.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_dq_dqs.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_pll.v	alt_ddr2_a2			verilogSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_seq.vhd	alt_ddr2_a2			vhdlSource
a2_ddr2_dimm_1GB_phy_alt_mem_phy_seq_wrapper.v	alt_ddr2_a2		+incdir+D:/user/matilail/funbase/svn/release_2/lib/TUT/ip.hwp/stor.alt_ddr2_a2/1.0/hdl	verilogSource
alt_ddrx_addr_cmd.v	alt_ddr2_a2			verilogSource
alt_ddrx_afi_block.v	alt_ddr2_a2			verilogSource
alt_ddrx_avalon_if.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_timer.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_timer_info.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_timer_wrapper.v	alt_ddr2_a2			verilogSource
alt_ddrx_bank_tracking.v	alt_ddr2_a2			verilogSource
alt_ddrx_bypass.v	alt_ddr2_a2			verilogSource
alt_ddrx_cache.v	alt_ddr2_a2			verilogSource
alt_ddrx_clock_and_reset.v	alt_ddr2_a2			verilogSource
alt_ddrx_cmd_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_cmd_queue.v	alt_ddr2_a2			verilogSource
alt_ddrx_controller.v	alt_ddr2_a2			verilogSource
alt_ddrx_csr.v	alt_ddr2_a2			verilogSource
alt_ddrx_ddr2_odt_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_ddr3_odt_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_decoder.v	alt_ddr2_a2			verilogSource
alt_ddrx_decoder_40.v	alt_ddr2_a2			verilogSource
alt_ddrx_decoder_72.v	alt_ddr2_a2			verilogSource
alt_ddrx_ecc.v	alt_ddr2_a2			verilogSource
alt_ddrx_encoder.v	alt_ddr2_a2			verilogSource
alt_ddrx_encoder_40.v	alt_ddr2_a2			verilogSource
alt_ddrx_encoder_72.v	alt_ddr2_a2			verilogSource
alt_ddrx_input_if.v	alt_ddr2_a2			verilogSource
alt_ddrx_odt_gen.v	alt_ddr2_a2			verilogSource
alt_ddrx_rank_monitor.v	alt_ddr2_a2			verilogSource
alt_ddrx_state_machine.v	alt_ddr2_a2			verilogSource
alt_ddrx_timers.v	alt_ddr2_a2			verilogSource
alt_ddrx_timers_fsm.v	alt_ddr2_a2			verilogSource
alt_ddrx_timing_param.v	alt_ddr2_a2			verilogSource
alt_ddrx_wdata_fifo.v	alt_ddr2_a2			verilogSource
alt_mem_phy_defines.v	alt_ddr2_a2			verilogSource
altera_avalon_half_rate_bridge.v	alt_ddr2_a2			verilogSource

+

3.5 Views

+

3.5.1 View: rtl

+

+    Type: non-hierarchical
+

4. Component TUT - ip.hwp.storage - hibi_mem_dma - 2.0

+

+
+ Description: HIBI memory DMA access IP.
+ IP-Xact file: hibi_mem_dma.comp.xml
+

+

4.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Mutable
+

+

4.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clk	in	1	0	0
hibi_addr_in	in	32	31	0
hibi_addr_out	out	32	31	0
hibi_av_out	out	1	0	0
hibi_comm_in	in	3	2	0
hibi_comm_out	out	3	2	0
hibi_data_in	in	32	31	0
hibi_data_out	out	32	31	0
hibi_empty_in	in	1	0	0
hibi_full_in	in	1	0	0
hibi_msg_addr_out	out	32	31	0
hibi_msg_av_out	out	1	0	0
hibi_msg_comm_in	in	3	2	0
hibi_msg_comm_out	out	3	2	0
hibi_msg_data_in	in	32	31	0
hibi_msg_data_out	out	32	31	0
hibi_msg_empty_in	in	1	0	0
hibi_msg_full_in	in	1	0	0
hibi_msg_re_out	out	1	0	0
hibi_msg_we_out	out	1	0	0
hibi_re_out	out	1	0	0
hibi_we_out	out	1	0	0
mem_addr_out	out	25	24	0
mem_be_out	out	32	31	0
mem_burst_begin_out	out	1	0	0
mem_burst_size_out	out	3	2	0
mem_init_done_in	in	1	0	0
mem_rd_req_out	out	1	0	0
mem_rdata_in	in	256	255	0
mem_rdata_valid_in	in	1	0	0
mem_ready_in	in	1	0	0
mem_wdata_out	out	256	255	0
mem_wr_req_out	out	1	0	0
rst_n	in	1	0	0

+

4.3 Bus interfaces

+

4.3.1 alt_ddr2_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• mem_init_done_in
+
• mem_wr_req_out
+
• mem_rd_req_out
+
• mem_addr_out
+
• mem_ready_in
+
• mem_rdata_valid_in
+
• mem_wdata_out
+
• mem_rdata_in
+
• mem_be_out
+
• mem_burst_begin_out
+
• mem_burst_size_out
+

+

4.3.2 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk
+

+

4.3.3 hibi_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• hibi_addr_out
+
• hibi_data_in
+
• hibi_data_out
+
• hibi_full_in
+
• hibi_comm_out
+
• hibi_we_out
+
• hibi_comm_in
+
• hibi_empty_in
+
• hibi_re_out
+
• hibi_msg_addr_out
+
• hibi_msg_data_in
+
• hibi_msg_data_out
+
• hibi_msg_full_in
+
• hibi_msg_comm_out
+
• hibi_msg_we_out
+
• hibi_msg_comm_in
+
• hibi_msg_empty_in
+
• hibi_msg_re_out
+
• hibi_addr_in
+

+

4.3.4 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

4.4 File sets

+

4.4.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
vhdlSource	vcom	-quiet -check_synthesis -work hibi_mem_dma	false

+

   4.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
fifo_ram.vhd	hibi_mem_dma			vhdlSource
fifo_u.vhd	hibi_mem_dma			vhdlSource
dual_port_ram_u.vhd	hibi_mem_dma			vhdlSource
onchip_ram_u.vhd	hibi_mem_dma			vhdlSource
dual_ram_async_read.vhd	hibi_mem_dma			vhdlSource
hibi_mem_dma.vhd	hibi_mem_dma			vhdlSource

+

4.4.2 Documentation

+

+    Identifiers:
+

+

   4.4.2.1 Files

+ + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
HIBI_MEM_DMA.docx				documentation	hibi_mem_dma IP block datasheet.

+

4.5 Views

+

4.5.1 View: rtl

+

+    Type: non-hierarchical
+ Description: HIBI_MEM_DMA vhdl source view
+    File sets contained in this view: +

+

+
• hdlSources
+

+

5. Component TUT - ip.hwp.accelerator - picture_manip - 1.0

+

+
+ Description: Simple picture manipulator IP to rotate 8-bit grayscale picture 90 degrees clockwise.
+ IP-Xact file: picture_manip.1.0.xml
+

+

5.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Mutable
+

+

5.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
clk	in	1	0	0
hibi_av_in	in	1	0	0
hibi_av_out	out	1	0	0
hibi_comm_in	in	5	4	0
hibi_comm_out	out	5	4	0
hibi_data_in	in	32	31	0
hibi_data_out	out	32	31	0
hibi_empty_in	in	1	0	0
hibi_full_in	in	1	0	0
hibi_one_d_in	in	1	0	0
hibi_one_p_in	in	1	0	0
hibi_re_out	out	1	0	0
hibi_we_out	out	1	0	0
rst_n	in	1	0	0

+

5.3 Bus interfaces

+

5.3.1 clk

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk
+

+

5.3.2 hibi_p

+

+    Interface mode: master
+    Ports used in this interface: +

+

+
• hibi_av_out
+
• hibi_one_d_in
+
• hibi_data_in
+
• hibi_data_out
+
• hibi_av_in
+
• hibi_full_in
+
• hibi_comm_out
+
• hibi_we_out
+
• hibi_comm_in
+
• hibi_empty_in
+
• hibi_re_out
+
• hibi_one_p_in
+

+

5.3.3 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

5.4 File sets

+

5.4.1 hdlSources

+

+    Identifiers:
+

+

   5.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
manip_memory.vhd	picture_manip			vhdlSource
picture_manip_pkg.vhd	picture_manip			vhdlSource
picture_manip.vhd	pciture_manip			vhdlSource

+

5.5 Views

+

5.5.1 View: rtl

+

+    Type: non-hierarchical
+    File sets contained in this view: +

+

+
• hdlSources
+

+

6. Component TUT - ip.hwp.communication - hibi_segment_small - 2.0

+

+
+ Description: HIBI segment block including two r4_wrapper and one r3_wrapper interfaces.
+ IP-Xact file: hibi_segment_small.2.0.xml
+

+

6.1 Kactus2 attributes

+

+    Product hierarchy: IP
+    Component implementation: HW
+    Component firmness: Parameterizable
+

+

6.2 Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Name	Direction	Width	Left bound	Right bound	Default value
agent_addr_in_17	in	32	31	0
agent_addr_out_17	out	32	31	0
agent_av_in_1	in	1	0	0
agent_av_in_2	in	1	0	0
agent_av_in_3	in	1	0	0
agent_av_in_4	in	1	0	0
agent_av_in_5	in	1	0	0
agent_av_in_6	in	1	0	0
agent_av_in_7	in	1	0	0
agent_av_in_8	in	1	0	0
agent_av_out_1	out	1	0	0
agent_av_out_2	out	1	0	0
agent_av_out_3	out	1	0	0
agent_av_out_4	out	1	0	0
agent_av_out_5	out	1	0	0
agent_av_out_6	out	1	0	0
agent_av_out_7	out	1	0	0
agent_av_out_8	out	1	0	0
agent_comm_in_1	in	3	2	0
agent_comm_in_17	in	3	2	0
agent_comm_in_2	in	3	2	0
agent_comm_in_3	in	3	2	0
agent_comm_in_4	in	3	2	0
agent_comm_in_5	in	3	2	0
agent_comm_in_6	in	3	2	0
agent_comm_in_7	in	3	2	0
agent_comm_in_8	in	3	2	0
agent_comm_out_1	out	3	2	0
agent_comm_out_17	out	3	2	0
agent_comm_out_2	out	3	2	0
agent_comm_out_3	out	3	2	0
agent_comm_out_4	out	3	2	0
agent_comm_out_5	out	3	2	0
agent_comm_out_6	out	3	2	0
agent_comm_out_7	out	3	2	0
agent_comm_out_8	out	3	2	0
agent_data_in_1	in	32	31	0
agent_data_in_17	in	32	31	0
agent_data_in_2	in	32	31	0
agent_data_in_3	in	32	31	0
agent_data_in_4	in	32	31	0
agent_data_in_5	in	32	31	0
agent_data_in_6	in	32	31	0
agent_data_in_7	in	32	31	0
agent_data_in_8	in	32	31	0
agent_data_out_1	out	32	31	0
agent_data_out_17	out	32	31	0
agent_data_out_2	out	32	31	0
agent_data_out_3	out	32	31	0
agent_data_out_4	out	32	31	0
agent_data_out_5	out	32	31	0
agent_data_out_6	out	32	31	0
agent_data_out_7	out	32	31	0
agent_data_out_8	out	32	31	0
agent_empty_out_1	out	1	0	0
agent_empty_out_17	out	1	0	0
agent_empty_out_2	out	1	0	0
agent_empty_out_3	out	1	0	0
agent_empty_out_4	out	1	0	0
agent_empty_out_5	out	1	0	0
agent_empty_out_6	out	1	0	0
agent_empty_out_7	out	1	0	0
agent_empty_out_8	out	1	0	0
agent_full_out_1	out	1	0	0
agent_full_out_17	out	1	0	0
agent_full_out_2	out	1	0	0
agent_full_out_3	out	1	0	0
agent_full_out_4	out	1	0	0
agent_full_out_5	out	1	0	0
agent_full_out_6	out	1	0	0
agent_full_out_7	out	1	0	0
agent_full_out_8	out	1	0	0
agent_msg_addr_in_17	in	32	31	0
agent_msg_addr_out_17	out	32	31	0
agent_msg_comm_in_17	in	3	2	0
agent_msg_comm_out_17	out	3	2	0
agent_msg_data_in_17	in	32	31	0
agent_msg_data_out_17	out	32	31	0
agent_msg_empty_out_17	out	1	0	0
agent_msg_full_out_17	out	1	0	0
agent_msg_one_p_out_17	out	1	0	0
agent_msg_re_in_17	in	1	0	0
agent_msg_we_in_17	in	1	0	0
agent_one_d_out_1	out	1	0	0
agent_one_d_out_2	out	1	0	0
agent_one_d_out_3	out	1	0	0
agent_one_d_out_4	out	1	0	0
agent_one_d_out_5	out	1	0	0
agent_one_d_out_6	out	1	0	0
agent_one_d_out_7	out	1	0	0
agent_one_d_out_8	out	1	0	0
agent_one_p_out_1	out	1	0	0
agent_one_p_out_17	out	1	0	0
agent_one_p_out_2	out	1	0	0
agent_one_p_out_3	out	1	0	0
agent_one_p_out_4	out	1	0	0
agent_one_p_out_5	out	1	0	0
agent_one_p_out_6	out	1	0	0
agent_one_p_out_7	out	1	0	0
agent_one_p_out_8	out	1	0	0
agent_re_in_1	in	1	0	0
agent_re_in_17	in	1	0	0
agent_re_in_2	in	1	0	0
agent_re_in_3	in	1	0	0
agent_re_in_4	in	1	0	0
agent_re_in_5	in	1	0	0
agent_re_in_6	in	1	0	0
agent_re_in_7	in	1	0	0
agent_re_in_8	in	1	0	0
agent_we_in_1	in	1	0	0
agent_we_in_17	in	1	0	0
agent_we_in_2	in	1	0	0
agent_we_in_3	in	1	0	0
agent_we_in_4	in	1	0	0
agent_we_in_5	in	1	0	0
agent_we_in_6	in	1	0	0
agent_we_in_7	in	1	0	0
agent_we_in_8	in	1	0	0
clk	in	1	0	0
rst_n	in	1	0	0

+

6.3 Bus interfaces

+

6.3.1 clk_in

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• clk
+

+

6.3.2 ddr2_ctrl_p

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• agent_comm_in_17
+
• agent_data_in_17
+
• agent_addr_in_17
+
• agent_we_in_17
+
• agent_re_in_17
+
• agent_comm_out_17
+
• agent_data_out_17
+
• agent_addr_out_17
+
• agent_full_out_17
+
• agent_one_p_out_17
+
• agent_empty_out_17
+
• agent_msg_re_in_17
+
• agent_msg_we_in_17
+
• agent_msg_addr_in_17
+
• agent_msg_data_in_17
+
• agent_msg_comm_in_17
+
• agent_msg_full_out_17
+
• agent_msg_one_p_out_17
+
• agent_msg_addr_out_17
+
• agent_msg_data_out_17
+
• agent_msg_comm_out_17
+
• agent_msg_empty_out_17
+

+

6.3.3 hibi_p1

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• agent_comm_in_1
+
• agent_data_in_1
+
• agent_av_in_1
+
• agent_we_in_1
+
• agent_re_in_1
+
• agent_comm_out_1
+
• agent_data_out_1
+
• agent_av_out_1
+
• agent_full_out_1
+
• agent_one_p_out_1
+
• agent_empty_out_1
+
• agent_one_d_out_1
+

+

6.3.4 hibi_p2

+

+    Interface mode: mirroredMaster
+    Ports used in this interface: +

+

+
• agent_comm_in_2
+
• agent_data_in_2
+
• agent_av_in_2
+
• agent_we_in_2
+
• agent_re_in_2
+
• agent_comm_out_2
+
• agent_data_out_2
+
• agent_av_out_2
+
• agent_full_out_2
+
• agent_one_p_out_2
+
• agent_empty_out_2
+
• agent_one_d_out_2
+

+

6.3.5 rst_n

+

+    Interface mode: slave
+    Ports used in this interface: +

+

+
• rst_n
+

+

6.4 File sets

+

6.4.1 hdlSources

+

+    Identifiers:
+    Default file builders: +

+ + + + + + + + + + + + +

File type	Command	Flags	Replace default flags
vhdlSource	vcom	-quiet -check_synthesis -work hibi_mem_dma	false

+

   6.4.1.1 Files

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

File name	Logical name	Build command	Build flags	Specified file types	Description
hibiv2_pkg.vhd	hibi			vhdlSource
Hibi_segment.vhd	hibi			vhdlSource
addr_data_demuxes.vhd	hibi			vhdlSource
addr_data_muxes.vhd	hibi			vhdlSource
addr_decoder.vhd	hibi			vhdlSource
cfg_init_pkg.vhd	hibi			vhdlSource
cfg_mem.vhd	hibi			vhdlSource
copy_of_multiclk_fifo.vhd	hibi			vhdlSource
double_fifo_demux_wr.vhd	hibi			vhdlSource
double_fifo_mux_rd.vhd	hibi			vhdlSource
dyn_arb.vhd	hibi			vhdlSource
fifo.vhd	hibi			vhdlSource
fifo_muxes.vhd	hibi			vhdlSource
hibi_wrapper_r1.vhd	hibi			vhdlSource
hibi_wrapper_r3.vhd	hibi			vhdlSource
hibi_wrapper_r4.vhd	hibi			vhdlSource
lfsr.vhd	hibi			vhdlSource
receiver.vhd	hibi			vhdlSource
rx_ctrl.vhd	hibi			vhdlSource
transmitter.vhd	hibi			vhdlSource
tx_ctrl.vhd	hibi			vhdlSource

+

6.5 Views

+

6.5.1 View: rtl

+

+    Type: non-hierarchical
+    File sets contained in this view: +

+

+
• hdlSources
+

+

+ + + +

+ + + Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png =================================================================== --- TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png (nonexistent) +++ TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png (revision 24)