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- from Rev 45 to Rev 46
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Rev 45 → Rev 46
/TUT/ip.hwp.communication/hibi/doc/hibi_v3_datasheet_2011_09_27.pdf
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Index: TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_datasheet_2011_09_27.pdf
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Index: TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_datasheet_2011_09_27.pdf
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--- TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_datasheet_2011_09_27.pdf (revision 45)
+++ TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_datasheet_2011_09_27.pdf (nonexistent)
TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_datasheet_2011_09_27.pdf
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Index: TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_perf.pptx
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Index: TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_perf.docx
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Index: TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_perf.docx
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--- TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_perf.docx (nonexistent)
+++ TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_perf.docx (revision 46)
TUT/ip.hwp.communication/hibi/doc/Datasheet/hibi_v3_perf.docx
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Index: TUT/ip.hwp.communication/hibi/doc/Datasheet/Latex/hibi_datasheet.tex
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--- TUT/ip.hwp.communication/hibi/doc/Datasheet/Latex/hibi_datasheet.tex (revision 45)
+++ TUT/ip.hwp.communication/hibi/doc/Datasheet/Latex/hibi_datasheet.tex (revision 46)
@@ -215,7 +215,7 @@
\begin{figure} [b]
\begin{center}
- {\includegraphics[width=0.49\textwidth]{../Fig/Eps/fig_soc_concept.eps}}
+ {\includegraphics[width=0.60\textwidth]{../Fig/Eps/fig_soc_concept.eps}}
\caption{Conceptual structure of system-on-chip}
\label{fig:soc_concept}
\end{center}
@@ -269,7 +269,7 @@
\begin{figure*}
\begin{center}
- {\includegraphics[width=0.6\textwidth]{../Fig/Eps/fig_topo_hibi_hierarchy.eps}}
+ {\includegraphics[width=0.85\textwidth]{../Fig/Eps/fig_topo_hibi_hierarchy.eps}}
\caption{Example of a hierarchical HIBI network with multiple clock domains and bus segments}
\label{fig:hierarchy}
\end{center}
@@ -379,7 +379,7 @@
\begin{figure}
\begin{center}
- {\includegraphics[width=0.5\textwidth]{../Fig/Eps/fig_basic_tx.eps}}
+ {\includegraphics[width=0.7\textwidth]{../Fig/Eps/fig_basic_tx.eps}}
\caption{Example of read and write operations.}
\label{fig:basic_tx}
\end{center}
@@ -387,7 +387,7 @@
\begin{figure}
\begin{center}
- {\includegraphics[width=0.3\textwidth]{../Fig/Eps/fig_basic_tx2.eps}}
+ {\includegraphics[width=0.4\textwidth]{../Fig/Eps/fig_basic_tx2.eps}}
\caption{Basic transactions are write and read.}
\label{fig:basic_tx2}
\end{center}
@@ -823,7 +823,7 @@
r3. This is because SDRAM ctrl distinguishes DMA configuration and
memory data traffic with priority of incoming data. It also prevents
dead-lock. Fig ~\ref{fig:ip_interface_variants} depicts variants of
-wrapper's IP side signals. Interfave type r1 is the ``native''
+wrapper's IP side signals. Interface type r1 is the ``native''
interface that is used inside all other variants.
\begin{figure*}
@@ -1653,6 +1653,36 @@
\end{figure*}
+
+
+\section{Performance and resource usage}
+
+\subsection{HIBI wrapper structure}
+
+The main resource the HIBI uses is it's wrappers. HIBI version 3 has three of them which include R1, R3 and R4. Figure shows how a R3 wrapper is constructed of a R1 wrapper which in itself has four separate fifos.
+
+\begin{figure*}
+ \caption{HIBI R3 wrapper block diagram}
+ \label{figure:r3_block_diagram}
+ \begin{center}
+ \includegraphics[width=0.9\textwidth]{../Fig/Eps/test.eps}
+ \end{center}
+\end{figure*}
+
+\subsection{Resource usage}
+
+The resource usage for invidual HIBI wrappers was acquired from a SoC that was synthesized to a Arria II GX FPGA on a Arria II GX development board. The SoC had two HIBI components with both attached to a R3 HIBI wrapper. The size of the fifos on these wrappers was set to 4 words which amounts to 128 bits on each fifo. Figure shows the resource usage layout on the FPGA as seen on the Chip Planner in Quartus II. The two wrappers are highlighted in red.
+
+
+
+\subsection{Simulated performance}
+
+The throughput was measured for a HIBI segment with two components, both of which were connected to the segment with a R3 wrapper. The sender transmitted a continous stream of 1024 words to a single address. And as the HIBI segment had the data and address buses muxed together, the minimum time to send the stream would be 1025 cycles.
+
+
+
+
+
\section {Summary}
/TUT/ip.hwp.communication/hibi/doc/hibi_v3_perf.pdf
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