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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

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    /funbase_ip_library/trunk
    from Rev 65 to Rev 66
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Rev 65 → Rev 66

/TUT/ip.hwp.communication/n2h2/tb/tbrx_conf_hibisend.dat
1,8 → 1,22
# Comments start with hash (#)
# Each line denotes 1 transfer
# Line structure:
# dest_agent delay_cycles num_of_words
#
# Values are integers
 
0 10 12
2 30 20
0 20 12
0 30 12
 
# The rx test initiates only 3 incoming transfers
# After this point, the DMA gets unexpected data
# and tries to interupt CPU. Tb cannot handle interrupt,
# so simulation freezes
 
0 40 12
0 50 12
0 60 12
0 70 12
0 80 12
# end on file
/TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx_str.do
18,5 → 18,5
vcom ./blocks/sram_scalable_v3.vhd
vcom ./blocks/tb_n2h2_tx_str.vhd
 
vsim -t 1ns work.tb_n2h2_tx
vsim -novopt -t 1ns work.tb_n2h2_tx
do blocks/wave_tb_n2h2_tx_str.do
/TUT/ip.hwp.communication/n2h2/tb/tbrx_conf_rx.dat
1,3 → 1,11
1111 1115 12
1159 1116 12
1207 1117 12
# Comments start with hash (#)
# Each line defines one reception channel configuration for N2H DMA
# Line structure
# mem_addr noc_addr n_words
#
# Values are integers
 
1000 200 12 # channel 0, gives data to avalon_reader 0
1048 202 12 # channel 1 -> av_rdr 0 (again)
3333 301 20 # channel 2 -> av_rdr 1
# end on file
/TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_rx.do
1,10 → 1,15
# Configuration file formats:
# Tests N2H2 reception
#
# tbrx_conf_hibisend.dat : dest_agent_n, delay, amount
# tbrx_conf_rx.dat : mem_addr, sender, irq_amount (=words to receive)
# tbrx_data_file.dat : mem_addr, sender, irq_amount (=words to receive)
# Compiles all files, starts simulation and adds signals to wave window
#
# The traffic is configured with following ASCII file formats:
#
# tbrx_conf_hibisend.dat : dest_agent delay_cycles num_of_words
#
# tbrx_conf_rx.dat : mem_addr, noc_addr, irq_amount (=words to receive)
# tbrx_data_file.dat : mem_addr, noc_addr, irq_amount (=words to receive)
#
#
 
 
 
34,5 → 39,8
vcom ./blocks/sram_scalable_v3.vhd
vcom ./blocks/tb_n2h2_rx.vhd
 
vsim -t 1ns work.tb_n2h2_rx
 
# Start simulation
 
vsim -t 1ns -novopt work.tb_n2h2_rx
do ./blocks/wave_tb_n2h2_rx.do
/TUT/ip.hwp.communication/n2h2/tb/setup_tb_n2h2_tx.do
17,7 → 17,7
 
 
vcom ./blocks/sram_scalable_v3.vhd
vcom ./blocks/tb_n2h2_rx.vhd
vcom ./blocks/tb_n2h2_tx.vhd
 
vsim -t 1ns work.tb_n2h2_tx
do blocks/wave_tb_n2h2_tx.do
/TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_pkg.vhd
1,107 → 1,187
-------------------------------------------------------------------------------
-- Title : Package for block-level testing of Nios-to-HIBI
-- Project :
-------------------------------------------------------------------------------
-- File : tb_n2h2_pkg.vhd
-- Author : Ari Kulmala
-- Company :
-- Created : 2005-03-22
-- Last update: 2011-11-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2005-03-22 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.txt_util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
 
package tb_n2h2_pkg is
type addr_array is array (0 to 7) of integer;
 
procedure read_data_file (
data : out integer;
file file_txt : text);
-- Noc addresses (HIBI addresses). These identify the active reception channel of the N2H DMA block
constant addresses_c : addr_array := (200, 250, 300, 444, 555, 666, 777, 888);
 
-- Addresses on the avalon bus to the memory = memory addresses of reception buffer
-- arrays
constant ava_addresses_c : addr_array := (1000, 3333, 5555, 7000000, 9000000, 11000000, 13000000, 15000000);
 
 
 
-- constant addresses_c : addr_array := (16#1000000#, 16#3000000#, 16#5000000#, 16#7000000#, 16#9000000#, 16#b000000#, 16#d000000#, 16#f000000#);
-- constant ava_addresses_c : addr_array := (1000000, 3000000, 5000000, 7000000, 9000000, 11000000, 13000000, 15000000);
 
constant conf_bits_c : integer := 4; -- number of configuration bits in CPU
 
procedure read_conf_file (
mem_addr : out integer;
sender : out integer;
dst_addr : out integer;
irq_amount : out integer;
-- max_amount : out integer;
-- max_amount : out integer;
file file_txt : text);
 
function log2 (
constant x : integer)
return integer;
 
type addr_array is array (0 to 7) of integer;
-- constant addresses_c : addr_array := (16#1000000#, 16#3000000#, 16#5000000#, 16#7000000#, 16#9000000#, 16#b000000#, 16#d000000#, 16#f000000#);
constant addresses_c : addr_array := (1111, 3333, 5555, 16#7000000#, 16#9000000#, 16#b000000#, 16#d000000#, 16#f000000#);
-- constant ava_addresses_c : addr_array := (1000000, 3000000, 5000000, 7000000, 9000000, 11000000, 13000000, 15000000);
constant ava_addresses_c : addr_array := (1111,3333,5555, 7000000, 9000000, 11000000, 13000000, 15000000);
function log2 (
constant x : integer)
return integer;
 
constant conf_bits_c : integer := 4; -- number of configuration bits in CPU
 
-- -- This has become obsolete (2011-11-11)
-- procedure read_data_file (
-- data : out integer;
-- file file_txt : text);
 
 
end tb_n2h2_pkg;
 
package body tb_n2h2_pkg is
 
procedure read_data_file (
data : out integer;
file file_txt : text) is
variable file_row : line;
variable file_sample : integer;
begin -- read_data_file
readline(file_txt, file_row);
read(file_row, file_sample);
data := file_sample;
end read_data_file;
 
-- Reads ASCII file that stores info how to confgiure N2H DMA
procedure read_conf_file (
mem_addr : out integer;
sender : out integer;
dst_addr : out integer;
irq_amount : out integer;
-- max_amount : out integer;
file file_txt : text) is
variable file_row : line;
variable file_sample : integer;
variable file_sample_hex : std_logic_vector(31 downto 0);
variable good : boolean ;
begin -- read_data_file
readline(file_txt, file_row);
variable file_row : line;
--variable file_sample : integer;
-- variable file_sample_hex : std_logic_vector(31 downto 0);
variable sample_ok : boolean := FALSE;
begin
 
-- hread(file_row, file_sample_hex);
-- mem_addr := conv_integer(file_sample_hex);
-- hread(file_row, file_sample_hex);
-- sender := conv_integer(file_sample_hex);
read(file_row,file_sample,good);
 
mem_addr := file_sample;
read(file_row, file_sample);
sender := file_sample;
read(file_row, file_sample);
irq_amount := file_sample;
-- read(file_row, file_sample);
-- max_amount := file_sample;
-- Loop until finding a line that is not a comment
while sample_ok = false and not(endfile(file_txt)) loop
readline(file_txt, file_row);
read (file_row, mem_addr, sample_ok);
 
if sample_ok = FALSE then
--Reading of the delay value failed
--=> assume that this line is comment or empty, and skip other it
-- assert false report "Skipped a line" severity note;
next; -- start new loop interation
end if;
 
 
read(file_row, dst_addr); --file_sample);
--dst_addr := file_sample;
read(file_row, irq_amount); -- file_sample);
--irq_amount := file_sample;
end loop;
 
 
-- readline(file_txt, file_row);
-- -- hread(file_row, file_sample_hex);
-- -- mem_addr := conv_integer(file_sample_hex);
-- -- hread(file_row, file_sample_hex);
-- -- dst_addr := conv_integer(file_sample_hex);
-- read(file_row, file_sample, sample_ok);
-- if sample_ok = true then
 
-- mem_addr := file_sample;
-- read(file_row, file_sample);
-- dst_addr := file_sample;
-- read(file_row, file_sample);
-- irq_amount := file_sample;
-- end if;
end read_conf_file;
 
 
-- Logarithm with base=2
function log2 (
constant x : integer)
return integer is
 
function log2 (
constant x : integer)
return integer is
variable tmp_v : integer := 1;
--variable i_v : integer := 0;
begin -- log2
--report "log2(x):x is " & integer'image(x);
for i in 0 to 31 loop
if tmp_v >= x then
-- report "ceil(log2(x)) is " & integer'image(i);
return i;
end if;
tmp_v := tmp_v * 2;
end loop; -- i
 
variable tmp_v : integer := 1;
variable i_v : integer := 0;
begin -- log2
report "x is " & integer'image(x);
for i in 0 to 31 loop
if tmp_v >= x then
-- report "ceil(log2(x)) is " & integer'image(i);
-- We should not ever come here, let's return a definitely illegal value
assert false report "Error in function log2(x)" severity warning;
return -1;
end log2;
 
return i;
end if;
tmp_v := tmp_v * 2;
end loop; -- i
 
-- We should not ever come here, return definitely illegal value
return -1;
end log2;
-- procedure read_data_file (
-- data : out integer;
-- file file_txt : text) is
-- variable file_row : line;
-- variable file_sample : integer;
-- begin -- read_data_file
-- readline(file_txt, file_row);
-- read(file_row, file_sample);
-- data := file_sample;
-- end read_data_file;
 
 
end tb_n2h2_pkg;
/TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_fo.do
1,84 → 1,82
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {TB top}
add wave -noupdate -format Literal /tb_n2h2_tx/test_control
add wave -noupdate -format Literal /tb_n2h2_tx/test_case_control
add wave -noupdate -format Logic /tb_n2h2_tx/clk
add wave -noupdate -format Logic /tb_n2h2_tx/clk2
add wave -noupdate -format Logic /tb_n2h2_tx/rst_n
add wave -noupdate -format Logic /tb_n2h2_tx/tx_status_from_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/tx_irq_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/amount_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/amount_vec_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/dpram_vec_addr_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/dpram_addr_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/comm_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_vec_from_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_from_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_av_from_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_full_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_comm_from_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_from_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_addr_from_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_read_from_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_vec_readdata_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_readdata_to_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_n2h_tx
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_readdatavalid_to_n2h_tx
add wave -noupdate -format Literal /tb_n2h2_tx/counter
add wave -noupdate -format Literal /tb_n2h2_tx/new_hibi_addr
add wave -noupdate -format Literal /tb_n2h2_tx/new_amount
add wave -noupdate -format Literal /tb_n2h2_tx/new_dpram_addr
add wave -noupdate -format Literal /tb_n2h2_tx/global_hibi_address
add wave -noupdate -format Literal /tb_n2h2_tx/global_amount
add wave -noupdate -format Literal /tb_n2h2_tx/global_comm
add wave -noupdate -format Literal /tb_n2h2_tx/global_dpram_addr
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_data_counter
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_addr_counter
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_amount
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_addr_sent
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_last_addr
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_addr_came
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_data_counter
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_amount
add wave -noupdate -divider {DUT tx}
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/clk
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/rst_n
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/avalon_addr_out
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_re_out
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/avalon_readdata_in
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_waitrequest_in
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_readdatavalid_in
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/hibi_data_out
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_av_out
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_full_in
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/hibi_comm_out
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_we_out
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/tx_start_in
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/tx_status_done_out
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_comm_in
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_hibi_addr_in
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_ram_addr_in
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/tx_amount_in
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/control_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/addr_cnt_en_r
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/addr_cnt_value_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/addr_cnt_load_r
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/addr_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/amount_cnt_en_r
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/amount_cnt_value_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/amount_cnt_load_r
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/amount_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/addr_amount_eq
add wave -noupdate -format Literal /tb_n2h2_tx/n2h2_tx_1/addr_to_stop_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/avalon_re_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/start_re_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_write_addr_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/data_src_sel
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_we_r
add wave -noupdate -format Logic /tb_n2h2_tx/n2h2_tx_1/hibi_stop_we_r
add wave -noupdate /tb_n2h2_tx/test_ctrl_r
add wave -noupdate /tb_n2h2_tx/test_case_ctrl_r
add wave -noupdate -divider {TB configures DMA tx}
add wave -noupdate /tb_n2h2_tx/clk
add wave -noupdate /tb_n2h2_tx/rst_n
add wave -noupdate /tb_n2h2_tx/tx_status_duv_tb
add wave -noupdate /tb_n2h2_tx/tx_irq_tb_duv
add wave -noupdate /tb_n2h2_tx/amount_tb_duv
add wave -noupdate /tb_n2h2_tx/dpram_addr_tb_duv
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_addr_tb_duv
add wave -noupdate -radix unsigned /tb_n2h2_tx/comm_tb_duv
add wave -noupdate -divider {Mem <-> DMA tx}
add wave -noupdate /tb_n2h2_tx/clk
add wave -noupdate /tb_n2h2_tx/avalon_read_duv_tb
add wave -noupdate -radix unsigned /tb_n2h2_tx/avalon_addr_duv_tb
add wave -noupdate -radix unsigned /tb_n2h2_tx/avalon_vec_readdata_tb_duv
add wave -noupdate /tb_n2h2_tx/avalon_waitrequest_tb_duv
add wave -noupdate /tb_n2h2_tx/avalon_readdatavalid_tb_duv
add wave -noupdate /tb_n2h2_tx/clk2
add wave -noupdate -divider {DMA tx -> Hibi}
add wave -noupdate /tb_n2h2_tx/clk
add wave -noupdate /tb_n2h2_tx/hibi_av_duv_tb
add wave -noupdate /tb_n2h2_tx/hibi_data_duv_tb
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_comm_duv_tb
add wave -noupdate /tb_n2h2_tx/hibi_we_duv_tb
add wave -noupdate /tb_n2h2_tx/hibi_full_tb_duv
add wave -noupdate -divider {TB signals}
add wave -noupdate /tb_n2h2_tx/counter_r
add wave -noupdate /tb_n2h2_tx/new_hibi_addr_r
add wave -noupdate /tb_n2h2_tx/new_amount_r
add wave -noupdate /tb_n2h2_tx/new_dpram_addr_r
add wave -noupdate /tb_n2h2_tx/global_hibi_addr_r
add wave -noupdate /tb_n2h2_tx/global_amount_r
add wave -noupdate /tb_n2h2_tx/global_comm_r
add wave -noupdate /tb_n2h2_tx/global_dpram_addr
add wave -noupdate /tb_n2h2_tx/avalon_data_counter_r
add wave -noupdate /tb_n2h2_tx/avalon_addr_counter_r
add wave -noupdate /tb_n2h2_tx/avalon_amount
add wave -noupdate /tb_n2h2_tx/avalon_addr_sent
add wave -noupdate /tb_n2h2_tx/avalon_last_addr
add wave -noupdate /tb_n2h2_tx/hibi_addr_came
add wave -noupdate /tb_n2h2_tx/hibi_data_counter_r
add wave -noupdate /tb_n2h2_tx/hibi_amount
add wave -noupdate -divider DUT
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/clk
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/tx_hibi_addr_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/tx_ram_addr_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/tx_amount_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/tx_comm_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/avalon_addr_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/avalon_readdata_in
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/hibi_av_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/hibi_data_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/hibi_comm_out
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/hibi_we_out
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/tx_status_done_out
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/clk
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/control_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/addr_cnt_en_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/addr_cnt_value_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/addr_cnt_load_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/addr_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/amount_cnt_en_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/amount_cnt_value_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/amount_cnt_load_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/amount_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/addr_amount_eq
add wave -noupdate -radix unsigned /tb_n2h2_tx/n2h2_tx_1/addr_to_stop_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/avalon_re_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/start_re_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/hibi_write_addr_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/data_src_sel
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/hibi_we_r
add wave -noupdate /tb_n2h2_tx/n2h2_tx_1/hibi_stop_we_r
add wave -noupdate -divider {Dut ends}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {100549517 ns} 0}
WaveRestoreCursors {{Cursor 1} {1103 ns} 0}
configure wave -namecolwidth 211
configure wave -valuecolwidth 100
configure wave -justifyvalue left
93,4 → 91,4
configure wave -timeline 0
configure wave -timelineunits ms
update
WaveRestoreZoom {29948127 ns} {164575814 ns}
WaveRestoreZoom {0 ns} {2036 ns}
/TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_str.vhd
5,8 → 5,10
-- File : tb_n2h2_tx.vhd
-- Author : kulmala3
-- Created : 30.03.2005
-- Last update: 2011-03-08
-- Description:
-- Last update: 2011-11-15
-- Description: DMA reads data from memory and writes them to
-- HIBI. Values are just running numbers and checked automatically.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
14,6 → 16,32
-- Date Version Author Description
-- 30.03.2005 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
36,15 → 64,14
constant amount_width_g : integer := 16;
 
 
constant wait_between_sends_c : integer := 2; -- unit: cycles
constant wait_between_sends_c : integer := 2; -- unit: cycles
constant hibi_full_c : integer := 2;
constant avalon_waitr_c : integer := 7;
--constant avalon_waitr_up_cc_c : integer := 1;
constant amount_max_c : integer := 63; -- lingest transfer in words
constant amount_max_c : integer := 63; -- longest transfer in words
constant incr_hibi_full_after_c : time := 1000000 ns; -- how often HIBI
-- goes full
 
 
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
54,42 → 81,51
signal Rst_n : std_logic;
constant Period : time := 10 ns;
 
type main_control_type is (idle, send, wait_one);
signal main_ctrl_r : main_control_type;
type main_control_type is (idle, send, wait_one);
signal main_ctrl_r : main_control_type;
 
signal amount_r : std_logic_vector(amount_width_g-1 downto 0);
signal mem_addr_r : std_logic_vector(data_width_g-1 downto 0);
signal amount_r : std_logic_vector(amount_width_g-1 downto 0);
signal mem_addr_r : std_logic_vector(data_width_g-1 downto 0);
 
 
-----------------------------------------------------------------------------
-- Tested sub-unit of Nios-to-HIBI
-----------------------------------------------------------------------------
component n2h2_tx
generic (
data_width_g : integer;
amount_width_g : integer);
data_width_g : integer;
addr_width_g : integer := 32;
amount_width_g : integer
);
port (
clk : in std_logic;
rst_n : in std_logic;
avalon_addr_out : out std_logic_vector(data_width_g-1 downto 0);
clk : in std_logic;
rst_n : in std_logic;
 
-- Avalon master interface for reading memory
avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0);
avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
avalon_re_out : out std_logic;
avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
avalon_waitrequest_in : in std_logic;
avalon_readdatavalid_in : in std_logic;
avalon_waitrequest_in : in std_logic;
hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
hibi_av_out : out std_logic;
hibi_full_in : in std_logic;
hibi_comm_out : out std_logic_vector(4 downto 0);
hibi_we_out : out std_logic;
tx_start_in : in std_logic;
tx_status_done_out : out std_logic;
tx_comm_in : in std_logic_vector(4 downto 0);
tx_hibi_addr_in : in std_logic_vector(data_width_g-1 downto 0);
tx_ram_addr_in : in std_logic_vector(data_width_g-1 downto 0);
tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0));
 
-- Hibi interface for writing
hibi_av_out : out std_logic;
hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
hibi_comm_out : out std_logic_vector(4 downto 0);
hibi_full_in : in std_logic;
hibi_we_out : out std_logic;
 
-- DMA conf interface
tx_start_in : in std_logic;
tx_status_done_out : out std_logic;
tx_comm_in : in std_logic_vector(4 downto 0);
tx_hibi_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
tx_ram_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
tx_amount_in : in std_logic_vector(amount_width_g-1 downto 0)
);
end component;
 
 
signal avalon_ready_r : std_logic;
 
signal avalon_addr_from_tx : std_logic_vector(data_width_g-1 downto 0);
signal avalon_re_from_tx : std_logic;
signal avalon_readdata_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
97,43 → 133,46
signal avalon_waitrequest_to_tx : std_logic;
signal avalon_waitrequest_to_tx2 : std_logic;
signal avalon_readdatavalid_to_tx : std_logic;
 
signal hibi_data_from_tx : std_logic_vector(data_width_g-1 downto 0);
signal hibi_av_from_tx : std_logic;
signal hibi_full_to_tx : std_logic := '0';
signal hibi_comm_from_tx : std_logic_vector(4 downto 0);
signal hibi_we_from_tx : std_logic;
signal tx_start_to_tx : std_logic := '0';
signal tx_status_done_from_tx : std_logic;
 
signal tx_comm_to_tx : std_logic_vector(4 downto 0) := (others => '0');
 
-- Configuration signals
signal tx_comm_to_tx : std_logic_vector(4 downto 0) := (others => '0');
signal tx_hibi_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
signal tx_ram_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
signal tx_amount_to_tx : std_logic_vector(amount_width_g-1 downto 0) := (others => '0');
signal tx_start_to_tx : std_logic := '0';
signal tx_status_done_from_tx : std_logic;
 
 
-----------------------------------------------------------------------------
--
-- Memory and Avalon
-----------------------------------------------------------------------------
constant rom_data_file_name_g : string := "ram_init.dat";
constant output_file_name_g : string := "ram_contents.dat";
constant write_trigger_g : natural := 16#6543#;
constant write_trigger_g : natural := 16#6543#; -- RAM gets dumped to file
constant ram_addr_width_g : integer := 16;
 
component sram_scalable
generic (
rom_data_file_name_g : string;
output_file_name_g : string;
write_trigger_g : natural;
addr_width_g : integer;
data_width_g : integer);
rom_data_file_name_g : string;
output_file_name_g : string;
write_trigger_g : natural;
addr_width_g : integer;
data_width_g : integer
);
port (
cs1_n_in : in std_logic;
cs2_in : in std_logic;
addr_in : in std_logic_vector(addr_width_g-1 downto 0);
data_inout : inout std_logic_vector(data_width_g-1 downto 0);
we_n_in : in std_logic;
oe_n_in : in std_logic);
cs1_n_in : in std_logic;
cs2_in : in std_logic;
addr_in : in std_logic_vector(addr_width_g-1 downto 0);
data_inout : inout std_logic_vector(data_width_g-1 downto 0);
we_n_in : in std_logic;
oe_n_in : in std_logic
);
end component;
 
signal cs1_n_to_ram : std_logic;
144,11 → 183,12
signal oe_n_to_ram : std_logic;
 
signal delayed_data_from_ram_r : std_logic_vector(data_width_g-1 downto 0);
signal avalon_ready_r : std_logic;
 
 
 
-----------------------------------------------------------------------------
--
-- Signal for modeling HIBI
-----------------------------------------------------------------------------
signal hibi_addr_r : std_logic_vector(data_width_g-1 downto 0);
signal hibi_amount_r : std_logic_vector(amount_width_g-1 downto 0);
158,10 → 198,10
signal avalon_amount_r : std_logic_vector(amount_width_g-1 downto 0);
signal wait_cnt_r : integer range 0 to wait_between_sends_c;
signal avalon_waitr_cnt_r : integer range 0 to avalon_waitr_c-1;
signal hibi_we_was_up_r : std_logic;
signal hibi_we_was_up_r : std_logic;
-- signal hibi_full_cnt_r : integer range 0 to hibi_full_c;
signal hibi_full_cnt_r : integer;
signal hibi_ready_r : std_logic;
signal hibi_full_cnt_r : integer;
signal hibi_ready_r : std_logic;
 
signal hibi_full_up_cc : integer := 0;
 
169,42 → 209,19
begin -- rtl
 
cs1_n_to_ram <= '0'; -- avalon_waitrequest_to_tx;
cs2_to_ram <= avalon_re_from_tx;
addr_to_ram <= conv_std_logic_vector(conv_integer(avalon_addr_from_tx)/4, ram_addr_width_g);
 
avalon_waitrequest_to_tx2 <= avalon_waitrequest_to_tx or (not avalon_re_from_tx);
avalon_readdata_to_tx <= delayed_data_from_ram_r;
 
delay_valid : process (clk, rst_n)
begin -- process delay_valid
if rst_n = '0' then -- asynchronous reset (active low)
 
elsif clk'event and clk = '1' then -- rising clock edge
-- memory latency 2 (note below the same signal assignment)
avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
 
end if;
end process delay_valid;
-- memory latency 1
-- avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
 
we_n_to_ram <= '1';
oe_n_to_ram <= '0';
 
 
-----------------------------------------------------------------------------
-- component instantiation
-- DUT component instantiation
--
------------------------------------------------------------------------------
DUT : n2h2_tx
--DUT: entity work.n2h2_tx
generic map (
data_width_g => data_width_g,
amount_width_g => amount_width_g)
data_width_g => data_width_g,
amount_width_g => amount_width_g)
port map (
clk => clk,
rst_n => rst_n,
clk => clk,
rst_n => rst_n,
 
avalon_addr_out => avalon_addr_from_tx,
avalon_re_out => avalon_re_from_tx,
211,22 → 228,22
avalon_readdata_in => avalon_readdata_to_tx,
avalon_waitrequest_in => avalon_waitrequest_to_tx2,
avalon_readdatavalid_in => avalon_readdatavalid_to_tx,
hibi_data_out => hibi_data_from_tx,
hibi_av_out => hibi_av_from_tx,
hibi_full_in => hibi_full_to_tx,
hibi_comm_out => hibi_comm_from_tx,
hibi_we_out => hibi_we_from_tx,
 
tx_start_in => tx_start_to_tx,
tx_status_done_out => tx_status_done_from_tx,
tx_comm_in => tx_comm_to_tx,
tx_hibi_addr_in => tx_hibi_addr_to_tx,
tx_ram_addr_in => tx_ram_addr_to_tx,
tx_amount_in => tx_amount_to_tx);
hibi_data_out => hibi_data_from_tx,
hibi_av_out => hibi_av_from_tx,
hibi_full_in => hibi_full_to_tx,
hibi_comm_out => hibi_comm_from_tx,
hibi_we_out => hibi_we_from_tx,
 
tx_start_in => tx_start_to_tx,
tx_status_done_out => tx_status_done_from_tx,
tx_comm_in => tx_comm_to_tx,
tx_hibi_addr_in => tx_hibi_addr_to_tx,
tx_ram_addr_in => tx_ram_addr_to_tx,
tx_amount_in => tx_amount_to_tx);
 
 
 
-----------------------------------------------------------------------------
-- Give commands to the tested block n2h2_tx
-- Asks to send longer and longer transfer
236,9 → 253,9
if rst_n = '0' then -- asynchronous reset (active low)
tx_start_to_tx <= '0';
tx_hibi_addr_to_tx <= X"0000ffff";
tx_comm_to_tx <= (others => 'Z'); --'0');
tx_ram_addr_to_tx <= (others => 'Z'); -- '0');
tx_amount_to_tx <= (others => 'Z'); -- '0');
tx_comm_to_tx <= (others => 'Z'); --'0');
tx_ram_addr_to_tx <= (others => 'Z'); -- '0');
tx_amount_to_tx <= (others => 'Z'); -- '0');
wait_cnt_r <= 0;
main_ctrl_r <= idle;
amount_r <= conv_std_logic_vector(1, amount_width_g); --(others => '0');
249,19 → 266,19
 
 
case main_ctrl_r is
when idle =>
-- Wait that tx is ready then few cycles between asking transfers
-- Wait that previous tx is ready and then few cycles more.
-- Increase the source memory address for every transfer
tx_start_to_tx <= '0';
 
if tx_status_done_from_tx = '1' then
wait_cnt_r <= wait_cnt_r+1;
wait_cnt_r <= wait_cnt_r+1;
 
if wait_cnt_r = wait_between_sends_c-1 then
wait_cnt_r <= 0;
main_ctrl_r <= send;
wait_cnt_r <= 0;
main_ctrl_r <= send;
if conv_integer(amount_r) > 1 then
mem_addr_r <= mem_addr_r+conv_integer(tx_amount_to_tx)*4;
else
274,7 → 291,7
 
when send =>
-- Ask to send a new transfer
-- Increase the mem addr, hibi addr
tx_start_to_tx <= '1';
tx_ram_addr_to_tx <= mem_addr_r;
tx_hibi_addr_to_tx <= tx_hibi_addr_to_tx+1;
281,15 → 298,15
tx_amount_to_tx <= amount_r;
tx_comm_to_tx <= "00010";
 
-- Increase the transfer length for the next time
-- Increase transfer length for the next time
if conv_integer(amount_r) >= amount_max_c then
amount_r <= conv_std_logic_vector(1, amount_width_g);
amount_r <= conv_std_logic_vector(1, amount_width_g);
else
amount_r <= amount_r+1;
amount_r <= amount_r+1;
end if;
main_ctrl_r <= idle;
 
-- Loop back to idle state
main_ctrl_r <= idle;
 
 
when others =>
297,9 → 314,9
end if;
end process test;
 
-- avalon_readdata_to_tx <= avalon_data_r;
-- avalon_readdata_to_tx <= avalon_data_r;
 
 
-----------------------------------------------------------------------------
-- Instantiate memory block
------------------------------------------------------------------------------
311,12 → 328,12
addr_width_g => ram_addr_width_g,
data_width_g => data_width_g)
port map (
cs1_n_in => cs1_n_to_ram,
cs2_in => cs2_to_ram,
addr_in => addr_to_ram,
data_inout => data_inout_ram,
we_n_in => we_n_to_ram,
oe_n_in => oe_n_to_ram
cs1_n_in => cs1_n_to_ram,
cs2_in => cs2_to_ram,
addr_in => addr_to_ram,
data_inout => data_inout_ram,
we_n_in => we_n_to_ram,
oe_n_in => oe_n_to_ram
);
 
 
323,14 → 340,38
 
-----------------------------------------------------------------------------
-- Imitate Avalon switch fabric between mem and n2h2_tx:
-- - delay addr going to memory by one cycle
-- - delay data coming from memory by one cycle
-- - delay the addr going to memory by one cycle
-- - delay the data coming from memory by one cycle
------------------------------------------------------------------------------
cs1_n_to_ram <= '0'; -- avalon_waitrequest_to_tx;
cs2_to_ram <= avalon_re_from_tx;
addr_to_ram <= conv_std_logic_vector(conv_integer(avalon_addr_from_tx)/4, ram_addr_width_g);
 
avalon_waitrequest_to_tx2 <= avalon_waitrequest_to_tx or (not avalon_re_from_tx);
avalon_readdata_to_tx <= delayed_data_from_ram_r;
 
 
delay_valid : process (clk, rst_n)
begin -- process delay_valid
if rst_n = '0' then -- asynchronous reset (active low)
 
elsif clk'event and clk = '1' then -- rising clock edge
-- memory latency 2 (note below the same signal assignment)
avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
 
end if;
end process delay_valid;
-- memory latency 1
-- avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
 
we_n_to_ram <= '1';
oe_n_to_ram <= '0';
 
avalon : process (clk2, rst_n)
begin -- process avalon
if rst_n = '0' then -- asynchronous reset (active low)
avalon_waitrequest_to_tx <= '1';
delayed_data_from_ram_r <= (others => 'Z'); --data_inout_ram;
delayed_data_from_ram_r <= (others => 'Z'); --data_inout_ram;
avalon_waitr_cnt_r <= 0;
 
 
338,7 → 379,7
 
if tx_start_to_tx = '1' then
avalon_addr_r <= mem_addr_r;
avalon_addr_r <= mem_addr_r;
end if;
 
delayed_data_from_ram_r <= data_inout_ram;
356,11 → 397,10
avalon_waitrequest_to_tx <= '1';
end if;
end if;
--avalon_waitrequest_to_tx <= '0';
--avalon_waitrequest_to_tx <= '0';
end process avalon;
 
 
 
-----------------------------------------------------------------------------
-- Imitate the HIBI wrapper that gets the data from n2h2_tx
------------------------------------------------------------------------------
376,10 → 416,10
 
elsif clk'event and clk = '1' then -- rising clock edge
 
-- Generate full signal
if hibi_we_was_up_r = '1' then
hibi_full_cnt_r <= hibi_full_cnt_r+1;
hibi_full_to_tx <= '1';
hibi_full_cnt_r <= hibi_full_cnt_r+1;
hibi_full_to_tx <= '1';
if hibi_full_cnt_r = hibi_full_up_cc then
hibi_full_to_tx <= '0';
hibi_full_cnt_r <= 0;
387,24 → 427,27
end if;
end if;
 
-- Take and check the incoming data
if hibi_we_from_tx = '1' then
if hibi_full_up_cc > 0 then
hibi_full_to_tx <= '1';
hibi_full_to_tx <= '1';
end if;
hibi_we_was_up_r <= '1';
assert hibi_comm_from_tx /= "00000" report "hibi comm error" severity error;
 
assert hibi_comm_from_tx /= "00000" report "Error. DMA sets comm=idle" severity error;
 
 
 
if hibi_av_from_tx = '1' then
-- address
-- Check incoming address
-- +1 because of the main test program value
assert hibi_addr_r+1 = hibi_data_from_tx report "hibi addr error" severity error;
hibi_addr_r <= hibi_addr_r+1;
 
else
-- data
-- Check incoming data
assert avalon_readdata_to_tx = hibi_data_from_tx report "hibi data error" severity error;
 
assert avalon_readdata_to_tx = hibi_data_from_tx report "hibi data error" severity error;
if hibi_data_r = 2**ram_addr_width_g-1 then
hibi_data_r <= (others => '0');
else
414,12 → 457,14
hibi_amount_r <= hibi_amount_r+1;
assert hibi_amount_r <= tx_amount_to_tx report "too many data" severity error;
end if;
 
else
-- DMA does not write to HIBI
if main_ctrl_r = send then
hibi_amount_r <= (others => '0');
hibi_amount_r <= (others => '0');
end if;
end if;
 
end if;
end process hibi;
 
427,30 → 472,30
-----------------------------------------------------------------------------
--
------------------------------------------------------------------------------
full_control: process
full_control : process
begin -- process full_control
wait for incr_hibi_full_after_c;
hibi_full_up_cc <= hibi_full_up_cc+1;
hibi_full_up_cc <= hibi_full_up_cc+1;
end process full_control;
 
 
 
-----------------------------------------------------------------------------
--
-- Generate clokcs and reset
------------------------------------------------------------------------------
CLOCK1 : process -- generate clock signal for design
CLOCK1 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
wait for PERIOD/2;
clktmp := not clktmp;
Clk <= clktmp;
clktmp := not clktmp;
Clk <= clktmp;
end process CLOCK1;
 
CLOCK2 : process -- generate clock signal for design
CLOCK2 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
Clk2 <= clktmp;
clktmp := not clktmp;
Clk2 <= clktmp;
wait for PERIOD/2;
end process CLOCK2;
 
/TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_reader.vhd
5,15 → 5,44
-- File : avalon_reader.vhd
-- Author : kulmala3
-- Created : 22.03.2005
-- Last update: 25.06.2007
-- Description: testbench block to model the avalon bus
-- Last update: 2011-11-11
-- Description: Testbench block to model the avalon bus.
--
-- Checks that write operations are to
-- consecutive addresess and that data values are running numbers.
-- Addr mismatch is reported with output port to the tb, and data
-- mismatch with assert.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 22.03.2005 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
27,7 → 56,7
entity avalon_reader is
generic (
data_file_g : string := "";
-- data_file_g : string := "";
addr_width_g : integer := 0;
data_width_g : integer
);
40,7 → 69,7
avalon_writedata_in : in std_logic_vector(data_width_g-1 downto 0);
avalon_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
avalon_waitrequest_out : out std_logic;
increment_data_ptr : in std_logic; -- hops over one data
increment_data_ptr : in std_logic; -- hops over one data, obsolete?
waitrequest_real_in : in std_logic;
 
-- tb gets
47,7 → 76,8
not_my_addr_out : out std_logic;
--tb gives.
init_in : in std_logic;
my_own_addr_in : in std_logic_vector(data_width_g-1 downto 0)
my_own_addr_in : in std_logic_vector(addr_width_g-1 downto 0)
--my_own_addr_in : in std_logic_vector(data_width_g-1 downto 0)
);
 
end avalon_reader;
54,23 → 84,27
 
architecture rtl of avalon_reader is
 
constant addr_offset_c : integer := data_width_g/8;
constant assign_waitreq_c : integer := 10; -- between 10 datas...
constant release_waitreq_c : integer := 3;
signal addr_counter_r : std_logic_vector(addr_width_g-1 downto 0);
signal data_counter_r : integer;
signal waitreq_counter_r : integer;
signal release_counter_r : integer;
signal waitrequest_to_n2h_rx : std_logic;
constant addr_offset_c : integer := data_width_g/8; -- #bytes
constant assign_waitreq_c : integer := 3; -- request wait after 10 datas...
constant release_waitreq_c : integer := 3; -- cycles
 
constant data_fixed_width_c : integer := 32;
signal addr_counter_r : std_logic_vector(addr_width_g-1 downto 0);
signal data_counter_r : integer;
signal waitreq_counter_r : integer;
signal release_counter_r : integer;
signal waitrequest_to_n2h_rx : std_logic;
 
constant data_fixed_width_c : integer := 32; -- bits
constant n_words_output_c : integer := data_width_g/ data_fixed_width_c;
-- signal data_r : std_logic_vector(data_fixed_width_c-1 downto 0); -- 32 bit words always!
begin -- rtl
 
avalon_waitrequest_out <= waitrequest_to_n2h_rx;
 
--
-- Drives wait_request high every now and then.
-- This tests that N2H2 handles the stalling correctly
--
process (clk, rst_n)
begin -- process
if rst_n = '0' then
80,22 → 114,24
elsif clk'event and clk = '1' then -- rising clock edge
if avalon_we_in = '1' then
 
-- Request wait after every n-th write operation
if (waitreq_counter_r = assign_waitreq_c) then
waitreq_counter_r <= 0;
waitrequest_to_n2h_rx <= '1';
else
waitrequest_to_n2h_rx <= '0';
waitreq_counter_r <= waitreq_counter_r+1;
-- waitrequest_to_n2h_rx <= '0'; Keep old value instead! ES 2011-11-10
waitreq_counter_r <= waitreq_counter_r+1;
end if;
 
end if;
 
-- Release the wait after few cycles
if waitrequest_to_n2h_rx = '1' then
release_counter_r <= release_counter_r+1;
if release_counter_r >= release_waitreq_c then
release_counter_r <= 0;
waitrequest_to_n2h_rx <= '0';
-- assert false report "kukkuu" severity note; -- ES
end if;
end if;
102,9 → 138,12
end if;
end process;
 
--
-- Checks the values coming from N2H2 to "mem" (=here)
--
process (clk, rst_n)
file data_file : text open read_mode is data_file_g;
variable data_r : integer;
-- file data_file : text open read_mode is data_file_g;
variable data_v : integer;
variable data_to_check_v : integer;
variable not_my_addr_v : integer;
113,10 → 152,20
addr_counter_r <= (others => '0');
data_counter_r <= 0;
not_my_addr_out <= '0';
data_r := 0;
data_v := 0;
not_my_addr_v := 0;
elsif clk'event and clk = '1' then -- rising clock edge
 
-- Synchronous clearing may be requested by tb between transfers
if init_in = '1' then
addr_counter_r <= (others => '0');
end if;
 
 
 
if avalon_we_in = '1' and waitrequest_real_in = '0' then
 
-- Check if incoming addr matches
if (addr_counter_r + my_own_addr_in) /= avalon_addr_in then
not_my_addr_out <= '1';
not_my_addr_v := 1;
125,44 → 174,40
not_my_addr_v := 0;
addr_counter_r <= addr_counter_r + addr_offset_c;
end if;
 
 
-- Check data if addr was ok.
-- Data values must be running numbers
if not_my_addr_v = 0 then
for i in 0 to n_words_output_c-1 loop
if avalon_be_in((i+1)*4-1 downto i*4) = "1111" then
data_to_check_v := conv_integer(avalon_writedata_in(data_fixed_width_c*(i+1)-1 downto data_fixed_width_c*i));
if data_r /= data_to_check_v then
assert false report "data mismatch on avalon!" severity error;
assert false report "wait: " & str(data_r) & "got: " & str(data_to_check_v) severity error;
if data_v /= data_to_check_v then
assert false report "Data mismatch on avalon!" severity error;
assert false report " waited for: " & str(data_v) & ", but got: " & str(data_to_check_v) severity error;
else
assert false report "Data OK" severity note;
end if;
 
data_r := data_r+1;
data_v := data_v+1;
else
assert false report "Byte enables were not 1...1" severity warning;
end if;
end loop; -- i
end if;
 
elsif increment_data_ptr = '1' and waitrequest_real_in = '0' and not_my_addr_v = 0 then
-- weren't actually writing, but data wre thrown away due to irq amount
-- -> update file here also
-- read_data_file (
-- data => data_r,
-- file_txt => data_file
-- );
-- ??? AK 25.06.2007
-- data_r := data_r +1;
-- elsif increment_data_ptr = '1' and waitrequest_real_in = '0' and not_my_addr_v = 0 then
-- -- weren't actually writing, but data wre thrown away due to irq amount
-- -- -> update file here also
-- -- read_data_file (
-- -- data => data_v,
-- -- file_txt => data_file
-- -- );
-- -- ??? AK 25.06.2007
-- -- data_v := data_v +1;
end if;
 
 
 
if init_in = '1' then
addr_counter_r <= (others => '0');
end if;
 
end if;
end process;
 
end rtl;
/TUT/ip.hwp.communication/n2h2/tb/blocks/hibi_sender_n2h2.vhd
5,10 → 5,13
-- File : hibi_sender_n2h2.vhd
-- Author : kulmala3
-- Created : 13.01.2005
-- Last update: 2011-03-09
-- Last update: 2011-11-11
-- Description: This blocks creates traffic for the HIBI block.
-- This block is used within tb_eigth_hibi_r4.vhd.
-- Reads a configraution file, where each line has 3 integers:
-- dest_agent delay_cycles num_of_words
--
-- This is derived from a block "hibi_sender" but modified for
-- testing Nios-to-HIBI2 (n2h2).
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
16,6 → 19,32
-- Date Version Author Description
-- 13.01.2005 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
23,12 → 52,12
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.tb_n2h2_pkg.all;
use work.tb_n2h2_pkg.all; -- incl. e.g. const array "addresses"
 
entity hibi_sender_n2h2 is
generic (
data_1_g : string := "";
--data_1_g : string := ""; -- obsolete?
conf_file_g : string := "";
own_number_g : integer := 0; -- 1-4
comm_width_g : integer := 5;
43,22 → 72,20
done_out : out std_logic; -- if this has finished
 
-- HIBI WRAPPER PORTS
agent_av_out : out std_logic;
agent_data_out : out std_logic_vector(data_width_g-1 downto 0);
agent_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
agent_empty_out : out std_logic;
agent_re_in : in std_logic;
agent_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
agent_data_out : out std_logic_vector(data_width_g-1 downto 0);
agent_av_out : out std_logic
agent_re_in : in std_logic
 
-- note that this only sends, so signals
-- agent_empty_in : in std_logic;
-- agent_one_d_in : in std_logic;
-- agent_re_out : out std_logic;
-- agent_av_in : in std_logic;
-- agent_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
-- agent_data_in : in std_logic_vector(data_width_g-1 downto 0);
-- aren't needed
 
 
-- note that this only sends, so these signals are removed
-- agent_empty_in : in std_logic;
-- agent_one_d_in : in std_logic;
-- agent_re_out : out std_logic;
-- agent_av_in : in std_logic;
-- agent_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
-- agent_data_in : in std_logic_vector(data_width_g-1 downto 0);
-- aren't needed
);
 
end hibi_sender_n2h2;
67,22 → 94,25
architecture rtl of hibi_sender_n2h2 is
 
 
-- Use only one command: basic write operation
constant hibi_write_c : std_logic_vector(comm_width_g-1 downto 0) := "00010";
 
 
-- right now gives a lot of warnings when other than 0
constant dbg_level : integer range 0 to 3 := 0; -- 0= no debug, use 0 for synthesis
 
 
-- Registers may be reset to 'Z' to 'X' so that reset state is clearly
-- distinguished from active state. Using dbg_level+Rst_Value array, the rst value may
-- be easily set to '0' for synthesis.
constant rst_value_arr : std_logic_vector (6 downto 0) := 'X' & 'Z' & 'X' & 'Z' & 'X' & 'Z' & '0';
 
constant hibi_write_c : std_logic_vector(4 downto 0) := "00010";
-- right now gives a lot of warnings when other than 0
constant dbg_level : integer range 0 to 3 := 0; -- 0= no debug, use 0 for synthesis
 
-- reads the (opened) file given. the file line structure is as follows:
-- This procedure reads the (opened) file. The file line structure is as follows:
-- 1st integer: destination agent (1,2,3,4) (not own!)
-- 2nd integer: delay before sending
-- 3rd integer: amount of data to be sent.
-- 2nd integer: delay cycles before sending
-- 3rd integer: amount of data words to be sent.
procedure read_hibi_conf_file (
dest_agent_n : out integer;
delay : out integer;
93,38 → 123,58
variable dest_agent_n_var : integer;
variable delay_var : integer;
variable amount_var : integer;
variable dest_ok : boolean := false; -- ES 2011-11-11
begin -- read_hibi_conf_file
 
begin -- read_hibi_conf_file
readline(conf_dat, file_row);
read (file_row, dest_agent_n_var);
read (file_row, delay_var);
read (file_row, amount_var);
dest_agent_n := dest_agent_n_var;
delay := delay_var;
amount := amount_var;
-- Loop until finding a line that is not a comment
while dest_ok = false and not(endfile(conf_dat)) loop
readline(conf_dat, file_row);
read (file_row, dest_agent_n_var, dest_ok);
 
if dest_ok = FALSE then
--Reading of the delay value failed
--=> assume that this line is comment or empty, and skip other it
-- assert false report "Skipped a line" severity note;
next; -- start new loop interation
end if;
 
read (file_row, delay_var);
read (file_row, amount_var);
 
-- Return the values
dest_agent_n := dest_agent_n_var;
delay := delay_var;
amount := amount_var;
end loop;
end read_hibi_conf_file;
 
 
 
-- Main FSM
type control_states is (read_hibi_conf, wait_sending, write_hibi, wait_hibi, finish, write_addr, pause);
signal control_r : control_states := read_hibi_conf;
 
 
-- fifo signals
signal data_to_fifo : std_logic_vector (1+5+data_width_g-1 downto 0);
 
-- Fifo signals
signal agent_comm_to_fifo : std_logic_vector (comm_width_g-1 downto 0);
signal agent_data_to_fifo : std_logic_vector(data_width_g-1 downto 0);
signal agent_av_to_fifo : std_logic;
signal data_to_fifo : std_logic_vector (1+comm_width_g+data_width_g-1 downto 0); --concatenated from above
signal we_to_fifo : std_logic;
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal re_to_fifo : std_logic;
signal data_from_fifo : std_logic_vector (1+5+data_width_g-1 downto 0);
signal data_from_fifo : std_logic_vector (1+comm_width_g+data_width_g-1 downto 0);
signal empty_from_fifo : std_logic;
signal one_d_from_fifo : std_logic;
 
-- internal
 
signal agent_comm_to_fifo : std_logic_vector (comm_width_g-1 downto 0);
signal agent_data_to_fifo : std_logic_vector(data_width_g-1 downto 0);
signal agent_av_to_fifo : std_logic;
 
--
 
-- internal
constant data_fixed_width_c : integer := 32;
constant n_words_output_c : integer := data_width_g/ data_fixed_width_c;
type dest_amount_cnt_type is array (0 to n_dest_g-1) of std_logic_vector(data_fixed_width_c-1 downto 0);
134,15 → 184,18
begin -- rtl
 
agent_av_out <= data_from_fifo(1+5+data_width_g-1);
agent_comm_out <= data_from_fifo(4+data_width_g downto data_width_g);
agent_av_out <= data_from_fifo(1+comm_width_g+data_width_g-1);
agent_comm_out <= data_from_fifo(comm_width_g+data_width_g-1 downto data_width_g);
agent_data_out <= data_from_fifo(data_width_g-1 downto 0);
data_to_fifo <= agent_av_to_fifo & agent_comm_to_fifo & agent_data_to_fifo;
 
 
--
-- Instead of full HIBI bus, we only need one FIFO. This component
-- puts data to the FIFO, that will be read by the DUT.
--
fifo_1 : entity work.fifo
generic map (
data_width_g => 1+5+data_width_g, -- av, comm, data
data_width_g => 1+comm_width_g+data_width_g, -- av, comm, data
depth_g => 10)
port map (
clk => clk,
156,16 → 209,18
empty_out => agent_empty_out,
one_d_out => one_d_from_fifo);
 
--
-- Generate transfers according to conf file
--
main : process (clk, rst_n)
file conf_data_file : text open read_mode is conf_file_g;
-- file data_file_1 : text open read_mode is data_1_g;
-- file data_file_1 : text open read_mode is data_1_g;
 
variable delay_r : integer;
variable amount_r : integer;
variable dest_agent_n_r : integer;
variable file_number_r : integer;
-- variable data_r : integer;
-- variable data_r : integer;
begin -- process main
if rst_n = '0' then -- asynchronous reset (active low)
control_r <= read_hibi_conf;
178,10 → 233,10
delay_r := 0;
dest_agent_n_r := 0;
for i in 0 to n_dest_g-1 loop
data_r(i) <= (others => '0');
data_r(i) <= (others => '0');
end loop; -- i
file_number_r := 0;
pause_ack <= '0';
file_number_r := 0;
pause_ack <= '0';
sent_packets_r <= 0;
190,8 → 245,8
case control_r is
when read_hibi_conf =>
-- If there's still data left, we read the configuration
-- file and act accordingly. if some delay is specified,
-- we go and wait it (wait_sending). if delay = 0,
-- file and act accordingly. If some delay is specified,
-- we go and wait it (wait_sending). If delay = 0,
-- then we send the address right away
if pause_in = '1' then
control_r <= pause;
219,7 → 274,7
 
 
when wait_sending =>
-- lets wait the given amount of time before proceeding with sending
-- Let's wait the given amount of time before proceeding with sending
delay_r := delay_r-1;
if delay_r = 0 then
control_r <= write_addr;
228,17 → 283,23
amount_r := amount_r;--dest_agent_n_r;
 
when write_addr =>
-- when hibi bus is free, we write the address to it and then
-- When there is room in fifo, we write the address to it and then
-- go to the state where the actual data is sent (write_hibi)
-- note that agent address is gotten from the array defined in
-- tb_eight_hibi_pkg.
-- Note that part of dst agent address is gotten from the array
-- defined in separate package.
if full_from_fifo = '0' then
we_to_fifo <= '1';
agent_av_to_fifo <= '1';
agent_comm_to_fifo <= hibi_write_c;
 
-- Addr defines not only the target, but also
-- identifies the sender and packet number.
-- Hence, sent addresses are always incremented by one.
agent_data_to_fifo <= conv_std_logic_vector
(addresses_c(dest_agent_n_r)+
own_number_g+sent_packets_r, data_width_g);
(addresses_c(dest_agent_n_r)
+ own_number_g + sent_packets_r
, data_width_g);
 
sent_packets_r <= sent_packets_r + 1;
control_r <= write_hibi;
else
250,7 → 311,8
end if;
when write_hibi =>
 
-- Outputs runnign numbers: 0,1,2...
if full_from_fifo = '0' then
 
for i in 0 to n_words_output_c-1 loop
292,12 → 354,12
control_r <= wait_hibi;
we_to_fifo <= '0';
end if;
-- agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
-- agent_av_to_fifo <= '0';
-- agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
-- agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
-- agent_av_to_fifo <= '0';
-- agent_comm_to_fifo <= (others => rst_value_arr(dbg_level*1));
 
when finish =>
-- notify that we're done.
-- Notify that we're done.
done_out <= '1';
agent_data_to_fifo <= (others => rst_value_arr(dbg_level*1));
we_to_fifo <= '0';
/TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_tx_str.do
1,82 → 1,82
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {TB top}
add wave -noupdate -format Logic /tb_n2h2_tx/clk
add wave -noupdate -format Logic /tb_n2h2_tx/clk2
add wave -noupdate -format Logic /tb_n2h2_tx/rst_n
add wave -noupdate -format Literal /tb_n2h2_tx/main_ctrl_r
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/amount_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/mem_addr_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/avalon_addr_from_tx
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_re_from_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/avalon_readdata_to_tx
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_tx
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_waitrequest_to_tx2
add wave -noupdate -format Logic /tb_n2h2_tx/avalon_readdatavalid_to_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/hibi_data_from_tx
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_av_from_tx
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_full_to_tx
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_comm_from_tx
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_from_tx
add wave -noupdate -format Logic /tb_n2h2_tx/tx_start_to_tx
add wave -noupdate -format Logic /tb_n2h2_tx/tx_status_done_from_tx
add wave -noupdate -format Literal /tb_n2h2_tx/tx_comm_to_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/tx_hibi_addr_to_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/tx_ram_addr_to_tx
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/tx_amount_to_tx
add wave -noupdate -format Logic /tb_n2h2_tx/cs1_n_to_ram
add wave -noupdate -format Logic /tb_n2h2_tx/cs2_to_ram
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/addr_to_ram
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/data_inout_ram
add wave -noupdate -format Logic /tb_n2h2_tx/we_n_to_ram
add wave -noupdate -format Logic /tb_n2h2_tx/oe_n_to_ram
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/delayed_data_from_ram_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/hibi_addr_r
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/hibi_amount_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/hibi_data_r
add wave -noupdate -format Literal /tb_n2h2_tx/wait_cnt_r
add wave -noupdate -format Literal /tb_n2h2_tx/avalon_waitr_cnt_r
add wave -noupdate -format Logic /tb_n2h2_tx/hibi_we_was_up_r
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_full_cnt_r
add wave -noupdate -format Literal /tb_n2h2_tx/hibi_full_up_cc
add wave -noupdate /tb_n2h2_tx/Clk
add wave -noupdate /tb_n2h2_tx/Clk2
add wave -noupdate /tb_n2h2_tx/Rst_n
add wave -noupdate /tb_n2h2_tx/main_ctrl_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/amount_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/mem_addr_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/avalon_addr_from_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/avalon_readdata_to_tx
add wave -noupdate /tb_n2h2_tx/avalon_re_from_tx
add wave -noupdate /tb_n2h2_tx/avalon_waitrequest_to_tx
add wave -noupdate /tb_n2h2_tx/avalon_waitrequest_to_tx2
add wave -noupdate /tb_n2h2_tx/avalon_readdatavalid_to_tx
add wave -noupdate /tb_n2h2_tx/hibi_av_from_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_data_from_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_comm_from_tx
add wave -noupdate /tb_n2h2_tx/hibi_we_from_tx
add wave -noupdate /tb_n2h2_tx/hibi_full_to_tx
add wave -noupdate /tb_n2h2_tx/tx_start_to_tx
add wave -noupdate /tb_n2h2_tx/tx_status_done_from_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/tx_hibi_addr_to_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/tx_ram_addr_to_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/tx_amount_to_tx
add wave -noupdate -radix unsigned /tb_n2h2_tx/tx_comm_to_tx
add wave -noupdate /tb_n2h2_tx/cs1_n_to_ram
add wave -noupdate /tb_n2h2_tx/cs2_to_ram
add wave -noupdate -radix unsigned /tb_n2h2_tx/addr_to_ram
add wave -noupdate -radix unsigned /tb_n2h2_tx/data_inout_ram
add wave -noupdate /tb_n2h2_tx/we_n_to_ram
add wave -noupdate /tb_n2h2_tx/oe_n_to_ram
add wave -noupdate -radix unsigned /tb_n2h2_tx/delayed_data_from_ram_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_addr_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_amount_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/hibi_data_r
add wave -noupdate /tb_n2h2_tx/wait_cnt_r
add wave -noupdate /tb_n2h2_tx/avalon_waitr_cnt_r
add wave -noupdate /tb_n2h2_tx/hibi_we_was_up_r
add wave -noupdate /tb_n2h2_tx/hibi_full_cnt_r
add wave -noupdate /tb_n2h2_tx/hibi_full_up_cc
add wave -noupdate -divider {DUT tx}
add wave -noupdate -format Logic /tb_n2h2_tx/dut/clk
add wave -noupdate -format Logic /tb_n2h2_tx/dut/rst_n
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/avalon_addr_out
add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_re_out
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/avalon_readdata_in
add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_waitrequest_in
add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_readdatavalid_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/hibi_data_out
add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_av_out
add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_full_in
add wave -noupdate -format Literal /tb_n2h2_tx/dut/hibi_comm_out
add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_we_out
add wave -noupdate -format Logic /tb_n2h2_tx/dut/tx_start_in
add wave -noupdate -format Logic /tb_n2h2_tx/dut/tx_status_done_out
add wave -noupdate -format Literal /tb_n2h2_tx/dut/tx_comm_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/tx_hibi_addr_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/tx_ram_addr_in
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/tx_amount_in
add wave -noupdate -format Literal /tb_n2h2_tx/dut/control_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_cnt_en_r
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/addr_cnt_value_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_cnt_load_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/addr_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/amount_cnt_en_r
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/amount_cnt_value_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/amount_cnt_load_r
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_tx/dut/amount_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/addr_amount_eq
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_tx/dut/addr_to_stop_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/avalon_re_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/start_re_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_write_addr_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/data_src_sel
add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_we_r
add wave -noupdate -format Logic /tb_n2h2_tx/dut/hibi_stop_we_r
add wave -noupdate /tb_n2h2_tx/DUT/clk
add wave -noupdate /tb_n2h2_tx/DUT/rst_n
add wave -noupdate /tb_n2h2_tx/DUT/avalon_re_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/avalon_addr_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/avalon_readdata_in
add wave -noupdate /tb_n2h2_tx/DUT/avalon_waitrequest_in
add wave -noupdate /tb_n2h2_tx/DUT/avalon_readdatavalid_in
add wave -noupdate /tb_n2h2_tx/DUT/hibi_av_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/hibi_data_out
add wave -noupdate /tb_n2h2_tx/DUT/hibi_comm_out
add wave -noupdate /tb_n2h2_tx/DUT/hibi_we_out
add wave -noupdate /tb_n2h2_tx/DUT/hibi_full_in
add wave -noupdate /tb_n2h2_tx/DUT/tx_start_in
add wave -noupdate /tb_n2h2_tx/DUT/tx_status_done_out
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/tx_comm_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/tx_hibi_addr_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/tx_ram_addr_in
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/tx_amount_in
add wave -noupdate /tb_n2h2_tx/DUT/control_r
add wave -noupdate /tb_n2h2_tx/DUT/addr_cnt_en_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/addr_cnt_value_r
add wave -noupdate /tb_n2h2_tx/DUT/addr_cnt_load_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/addr_r
add wave -noupdate /tb_n2h2_tx/DUT/amount_cnt_en_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/amount_cnt_value_r
add wave -noupdate /tb_n2h2_tx/DUT/amount_cnt_load_r
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/amount_r
add wave -noupdate /tb_n2h2_tx/DUT/addr_amount_eq
add wave -noupdate -radix unsigned /tb_n2h2_tx/DUT/addr_to_stop_r
add wave -noupdate /tb_n2h2_tx/DUT/avalon_re_r
add wave -noupdate /tb_n2h2_tx/DUT/start_re_r
add wave -noupdate /tb_n2h2_tx/DUT/hibi_write_addr_r
add wave -noupdate /tb_n2h2_tx/DUT/data_src_sel
add wave -noupdate /tb_n2h2_tx/DUT/hibi_we_r
add wave -noupdate /tb_n2h2_tx/DUT/hibi_stop_we_r
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {125 ns} 0}
WaveRestoreCursors {{Cursor 1} {175 ns} 0}
configure wave -namecolwidth 211
configure wave -valuecolwidth 100
configure wave -justifyvalue left
91,4 → 91,4
configure wave -timeline 0
configure wave -timelineunits ms
update
WaveRestoreZoom {45 ns} {201 ns}
WaveRestoreZoom {0 ns} {676 ns}
/TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_rx.vhd
1,11 → 1,10
-------------------------------------------------------------------------------
-- Title : Testbench for design "n2h2_rx"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_n2h2_rx.vhdl
-- Author : kulmala3
-- Created : 22.03.2005
-- Last update: 2011-03-09
-- Last update: 2011-11-11
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
13,7 → 12,34
-- Revisions :
-- Date Version Author Description
-- 22.03.2005 1.0 AK Created
-- 2011-11-04 1.01 ES Commenting
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
21,116 → 47,148
use ieee.std_logic_unsigned.all;
use work.tb_n2h2_pkg.all;
-- use work.log2_pkg.all;
-------------------------------------------------------------------------------
 
 
entity tb_n2h2_rx is
 
end tb_n2h2_rx;
 
-------------------------------------------------------------------------------
 
 
architecture tb of tb_n2h2_rx is
 
signal clk : std_logic := '0';
signal clk2 : std_logic := '0';
signal rst_n : std_logic := '0';
-- Includes following components
-- DUT i.e. Nios-to-HIBI v.2 DMA controller
-- config_writer initializes DMA
-- config_reader reads the configuration just in case
-- config_mux multiplexes addr to DUT from cfg_writer and reader
-- hibi_sender models incoming data from HIBI bus
-- avalon_readers model the DP-RAM where DMA writes
 
-- component n2h2 rx generics
constant n_chans_c : integer := 3;
constant n_chans_bits_c : integer := 2;
constant data_width_c : integer := 64; -- 32 and 64 legal
constant addr_width_c : integer := 32;
constant comm_width_c : integer := 5;
constant hibi_addr_cmp_hi_c : integer := 31;
constant hibi_addr_cmp_lo_c : integer := 0;
constant amount_width_c : integer := 5; -- 2**5 flits max
 
-- component ports
signal avalon_addr_from_rx : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_we_from_rx : std_logic;
signal avalon_be_from_rx : std_logic_vector(data_width_c/8-1 downto 0);
signal avalon_writedata_from_rx : std_logic_vector(data_width_c-1 downto 0);
signal avalon_waitrequest_to_rx : std_logic;
signal avalon_waitreqvec_to_rx : std_logic_vector(n_chans_c-1 downto 0);
signal hibi_data_to_rx : std_logic_vector(data_width_c-1 downto 0);
signal hibi_av_to_rx : std_logic;
signal hibi_empty_to_rx : std_logic;
signal hibi_comm_to_rx : std_logic_vector(4 downto 0);
-- Rough data_flow
--
-- cfdg_writer ---> mux ---> DUT <---- hibi_sender
-- ^ |
-- cfg_reader < -------| |-------> avalon_reader(s)
--
--
 
signal hibi_re_from_rx : std_logic;
signal avalon_cfg_addr_to_rx : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
signal avalon_cfg_writedata_to_rx : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_cfg_we_to_rx : std_logic;
signal avalon_cfg_readdata_from_rx : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_cfg_re_to_rx : std_logic;
signal avalon_cfg_cs_to_rx : std_logic;
signal rx_irq_from_rx : std_logic;
signal tx_start_from_rx : std_logic;
signal tx_status_done_to_rx : std_logic;
 
-- config writer
constant conf_file_c : string := "tbrx_conf_rx.dat";
constant conf_file_hsender_c : string := "tbrx_conf_hibisend.dat";
constant data_file_c : string := "tbrx_data_file.dat";
signal start_to_cfg : std_logic;
signal avalon_cfg_addr_from_cfg : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
-- signal avalon_cfg_we_from_cfg : std_logic;
signal avalon_cfg_cs_from_cfg : std_logic;
signal done_from_cfg : std_logic;
signal init_to_cfg : std_logic;
constant conf_file_hsender_c : string := "tbrx_conf_hibisend.dat";
constant conf_file_c : string := "tbrx_conf_rx.dat";
constant data_file_c : string := "tbrx_data_file.dat";
 
-- config reader
signal start_to_cfg_reader : std_logic;
signal avalon_cfg_addr_from_cfg_reader : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
-- signal avalon_cfg_readdata_to_cfg_reader : std_logic_vector(data_width_c-1 downto 0);
-- signal avalon_cfg_re_from_cfg_reader : std_logic;
signal avalon_cfg_cs_from_cfg_reader : std_logic;
signal done_from_cfg_reader : std_logic;
-- component n2h2 rx generics
constant n_chans_c : integer := 3; -- # simultaneous rx transfers
constant n_chans_bits_c : integer := 2; -- log2(n_chans_c)
constant data_width_c : integer := 64; -- 32b and 64b are legal
constant addr_width_c : integer := 32; -- In bits
constant comm_width_c : integer := 5; -- In bits
constant hibi_addr_cmp_hi_c : integer := 31; -- How many incoming addr
constant hibi_addr_cmp_lo_c : integer := 0; -- addr bits are used
constant amount_width_c : integer := 5; -- 2**5 flits max
 
-- hibi writer
signal done_from_hibi_sender : std_logic;
signal pause_hibi_send : std_logic;
signal pause_ack_hibi_send : std_logic;
-- avalon reader
signal init_to_reader : std_logic_vector(n_chans_c-1 downto 0);
signal not_my_addr_from_readers : std_logic_vector(n_chans_c-1 downto 0);
 
 
-- clock and reset
constant Period : time := 10 ns;
 
 
signal clk : std_logic := '0';
signal clk2 : std_logic := '0';
signal rst_n : std_logic := '0';
 
 
-- cpu side signals
 
-- system control signals
-- system control signals.
-- TB has state machine taht starts and stops helper blocks, such
-- config_writer and hibi_sender
type system_control_states is (config, wait_for_config, check_config,
wait_check, wait_for_irq);
signal system_control_r : system_control_states;
signal hibi_sender_start : std_logic;
signal hibi_sender_rst_n : std_logic;
type chan_data_array is array (n_chans_c-1 downto 0) of std_logic_vector(data_width_c-1 downto 0);
signal my_own_addr_c : chan_data_array;
-- signal reset_buses_r : std_logic;
type chan_addr_array is array (n_chans_c-1 downto 0) of std_logic_vector(addr_width_c-1 downto 0);
signal my_own_addr : chan_addr_array;
 
signal avalon_reader_rst_n : std_logic;
signal hibi_data_read : std_logic;
 
signal irq_was_up : std_logic;
signal irq_counter : integer;
 
 
 
-- Component ports: from CPU (=cfg writer), from HIBI, and to memory
signal avalon_cfg_addr_to_dma : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
signal avalon_cfg_writedata_to_dma : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_cfg_we_to_dma : std_logic;
signal avalon_cfg_readdata_from_dma : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_cfg_re_to_dma : std_logic;
signal avalon_cfg_cs_to_dma : std_logic;
signal rx_irq_from_dma : std_logic;
signal tx_start_from_dma : std_logic;
signal tx_status_done_to_dma : std_logic;
 
signal hibi_av_to_dma : std_logic;
signal hibi_data_to_dma : std_logic_vector(data_width_c-1 downto 0);
signal hibi_comm_to_dma : std_logic_vector(4 downto 0);
signal hibi_empty_to_dma : std_logic;
signal hibi_re_from_dma : std_logic;
 
signal avalon_addr_from_dma : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_writedata_from_dma : std_logic_vector(data_width_c-1 downto 0);
signal avalon_we_from_dma : std_logic;
signal avalon_be_from_dma : std_logic_vector(data_width_c/8-1 downto 0);
signal avalon_waitrequest_to_dma : std_logic;
signal avalon_waitreqvec_to_dma : std_logic_vector(n_chans_c-1 downto 0);
 
 
 
-- Config writer
signal start_to_cfgw : std_logic;
signal avalon_cfg_addr_from_cfgw : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
signal avalon_cfg_cs_from_cfgw : std_logic;
signal done_from_cfgw : std_logic;
signal init_to_cfgw : std_logic;
 
-- Config reader
signal start_to_cfgr : std_logic;
signal avalon_cfg_addr_from_cfgr : std_logic_vector(log2(n_chans_c)+conf_bits_c-1 downto 0);
signal avalon_cfg_cs_from_cfgr : std_logic;
signal done_from_cfgr : std_logic;
 
-- Tb <-> hibi writer
signal done_from_hibi_sender : std_logic;
signal pause_hibi_send : std_logic;
signal pause_ack_hibi_send : std_logic;
 
-- Tb <-> Avalon reader
signal init_to_reader : std_logic_vector(n_chans_c-1 downto 0);
signal not_my_addr_from_readers : std_logic_vector(n_chans_c-1 downto 0);
 
 
 
begin -- tb
tx_status_done_to_rx <= '0';
 
hibi_sender_rst_n <= hibi_sender_start and rst_n;
tx_status_done_to_dma <= '0';
 
--
-- This process gives start pulses the helper components
-- and check interrupt reuqest from the DMA
--
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
system_control_r <= config;
start_to_cfg_reader <= '0';
start_to_cfg <= '0';
hibi_sender_start <= '0';
-- reset_buses_r <= '1';
init_to_cfg <= '0';
irq_was_up <= '0';
irq_counter <= 0;
pause_hibi_send <= '0';
system_control_r <= config;
start_to_cfgr <= '0';
start_to_cfgw <= '0';
hibi_sender_start <= '0';
-- reset_buses_r <= '1';
init_to_cfgw <= '0';
irq_was_up <= '0';
irq_counter <= 0;
pause_hibi_send <= '0';
for i in n_chans_c-1 downto 0 loop
init_to_reader(i) <= '0';
end loop; -- i
139,25 → 197,25
case system_control_r is
when config =>
-- write the dma config
start_to_cfg <= '1';
start_to_cfgw <= '1';
system_control_r <= wait_for_config;
when wait_for_config =>
start_to_cfg <= '0';
start_to_cfgw <= '0';
-- wait until it finishes configuring all channels
if done_from_cfg = '1' then
if done_from_cfgw = '1' then
system_control_r <= check_config;
end if;
 
when check_config =>
-- check that the config is written alright
start_to_cfg_reader <= '1';
system_control_r <= wait_check;
start_to_cfgr <= '1';
system_control_r <= wait_check;
 
when wait_check =>
-- wait for check to complete
start_to_cfg_reader <= '0';
if done_from_cfg_reader = '1' then
start_to_cfgr <= '0';
if done_from_cfgr = '1' then
system_control_r <= wait_for_irq;
-- unleash the hibi_sender
hibi_sender_start <= '1';
165,26 → 223,26
 
when wait_for_irq =>
-- check that irq amounts etc are all right.
-- TODO stuff here.
init_to_cfg <= '0';
if done_from_cfg = '1' then
-- TODO stuff here, e.g. acknowleding the interrupt
init_to_cfgw <= '0';
if done_from_cfgw = '1' then
pause_hibi_send <= '0';
end if;
 
if rx_irq_from_rx = '1' and irq_was_up = '0' then
if rx_irq_from_dma = '1' and irq_was_up = '0' then
irq_counter <= irq_counter + 1;
irq_was_up <= '1';
elsif rx_irq_from_rx = '0' then
elsif rx_irq_from_dma = '0' then
irq_was_up <= '0';
end if;
 
if irq_counter = n_chans_c then
if pause_ack_hibi_send = '1' and hibi_empty_to_rx = '1' then
init_to_cfg <= '1';
if pause_ack_hibi_send = '1' and hibi_empty_to_dma = '1' then
init_to_cfgw <= '1';
pause_hibi_send <= '1';
irq_counter <= 0;
else
init_to_cfg <= '0';
init_to_cfgw <= '0';
pause_hibi_send <= '1';
end if;
end if;
197,18 → 255,22
end if;
end process;
 
waitreq : process (avalon_waitreqvec_to_rx)
--
-- OR the wait requests together
--
waitreq : process (avalon_waitreqvec_to_dma)
begin -- process waitreq
if avalon_waitreqvec_to_rx /= conv_std_logic_vector(0, n_chans_c) then
avalon_waitrequest_to_rx <= '1';
if avalon_waitreqvec_to_dma /= conv_std_logic_vector(0, n_chans_c) then
avalon_waitrequest_to_dma <= '1';
else
avalon_waitrequest_to_rx <= '0';
avalon_waitrequest_to_dma <= '0';
end if;
end process waitreq;
 
 
-- component instantiation
--
-- Design-undet-test instantiation
--
DUT : entity work.n2h2_rx_channels
generic map (
n_chans_g => n_chans_c,
221,48 → 283,34
port map (
clk => clk,
rst_n => rst_n,
avalon_addr_out => avalon_addr_from_rx,
avalon_we_out => avalon_we_from_rx,
avalon_be_out => avalon_be_from_rx,
avalon_writedata_out => avalon_writedata_from_rx,
avalon_waitrequest_in => avalon_waitrequest_to_rx,
hibi_data_in => hibi_data_to_rx,
hibi_av_in => hibi_av_to_rx,
hibi_empty_in => hibi_empty_to_rx,
hibi_comm_in => hibi_comm_to_rx,
hibi_re_out => hibi_re_from_rx,
avalon_cfg_addr_in => avalon_cfg_addr_to_rx,
avalon_cfg_writedata_in => avalon_cfg_writedata_to_rx,
avalon_cfg_we_in => avalon_cfg_we_to_rx,
avalon_cfg_readdata_out => avalon_cfg_readdata_from_rx,
avalon_cfg_re_in => avalon_cfg_re_to_rx,
avalon_cfg_cs_in => avalon_cfg_cs_to_rx,
rx_irq_out => rx_irq_from_rx,
tx_start_out => tx_start_from_rx,
tx_status_done_in => tx_status_done_to_rx);
-- Outgoing data to memory
avalon_addr_out => avalon_addr_from_dma,
avalon_writedata_out => avalon_writedata_from_dma,
avalon_we_out => avalon_we_from_dma,
avalon_be_out => avalon_be_from_dma,
avalon_waitrequest_in => avalon_waitrequest_to_dma,
-- Incoming data from hibi
hibi_av_in => hibi_av_to_dma,
hibi_data_in => hibi_data_to_dma,
hibi_comm_in => hibi_comm_to_dma,
hibi_empty_in => hibi_empty_to_dma,
hibi_re_out => hibi_re_from_dma,
-- Incoming configurationg from Avalon (=cpu = conf writer)
avalon_cfg_addr_in => avalon_cfg_addr_to_dma,
avalon_cfg_writedata_in => avalon_cfg_writedata_to_dma,
avalon_cfg_we_in => avalon_cfg_we_to_dma,
avalon_cfg_readdata_out => avalon_cfg_readdata_from_dma,
avalon_cfg_re_in => avalon_cfg_re_to_dma,
avalon_cfg_cs_in => avalon_cfg_cs_to_dma,
rx_irq_out => rx_irq_from_dma,
tx_start_out => tx_start_from_dma,
tx_status_done_in => tx_status_done_to_dma
);
 
 
cfg_mux : process (avalon_cfg_cs_from_cfg, avalon_cfg_cs_from_cfg_reader,
avalon_cfg_addr_from_cfg_reader, avalon_cfg_addr_from_cfg)
variable vector : std_logic_vector(1 downto 0);
begin -- process cfg mux
vector := avalon_cfg_cs_from_cfg & avalon_cfg_cs_from_cfg_reader;
case vector is
when "01" =>
avalon_cfg_addr_to_rx <= avalon_cfg_addr_from_cfg_reader;
avalon_cfg_cs_to_rx <= avalon_cfg_cs_from_cfg_reader;
 
when others =>
-- when "00" | "10" | "11" =>
avalon_cfg_addr_to_rx <= avalon_cfg_addr_from_cfg;
avalon_cfg_cs_to_rx <= avalon_cfg_cs_from_cfg;
end case;
end process cfg_mux;
 
assert not_my_addr_from_readers /= "111" report "address mismatch on avalon!" severity error;
 
--
-- This configures DMA for receiving
--
avalon_cfg_writer_1 : entity work.avalon_cfg_writer
generic map (
n_chans_g => n_chans_c,
271,15 → 319,19
port map (
clk => clk,
rst_n => rst_n,
start_in => start_to_cfg,
avalon_cfg_addr_out => avalon_cfg_addr_from_cfg,
avalon_cfg_writedata_out => avalon_cfg_writedata_to_rx,
avalon_cfg_we_out => avalon_cfg_we_to_rx,
avalon_cfg_cs_out => avalon_cfg_cs_from_cfg,
init_in => init_to_cfg,
done_out => done_from_cfg
start_in => start_to_cfgw,
avalon_cfg_addr_out => avalon_cfg_addr_from_cfgw,
avalon_cfg_writedata_out => avalon_cfg_writedata_to_dma,
avalon_cfg_we_out => avalon_cfg_we_to_dma,
avalon_cfg_cs_out => avalon_cfg_cs_from_cfgw,
init_in => init_to_cfgw,
done_out => done_from_cfgw
);
-- different clock...
 
--
-- This reads the above configuration from DMA
--
-- different clock...
avalon_cfg_reader_1 : entity work.avalon_cfg_reader
generic map (
n_chans_g => n_chans_c,
288,19 → 340,46
port map (
clk => clk2,
rst_n => rst_n,
start_in => start_to_cfg_reader,
avalon_cfg_addr_out => avalon_cfg_addr_from_cfg_reader,
avalon_cfg_readdata_in => avalon_cfg_readdata_from_rx,
avalon_cfg_re_out => avalon_cfg_re_to_rx,
avalon_cfg_cs_out => avalon_cfg_cs_from_cfg_reader,
done_out => done_from_cfg_reader
start_in => start_to_cfgr,
avalon_cfg_addr_out => avalon_cfg_addr_from_cfgr,
avalon_cfg_readdata_in => avalon_cfg_readdata_from_dma,
avalon_cfg_re_out => avalon_cfg_re_to_dma,
avalon_cfg_cs_out => avalon_cfg_cs_from_cfgr,
done_out => done_from_cfgr
);
 
--
-- Mimic Avalon so that configuration can be both written and read
-- to/from DMA
cfg_mux : process (avalon_cfg_cs_from_cfgw, avalon_cfg_cs_from_cfgr,
avalon_cfg_addr_from_cfgr, avalon_cfg_addr_from_cfgw)
variable vector : std_logic_vector(1 downto 0);
begin -- process cfg mux
vector := avalon_cfg_cs_from_cfgw & avalon_cfg_cs_from_cfgr;
case vector is
when "01" =>
avalon_cfg_addr_to_dma <= avalon_cfg_addr_from_cfgr;
avalon_cfg_cs_to_dma <= avalon_cfg_cs_from_cfgr;
 
when others =>
-- when "00" | "10" | "11" =>
avalon_cfg_addr_to_dma <= avalon_cfg_addr_from_cfgw;
avalon_cfg_cs_to_dma <= avalon_cfg_cs_from_cfgw;
end case;
end process cfg_mux;
 
 
 
--
-- This models the traffic coming from HIBI bus to DMA.
--
hibi_sender_n2h2_1 : entity work.hibi_sender_n2h2
generic map (
data_1_g => data_file_c,
--data_1_g => data_file_c, -- obsolete?
conf_file_g => conf_file_hsender_c,
own_number_g => 4,
own_number_g => 0, -- used to be 4, ES 2011-11-11
comm_width_g => comm_width_c,
data_width_g => data_width_c
)
310,21 → 389,30
pause_in => pause_hibi_send,
pause_ack => pause_ack_hibi_send,
done_out => done_from_hibi_sender,
agent_empty_out => hibi_empty_to_rx,
agent_re_in => hibi_re_from_rx,
agent_comm_out => hibi_comm_to_rx,
agent_data_out => hibi_data_to_rx,
agent_av_out => hibi_av_to_rx
 
agent_av_out => hibi_av_to_dma,
agent_data_out => hibi_data_to_dma,
agent_comm_out => hibi_comm_to_dma,
agent_empty_out => hibi_empty_to_dma,
agent_re_in => hibi_re_from_dma
);
 
hibi_data_read <= hibi_empty_to_rx nor hibi_av_to_rx;
hibi_sender_rst_n <= hibi_sender_start and rst_n;
 
 
 
--
-- Check the data written to mem. There is a separate
-- checker module (avalon_reader) for each rx channel
--
avalon_reader_rst_n <= rst_n;
avalon : for i in n_chans_c-1 downto 0 generate
my_own_addr_c(i) <= conv_std_logic_vector(ava_addresses_c(i), data_width_c);
--my_own_addr(i) <= conv_std_logic_vector(ava_addresses_c(i), data_width_c);
my_own_addr(i) <= conv_std_logic_vector(ava_addresses_c(i), addr_width_c);
 
avalon_reader_i : entity work.avalon_reader
generic map (
data_file_g => data_file_c,
-- data_file_g => data_file_c,
addr_width_g => addr_width_c,
data_width_g => data_width_c
)
331,21 → 419,30
port map (
clk => clk,
rst_n => avalon_reader_rst_n,
avalon_we_in => avalon_we_from_rx,
avalon_be_in => avalon_be_from_rx,
increment_data_ptr => hibi_data_read,
waitrequest_real_in => avalon_waitrequest_to_rx,
avalon_writedata_in => avalon_writedata_from_rx,
avalon_addr_in => avalon_addr_from_rx,
avalon_waitrequest_out => avalon_waitreqvec_to_rx(i),
my_own_addr_in => my_own_addr_c(i),
avalon_addr_in => avalon_addr_from_dma,
avalon_writedata_in => avalon_writedata_from_dma,
avalon_we_in => avalon_we_from_dma,
avalon_be_in => avalon_be_from_dma,
waitrequest_real_in => avalon_waitrequest_to_dma,
avalon_waitrequest_out => avalon_waitreqvec_to_dma(i),
increment_data_ptr => hibi_data_read, -- obsolete?
my_own_addr_in => my_own_addr(i),
not_my_addr_out => not_my_addr_from_readers(i),
init_in => pause_hibi_send
);
end generate avalon;
 
hibi_data_read <= hibi_empty_to_dma nor hibi_av_to_dma; -- obsolete?
assert not_my_addr_from_readers /= "111" report "Address mismatch on avalon!" severity error;
 
 
 
 
 
--
-- Generate clocks and reset
--
 
CLOCK1 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
/TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx.vhd
5,7 → 5,7
-- File : tb_n2h2_tx.vhd
-- Author : kulmala3
-- Created : 30.03.2005
-- Last update: 2011-03-09
-- Last update: 2011-11-11
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
14,6 → 14,32
-- Date Version Author Description
-- 30.03.2005 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
/TUT/ip.hwp.communication/n2h2/tb/blocks/wave_tb_n2h2_rx.do
1,107 → 1,113
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {TB top}
add wave -noupdate -format Logic /tb_n2h2_rx/clk
add wave -noupdate -format Logic /tb_n2h2_rx/clk2
add wave -noupdate -format Logic /tb_n2h2_rx/rst_n
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_addr_from_rx
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_we_from_rx
add wave -noupdate -format Literal /tb_n2h2_rx/avalon_be_from_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_writedata_from_rx
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_waitrequest_to_rx
add wave -noupdate -format Literal /tb_n2h2_rx/avalon_waitreqvec_to_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/hibi_data_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/hibi_av_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/hibi_empty_to_rx
add wave -noupdate -format Literal /tb_n2h2_rx/hibi_comm_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/hibi_re_from_rx
add wave -noupdate -format Literal /tb_n2h2_rx/avalon_cfg_addr_to_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_cfg_writedata_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_we_to_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/avalon_cfg_readdata_from_rx
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_re_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_cs_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/rx_irq_from_rx
add wave -noupdate -format Logic /tb_n2h2_rx/tx_start_from_rx
add wave -noupdate -format Logic /tb_n2h2_rx/tx_status_done_to_rx
add wave -noupdate -format Logic /tb_n2h2_rx/start_to_cfg
add wave -noupdate -format Literal /tb_n2h2_rx/avalon_cfg_addr_from_cfg
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_cs_from_cfg
add wave -noupdate -format Logic /tb_n2h2_rx/done_from_cfg
add wave -noupdate -format Logic /tb_n2h2_rx/init_to_cfg
add wave -noupdate -format Logic /tb_n2h2_rx/start_to_cfg_reader
add wave -noupdate -format Literal /tb_n2h2_rx/avalon_cfg_addr_from_cfg_reader
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_cfg_cs_from_cfg_reader
add wave -noupdate -format Logic /tb_n2h2_rx/done_from_cfg_reader
add wave -noupdate -format Logic /tb_n2h2_rx/done_from_hibi_sender
add wave -noupdate -format Logic /tb_n2h2_rx/pause_hibi_send
add wave -noupdate -format Logic /tb_n2h2_rx/pause_ack_hibi_send
add wave -noupdate -format Literal /tb_n2h2_rx/not_my_addr_from_readers
add wave -noupdate -format Literal /tb_n2h2_rx/system_control_r
add wave -noupdate -format Logic /tb_n2h2_rx/hibi_sender_start
add wave -noupdate -format Logic /tb_n2h2_rx/hibi_sender_rst_n
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/my_own_addr_c
add wave -noupdate -format Logic /tb_n2h2_rx/avalon_reader_rst_n
add wave -noupdate -format Logic /tb_n2h2_rx/hibi_data_read
add wave -noupdate -format Logic /tb_n2h2_rx/irq_was_up
add wave -noupdate -format Literal /tb_n2h2_rx/irq_counter
add wave -noupdate /tb_n2h2_rx/system_control_r
add wave -noupdate -radix hexadecimal -childformat {{/tb_n2h2_rx/my_own_addr(2) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(1) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0) -radix hexadecimal -childformat {{/tb_n2h2_rx/my_own_addr(0)(63) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(62) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(61) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(60) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(59) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(58) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(57) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(56) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(55) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(54) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(53) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(52) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(51) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(50) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(49) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(48) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(47) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(46) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(45) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(44) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(43) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(42) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(41) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(40) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(39) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(38) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(37) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(36) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(35) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(34) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(33) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(32) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(31) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(30) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(29) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(28) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(27) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(26) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(25) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(24) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(23) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(22) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(21) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(20) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(19) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(18) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(17) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(16) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(15) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(14) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(13) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(12) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(11) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(10) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(9) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(8) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(7) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(6) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(5) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(4) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(3) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(2) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(1) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(0) -radix hexadecimal}}}} -subitemconfig {/tb_n2h2_rx/my_own_addr(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0) {-height 15 -radix hexadecimal -childformat {{/tb_n2h2_rx/my_own_addr(0)(63) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(62) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(61) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(60) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(59) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(58) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(57) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(56) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(55) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(54) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(53) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(52) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(51) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(50) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(49) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(48) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(47) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(46) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(45) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(44) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(43) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(42) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(41) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(40) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(39) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(38) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(37) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(36) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(35) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(34) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(33) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(32) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(31) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(30) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(29) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(28) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(27) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(26) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(25) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(24) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(23) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(22) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(21) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(20) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(19) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(18) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(17) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(16) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(15) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(14) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(13) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(12) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(11) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(10) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(9) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(8) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(7) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(6) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(5) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(4) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(3) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(2) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(1) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(0) -radix hexadecimal}}} /tb_n2h2_rx/my_own_addr(0)(63) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(62) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(61) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(60) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(59) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(58) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(57) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(56) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(55) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(54) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(53) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(52) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(51) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(50) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(49) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(48) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(47) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(46) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(45) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(44) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(43) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(42) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(41) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(40) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(39) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(38) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(37) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(36) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(35) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(34) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(33) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(32) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(31) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(30) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(29) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(28) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(27) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(26) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(25) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(24) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(23) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(22) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(21) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(20) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(19) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(18) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(17) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(16) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(15) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(14) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(13) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(12) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(11) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(10) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(9) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(8) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(7) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(6) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(5) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(4) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(3) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(0) {-height 15 -radix hexadecimal}} /tb_n2h2_rx/my_own_addr
add wave -noupdate /tb_n2h2_rx/rx_irq_from_dma
add wave -noupdate /tb_n2h2_rx/irq_was_up
add wave -noupdate /tb_n2h2_rx/irq_counter
add wave -noupdate -divider {Configuring the DMA}
add wave -noupdate /tb_n2h2_rx/clk
add wave -noupdate /tb_n2h2_rx/clk2
add wave -noupdate /tb_n2h2_rx/rst_n
add wave -noupdate /tb_n2h2_rx/init_to_cfgw
add wave -noupdate /tb_n2h2_rx/start_to_cfgw
add wave -noupdate /tb_n2h2_rx/avalon_cfg_cs_to_dma
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_addr_to_dma
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_writedata_to_dma
add wave -noupdate /tb_n2h2_rx/avalon_cfg_we_to_dma
add wave -noupdate /tb_n2h2_rx/done_from_cfgw
add wave -noupdate /tb_n2h2_rx/avalon_reader_rst_n
add wave -noupdate /tb_n2h2_rx/start_to_cfgr
add wave -noupdate /tb_n2h2_rx/avalon_cfg_cs_to_dma
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_addr_to_dma
add wave -noupdate /tb_n2h2_rx/avalon_cfg_re_to_dma
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_readdata_from_dma
add wave -noupdate /tb_n2h2_rx/done_from_cfgr
add wave -noupdate /tb_n2h2_rx/tx_start_from_dma
add wave -noupdate /tb_n2h2_rx/tx_status_done_to_dma
add wave -noupdate /tb_n2h2_rx/not_my_addr_from_readers
add wave -noupdate -divider {HIBI -> DMA}
add wave -noupdate /tb_n2h2_rx/clk
add wave -noupdate /tb_n2h2_rx/rst_n
add wave -noupdate /tb_n2h2_rx/hibi_sender_rst_n
add wave -noupdate /tb_n2h2_rx/hibi_sender_start
add wave -noupdate /tb_n2h2_rx/hibi_av_to_dma
add wave -noupdate -radix hexadecimal -childformat {{/tb_n2h2_rx/hibi_data_to_dma(63) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(62) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(61) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(60) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(59) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(58) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(57) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(56) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(55) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(54) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(53) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(52) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(51) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(50) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(49) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(48) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(47) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(46) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(45) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(44) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(43) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(42) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(41) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(40) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(39) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(38) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(37) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(36) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(35) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(34) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(33) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(32) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(31) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(30) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(29) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(28) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(27) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(26) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(25) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(24) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(23) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(22) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(21) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(20) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(19) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(18) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(17) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(16) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(15) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(14) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(13) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(12) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(11) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(10) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(9) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(8) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(7) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(6) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(5) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(4) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(3) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(2) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(1) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(0) -radix hexadecimal}} -subitemconfig {/tb_n2h2_rx/hibi_data_to_dma(63) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(62) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(61) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(60) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(59) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(58) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(57) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(56) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(55) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(54) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(53) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(52) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(51) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(50) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(49) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(48) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(47) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(46) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(45) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(44) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(43) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(42) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(41) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(40) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(39) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(38) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(37) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(36) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(35) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(34) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(33) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(32) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(31) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(30) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(29) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(28) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(27) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(26) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(25) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(24) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(23) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(22) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(21) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(20) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(19) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(18) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(17) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(16) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(15) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(14) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(13) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(12) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(11) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(10) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(9) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(8) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(7) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(6) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(5) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(4) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(3) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(0) {-height 15 -radix hexadecimal}} /tb_n2h2_rx/hibi_data_to_dma
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/hibi_comm_to_dma
add wave -noupdate /tb_n2h2_rx/hibi_re_from_dma
add wave -noupdate /tb_n2h2_rx/hibi_empty_to_dma
add wave -noupdate /tb_n2h2_rx/pause_hibi_send
add wave -noupdate /tb_n2h2_rx/pause_ack_hibi_send
add wave -noupdate -divider {DMA -> mem}
add wave -noupdate /tb_n2h2_rx/clk
add wave -noupdate /tb_n2h2_rx/rst_n
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_addr_from_dma
add wave -noupdate /tb_n2h2_rx/avalon_we_from_dma
add wave -noupdate /tb_n2h2_rx/avalon_be_from_dma
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_writedata_from_dma
add wave -noupdate /tb_n2h2_rx/avalon_waitrequest_to_dma
add wave -noupdate /tb_n2h2_rx/avalon_waitreqvec_to_dma
add wave -noupdate -divider {DUT rx}
add wave -noupdate -format Logic /tb_n2h2_rx/dut/clk
add wave -noupdate -format Logic /tb_n2h2_rx/dut/rst_n
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_addr_out
add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_we_out
add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_be_out
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_writedata_out
add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_waitrequest_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/hibi_data_in
add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_av_in
add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_empty_in
add wave -noupdate -format Literal /tb_n2h2_rx/dut/hibi_comm_in
add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_re_out
add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_cfg_addr_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_cfg_writedata_in
add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_cfg_we_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_cfg_readdata_out
add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_cfg_re_in
add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_cfg_cs_in
add wave -noupdate -format Logic /tb_n2h2_rx/dut/rx_irq_out
add wave -noupdate -format Logic /tb_n2h2_rx/dut/tx_start_out
add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_comm_out
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_mem_addr_out
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_hibi_addr_out
add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_amount_out
add wave -noupdate -format Logic /tb_n2h2_rx/dut/tx_status_done_in
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/mem_addr_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/sender_addr_r
add wave -noupdate -format Literal -radix unsigned /tb_n2h2_rx/dut/irq_amount_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/control_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_mem_addr_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/tx_hibi_addr_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_amount_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/tx_comm_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/init_chan_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/irq_chan_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/current_mem_addr_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/current_be_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_be_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/status_r
add wave -noupdate -format Logic /tb_n2h2_rx/dut/irq_reset_r
add wave -noupdate -format Logic /tb_n2h2_rx/dut/hibi_re_r
add wave -noupdate -format Logic /tb_n2h2_rx/dut/avalon_we_r
add wave -noupdate -format Logic /tb_n2h2_rx/dut/unknown_rx
add wave -noupdate -format Logic /tb_n2h2_rx/dut/unknown_rx_irq_r
add wave -noupdate -format Logic /tb_n2h2_rx/dut/unknown_rx_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_addr_r
add wave -noupdate -format Logic /tb_n2h2_rx/dut/curr_chan_avalon_we_r
add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_wes
add wave -noupdate -format Literal /tb_n2h2_rx/dut/matches
add wave -noupdate -format Literal /tb_n2h2_rx/dut/matches_cmb
add wave -noupdate -format Literal /tb_n2h2_rx/dut/irq_ack_r
add wave -noupdate -format Literal -radix hexadecimal /tb_n2h2_rx/dut/avalon_addr_temp
add wave -noupdate -format Literal /tb_n2h2_rx/dut/avalon_be_temp
add wave -noupdate /tb_n2h2_rx/DUT/clk
add wave -noupdate /tb_n2h2_rx/DUT/rst_n
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_cfg_addr_in
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_cfg_writedata_in
add wave -noupdate /tb_n2h2_rx/DUT/avalon_cfg_we_in
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_cfg_readdata_out
add wave -noupdate /tb_n2h2_rx/DUT/avalon_cfg_re_in
add wave -noupdate /tb_n2h2_rx/DUT/avalon_cfg_cs_in
add wave -noupdate /tb_n2h2_rx/DUT/rx_irq_out
add wave -noupdate /tb_n2h2_rx/DUT/tx_start_out
add wave -noupdate /tb_n2h2_rx/DUT/tx_comm_out
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_mem_addr_out
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_hibi_addr_out
add wave -noupdate /tb_n2h2_rx/DUT/tx_amount_out
add wave -noupdate /tb_n2h2_rx/DUT/tx_status_done_in
add wave -noupdate /tb_n2h2_rx/DUT/clk
add wave -noupdate /tb_n2h2_rx/DUT/rst_n
add wave -noupdate -radix unsigned /tb_n2h2_rx/DUT/avalon_addr_out
add wave -noupdate /tb_n2h2_rx/DUT/avalon_we_out
add wave -noupdate /tb_n2h2_rx/DUT/avalon_be_out
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_writedata_out
add wave -noupdate /tb_n2h2_rx/DUT/avalon_waitrequest_in
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/hibi_data_in
add wave -noupdate /tb_n2h2_rx/DUT/hibi_av_in
add wave -noupdate /tb_n2h2_rx/DUT/hibi_empty_in
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/hibi_comm_in
add wave -noupdate /tb_n2h2_rx/DUT/hibi_re_out
add wave -noupdate /tb_n2h2_rx/DUT/clk
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/mem_addr_r
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/sender_addr_r
add wave -noupdate -radix unsigned /tb_n2h2_rx/DUT/irq_amount_r
add wave -noupdate /tb_n2h2_rx/DUT/control_r
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_mem_addr_r
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_hibi_addr_r
add wave -noupdate /tb_n2h2_rx/DUT/tx_amount_r
add wave -noupdate /tb_n2h2_rx/DUT/tx_comm_r
add wave -noupdate /tb_n2h2_rx/DUT/init_chan_r
add wave -noupdate /tb_n2h2_rx/DUT/irq_chan_r
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/current_mem_addr_r
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/current_be_r
add wave -noupdate /tb_n2h2_rx/DUT/avalon_be_r
add wave -noupdate /tb_n2h2_rx/DUT/status_r
add wave -noupdate /tb_n2h2_rx/DUT/irq_reset_r
add wave -noupdate /tb_n2h2_rx/DUT/hibi_re_r
add wave -noupdate /tb_n2h2_rx/DUT/avalon_we_r
add wave -noupdate /tb_n2h2_rx/DUT/unknown_rx
add wave -noupdate /tb_n2h2_rx/DUT/unknown_rx_irq_r
add wave -noupdate /tb_n2h2_rx/DUT/unknown_rx_r
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_addr_r
add wave -noupdate /tb_n2h2_rx/DUT/curr_chan_avalon_we_r
add wave -noupdate /tb_n2h2_rx/DUT/avalon_wes
add wave -noupdate /tb_n2h2_rx/DUT/matches
add wave -noupdate /tb_n2h2_rx/DUT/matches_cmb
add wave -noupdate /tb_n2h2_rx/DUT/irq_ack_r
add wave -noupdate -radix hexadecimal -childformat {{/tb_n2h2_rx/DUT/avalon_addr_temp(31) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(30) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(29) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(28) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(27) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(26) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(25) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(24) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(23) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(22) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(21) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(20) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(19) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(18) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(17) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(16) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(15) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(14) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(13) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(12) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(11) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(10) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(9) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(8) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(7) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(6) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(5) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(4) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(3) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(2) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(1) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(0) -radix hexadecimal}} -subitemconfig {/tb_n2h2_rx/DUT/avalon_addr_temp(31) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(30) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(29) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(28) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(27) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(26) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(25) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(24) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(23) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(22) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(21) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(20) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(19) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(18) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(17) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(16) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(15) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(14) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(13) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(12) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(11) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(10) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(9) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(8) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(7) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(6) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(5) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(4) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(3) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(0) {-height 15 -radix hexadecimal}} /tb_n2h2_rx/DUT/avalon_addr_temp
add wave -noupdate /tb_n2h2_rx/DUT/avalon_be_temp
add wave -noupdate -divider {Dut ends}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1191 ns} 0}
configure wave -namecolwidth 211
WaveRestoreCursors {{Cursor 1} {759 ns} 0}
configure wave -namecolwidth 274
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
115,4 → 121,4
configure wave -timeline 0
configure wave -timelineunits ms
update
WaveRestoreZoom {0 ns} {2052 ns}
WaveRestoreZoom {506 ns} {1506 ns}
/TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_reader.vhd
5,7 → 5,7
-- File : avalon_cfg_reader.vhd
-- Author : kulmala3
-- Created : 22.03.2005
-- Last update: 2010/05/07
-- Last update: 2011-11-10
-- Description: testbench block to test the config of the dma via avalon
-------------------------------------------------------------------------------
-- Copyright (c) 2005
14,6 → 14,32
-- Date Version Author Description
-- 22.03.2005 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
55,7 → 81,7
process (clk, rst_n)
file conf_file : text open read_mode is conf_file_g;
variable mem_addr_r : integer;
variable sender_r : integer;
variable dst_addr_r : integer;
variable irq_amount_r : integer;
variable max_amount_r : integer;
begin -- process
85,7 → 111,7
when 1 =>
read_conf_file (
mem_addr => mem_addr_r ,
sender => sender_r,
dst_addr => dst_addr_r,
irq_amount => irq_amount_r,
-- max_amount => max_amount_r,
file_txt => conf_file
101,7 → 127,7
 
when 2 =>
 
assert avalon_cfg_readdata_in = conv_std_logic_vector(sender_r, data_width_g) report "config mismatch sender addr" severity error;
assert avalon_cfg_readdata_in = conv_std_logic_vector(dst_addr_r, data_width_g) report "config mismatch sender addr" severity error;
avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
conv_std_logic_vector(2, conf_bits_c);
avalon_cfg_re_out <= '1';
/TUT/ip.hwp.communication/n2h2/tb/blocks/fifo.vhd
10,6 → 10,32
--
-- 15.12.04 ES: names changed
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
/TUT/ip.hwp.communication/n2h2/tb/blocks/avalon_cfg_writer.vhd
5,8 → 5,9
-- File : avalon_cfg_writer.vhd
-- Author : kulmala3
-- Created : 22.03.2005
-- Last update: 2010/05/07
-- Description: testbench block to config the dma via avalon
-- Last update: 2011-11-10
-- Description: Testbench block to config the dma via avalon.
-- Gets the needed values from an ASCII file.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
14,6 → 15,32
-- Date Version Author Description
-- 22.03.2005 1.0 AK Created
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
 
library ieee;
49,8 → 76,14
signal state_r : integer;
signal init_state_r : integer;
signal chan_counter_r : integer;
 
 
begin -- rtl
 
--
-- Simple state machine, states are just numbered 0,1,2...8
-- Separate part for init on the bottom
--
process (clk, rst_n)
file conf_file : text open read_mode is conf_file_g;
variable mem_addr_r : integer;
81,18 → 114,20
end if;
 
when 1 =>
-- Read file and configure mem addr
read_conf_file (
mem_addr => mem_addr_r ,
sender => sender_r,
dst_addr => sender_r,
irq_amount => irq_amount_r,
-- max_amount => max_amount_r,
-- max_amount => max_amount_r,
file_txt => conf_file
);
 
assert false report "mem_addr: " & str(mem_addr_r) severity note;
assert false report "sender_r: " & str(sender_r) severity note;
assert false report "irq_amount_r: " & str(irq_amount_r) severity note;
-- assert false report "max_amount_r: " & str(max_amount_r) severity note;
assert false report "dst_addr: " & str(sender_r) severity note;
assert false report "irq_amount: " & str(irq_amount_r) severity note;
-- assert false report "max_amount_r: " & str(max_amount_r) severity note;
 
avalon_cfg_writedata_out <= conv_std_logic_vector(mem_addr_r, data_width_g);
avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
102,7 → 137,9
state_r <= 2;
 
when 2 =>
-- Configure noc_addr_r (originally called "sender_r")
 
avalon_cfg_writedata_out <= conv_std_logic_vector(sender_r, data_width_g);
avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
conv_std_logic_vector(1, conf_bits_c);
112,7 → 149,8
state_r <= 3;
when 3 =>
 
-- Confgure expexted word count
avalon_cfg_writedata_out <= conv_std_logic_vector(irq_amount_r, data_width_g);
avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
conv_std_logic_vector(2, conf_bits_c);
132,7 → 170,7
-- state_r <= 5;
 
when 5 =>
-- set init bit
-- Set init bit
avalon_cfg_writedata_out <= (others => '0');
avalon_cfg_writedata_out(chan_counter_r) <= '1';
avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
142,7 → 180,7
state_r <= 6;
 
when 6 =>
-- set irq_ena bit
-- Set irq_ena bit
avalon_cfg_writedata_out <= (others => '0');
avalon_cfg_writedata_out(1) <= '1';
avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
162,11 → 200,15
-- state_r <= 7;
 
when 7 =>
-- Go to next channel
avalon_cfg_cs_out <= '0';
chan_counter_r <= chan_counter_r+1;
state_r <= 8;
 
when 8 =>
-- Configure next channel or start over
if chan_counter_r = n_chans_g then
state_r <= 0;
chan_counter_r <= 0;
179,6 → 221,9
when others => null;
end case;
 
 
 
if init_in = '1' then
init_state_r <= 1;
end if;
/TUT/ip.hwp.communication/n2h2/tb/blocks/tb_n2h2_tx_fo.vhd
1,15 → 1,13
------------------------------------------------------------
-- Project : Engine
-- Author : Ari Kulmala
-- e-mail : ari.kulmala@tut.fi
-- Date : 7.7.2004
-- File : tb_n2h_tx.vhdl
-- Design : testbench for nios to hibi transmitter
-- Try with N2H2 TX
-- Project : Engine
-- Author : Ari Kulmala
-- e-mail : ari.kulmala@tut.fi
-- Date : 7.7.2004
-- File : tb_n2h_tx.vhdl
-- Design : Syncronous testbench for Nios-to-Hibi v2 (N2H2 )transmitter
-- Unlike rx tb, this does not use config file, but
-- all the tests are hard-coded into this file.
------------------------------------------------------------
-- Description : a testbench for n2h_tx individual testing.
-- synchronous.
------------------------------------------------------------
-- $Log$
-- Revision 1.1 2005/04/14 06:45:55 kulmala3
-- First version to CVS
17,12 → 15,42
-- 31.08.04 AK Streaming
-- 05.01.04 AK Interface signals naming changed.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This file is part of HIBI
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
use work.txt_util.all;
 
 
entity tb_n2h2_tx is
 
end tb_n2h2_tx;
30,318 → 58,322
architecture rtl of tb_n2h2_tx is
constant PERIOD : time := 50 ns;
 
constant data_width_g : integer := 32;
constant amount_width_g : integer := 9;
constant addr_width_g : integer := 32;
constant addr_offset_c : integer := (data_width_g)/8;
constant data_width_c : integer := 32; -- bits
constant amount_width_c : integer := 9; -- at max 2^amount words sent
constant addr_width_c : integer := 32; -- bits
constant addr_offset_c : integer := (data_width_c)/8;
 
constant comm_write : std_logic_vector(4 downto 0) := "00010";
constant comm_idle : std_logic_vector(4 downto 0) := "00000";
constant comm_write_msg : std_logic_vector(4 downto 0) := "00011";
constant comm_write_c : std_logic_vector(4 downto 0) := "00010";
constant comm_idle_c : std_logic_vector(4 downto 0) := "00000";
constant comm_write_msg_c : std_logic_vector(4 downto 0) := "00011";
 
constant data_start : integer := 0;
constant data_start_c : integer := 0;
constant wait_req_freq_c : integer := 10;
 
 
type test_states is (test1, test2, test3, stop_tests);
signal test_control : test_states := test1;
type test_case_states is (assign, trigger, monitor, finish);
signal test_case_control : test_case_states := trigger;
 
-- Clk and reset
signal clk : std_logic;
signal clk2 : std_logic;
signal rst_n : std_logic;
 
 
-- Two-level FSM in the testbench
-- There are multiple test cases, and each has 4 phases
type test_states is (test1, test2, test3, stop_tests);
type test_case_states is (assign, trigger, monitor, finish);
signal test_ctrl_r : test_states := test1;
signal test_case_ctrl_r : test_case_states := trigger;
 
 
 
-- signals from n2h_tx
signal tx_status_from_n2h_tx : std_logic := '0';
signal tx_busy_from_n2h_tx : std_logic;
signal tx_status_duv_tb : std_logic := '0';
signal tx_busy_duv_tb : std_logic;
 
-- signals to n2h_tx
signal internal_wait_to_n2h_tx : std_logic := '0';
signal tx_irq_to_n2h_tx : std_logic;
signal Amount_to_n2h_tx : integer := 0;
signal Amount_vec_to_n2h_tx : std_logic_vector(amount_width_g-1 downto 0);
signal dpram_vec_addr_to_n2h_tx : std_logic_vector(addr_width_g-1 downto 0);
signal dpram_addr_to_n2h_tx : integer := 0;
signal comm_to_n2h_tx : std_logic_vector(4 downto 0);
--hibi
signal hibi_data_vec_from_n2h_tx : std_logic_vector(data_width_g-1 downto 0);
signal hibi_data_from_n2h_tx : integer := 0;
signal hibi_av_from_n2h_tx : std_logic := '0';
signal hibi_full_to_n2h_tx : std_logic := '1';
signal hibi_comm_from_n2h_tx : std_logic_vector(4 downto 0);
signal hibi_we_from_n2h_tx : std_logic;
-- avalon
signal avalon_addr_from_n2h_tx : std_logic_vector(addr_width_g-1 downto 0);
signal avalon_read_from_n2h_tx : std_logic;
signal avalon_vec_readdata_to_n2h_tx : std_logic_vector(data_width_g-1 downto 0);
signal avalon_readdata_to_n2h_tx : integer := 0;
signal avalon_waitrequest_to_n2h_tx : std_logic;
signal avalon_readdatavalid_to_n2h_tx : std_logic;
-- signals from tb to n2h_tx
signal internal_wait_tb_duv : std_logic := '0';
signal tx_irq_tb_duv : std_logic;
signal amount_tb_duv : integer := 0;
signal amount_vec_tb_duv : std_logic_vector(amount_width_c-1 downto 0);
signal dpram_vec_addr_tb_duv : std_logic_vector(addr_width_c-1 downto 0);
signal dpram_addr_tb_duv : integer := 0;
signal hibi_addr_tb_duv : std_logic_vector (data_width_c-1 downto 0); -- 2011-11-11
signal comm_tb_duv : std_logic_vector(4 downto 0);
 
 
 
--Duv=tx writes to hibi with these
signal hibi_av_duv_tb : std_logic := '0';
signal hibi_data_duv_tb : integer := 0;
signal hibi_data_vec_duv_tb : std_logic_vector(data_width_c-1 downto 0);
signal hibi_comm_duv_tb : std_logic_vector(4 downto 0);
signal hibi_we_duv_tb : std_logic;
signal hibi_full_tb_duv : std_logic := '1';
 
-- Duv=tx reads meemory via these avalon signals
signal avalon_addr_duv_tb : std_logic_vector(addr_width_c-1 downto 0);
signal avalon_read_duv_tb : std_logic;
signal avalon_vec_readdata_tb_duv : std_logic_vector(data_width_c-1 downto 0);
signal avalon_readdata_tb_duv : integer := 0;
signal avalon_waitrequest_tb_duv : std_logic;
signal avalon_readdatavalid_tb_duv : std_logic;
 
 
 
-- others
signal counter : integer := 0; -- temp counter, no special func
signal new_hibi_addr : integer := 0;
signal new_amount : integer := 0;
signal new_dpram_addr : integer := 0;
signal counter_r : integer := 0; -- temp counter_r, no special func
signal new_hibi_addr_r : integer := 0;
signal new_amount_r : integer := 0;
signal new_dpram_addr_r : integer := 0;
 
 
 
 
-- which address hibi should get next
signal global_hibi_address : integer := 0;
signal global_hibi_addr_r : integer := 0;
-- global number of data in next packet
signal global_amount : integer := 0;
signal global_comm : std_logic_vector(4 downto 0);
signal global_dpram_addr : integer := 0; -- given dpram addr
signal global_amount_r : integer := 0;
signal global_comm_r : std_logic_vector(4 downto 0);
signal global_dpram_addr : integer := 0; -- given dpram addr
 
-- check avalon signals
signal avalon_data_counter : integer := data_start; -- data sent
signal avalon_addr_counter : integer := 0; -- avalon addr right?
signal avalon_amount : integer := 0; -- how many data
signal avalon_addr_sent : std_logic := '0'; -- if already gave address
signal avalon_last_addr : integer := 0; -- store the old addr
-- signal avalon_gave_data : std_logic := 0; -- avalon timing
-- signal avalon_ok : std_logic := '0'; -- all the avalon data ok
signal avalon_data_counter_r : integer := data_start_c; -- data sent
signal avalon_addr_counter_r : integer := 0; -- avalon addr right?
signal avalon_amount : integer := 0; -- how many data
signal avalon_addr_sent : std_logic := '0'; -- if already gave address
signal avalon_last_addr : integer := 0; -- store the old addr
-- signal avalon_gave_data : std_logic := 0; -- avalon timing
-- signal avalon_ok : std_logic := '0'; -- all the avalon data ok
 
-- check hibi signals
signal hibi_addr_came : std_logic := '0';
signal hibi_data_counter : integer := data_start; -- data received
signal hibi_addr : integer := 0; -- right hibi addr
signal hibi_amount : integer := 0; -- how many datas hibi has received
-- signal hibi_ok : std_logic := '0'; --hibi received all ok.
begin -- rtl
signal hibi_addr_came : std_logic; --:= '0';
signal hibi_data_counter_r : integer := data_start_c; -- data received
signal hibi_addr : integer := 0; -- right hibi addr
signal hibi_amount : integer := 0; -- how many datas hibi has received
-- signal hibi_ok : std_logic := '0'; --hibi received all ok.
 
hibi_data_from_n2h_tx <= conv_integer(hibi_data_vec_from_n2h_tx);
Amount_vec_to_n2h_tx <= conv_std_logic_vector(Amount_to_n2h_tx, amount_width_g);
dpram_vec_addr_to_n2h_tx <=
conv_std_logic_vector(dpram_addr_to_n2h_tx, addr_width_g);
avalon_vec_readdata_to_n2h_tx <=
conv_std_logic_vector(avalon_readdata_to_n2h_tx, data_width_g);
 
begin -- rtl
 
--
-- Instantiate DUV. Note that this is just one sbu-block
-- from N2H.
--
--
n2h2_tx_1 : entity work.n2h2_tx
generic map (
data_width_g => data_width_g,
amount_width_g => amount_width_g)
data_width_g => data_width_c,
amount_width_g => amount_width_c
)
port map (
clk => clk,
rst_n => rst_n,
-- Avalon master read interface
avalon_addr_out => avalon_addr_from_n2h_tx,
avalon_re_out => avalon_read_from_n2h_tx,
avalon_readdata_in => avalon_vec_readdata_to_n2h_tx,
avalon_waitrequest_in => avalon_waitrequest_to_n2h_tx,
avalon_readdatavalid_in => avalon_readdatavalid_to_n2h_tx, -- ES 2010/05/07
-- hibi write interface
hibi_data_out => hibi_data_vec_from_n2h_tx,
hibi_av_out => hibi_av_from_n2h_tx,
hibi_full_in => hibi_full_to_n2h_tx,
hibi_comm_out => hibi_comm_from_n2h_tx,
hibi_we_out => hibi_we_from_n2h_tx,
clk => clk,
rst_n => rst_n,
 
-- DMA conf interface
tx_start_in => tx_irq_to_n2h_tx,
tx_status_done_out => tx_status_from_n2h_tx,
tx_comm_in => comm_to_n2h_tx,
tx_hibi_addr_in => (others => '0'),
tx_ram_addr_in => dpram_vec_addr_to_n2h_tx,
tx_amount_in => Amount_vec_to_n2h_tx
-- Avalon master read interface to access the memory
avalon_addr_out => avalon_addr_duv_tb,
avalon_readdata_in => avalon_vec_readdata_tb_duv,
avalon_re_out => avalon_read_duv_tb,
avalon_waitrequest_in => avalon_waitrequest_tb_duv,
avalon_readdatavalid_in => avalon_readdatavalid_tb_duv, -- ES 2010/05/07
 
-- Hibi interface for sending data
hibi_data_out => hibi_data_vec_duv_tb,
hibi_av_out => hibi_av_duv_tb,
hibi_full_in => hibi_full_tb_duv,
hibi_comm_out => hibi_comm_duv_tb,
hibi_we_out => hibi_we_duv_tb,
 
-- DMA configuration interface, driven by "N2H ctrl logic" (=tb here)
tx_start_in => tx_irq_tb_duv,
tx_status_done_out => tx_status_duv_tb,
tx_comm_in => comm_tb_duv,
tx_hibi_addr_in => hibi_addr_tb_duv, --(others => '0'),
tx_ram_addr_in => dpram_vec_addr_tb_duv,
tx_amount_in => amount_vec_tb_duv
);
 
 
-- tx : n2h_tx
-- generic map (
-- data_width_g => data_width_g,
-- amount_width_g => amount_width_g,
-- addr_width_g => addr_width_g
-- )
 
-- port map (
-- clk => clk,
-- rst_n => rst_n,
-- tx_busy_out => tx_busy_from_n2h_tx,
-- comm_in => comm_to_n2h_tx,
-- Amount_in => Amount_vec_to_n2h_tx,
-- dpram_addr_in => dpram_vec_addr_to_n2h_tx,
-- tx_irq_in => tx_irq_to_n2h_tx,
-- tx_status_out => tx_status_from_n2h_tx,
-- avalon_addr_out => avalon_addr_from_n2h_tx,
-- avalon_re_out => avalon_read_from_n2h_tx,
-- avalon_readdata_in => avalon_vec_readdata_to_n2h_tx,
-- avalon_readdatavalid_in => avalon_readdatavalid_to_n2h_tx,
-- avalon_waitrequest_in => avalon_waitrequest_to_n2h_tx,
-- internal_wait_in => internal_wait_to_n2h_tx,
-- hibi_data_out => hibi_data_vec_from_n2h_tx,
-- hibi_comm_out => hibi_comm_from_n2h_tx,
-- hibi_av_out => hibi_av_from_n2h_tx,
-- hibi_we_out => hibi_we_from_n2h_tx,
-- hibi_full_in => hibi_full_to_n2h_tx
-- );
 
-- check_avalon and check_hibi continuously monitor avalon and hibi
-- buses. the tests doesn't have to check whether the data came right,
-- those do it automatically. that's because the sent data is implemented
-- as a counter, so that the incoming data should be in order.
-- if theres too much data read from avalon, hibi gets wrong packets
-- Processes check_avalon and check_hibi continuously monitor avalon and hibi
-- buses and automatically check whether the data came right.
-- It's simple because the sent data is implemented
-- as a counter and hence the incoming data should be in order.
-- If theres too much data read from avalon, hibi gets wrong packets
-- and informs.
-- if theres too much/few data sent to hibi, hibi informs.
-- If theres too much/few data sent to hibi, hibi informs also.
 
 
-- test is the main process that is implented as a state machine
-- TB uses integers. Convert them to/from bit vectors for port mapping
hibi_data_duv_tb <= to_integer(unsigned(hibi_data_vec_duv_tb));
amount_vec_tb_duv <= std_logic_vector(to_unsigned(amount_tb_duv, amount_width_c));
dpram_vec_addr_tb_duv <=
std_logic_vector(to_unsigned(dpram_addr_tb_duv, addr_width_c));
avalon_vec_readdata_tb_duv <=
std_logic_vector(to_unsigned(avalon_readdata_tb_duv, data_width_c))
when avalon_readdatavalid_tb_duv = '1' else (others => 'Z');
hibi_addr_tb_duv <= std_logic_vector (to_unsigned(global_hibi_addr_r, data_width_c));
 
 
--
-- "Test" is the main process that is implented as a state machine
-- (test1, test2 ... etc) so that new tests can be easily implemented
--
test : process (clk, rst_n)
begin -- process test
if rst_n = '0' then -- asynchronous reset (active low)
test_control <= test2;
test_case_control <= assign;
test_ctrl_r <= test1; -- test2;
test_case_ctrl_r <= trigger; --assign;
 
-- Initializations added 2011-11-11, ES
comm_tb_duv <= comm_idle_c;
global_comm_r <= comm_idle_c;
tx_irq_tb_duv <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case test_control is
case test_ctrl_r is
 
-----------------------------------------------------------------------
-- tests is controlled by following signals, which must be set
-- global_hibi_address
-- global_amount
-- global_comm
 
-- TEST 1 IS OBSOLETE
--
-- tests are controlled by following signals, which must be set
-- global_hibi_addr_r = where to send
-- global_amount_r = how much to send
-- global_comm_r = which command to use
-----------------------------------------------------------------------
when test1 =>
-- basic test. tests action under hibi_full signal
when test1 =>
-- Basic test: tests action under hibi_full signal
-- and how one packet is transferred.
case test_case_control is
case test_case_ctrl_r is
when trigger =>
-- assign and trigger irq.
 
 
if tx_status_from_n2h_tx = '1' then
global_amount <= 4;
Amount_to_n2h_tx <= 4;
global_hibi_address <= 230;
global_comm <= comm_write;
comm_to_n2h_tx <= comm_write;
tx_irq_to_n2h_tx <= '1';
dpram_addr_to_n2h_tx <= 8;
global_dpram_addr <= 8;
test_case_control <= monitor;
-- assert hibi full signal
hibi_full_to_n2h_tx <= '1';
if tx_status_duv_tb = '1' then
global_amount_r <= 1; --4;
amount_tb_duv <= 1; --4;
global_hibi_addr_r <= 230;
global_comm_r <= comm_write_c;
comm_tb_duv <= comm_write_c;
tx_irq_tb_duv <= '1';
dpram_addr_tb_duv <= 8;
global_dpram_addr <= 8;
test_case_ctrl_r <= monitor;
 
-- Assert hibi full signal
hibi_full_tb_duv <= '1';
 
else
assert false report "cannot start test, tx_status low" severity note;
assert false report "Cannot start test1, tx_status low" severity note;
end if;
 
when monitor =>
tx_irq_to_n2h_tx <= '0';
tx_irq_tb_duv <= '0';
 
counter <= counter+1;
if counter < 10 then
test_case_control <= monitor;
counter_r <= counter_r+1;
if counter_r < 10 then
test_case_ctrl_r <= monitor;
else
hibi_full_to_n2h_tx <= '0';
test_case_control <= finish;
hibi_full_tb_duv <= '0';
test_case_ctrl_r <= finish;
end if;
 
-- if tx_status_from_n2h_tx = '1' then
-- -- values read.
-- Amount_to_n2h_tx <= 0;
-- dpram_addr_to_n2h_tx <= 0;
-- comm_to_n2h_tx <= comm_idle;
-- -- lets test the full signal
-- end if;
-- if tx_status_duv_tb = '1' then
-- -- values read.
-- amount_tb_duv <= 0;
-- dpram_addr_tb_duv <= 0;
-- comm_tb_duv <= comm_idle_c;
-- -- lets test the full signal
-- end if;
 
when finish =>
if tx_status_from_n2h_tx = '1' then
if tx_status_duv_tb = '1' then
assert false report "test1 finished." severity note;
test_control <= test2;
test_case_control <= assign;
counter <= 0;
test_ctrl_r <= test2;
test_case_ctrl_r <= assign;
counter_r <= 0;
else
test_case_control <= finish;
test_case_ctrl_r <= finish;
end if;
 
 
when others => null;
end case;
when test2 =>
-- tests how multiple packets are transferred and
when test2 =>
-- Tests how multiple packets are transferred and
-- how max values are treated.
 
case test_case_control is
case test_case_ctrl_r is
when assign =>
-- we always go to trigger next, unless otherwise noted.
test_case_control <= trigger;
test_case_ctrl_r <= trigger;
-- assign new values
if counter = 0 then
new_amount <= 6;
new_hibi_addr <= 6302;
new_dpram_addr <= 400;
elsif counter = 1 then
new_amount <= 172;
new_hibi_addr <= 30;
new_dpram_addr <= 300;
elsif counter = 2 then
new_amount <= 1;
new_hibi_addr <= 21;
new_dpram_addr <= 323;
elsif counter = 3 then
new_amount <= 14;
new_hibi_addr <= 54;
new_dpram_addr <= 12;
elsif counter = 4 then
new_amount <= 6;
new_hibi_addr <= 602;
new_dpram_addr <= 40;
elsif counter = 5 then
new_amount <= 9;
new_hibi_addr <= 64510;
new_dpram_addr <= 511;
if counter_r = 0 then
new_amount_r <= 6;
new_hibi_addr_r <= 6302;
new_dpram_addr_r <= 400;
elsif counter_r = 1 then
new_amount_r <= 172;
new_hibi_addr_r <= 30;
new_dpram_addr_r <= 300;
elsif counter_r = 2 then
new_amount_r <= 1;
new_hibi_addr_r <= 21;
new_dpram_addr_r <= 323;
elsif counter_r = 3 then
new_amount_r <= 14;
new_hibi_addr_r <= 54;
new_dpram_addr_r <= 12;
elsif counter_r = 4 then
new_amount_r <= 6;
new_hibi_addr_r <= 602;
new_dpram_addr_r <= 40;
elsif counter_r = 5 then
new_amount_r <= 9;
new_hibi_addr_r <= 64510;
new_dpram_addr_r <= 511;
else
--stop the tests
test_control <= stop_tests;
test_case_control <= assign;
test_ctrl_r <= stop_tests;
test_case_ctrl_r <= assign;
end if;
 
counter <= counter+1;
counter_r <= counter_r+1;
 
when trigger =>
-- assign and trigger irq.
 
if tx_status_from_n2h_tx = '1' then
global_amount <= new_amount;
Amount_to_n2h_tx <= new_amount;
global_hibi_address <= new_hibi_addr;
global_comm <= comm_write;
comm_to_n2h_tx <= comm_write;
tx_irq_to_n2h_tx <= '1';
dpram_addr_to_n2h_tx <= new_dpram_addr;
global_dpram_addr <= new_dpram_addr;
test_case_control <= monitor;
if tx_status_duv_tb = '1' then
global_amount_r <= new_amount_r;
amount_tb_duv <= new_amount_r;
global_hibi_addr_r <= new_hibi_addr_r;
global_comm_r <= comm_write_c;
comm_tb_duv <= comm_write_c;
tx_irq_tb_duv <= '1';
dpram_addr_tb_duv <= new_dpram_addr_r;
global_dpram_addr <= new_dpram_addr_r;
test_case_ctrl_r <= monitor;
-- deassert hibi full signal, just in case
hibi_full_to_n2h_tx <= '0';
hibi_full_tb_duv <= '0';
 
else
assert false report "cannot start test, tx_status low" severity note;
assert false report "Cannot start test, tx_status low" severity note;
end if;
 
when monitor =>
tx_irq_to_n2h_tx <= '0';
-- if tx_status_from_n2h_tx = '1' then
-- -- values read.
-- Amount_to_n2h_tx <= 0;
-- dpram_addr_to_n2h_tx <= 0;
-- comm_to_n2h_tx <= comm_idle;
tx_irq_tb_duv <= '0';
-- if tx_status_duv_tb = '1' then
-- -- values read.
-- amount_tb_duv <= 0;
-- dpram_addr_tb_duv <= 0;
-- comm_tb_duv <= comm_idle_c;
-- lets test the full signal
test_case_control <= finish;
-- end if;
test_case_ctrl_r <= finish;
-- end if;
 
when finish =>
if tx_status_from_n2h_tx = '1' then
if tx_status_duv_tb = '1' then
assert false report "test2 finished." severity note;
test_case_control <= assign;
test_case_ctrl_r <= assign;
else
test_case_control <= finish;
test_case_ctrl_r <= finish;
end if;
 
 
349,59 → 381,82
end case;
when test3 =>
when stop_tests =>
assert false report "all tests finished." severity failure;
when others => null;
assert false report "All tests finished." severity failure;
when others => null;
end case;
end if;
end process test;
 
-- checks whether incoming data to hibi is right
check_hibi : process (clk)
 
 
--
-- Checks whether data going to hibi is right
--
check_hibi : process (clk) -- (clk)
begin -- process check_hibi
if clk = '1' and clk'event then
if rst_n = '0' then
hibi_addr_came <= '0';
elsif clk = '1' and clk'event then
 
assert hibi_amount >= 0 report "Hibi amount negative - too much data" severity warning;
 
 
-- Not expecting more data
if hibi_amount = 0 then
hibi_addr_came <= '0';
end if;
 
assert hibi_amount >= 0 report "hibi amount negative - too much data" severity warning;
 
if hibi_we_from_n2h_tx = '1' then
-- DMA writes. Check the addr and data
if hibi_we_duv_tb = '1' then
 
if hibi_comm_from_n2h_tx /= global_comm then
assert false report "hibi command failure - not as expected" severity warning;
if hibi_comm_duv_tb /= global_comm_r then
assert false report "Hibi command failure - expected" & str(global_comm_r) severity warning;
end if;
 
-- if address valid comes before we have received all the data
-- we expected, thats wrong
if hibi_av_from_n2h_tx = '1' then
 
if hibi_av_duv_tb = '1' then
-- DMA writes addr
 
-- Address valid should not come before we have received all the data
if hibi_amount = 0 then
if hibi_data_from_n2h_tx = global_hibi_address then
if hibi_data_duv_tb = global_hibi_addr_r then
hibi_addr_came <= '1';
hibi_amount <= global_amount;
hibi_amount <= global_amount_r;
assert false report "Hibi addr OK " & str(hibi_data_duv_tb) severity note;
else
assert false report "hibi address wasn't expected" severity warning;
assert false report "Hibi address error, expected " & str(global_hibi_addr_r)
& ", but got " & str(hibi_data_duv_tb)
severity warning;
end if;
 
else
assert false report "Hibi data failure, address came but shouldn't have" severity warning;
assert false report "Hibi data failure, address came before prev transfer is completed" severity warning;
end if;
 
else
-- if address has been received
-- DMA writes data
-- Data must be correct and come after addr
 
if hibi_addr_came = '1' then
-- and the data is right
if hibi_data_from_n2h_tx = hibi_data_counter then
hibi_data_counter <= hibi_data_counter+1;
hibi_amount <= hibi_amount-1;
if hibi_data_duv_tb = hibi_data_counter_r then
assert false report "Hibi data OK " & str(hibi_data_duv_tb) severity note;
hibi_data_counter_r <= hibi_data_counter_r+1;
hibi_amount <= hibi_amount-1;
if hibi_amount = 1 then
hibi_addr_came <= '0';
hibi_addr_came <= '0';
end if;
else
assert false report "hibi data was wrong" severity warning;
assert false report "Hibi data error, expexted " & str(hibi_data_counter_r)
& ", but got " & str(hibi_data_duv_tb)
severity warning;
end if;
 
else
assert false report "data came before an address" severity warning;
assert false report "Data " & str(hibi_data_duv_tb) & " came before an address" severity warning;
end if;
end if;
 
410,100 → 465,138
 
end process check_hibi;
 
check_avalon : process (clk2)
variable waitreq_cnt_r : integer := 0;
 
--
--
--
check_avalon : process (clk2, rst_n)
variable waitreq_cnt_r : integer := 0;
variable expected_ava_addr_v : integer := -1;
begin -- process check_avalon
if clk2'event and clk2 = '1' then -- rising clock edge
if rst_n = '0' then
-- reset added 2011-11-11, ES
avalon_readdatavalid_tb_duv <= '0';
avalon_waitrequest_tb_duv <= '0';
--elsif clk2'event and clk2 = '1' then -- rising clock edge
elsif clk'event and clk = '1' then -- rising clock edge
 
--assert avalon_amount >= 0 report "avalon amount negative - tried to read too much data" severity warning;
 
avalon_last_addr <= conv_integer(avalon_addr_from_n2h_tx);
avalon_last_addr <= to_integer(unsigned(avalon_addr_duv_tb));
 
assert avalon_amount >= 0 report "avalon amount negative - tried to read too much data" severity warning;
 
if avalon_read_from_n2h_tx = '1' and avalon_waitrequest_to_n2h_tx = '0' then --and
-- avalon_readdatavalid_to_n2h_tx = '1' then
-- avalon_readdatavalid_to_n2h_tx <= '1';
if (global_dpram_addr + avalon_addr_counter) /=
avalon_addr_from_n2h_tx then
assert false report "address to avalon is wrong" severity warning;
else
if (global_dpram_addr + avalon_addr_counter) = (2**addr_width_g-2) then
avalon_addr_counter <= 0 - global_dpram_addr;
elsif (global_dpram_addr + avalon_addr_counter) = (2**addr_width_g-1) then
-- DMA reads memory
if avalon_read_duv_tb = '1' then
if avalon_waitrequest_tb_duv = '0' then
 
avalon_readdatavalid_tb_duv <= '1';
 
-- Calculate the expected address
expected_ava_addr_v := global_dpram_addr + avalon_addr_counter_r; --es
 
if (expected_ava_addr_v) = (2**addr_width_c-2) then
avalon_addr_counter_r <= 0 - global_dpram_addr;
elsif (expected_ava_addr_v) = (2**addr_width_c-1) then
-- odd number (eg. 511) overflow, add one.
avalon_addr_counter <= 1 - global_dpram_addr;
avalon_addr_counter_r <= 1 - global_dpram_addr;
else
avalon_addr_counter <= avalon_addr_counter + addr_offset_c;
avalon_addr_counter_r <= avalon_addr_counter_r + addr_offset_c;
end if;
end if;
 
--avalon_waitrequest_to_n2h_tx <= '0';
avalon_readdatavalid_to_n2h_tx <= '1';
if avalon_addr_sent = '0' then
-- first slot contains address
avalon_readdata_to_n2h_tx <= global_hibi_address;
avalon_addr_sent <= '1';
avalon_amount <= global_amount;
else
-- now the data
if avalon_last_addr = avalon_addr_from_n2h_tx then
avalon_readdata_to_n2h_tx <= avalon_data_counter;
avalon_data_counter <= avalon_data_counter;
avalon_amount <= avalon_amount;
-- Check addr
assert expected_ava_addr_v = avalon_addr_duv_tb report "Avalon address error, expected "
& str(expected_ava_addr_v)
& ", but got " & str(to_integer(unsigned(avalon_addr_duv_tb)))
severity warning;
 
-- Generate the data that comes from the "memory"
if avalon_addr_sent = '0' then
-- 2011-11-11 not sending addr anymore in the beginning
-- modifcation is prograa, not yet complete....
avalon_readdata_tb_duv <= avalon_data_counter_r;
avalon_data_counter_r <= avalon_data_counter_r+1;
avalon_addr_sent <= '1';
avalon_amount <= global_amount_r;
-- -- first slot contains address
-- avalon_readdata_tb_duv <= global_hibi_addr_r;
-- avalon_addr_sent <= '1';
-- avalon_amount <= global_amount_r;
 
else
avalon_readdata_to_n2h_tx <= avalon_data_counter;
avalon_data_counter <= avalon_data_counter+1;
avalon_amount <= avalon_amount-1;
end if;
if avalon_amount = 1 then
-- next we expect that a new packet should be sent.
avalon_addr_sent <= '0';
avalon_addr_counter <= 0;
end if;
-- now the data
if avalon_last_addr = avalon_addr_duv_tb then
avalon_readdata_tb_duv <= avalon_data_counter_r;
avalon_data_counter_r <= avalon_data_counter_r;
avalon_amount <= avalon_amount;
else
avalon_readdata_tb_duv <= avalon_data_counter_r;
avalon_data_counter_r <= avalon_data_counter_r+1;
avalon_amount <= avalon_amount-1;
end if;
 
if avalon_amount = 1 then
-- next we expect that a new packet should be sent.
avalon_addr_sent <= '0';
avalon_addr_counter_r <= 0;
end if;
 
end if;
end if;
-- elsif avalon_read_from_n2h_tx = '1' and avalon_readdatavalid_to_n2h_tx = '0' then
-- avalon_readdatavalid_to_n2h_tx <= '1';
-- avalon_waitrequest_to_n2h_tx <= '0';
else
-- Not reading
avalon_readdatavalid_tb_duv <= '0';
end if;
 
-- avalon_readdata_to_n2h_tx <= 0;
--avalon_waitrequest_to_n2h_tx <= '1';
-- avalon_readdatavalid_to_n2h_tx <= '0';
end if;
avalon_waitrequest_to_n2h_tx <= '0'; -- was always
waitreq_cnt_r := waitreq_cnt_r +1;
 
 
-- Generate occasional wait requests to DMA
avalon_waitrequest_tb_duv <= '0'; -- was always
waitreq_cnt_r := waitreq_cnt_r +1;
-- generate waitreq
if waitreq_cnt_r = wait_req_freq_c then
avalon_waitrequest_to_n2h_tx <= '1';
waitreq_cnt_r := 0;
avalon_waitrequest_tb_duv <= '1' and avalon_read_duv_tb;
waitreq_cnt_r := 0;
end if;
 
 
end if;
end if; -- rst/clk
end process check_avalon;
 
CLOCK1 : process -- generate clock signal for design
 
--
-- Generate clocks and reset
--
CLOCK1 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
wait for PERIOD/2;
clktmp := not clktmp;
Clk <= clktmp;
clktmp := not clktmp;
clk <= clktmp;
end process CLOCK1;
 
-- clk2 <= clk after PERIOD/4; -- 2011-11-15 ES
-- different phase for the avalon bus
CLOCK2 : process -- generate clock signal for design
CLOCK2 : process -- generate clock signal for design
variable clk2tmp : std_logic := '0';
begin
clk2tmp := not clk2tmp;
Clk2 <= clk2tmp;
clk2tmp := not clk2tmp;
clk2 <= clk2tmp;
wait for PERIOD/2;
end process CLOCK2;
 
RESET : process
begin
Rst_n <= '0'; -- Reset the testsystem
rst_n <= '0'; -- Reset the testsystem
wait for 6*PERIOD; -- Wait
Rst_n <= '1'; -- de-assert reset
rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
/TUT/ip.hwp.communication/n2h2/tb/tbrx_data_file.dat
1,3 → 1,5
2011-11-10 This files seems to be obsolete, ES
 
1111 1115 12
1111 1116 12
1111 1117 12

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