URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/funbase_ip_library/trunk
- from Rev 70 to Rev 71
- ↔ Reverse comparison
Rev 70 → Rev 71
/TUT/ip.hwp.accelerator/port_blinker/1.0/port_blinker.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 10:48:51 pe loka 21 2011--> |
<spirit:component> |
<!--Created by Kactus 2 document generator 14:14:24 30.11.2011--> |
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.accelerator</spirit:library> |
<spirit:name>port_blinker</spirit:name> |
204,6 → 204,7
</spirit:file> |
</spirit:fileSet> |
</spirit:fileSets> |
<spirit:description>Counts up and inverts output when reaching the limit value. Then start over again.</spirit:description> |
<spirit:vendorExtensions> |
<kactus2:extensions> |
<kactus2:kts_attributes> |
/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd
28,11 → 28,12
-- File : port_blinker.vhd |
-- Author : Juha Arvio |
-- Company : TUT |
-- Last update: 20.10.2011 |
-- Last update: 2011-11-30 |
-- Version : 0.1 |
-- Platform : |
------------------------------------------------------------------------------- |
-- Description: |
-- Description: Counts up and inverts output when reaching the limit value. |
-- Then start over again. |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
45,40 → 46,37
use ieee.std_logic_unsigned.all; |
|
entity port_blinker is |
generic ( SIGNAL_WIDTH : integer := 32 ); |
|
generic ( |
SIGNAL_WIDTH : integer := 32 |
); |
port ( |
clk : in std_logic; |
clk : in std_logic; |
rst_n : in std_logic; |
|
ena_in : in std_logic; |
val_in : in std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
port_out : out std_logic ); |
|
ena_in : in std_logic; |
val_in : in std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
port_out : out std_logic |
); |
|
end port_blinker; |
|
architecture rtl of port_blinker is |
function i2s(value : integer; width : integer) return std_logic_vector is |
begin |
return conv_std_logic_vector(value, width); |
end; |
|
function s2i(value : std_logic_vector) return integer is |
begin |
return conv_integer(value); |
end; |
|
|
signal port_level_r : std_logic; |
signal val_cnt_r : std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
signal val_cnt_r : std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
|
begin |
|
port_out <= port_level_r; |
|
|
-- |
-- Count upwards until reaching the value in the input |
-- |
process (clk, rst_n) |
begin |
if (rst_n = '0') then |
port_level_r <= '0'; |
val_cnt_r <= (others => '0'); |
val_cnt_r <= (others => '0'); |
|
elsif (clk'event and clk = '1') then |
|
87,7 → 85,7
else |
if (val_cnt_r = val_in) then |
port_level_r <= not(port_level_r); |
val_cnt_r <= (others => '0'); |
val_cnt_r <= (others => '0'); |
else |
val_cnt_r <= val_cnt_r + 1; |
end if; |
/TUT/ip.hwp.accelerator/sig_gen/1.0/sig_gen.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 15:26:11 pe loka 21 2011--> |
<spirit:component> |
<!--Created by Kactus 2 document generator 14:08:07 30.11.2011--> |
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.accelerator</spirit:library> |
<spirit:name>sig_gen</spirit:name> |
187,10 → 187,12
<spirit:modelParameters> |
<spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped"> |
<spirit:name>SIGNAL_VAL</spirit:name> |
<spirit:value>100000000</spirit:value> |
<spirit:description>Constant value driven to the output</spirit:description> |
<spirit:value>50000000</spirit:value> |
</spirit:modelParameter> |
<spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped"> |
<spirit:name>SIGNAL_WIDTH</spirit:name> |
<spirit:description>In bits</spirit:description> |
<spirit:value>32</spirit:value> |
</spirit:modelParameter> |
</spirit:modelParameters> |
208,6 → 210,7
</spirit:file> |
</spirit:fileSet> |
</spirit:fileSets> |
<spirit:description>Generates a constant value to the output bus and an enable signal that can be toggled.</spirit:description> |
<spirit:vendorExtensions> |
<kactus2:extensions> |
<kactus2:kts_attributes> |
/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd
28,11 → 28,12
-- File : sig_gen.vhd |
-- Author : Juha Arvio |
-- Company : TUT |
-- Last update: 20.10.2011 |
-- Last update: 2011-11-30 |
-- Version : 0.1 |
-- Platform : |
------------------------------------------------------------------------------- |
-- Description: |
-- Description: Generates a constant value to the output bus and an enable |
-- signal that can be toggled. |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
45,48 → 46,54
use ieee.std_logic_unsigned.all; |
|
entity sig_gen is |
generic ( SIGNAL_VAL : integer := 100000000; |
SIGNAL_WIDTH : integer := 32 ); |
|
generic ( |
SIGNAL_VAL : integer := 5000000; -- Constant value driven to the output |
SIGNAL_WIDTH : integer := 32 -- In bits |
); |
port ( |
clk : in std_logic; |
clk : in std_logic; |
rst_n : in std_logic; |
|
toggle_in : in std_logic; |
sig_out : out std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
ena_out : out std_logic ); |
|
toggle_in : in std_logic; |
sig_out : out std_logic_vector(SIGNAL_WIDTH-1 downto 0); |
ena_out : out std_logic |
); |
|
end sig_gen; |
|
architecture rtl of sig_gen is |
|
function i2s(value : integer; width : integer) return std_logic_vector is |
begin |
return conv_std_logic_vector(value, width); |
end; |
|
|
function s2i(value : std_logic_vector) return integer is |
begin |
return conv_integer(value); |
end; |
|
|
signal toggle_d1_r : std_logic; |
signal toggle_r : std_logic; |
signal ena_r : std_logic; |
begin |
|
sig_out <= i2s(SIGNAL_VAL, SIGNAL_WIDTH); |
ena_out <= toggle_r; |
|
ena_out <= ena_r; |
|
-- |
-- Detects a rising edge in toggle-input |
-- |
process (clk, rst_n) |
begin |
if (rst_n = '0') then |
toggle_d1_r <= '0'; |
toggle_r <= '0'; |
ena_r <= '0'; |
|
elsif (clk'event and clk = '1') then |
toggle_d1_r <= toggle_in; |
|
|
if ((toggle_in = '1') and (toggle_d1_r = '0')) then |
toggle_r <= not(toggle_r); |
ena_r <= not(ena_r); |
end if; |
end if; |
end process; |