URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/funbase_ip_library/trunk
- from Rev 81 to Rev 82
- ↔ Reverse comparison
Rev 81 → Rev 82
/TUT/ip.hwp.interface/led_pkt_codec_mk2/1.0/led_pkt_codec_mk2.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 19:49:44 ke marras 9 2011--> |
<spirit:component> |
<!--Created by Kactus 2 document generator 15:20:17 01.12.2011--> |
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.interface</spirit:library> |
<spirit:name>led_pkt_codec_mk2</spirit:name> |
196,6 → 196,15
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>rtl</spirit:name> |
<spirit:envIdentifier>VHDL::</spirit:envIdentifier> |
<spirit:fileSetRef> |
<spirit:localName>HDLsources</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
</spirit:views> |
<spirit:ports> |
<spirit:port> |
<spirit:name>clk</spirit:name> |
205,7 → 214,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
222,7 → 231,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
239,7 → 248,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
256,7 → 265,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
273,7 → 282,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
286,7 → 295,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
299,7 → 308,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
312,7 → 321,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
325,7 → 334,7
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef></spirit:viewNameRef> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
343,6 → 352,12
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags> |
</spirit:buildCommand> |
</spirit:file> |
<spirit:defaultFileBuilder> |
<spirit:fileType>vhdlSource</spirit:fileType> |
<spirit:command>vcom</spirit:command> |
<spirit:flags>-quiet -check_synthesis</spirit:flags> |
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags> |
</spirit:defaultFileBuilder> |
</spirit:fileSet> |
</spirit:fileSets> |
<spirit:description>Inverts led for evey data word received.</spirit:description> |