URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/funbase_ip_library/trunk
- from Rev 85 to Rev 86
- ↔ Reverse comparison
Rev 85 → Rev 86
/TUT/ip.hwp.accelerator/port_blinker/1.0/port_blinker.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 14:14:24 30.11.2011--> |
<!--Created by Kactus 2 document generator 13:36:18 02.12.2011--> |
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.accelerator</spirit:library> |
132,6 → 132,15
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>rtl</spirit:name> |
<spirit:envIdentifier>vhdl::</spirit:envIdentifier> |
<spirit:fileSetRef> |
<spirit:localName>hdlSources</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
</spirit:views> |
<spirit:ports> |
<spirit:port> |
<spirit:name>clk</spirit:name> |
141,6 → 150,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
151,6 → 167,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
161,6 → 184,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
171,6 → 201,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
181,6 → 218,13
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |
/TUT/ip.hwp.accelerator/sig_gen/1.0/sig_gen.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?> |
<!--Created by Kactus 2 document generator 14:08:07 30.11.2011--> |
<!--Created by Kactus 2 document generator 13:36:38 02.12.2011--> |
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd"> |
<spirit:vendor>TUT</spirit:vendor> |
<spirit:library>ip.hwp.accelerator</spirit:library> |
132,6 → 132,15
</spirit:busInterface> |
</spirit:busInterfaces> |
<spirit:model> |
<spirit:views> |
<spirit:view> |
<spirit:name>rtl</spirit:name> |
<spirit:envIdentifier>vhdl::</spirit:envIdentifier> |
<spirit:fileSetRef> |
<spirit:localName>hdlSources</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
</spirit:views> |
<spirit:ports> |
<spirit:port> |
<spirit:name>clk</spirit:name> |
141,6 → 150,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
151,6 → 167,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
161,6 → 184,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
171,6 → 201,13
<spirit:left>31</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
<spirit:port> |
181,6 → 218,13
<spirit:left>0</spirit:left> |
<spirit:right>0</spirit:right> |
</spirit:vector> |
<spirit:wireTypeDefs> |
<spirit:wireTypeDef> |
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName> |
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition> |
<spirit:viewNameRef>rtl</spirit:viewNameRef> |
</spirit:wireTypeDef> |
</spirit:wireTypeDefs> |
</spirit:wire> |
</spirit:port> |
</spirit:ports> |